Display panel and display device

Abstract

The application discloses a display panel and a display device, which comprise a pixel circuit and a light-emitting element; a driving module of the pixel circuit is used for providing a driving current to the light-emitting element; a data writing module of the pixel circuit provides a data signal in a data writing stage; an initialization module of the pixel circuit provides an initialization signal in an initialization writing stage; one frame of picture time of the display panel at least comprises a data writing frame; the data writing frame comprises the initialization writing stage, the data writing stage and a light-emitting stage; in the same data writing frame, a time period between a starting moment of the initialization writing stage and a starting moment of the data writing stage is an initialization stage; the length of the initialization stage in a first mode is different from the length of the initialization stage in a second mode, and / or the length of the initialization writing stage in the first mode is different from the length of the initialization writing stage in the second mode, so that the initialization condition of a driving transistor can be adjusted according to a brightness mode.

Description

Technical Field

[0001] This invention relates to the field of display panel technology, and more particularly to a display panel and a display device. Background Technology

[0002] Display panels typically contain pixel circuits and light-emitting elements. The driving transistors in the pixel circuits can provide driving current to the light-emitting elements based on the data signals they receive, thereby driving the light-emitting elements to emit light and enabling the display panel to display the corresponding image.

[0003] However, over time, the internal characteristics of the driving transistors in the pixel circuit change slowly, causing the threshold voltage of the driving transistors to drift. Moreover, the threshold drift of the driving transistors varies under different display brightness, thus affecting the display uniformity of the display panel. Summary of the Invention

[0004] The present invention provides a display panel and a display device for initializing the driving transistors to different degrees for different brightness modes, thereby improving the display uniformity of the display panel under different brightness modes.

[0005] According to one aspect of the present invention, a display panel is provided, comprising: pixel circuitry and light-emitting elements;

[0006] The pixel circuit includes a driving module, an initialization module, and a data writing module; the driving module includes a driving transistor.

[0007] The driving module is used to selectively provide driving current to the light-emitting element;

[0008] The operation of the pixel circuit includes a data writing stage and an initialization writing stage; in the data writing stage, the data writing module provides a data signal; in the initialization writing stage, the initialization module provides an initialization signal.

[0009] The display panel's frame duration includes at least a data writing frame; the data writing frame includes the initialization writing phase, the data writing phase, and the light emission phase;

[0010] Within the same data write frame, the time period between the start time of the initialization write phase and the start time of the data write phase is the initialization phase;

[0011] The display panel has a first mode and a second mode; the display brightness of the display panel in the first mode is different from that in the second mode.

[0012] The length of the initialization phase in the first mode is different from the length of the initialization phase in the second mode, and / or the length of the initialization write phase in the first mode is different from the length of the initialization write phase in the second mode.

[0013] In a second aspect, embodiments of the present invention provide a display device including the display panel described in the first aspect.

[0014] The technical solution of this invention uses the time period between the start time of the initialization writing phase and the start time of the data writing phase within the same data writing frame as the initialization phase. By using the initialization signal written during the initialization writing phase and / or the initialization phase, the problem of internal ion polarization and threshold voltage drift caused by the long-term constant voltage difference between the source and / or drain of the driving transistor and its gate can be improved. Simultaneously, when the display panel is in different modes, it exhibits different display brightness, and the gate voltage of the driving transistor differs when the display panel exhibits different display brightness. In this case, by controlling the different durations of at least one of the initialization writing phase and / or the initialization phase in different brightness modes, the bias state of the driving transistor in each brightness mode can be specifically adjusted, thereby ensuring display uniformity in different brightness modes.

[0015] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0018] Figure 2 This is a schematic diagram of the pixel circuit in a display panel provided by an embodiment of the present invention;

[0019] Figure 3 This is a driving timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0020] Figure 4 This is a driving timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0021] Figure 5 This is a driving timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0022] Figure 6 This is a driving timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0023] Figure 7 This is a driving timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0024] Figure 8 This is a driving timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0025] Figure 9 This is a driving timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0026] Figure 10 This is a schematic diagram of the pixel circuit structure in another display panel provided by an embodiment of the present invention;

[0027] Figure 11 Is with Figure 10 A corresponding timing diagram of the pixel circuit in a display panel;

[0028] Figure 12 This is a driving timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0029] Figure 13 This is a driving timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0030] Figure 14 This is a driving timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0031] Figure 15 This is a driving timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0032] Figure 16 This is a driving timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0033] Figure 17 This is a driving timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0034] Figure 18 This is a driving timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0035] Figure 19This is a driving timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0036] Figure 20 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0037] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0038] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a system, product, or device comprising a series of units is not necessarily limited to those steps or units explicitly listed, but may include other units not explicitly listed or inherent to such products or devices.

[0039] Self-emissive display panels include pixel circuits and light-emitting elements. The pixel circuits include driving transistors. By providing a data signal to the gate of the driving transistor, the driving transistor converts the data signal into a driving current to drive the light-emitting element to emit light. However, when the driving transistor is turned on, for PMOS transistors, its gate potential may be higher than its drain potential, and for NMOS transistors, its gate potential may be lower than its drain potential. If this state is maintained for a long time, the ions inside the driving transistor will become polarized, resulting in a built-in electric field inside the driving transistor. This causes the threshold voltage of the driving transistor to drift continuously, biasing the driving transistor and affecting the stability of the driving current provided by the driving transistor, thereby affecting the light-emitting stability of the light-emitting element.

[0040] Furthermore, when the display panel presents different display brightness, the data signals provided to the driving transistor will be different, or the light emission duration of the light-emitting element will be different, resulting in different bias conditions of the driving transistor, that is, different threshold voltage drift of the driving transistor, which affects the display uniformity of the display panel under different display brightness, and thus affects the display effect of the display panel.

[0041] To address the aforementioned technical problems, this invention uses an initialization phase, defined as the time interval between the start of the initialization writing phase and the start of the data writing phase within the same data writing frame. By incorporating the initialization signals written during the initialization writing phase and / or the initialization phase, the internal ion polarization and threshold voltage drift caused by the prolonged instability of the voltage difference between the source and / or drain of the driving transistor and its gate can be mitigated. Furthermore, when the display panel is in different modes, it exhibits different display brightness, and the gate voltage of the driving transistor varies with these brightness levels. By controlling the duration of at least one of the initialization writing phase and / or the initialization phase in different brightness modes, the bias state of the driving transistor in each brightness mode can be specifically adjusted, thereby ensuring display uniformity across different brightness modes.

[0042] The above is the core idea of ​​this invention. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention. The technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings.

[0043] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of the pixel circuit structure in a display panel provided by an embodiment of the present invention. Figure 3 This is a driving timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention, for reference. Figures 1 to 3 This invention provides a display panel 10, which includes a pixel circuit 100 and a light-emitting element 200. The pixel circuit 100 includes a driving module 11, an initialization module 12, and a data writing module 13. The driving module 11 includes a driving transistor M1. The driving module 11 is used to selectively provide driving current to the light-emitting element 200. The operation of the pixel circuit 100 includes a data writing stage T2 and an initialization writing stage T1. In the data writing stage T2, the data writing module 13 provides a data signal Vdata. In the initialization writing stage T1, the initialization module 12 provides an initialization signal Vref1.

[0044] It is understood that the display panel 10 may include an array of pixel circuits 100 and light-emitting elements 200 electrically connected to each pixel circuit 100. By providing data signals to each pixel circuit 100, the driving module 11 in the pixel circuit 100 can selectively provide driving current to the light-emitting element 200 to drive the light-emitting element 200 to emit light, so that the display panel 10 can present the corresponding display image.

[0045] Since the light-emitting element 200 is typically a current-driven element, and the data signal received by the pixel circuit 100 is typically a voltage signal, by setting a driving transistor M1 in the driving module 11, the data signal received by the pixel circuit 100 can be written to the gate of the driving transistor M1. Furthermore, by providing a positive power supply signal PVDD to the source or drain of the driving transistor M1, the driving transistor M1 generates a corresponding driving current based on the voltage difference between its gate potential and the positive power supply signal PVDD, as well as the threshold voltage of the driving transistor M1, and provides it to the light-emitting element 200, thereby driving the light-emitting element 200 to emit light at a corresponding brightness. At this time, one of the source and drain of the driving transistor M1 can be coupled to the positive power supply signal terminal, and the other can be coupled to the anode of the light-emitting element 200. The cathode of the light-emitting element 200 can be electrically connected to the negative power supply signal terminal. Thus, since there is a voltage difference between the positive power supply signal PVDD at the positive power supply signal terminal and the negative power supply signal PVEE at the negative power supply signal terminal, a current path is formed, which enables the driving transistor M1 to generate a driving current and provide it to the light-emitting element 200, driving the light-emitting element 200 to emit light.

[0046] It is understood that the active layer material of the driving transistor M1 in the driving module 11 may include low-temperature polycrystalline silicon, which gives it a high carrier mobility, thereby meeting the requirements of high response speed and low power consumption. In this case, the driving transistor M1 can be a PMOS type transistor. In other optional embodiments, the active layer material of the driving transistor M1 may also include oxide semiconductor material. In this case, the driving transistor M1 can be an NMOS type transistor. Provided that the core inventive points of this invention can be achieved, this invention does not specifically limit the material and type of the driving transistor M1.

[0047] It should be noted that the source and drain of a transistor are not constant, but change as the state of the transistor changes. Figure 2 The example shown only illustrates the case where the driving transistor M1 is a PMOS type transistor. In this case, the drain of the driving transistor M1 is coupled to the light-emitting element 200, and for the PMOS type driving transistor M1, the driving current I generated by the driving transistor M1 is k(PVDD-Vdata). 2Positive correlation. The positive power signal PVDD is usually a constant value. When PVDD is always greater than Vdata, the smaller Vdata is, the larger the driving current I is, and the greater the display brightness of the light-emitting element 200.

[0048] For ease of description, unless otherwise specified, the embodiments of the present invention all use PMOS transistors as an example to illustrate the technical solutions of the embodiments of the present invention.

[0049] Among them, reference Figure 2 As shown, the pixel circuit 100 may further include an initialization module 12. One end of the initialization module 12 receives an initialization signal Vref1, and the other end is electrically connected to the gate of the driving transistor M1. During the initialization phase T1, the initialization module 12 can transmit the initialization signal Vref1 to the gate of the driving transistor M1 to initialize the gate of the driving transistor M1. Specifically, the initialization module 12 can be turned on or off under the control of the scan signal S-N1, and when the scan signal SN-1 controls the initialization module 12 to be turned on, the initialization signal Vref1 is transmitted to the gate of the driving transistor M1. At this time, the initialization module 12 may include an initialization transistor M2. The gate of the initialization transistor T2 receives the scan signal S-N1, the first terminal of the initialization transistor M2 receives the initialization signal Vref1, and the second terminal of the initialization transistor M2 is electrically connected to the gate of the driving transistor M1 at node N1.

[0050] Continue to refer to Figure 2 As shown, the pixel circuit 100 also includes a data writing module 13, which provides a data signal Vdata to the gate of the driving transistor M1 during the data writing stage T2. Specifically, when the data signal Vdata received by the driving transistor M1 is different, the driving current generated by the driving transistor M1 is different, resulting in different light-emitting brightness of the light-emitting element 200. One end of the data writing module 13 can receive the data signal Vdata, and the other end of the data writing module 13 can be electrically connected to the source of the driving transistor M1 at node N2. The data writing module 13 can be turned on or off under the control of the scan signal SP. When the scan signal SP controls the data writing module 13 to be turned on, the data writing module 13 can write the data signal Vdata to the source of the driving transistor M1, and the data is transmitted from the source of the driving transistor M1 to its gate. At this time, the data writing module 13 may include a data writing transistor M3, the gate of which can receive the scan signal SP, the first terminal of which receives the data signal Vdata, and the second terminal of which is electrically connected to the source of the driving transistor M1.

[0051] Optional, continue to refer to Figure 2As shown, the pixel circuit 100 may further include a compensation module 14, which is electrically connected between the drain and gate of the driving transistor M1. Specifically, one end of the compensation module 14 is electrically connected to the drain of the driving transistor M1 at node N3, and the other end is electrically connected to the gate of the driving transistor M1 at node N1. The compensation module 14 can compensate the threshold voltage of the driving transistor M1 to the gate of the driving transistor M1 while the data signal Vdata is being written, so as to offset or mitigate the influence of the threshold voltage of the driving transistor M1 on the driving current provided by the driving transistor M1 when the driving module M1 provides driving current to the light-emitting element 200. For example, the compensation module 14 can be turned on or off under the control of the scan signal S-N2. When the compensation module 14 is turned on under the control of the scan signal S-N2, the compensation module 14 can adjust the voltage between the gate and drain of the driving transistor M1 and compensate for the threshold voltage of the driving transistor M1. At this time, the compensation module 14 may include a compensation transistor M4, the first terminal of which is electrically connected to the drain of the driving transistor M1, the second terminal of which is electrically connected to the gate of the driving transistor M1, and the gate of the compensation transistor M4 receives the scan signal S-N2.

[0052] Optional, continue to refer to Figure 2 As shown, the pixel circuit 100 may further include a reset module 15. This reset module 15 can provide a reset signal Vref2 to the anode of the light-emitting element 200 to reset the anode of the light-emitting element 200, preventing the signal provided to the anode of the light-emitting element 200 in the previous light-emitting stage from affecting the light-emitting accuracy of the light-emitting element 200 in the next light-emitting stage. Thus, the reset stage in which the reset module 15 provides the reset signal Vref2 to the light-emitting element 200 should be located in the non-light-emitting stage before the light-emitting stage. Specifically, one end of the reset module 15 can receive the reset signal Vref2, and the other end can be electrically connected to the anode of the light-emitting element 200. The reset module 15 can be turned on or off under the control of the scan signal SP. When the scan signal SP controls the reset module 15 to be turned on, the reset module 15 can transmit the reset signal Vref2 to the anode of the light-emitting element 200 to reset the light-emitting element 200. At this time, the reset module 15 may include a reset transistor M5, the gate of which can receive a scan signal SP, the first terminal of which receives a reset signal Vref2, and the second terminal of which is electrically connected to the anode of the light-emitting element 200.

[0053] Optional, continue to refer to Figure 2As shown, the pixel circuit 100 may further include a light-emitting control module 16, which can control the timing of the driving transistor M1 providing driving current to the light-emitting element 200. The light-emitting control module 16 can be connected in series with the light-emitting element 200 and the driving transistor M1 between the positive power supply signal terminal and the negative power supply signal terminal. The light-emitting control module 16 may include a first light-emitting control transistor M6 and a second light-emitting control transistor M7. The gates of both the first and second light-emitting control transistors receive a light-emitting control signal Emit. The first terminal of the first light-emitting control transistor M6 receives a positive power supply signal PVDD. The second terminal of the first light-emitting control transistor M6 is electrically connected to the source of the driving transistor M1. The first terminal of the second light-emitting control transistor M7 is electrically connected to the drain of the driving transistor M1, and the second terminal of the second light-emitting control transistor M7 is electrically connected to the anode of the light-emitting element 200. The light-emitting control signal Emit can be a pulse signal. When both the first light-emitting control transistor M6 and the second light-emitting control transistor M7 are NMOS transistors, a high level of the Emit signal turns both transistors on, while a low level turns them off. Conversely, when both transistors are PMOS transistors, a low level of the Emit signal turns them on, while a high level turns them off. Thus, by controlling the duty cycle of the Emit signal, the on-time of the first and second light-emitting control transistors M6 and M7 can be controlled.

[0054] In addition, continue to refer to Figure 2 The pixel circuit 100 may further include a storage capacitor C, which can be used to store the gate potential of the driving transistor M1. The specific connection method of the storage capacitor C can be determined according to specific circumstances. Provided that the storage of the gate potential of the driving transistor M1 can be achieved, this embodiment of the invention does not specifically limit the connection method of the storage capacitor.

[0055] Continue to refer to Figures 1 to 3The display panel 10's frame duration includes at least a data writing frame T; the data writing frame T includes an initialization writing phase T1, a data writing phase T2, and a light emission phase T3. In the initialization phase T1, the initialization module 12 is turned on under the control of the scan signal S-N1, writing the initialization signal Vref1 to the first node N1 electrically connected to the gate of the driving transistor M1 to initialize the gate of the driving transistor M1. In the data writing phase T2, the data writing module 13 is turned on under the control of the scan signal SP, and the compensation module 14 is turned on under the control of the scan signal S-N2, causing the data signal Vdata to be written sequentially through the data writing transistor M3, the driving transistor M1, and the compensation transistor M4 to the gate of the driving transistor M1. Simultaneously, in the data writing phase T2, the reset module 15 is turned on under the control of the scan signal SP, writing the reset signal Vref2 to the anode of the light-emitting element 200 to initialize the anode of the light-emitting element 200. During the light-emitting stage T3, the light-emitting control module 16 is turned on under the control of the light-emitting control signal Emit, so that the driving module 11 generates a driving current that can be transmitted to the anode of the light-emitting element 200. The positive power supply signal PVDD passes through the light-emitting control module 16 and the driving module 11, thereby generating a driving current to drive the light-emitting element 200 to emit light.

[0056] Meanwhile, the display panel 10 can operate in different modes under different application scenarios, and in different operating modes, the display panel 10 can display different brightness levels. For example, in brighter environments, to ensure that the image displayed by the display panel 10 is recognizable to the human eye, the display brightness of the image displayed by the display panel 10 is usually controlled to be higher; in darker environments, to prevent the high brightness of the image displayed by the display panel 10 from causing damage to the human eye, the display brightness of the image displayed by the display panel 10 is usually controlled to be lower. Specifically, by adjusting the relationship between grayscale (i.e., the luminous brightness level of the light-emitting element) and the data signal, the display panel 10 can achieve different display brightness levels in different operating modes.

[0057] When the operating modes of the display panel 10 include a first mode N1 and a second mode N2, and the brightness of the display panel 10 in the first mode N1 is different from that in the second mode N2, when the display panel 10 presents the same image in the first mode N1 and the second mode N2 respectively, there is a difference between the data signal Vdata received by the gate of the driving transistor M1 in the same pixel circuit 100 in the first mode N1 and the data signal Vdata in the second mode N2. This causes a voltage difference between the gate and the source and / or drain of the driving transistor M1 in the pixel circuit 100 in different modes, resulting in a different bias condition of the driving transistor M1 in the pixel circuit 100 in the first mode N1 and the second mode N2.

[0058] Therefore, when the display mode of the display panel 10 includes a first mode N1 and a second mode N2; the display brightness of the display panel 10 in the first mode N1 is different from that in the second mode N2; the length of the initialization phase Ta in the first mode N1 is different from that in the second mode N2; and / or the length of the initialization write phase T1 in the first mode N1 is different from that in the second mode N2. Wherein, the initialization phase Ta is the time period between the start time of the initialization write phase T1 and the start time of the data write phase T2 within the same data write frame T.

[0059] Specifically, in the first and second modes, the initialization write phase T1 and / or the initialization phase Ta used to adjust the bias of the driving transistor M1 can differ, resulting in differences in the duration for which the gate of the driving transistor M1 holds the initialization signal Vref1. When the voltage at the source and / or drain of the driving transistor M1 is Vs / d, if the initialization duration of the gate of the driving transistor M1 is different, the duration of the voltage difference between the gate and the source and / or drain of the driving transistor M1, which is the initialization signal Vref1-Vs / d, will also be different, thus causing the driving transistor M1 to have different bias states. In other words, the different bias states of the driving transistor M1 can be caused by the different durations of the corresponding voltage difference held between the gate and the source and / or drain, thereby balancing the bias generated by the driving transistor M1 writing different voltage data signals Vdata in the data write phase T2 of different modes.

[0060] Understandable Figure 3The example only illustrates that the initialization write phase T1 in the first mode N1 differs from the initialization write phase T1 in the second mode N2. Similarly, the initialization phase Ta in the first mode N1 also differs from the initialization phase Ta in the second mode N2. In other embodiments, only the initialization write phase T1 differs between modes. In this case, the time for providing the initialization signal Vref1 to the gate of the driving transistor M1 differs between modes, so that the gate of the driving transistor M1 remains at the initialization signal Vref1 for different durations in different modes. Alternatively, in other optional embodiments, only the initialization phase Ta differs between modes. Similarly, the time for the gate of the driving transistor M1 remains at the initialization signal Vref1 differs between modes. Without specifically limiting the invention to the core inventive points, the embodiments of the present invention are designed to achieve these goals.

[0061] It should be noted that the above description is merely an illustrative example of the case where, upon entering the initialization phase Ta, the gate signal of the driving transistor M1 remains consistent with the initialization signal Vref1, while the source and drain signals of the driving transistor remain as they were before the initialization phase Ta. However, in this embodiment of the invention, the source and drain signals of the driving transistor M1 can also change as the initialization phase Ta progresses.

[0062] For example, in combination Figure 4 and Figure 2 As shown, when entering the initialization phase Ta, the effective level of the scan signal S-N1 used to control the conduction of the initialization module 12 and the effective level of the scan signal S-N2 used to control the conduction of the compensation module 12 can overlap for a time of ΔT. During this time, within ΔT, the scan signal S-N1 controls the initialization module 12 to conduct, while the scan signal S-N2 controls the compensation module 14 to conduct. This allows the initialization signal Vref1 to be transmitted through the initialization module 12 to the gate of the driving transistor M1, and then by the compensation module 14 to the drain of the driving transistor. This ensures that the signals at the gate, drain, and source of the driving transistor M1 are close to the initialization signal Vref1. In this way, the drain and gate voltages of the driving transistor M1 can be kept as consistent as possible, ensuring that the voltage difference between the gate and drain of the driving transistor M1 is sufficiently small. This allows the driving transistor M1 to transition from a biased state to an unbiased state, effectively reducing the threshold drift caused by the bias of the driving transistor M1.

[0063] Furthermore, if the initialization signal Vref1 provided by the initial module 12 to the gate of the driving transistor M1 can control the initialization transistor M1 to be in the on state, then within the time ΔT, the initialization signal Vref1 can also be transmitted to the source of the initialization transistor M1, so that the voltages of the gate, source and drain of the driving transistor M1 are kept consistent, so as to effectively adjust the bias of the driving transistor M1, thereby ensuring the overall display effect of the display panel 10.

[0064] In summary, the display panel provided in this embodiment of the invention controls the duration of at least one of the initialization writing phase and / or initialization phase in different brightness modes to specifically adjust the bias state of the driving transistor in each brightness mode, thereby initializing the driving transistor M1 to different degrees and adjusting the bias of the driving transistor M1 to different degrees, ensuring the working stability of the driving transistor M1, further ensuring the display uniformity in different brightness modes, and improving the display effect of the display panel 10.

[0065] It is understood that the operating modes of the display panel mentioned in the embodiments of the present invention, including the first mode N1 and the second mode N2, do not simply refer to two operating modes of the display panel. Rather, the first mode N1 and the second mode N2 represent different operating modes of the display panel, and the display panel will have different brightness in different operating modes. In the embodiments of the present invention, the operating modes of the display panel are different in different application scenarios, resulting in different brightness levels of the display panel. For ease of description, unless otherwise specified, the embodiments of the present invention use the example of a display panel operating with two modes (the first mode and the second mode) to illustrate the technical solution of the embodiments of the present invention.

[0066] Optional, continue to refer to the references Figure 2 and Figure 3 In the first mode N1, the brightness of the display panel 10 is less than that in the second mode N2. In the first mode N1, the length of the initialization write phase T1 is t11 and the length of the initialization phase Ta is t12. In the second mode N2, the length of the initialization write phase T1 is t21 and the length of the initialization phase Ta is t22. Wherein, t21>t11 and t22>t12.

[0067] In this process, by adjusting the relationship between grayscale (i.e., the brightness level of the light-emitting element) and data signal, the display panel can have different display brightness in different operating modes. If the brightness of the display panel in the first mode N1 is less than the brightness of the display panel 10 in the second mode N2, that is, in the first mode N1, when the brightness level (i.e., grayscale) presented by the light-emitting element 200 is n, the data signal that needs to be provided to the driving transistor M1 in the pixel circuit 100 is Vdata1; while in the second mode N2, when the brightness level presented by the light-emitting element 200 is also n, the data signal that needs to be provided to the driving transistor M1 in the pixel circuit 100 is Vdata2. If the driving transistor M1 is a PMOS transistor, then Vdata1 will be greater than Vdata2. Thus, the voltage difference between the gate and the source of the driving transistor M1 in the first mode N1 will be greater than the voltage difference between the gate and the source of the driving transistor M1 in the second mode N2, resulting in different bias conditions for the driving transistor M1 in the first mode N1 and the second mode N2. At this time, it is necessary to adjust the bias of the driving transistor M1 according to the different operating modes of the display panel 10.

[0068] Specifically, in the second mode N2, the voltage of the data signal Vdata2 written to the gate of the driving transistor M1 during the data writing phase T2 is relatively small, resulting in a weaker internal ion polarization of the driving transistor M1 due to the data signal Vdata2. In this case, the duration for which the gate of the driving transistor M1 is held at the initialization signal Vref1 can be increased, allowing the driving transistor M1 to exhibit a stronger internal ion polarization under the action of the initialization signal Vref1, thus achieving a higher initialization level. Conversely, in the first mode N1, the voltage of the data signal Vdata1 written to the gate of the driving transistor M1 during the data writing phase T2 is relatively large, resulting in a stronger internal ion polarization of the driving transistor M1 due to the data signal Vdata1. In this case, the duration for which the gate of the driving transistor M1 is held at the initialization signal Vref1 can be shortened, resulting in a weaker internal ion polarization under the action of the initialization signal Vref1, thus achieving a lower initialization level. Thus, by making the duration of the initialization phase Ta and the initialization writing phase T1 in high brightness mode longer than those in low brightness mode, the internal ion polarization and threshold voltage drift caused by the different data signals Vdata supplied to the gate of the driving transistor M1 under different brightness levels can be balanced or improved. This balances the bias situation generated after the data signal Vdata is supplied to the driving transistor M1, ensuring that the bias situation of the driving transistor M1 remains consistent when entering the light emission phase T3 in different modes. This allows the driving transistor M1 to accurately generate the driving current, which is beneficial to improving the display effect of the display panel and the display uniformity of the display panel in different modes.

[0069] Understandable Figure 3 The example only illustrates that when the brightness of the display panel in the first mode N1 is less than that in the second mode, the initialization write phase T1 time length in the first mode N1 is less than the initialization write phase T1 time length in the second mode N2. Simultaneously, the initialization phase Ta time length in the first mode N1 is also less than the initialization phase Ta time length in the second mode N2. However, in other embodiments of the invention, such as... Figure 5 As shown, it is also possible that the initialization phase Ta time length under the first mode N is less than the initialization phase Ta time length under the second mode N2, i.e., t21>t11; or, as Figure 6 As shown, the initialization write phase T1 time length can also be shorter than the initialization write phase T1 time length in the second mode N2, i.e., t22>t12. Provided that the core inventive points of this embodiment are achieved, this embodiment does not impose specific limitations in this regard.

[0070] Optional, continue to refer to Figures 1 to 3 As shown, when the data write frame T includes a non-light-emitting phase Tb, and the non-light-emitting phase Tb includes a data write phase T2 and an initialization write phase T1, the time interval between the start time of the non-light-emitting phase Tb and the start time of the initialization write phase T1 is the first time interval Tn1; under the first mode N1, the length of the first time interval Tn1 is t13; under the second mode N2, the length of the first time interval Tn1 is t23; where t23 <t13。

[0071] The data writing frame T includes a non-light-emitting stage Tb and a light-emitting stage T3. The light-emitting stage T3 is the light-emitting control signal Emit, which is the enable signal. At this time, the first light-emitting control transistor M6 and the second light-emitting control transistor M7 are turned on, and the driving module 11 can provide driving current to the light-emitting element 200. In the non-light-emitting stage Tb, the light-emitting control signal Emit is disabled. During this stage, the driving module 11 cannot provide driving current to the light-emitting element 200, and the light-emitting element 200 does not emit light. This ensures that changes in the gate voltage of the driving transistor M1 do not affect the overall display brightness of the display panel. Thus, in the non-light-emitting stage Tb, an initialization writing stage T1 and a data writing stage T2 can be set. In the initialization writing stage T1, the driving transistor M1 can be initialized to clear the data signal Vdata written to the gate of the driving transistor M1 from the previous frame of display and control the driving transistor M1 to be in the on state, preparing for the writing of the data signal Vdata from the current frame of display. In the data writing stage T2, the data signal Vdata can be controlled to be written to the gate of the driving transistor M1, and the threshold voltage of the driving transistor M1 can be compensated so that in the light-emitting stage T3, the driving current provided by the driving transistor M1 is independent of its own threshold voltage.

[0072] In addition, the non-light-emitting phase Tb also includes a first time period Tn1, which is the time period between the start time of the non-light-emitting phase Tb and the start time of the initialization writing phase T1. The length of the first time period Tn1 can determine the time to start the initialization of the driving transistor M1, and thus determine the length of time the gate of the driving transistor M1 is kept as the initialization signal Vref1, or the length of time the gate of the driving transistor M1 is initialized, that is, the degree of initialization of the driving transistor M1.

[0073] Specifically, when the brightness of the display panel 10 in the first mode N1 is less than that in the second mode N2, the duration of the first time period Tn1 in the first mode N1 can be adjusted to be longer. This allows for a longer time to enter the initialization stage Ta after entering the non-light-emitting stage Tb in the first mode, thus allowing the gate of the driving transistor M1 to maintain the data signal of the previous frame for a longer period during the non-light-emitting stage Tb. In contrast, the duration of the first time period Tn1 in the second mode N2 is shorter, allowing for a faster entry into the initialization stage Ta after entering the non-light-emitting stage Tb in the second mode. This helps to shorten the time during which the gate of the driving transistor M1 maintains the data signal of the previous frame during the non-light-emitting stage Tb. In this way, a sufficiently long initialization phase Ta is provided for the higher brightness second mode N2, while a shorter initialization phase Ta is provided for the lower brightness first mode N1. This allows for a balanced adjustment of the bias of the driving transistor M1 across different modes by setting the initialization phase Ta duration under both modes (i.e., the duration for which the gate of the driving transistor M1 holds the initialization signal Vref1), thereby ensuring the overall display effect of the display panel 10. Adjusting the time difference for entering the initialization writing phase T1 ensures sufficient time is reserved for writing data signals, further guaranteeing the overall display effect of the display panel 10.

[0074] Optional, Figure 7 This is a driving timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention, in conjunction with reference to [reference needed]. Figure 1 , Figure 2 and Figure 7 As shown, for the same data write frame T, the time interval between the end time of the initialization write phase T1 and the start time of the data write phase T2 is the second time interval Tn2; under the first mode N1, the length of the second time interval Tn2 is t14; under the second mode N2, the length of the second time interval Tn2 is t24; wherein, when t21>t11 and t22>t12, t24 <t14。

[0075] When the non-light-emitting phase Tb also includes a second time period Tn2, which is the time period between the end of the initialization writing phase T1 and the start of the data writing phase T2, the length of the second time period Tn2 can determine the duration for which the gate of the driving transistor M1 continues to be the initialization signal Vref1 after the initialization signal Vref1 is written to the gate of the driving transistor M1.

[0076] Specifically, since the brightness of the display panel 10 in the first mode N1 is less than that in the second mode N2, the second time period Tn2 in the first mode N1 can be adjusted to be longer, so that after the initialization write stage T1 in the first mode N1, the gate of the driving transistor M1 continues to hold the initialization signal Vref1 for a longer period of time; while in the second mode, the second time period Tn2 is shorter, so that after the initialization write stage T1 in the second mode N2, the gate of the driving transistor M1 continues to hold the initialization signal Vref1 for a shorter period of time. In this way, a sufficiently long initialization write stage T1 can be reserved for the brighter second mode N2, while a shorter initialization write stage T1 can be reserved for the lower brightness first mode N1. Thus, by setting the duration of the initialization write stage T1 in the first mode N1 and the second mode N2, that is, the duration of providing the initialization signal Vref1 to the gate of the driving transistor M1, the balance of the bias adjustment of the driving transistor M1 in different modes can be ensured. In other words, the first mode N1 with lower brightness ends the initialization writing stage T1 first, and the second mode N2 with higher brightness ends the initialization writing stage T1 later. This is to better balance the bias of the driving transistor M1 caused by the voltage of the data signal Vdata, thereby ensuring the balance of the bias adjustment of the driving transistor M1 in different display modes, and thus ensuring the overall display effect of the display panel 10.

[0077] Optional, continue to refer to Figures 1 to 3 As shown, for the same data write frame T, the time period between the end time of the initialization write phase T1 and the start time of the data write phase T2 is the second time period Tn2; under the first mode N1, the length of the second time period Tn2 is t14; under the second mode N2, the length of the second time period Tn2 is t24; where, when t21>t11 and t22>t12, t24=t14.

[0078] Specifically, since the length of the second time period Tn2 determines the end time of writing the initialization signal Vref1 to the gate of the driving transistor M1, when the second time period Tn2 is the same for the lower brightness first mode N1 and the higher brightness second mode N2, the end time of the initialization writing phase T1 can be made the same. That is, the duration for which the gate of the driving transistor M1 remains as the initialization signal Vref1 after the initialization writing phase T1 is the same. In this case, the start time of the initialization writing phase T1 of the higher brightness second mode N2 can be set to be earlier than the start time of the initialization writing phase T1 of the lower brightness first mode N1, so that the length of the initialization writing phase T1 of the higher brightness second mode N2 is greater than the length of the initialization writing phase T1 of the lower brightness first mode N1, and the length of the initialization phase Ta of the higher brightness second mode N2 is greater than the length of the initialization phase Ta of the lower brightness first mode N1. This can better balance the voltage of the data signal Vdata and the bias generated by the driving transistor M1, ensuring the overall display effect of the display panel 10.

[0079] Optional, see reference Figure 1 , Figure 2 and Figure 5 As shown, the brightness of the display panel 10 in the first mode N1 is less than the brightness of the display panel 10 in the second mode N2; in the first mode N1, the length of the initialization write stage T1 is t11 and the length of the initialization stage Ta is t12; in the second mode N2, the length of the initialization write stage T1 is t21 and the length of the initialization stage Ta is t22; where t21>t11 and t22=t12.

[0080] Among them, reference Figure 5 As shown, the length of the initialization write phase T1 in the first mode N1 is t11, which is less than the length of the initialization write phase T1 in the second mode N2, which is t21, i.e., t21>t11. This means that in the second mode N2 with higher brightness, the duration of the initialization write phase T1 is increased, thereby ensuring that the driving transistor M1 can adjust its gate voltage during the initialization write phase T1, resulting in a higher degree of initialization for the driving transistor M1. Conversely, in the first mode N1 with lower brightness, the duration of the initialization write phase T1 is decreased, thereby ensuring that the driving transistor M1 can adjust its gate voltage during the initialization write phase T1, resulting in a lower degree of initialization for the driving transistor M1. In this way, the bias caused by the writing of the data signal Vdata of the driving transistor M1 in different modes can be balanced.

[0081] Correspondingly, the length of the initialization phase Ta for the first mode N1 and the second mode N2 can be set to the same value, i.e. t22 = t12. This ensures differentiated initialization of the driving transistor M1 in different modes, while setting the duration of other signals (such as the effective pulses of the scan signal SP and the light emission control signal Emit) to the same value. This ensures overall regularity and simplifies the control of the overall signal writing timing by the display panel 10.

[0082] Optional, continue to refer to Figure 1 , Figure 2 and Figure 5 As shown, the data write frame T includes a non-light-emitting phase Tb; the non-light-emitting phase Tb includes a data write phase T2 and an initialization write phase T1; in the same non-light-emitting phase Tb, the time interval between the start time of the non-light-emitting phase Tb and the start time of the initialization write phase T1 is the first time interval Tn1; under the first mode N1, the length of the first time interval Tn1 is t13; under the second mode N2, the length of the first time interval Tn1 is t23; where t23 = t13.

[0083] For details, please refer to Figure 5 As shown, the length of the first time period Tn1 of the first mode N1 is equal to the length of the first time period Tn1 of the second mode N2, i.e., t23 = t13. This means that regardless of whether it is the lower brightness first mode N1 or the higher brightness second mode N2, both enter the initialization writing stage T1 with the same timing interval, ensuring timing regularity and simplifying the control of the overall signal writing timing by the display panel 10. Simultaneously, by ensuring that the first mode N1 and the second mode N2 satisfy t21 > t11 and t22 = t12, the length of the initialization writing stage T1 under the higher brightness second mode N2 can be increased. This ensures that the driving transistor M1 under the higher brightness second mode N2 has a higher degree of initialization in the initialization writing stage T1, ensuring that the bias state of the driving transistor M1 remains consistent during the light emission stage T3 of different modes.

[0084] Optional, continue to refer to Figures 1 to 3 As shown, in the same data write frame T, the time period between the start time of the data write stage T2 and the start time of the light emission stage T3 is the data maintenance stage T2a; the data maintenance stage T2a under the first mode N1 and the data maintenance stage T2a under the second mode N2 have the same length.

[0085] Specifically, upon entering the data writing stage T2, the data signal Vdata is written to the gate of the driving transistor M1, causing the voltage at the gate of the driving transistor M1 to change from the voltage of the initialization signal Vref1 to the voltage of the data signal Vdata. Under the influence of the data signal Vdata, the driving transistor M1 will also have a certain bias. When the initialization stage Ta and / or the initialization writing stage T1 are set to different durations for different modes to balance the bias caused by the different data signals in different modes, the data holding stage T2a of the first mode N1 and the second mode N2 can be set to have the same duration. This ensures that the gate of the driving transistor M1 remains at the data signal Vdata for the same duration before the light emission stage T3 of the first mode N1 and the second mode N2. This makes the bias of the driving transistor M1 in the data holding stage T2a of the first mode N1 and the second mode N2 only related to its data signal Vdata. Thus, by setting the duration of the initialization stage Ta and / or the initialization writing stage T1 for different modes accordingly, the driving timing of the pixel circuit 100 can be simplified, and the overall driving cost can be reduced.

[0086] Optional, Figure 8 This is a driving timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention, for reference. Figure 1 , Figure 2 and Figure 8 As shown, in the same data write frame T, the time period between the start time of the data write stage T2 and the start time of the light emission stage T3 is the data maintenance stage T2a; the length of the data maintenance stage T2a under the first mode N1 is different from that under the second mode N2.

[0087] Specifically, during the data maintenance phase T2a, the gate signal of the driving transistor M1 is consistent with the data signal Vdata. However, the data signal Vdata written to the gate of the driving transistor M1 varies in different modes, resulting in different bias conditions of the driving transistor M1 due to the different data signals Vdata. At this time, although the driving transistor M1 is initialized to different degrees for the data signal written to the driving transistor M1 by setting the duration of the initialization phase Ta and / or the initialization writing phase T1, the duration of the initialization phase Ta and / or the initialization writing phase T1 is limited. Therefore, in order to ensure that the bias of the driving transistor M1 remains consistent when entering the light emission phase T3 in different modes, the length of the data holding phase Ta2 in different modes can also be set according to the difference of the written data signal. This allows the bias caused by the voltage of the written data signal Vdata to be superimposed with the bias when the gate of the driving transistor M1 is held at the initialization signal Vref1 and the bias when the gate of the driving transistor M1 is held at the data signal Vdata. This allows the driving transistor M1 to recover to a fixed bias state, thereby improving the consistency of the bias of the driving transistor M1 in different modes and helping to ensure the display uniformity of the display panel 10.

[0088] It is understood that the duration of the data maintenance phase may vary depending on the brightness mode. For example, the duration of the data maintenance phase in the first mode may be longer than that in the second mode, or the duration of the data maintenance phase in the first mode may be shorter than that in the second mode. The duration can be set according to actual needs. Under the premise that the bias of the driving transistor M1 can be kept consistent in different modes, this embodiment of the invention does not impose specific limitations on this.

[0089] Optional, Figure 9 This is a driving timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention, for reference. Figures 1 to 2 and Figure 9 As shown, the operation of the pixel circuit 100 may also include a bias stage Tv; during the bias stage Tv, the data writing module 13 provides a bias signal Vobs.

[0090] Specifically, the pixel circuit 100 includes a bias stage Tv. During the bias stage Tv, the pixel circuit 100 can provide a bias signal Vobs to the source and / or drain of the driving transistor M1, so that the voltage of the source and / or drain of the driving transistor M1 is consistent with the bias signal Vobs. This makes the voltage difference between the gate and the source and / or drain of the driving transistor M1 consistent with the difference between the data signal Vdata and the bias signal Vobs, thereby adjusting the bias state of the driving transistor M1. This improves or eliminates the phenomenon of threshold voltage drift of the driving transistor M1 caused by the long-term fixed voltage difference between the gate and the source and / or drain of the driving transistor M1, thereby improving the display uniformity of the display panel 10 and ensuring the display effect of the display panel 10.

[0091] Meanwhile, the data writing module 13 is reused as a module that provides the bias signal Vobs. That is, the data writing module 13 provides the data signal Vdata to the driving transistor M1 during the data writing stage T2, and provides the bias signal Vobs to the driving transistor M1 during the bias stage Tv. On the one hand, this can ensure the bias adjustment of the driving transistor M1, and on the other hand, it can save the setting space of the pixel circuit 100, and ensure the uniformity of the bias adjustment of the display panel 10, thus ensuring the display balance of the display panel 10.

[0092] It should be noted that, in conjunction with references Figure 2 and Figure 9As shown, the data writing module 13 is turned on or off under the control of the scan signal SP. At this time, the data writing module 13 may include a data writing transistor M3. The gate of the data writing transistor M3 receives the scan signal SP, the first terminal of the data writing transistor M3 receives the data signal Vdata or the bias signal Vobs, and the second terminal of the data writing transistor M3 is electrically connected to the source of the driving transistor M1. During the data writing stage T2, the scan signal SP controls the data writing transistor M3 to turn on. The first terminal of the data writing transistor M3 receives the data signal Vdata and transmits it to the source of the driving transistor M1, and then through the driving transistor M1 and the compensation transistor M4 to the gate of the driving transistor M1. During the bias stage Tv, the scan signal SP again controls the data writing transistor M3 to turn on. The first terminal of the data writing transistor M3 receives the bias signal Vobs and transmits it to the source of the driving transistor M1, and can also transmit it to the drain of the driving transistor M1. At this time, there is no need to set separate transistors for providing bias signals and data signals, which simplifies the structure of the pixel circuit 100 and helps to increase the number of pixel circuits 100 per unit area of ​​the display panel 10, thereby improving the resolution of the display panel 10. At the same time, when the transistors providing bias signals Vobs and data signals Vdata are the same write transistor M2, the write transistor M2 can be controlled to conduct in the bias stage Tb and the data writing stage Ta respectively by the same scan signal SP, so as to reduce the number of signals provided to the pixel circuit 100, thereby simplifying the structure of the moving register of the display panel 10 for providing the scan signal SP and improving the narrow bezel of the display panel 10.

[0093] In this configuration, the gates of the write transistors M2 in the pixel circuits located in the same row typically receive the same scan signal SP, and the write transistors M2 in the same column are typically electrically connected to the same first signal line L1. This first signal line L1 is used for time-division multiplexing of the data signals Vdata of each write transistor M2. At this time, the bias stage Tb of the i-th row pixel circuit 100 can overlap with the data writing stage Ta of the (i+j)-th row pixel circuit 100, and the data signal Vdata of the (i+j)-th row pixel circuit 100 can be multiplexed as the bias signal Vobs of the i-th row pixel circuit 100. This eliminates the need to provide additional bias signals Vobs to each pixel circuit 100, which helps to reduce the number of signals provided to the pixel circuit 100, thereby simplifying the structure of the display panel 10. Correspondingly, since there are differences between the data signals Vdata of the pixel circuits 100 located in the same column, the bias signals Vobs provided to each pixel circuit 100 in the data writing frame DT are non-fixed signals.

[0094] In other optional embodiments, when the bias signal Vobs of the i-th row pixel circuit 100 does not reuse the data signal Vdata of the (i+j)-th row pixel circuit 100, the bias stages Tb of each row pixel circuit 100 can be entered sequentially or simultaneously after the data writing stage Ta of the last row pixel circuit 100. At this time, all signal lines can transmit the bias signal Vobs simultaneously. The voltage of the bias signal Vobs can be a fixed value so that the bias signal Vobs transmitted in each signal line remains unchanged, preventing the signal lines from being continuously charged / discharged due to frequent changes in the bias signal Vobs, which would result in additional power consumption. That is, by making the voltage of the bias signal Vobs a fixed value, it is beneficial to reduce the power consumption of the display panel 10.

[0095] In another alternative embodiment, Figure 10 This is a schematic diagram of the pixel circuit structure in another display panel provided by an embodiment of the present invention. Figure 11 Is with Figure 10 A corresponding timing diagram for driving the pixel circuit in a display panel, in conjunction with a reference. Figure 10 and Figure 11 As shown, the data writing module 13 may include a first transistor M31 and a second transistor M32; the gate of the first transistor M31 receives a first scan signal S-P1, the first terminal of the first transistor M31 receives a data signal Vdata, and the second terminal of the first transistor M31 is electrically connected to the driving module 11, for example, the second terminal of the first transistor M31 may be electrically connected to the source of the driving transistor M1 in the driving module 11; during the data writing stage T2, the first scan signal S-P1 controls the first transistor M31 to be turned on, so that the data signal Vdata can pass through the first transistor M31 and the driving transistor M1. The compensation module 14 transmits the signal to the gate of the driving transistor M1; the gate of the second transistor M32 receives the second scan signal S-P2, the first terminal of the second transistor M32 receives the bias signal Vobs, and the second terminal of the second transistor M32 is electrically connected to the driving module 11. For example, the second terminal of the second transistor M32 can be electrically connected to the source of the driving transistor M1 in the driving module 11. During the biasing phase, the second scan signal S-P2 controls the second transistor M32 to turn on, so that the bias signal Vobs can be transmitted to the source of the driving transistor M1, and also to the drain of the driving transistor M1. In this way, different transistors are used to transmit the data signal Vdata and the bias signal Vobs respectively, so that the transmission of the data signal Vdata and the bias signal Vobs do not affect each other, which is beneficial to improving the accuracy of the transmitted signal.

[0096] Understandable Figure 10The example shown is only illustrative of the case where the second terminals of both the first transistor M31 and the second transistor M32 are electrically connected to the source of the driving transistor M1. In other embodiments of the present invention, one of the first transistor and the second transistor may be electrically connected to the source of the driving transistor, and the other may be electrically connected to the drain of the driving transistor. Provided that the core inventive points of the embodiments of the present invention can be achieved, the embodiments of the present invention do not specifically limit the connection method between the first transistor, the second transistor and the driving transistor.

[0097] Optionally, when the transistors transmitting the data signal Vdata and the bias signal Vobs are different transistors, the voltage of the bias signal Vobs provided to each pixel circuit can be a fixed value. This way, the voltage of the bias signal Vobs provided does not need to be changed within the time of one frame of the display panel, avoiding additional power consumption caused by frequent voltage jumps of the bias signal Vobs, which is beneficial to the low power consumption of the display panel.

[0098] In an optional embodiment, when the voltage of the bias signal is V11 in the first mode and V21 in the second mode, V11 can be made equal to V21. In this way, the voltage of the bias signal Vobs provided to the driving transistor M1 is the same in different modes, so that the voltage of the bias signal Vobs does not need to be changed when switching modes, thus preventing additional power consumption due to the voltage of the bias signal Vobs, which is beneficial to the low power consumption of the display panel.

[0099] Optional, Figure 12 This is another driving timing diagram of the pixel circuit in a display panel provided by an embodiment of the present invention. Figure 13 This is a driving timing diagram of the pixel circuit in another display panel provided by an embodiment of the present invention, for reference. Figure 2 and Figure 12 or Figure 10 and Figure 13 When the data write frame T includes an offset phase Tv, the offset phase Tv is located between the data write phase T2 and the light emission phase T3 within the same data write frame T; the time interval between the start time of the initialization phase Ta and the start time of the offset phase Tv within the same data write frame T is the third time interval Tn3; the brightness of the display panel 10 in the first mode N1 is less than the brightness of the display panel 10 in the second mode N2; in the first mode N1, the length of the third time interval Tn3 is t31; in the second mode N2, the length of the third time interval Tn3 is t41; where t31 <t41。

[0100] Within the same data write frame T, the bias phase Tv is located between the data write phase T2 and the light emission phase T3. That is, after the data write module 13 outputs the data signal Vdata to the driving transistor M1 in the data write phase T2, it then inputs the bias signal Vobs to the driving transistor M1 in the bias phase Tv, ensuring that the voltage difference between the gate and its source and / or drain of the driving transistor M1 after the bias phase Tv is Vdata - Vobs. When the same data write frame T also includes a third time period Tn3, which is the time period between the start of the initialization phase Ta and the start of the bias phase Tv, the length of this third time period Tn3 reflects the total writing time of the initialization signal Vref1 and the data signal Vdata before entering the bias phase Tv.

[0101] Specifically, by making the length of the third time period Tn3 in the higher brightness second mode greater than the length of the third time period Tn3 in the lower brightness first mode, the total time for biasing the gate of the driving transistor M1 using the initialization signal Vref1 and the time for biasing the driving transistor M1 using the data signal Vdata in the higher brightness second mode is longer, so as to offset or improve the bias caused by the lower voltage of the written data signal vdata; similarly, by making the total time for biasing the gate of the driving transistor M1 using the initialization signal Vref1 and the time for biasing the driving transistor M1 using the data signal Vdata in the higher brightness first mode shorter, so as to offset or improve the bias caused by the higher voltage of the written data signal vdata, thereby ensuring the overall balance of bias adjustment in different modes, and thus ensuring the uniformity of display on the display panel in different modes.

[0102] Optional, continue to refer to Figure 2 and Figure 12 or Figure 10 and Figure 13 For the same data write frame T, the time period between the start time of the data write phase T2 and the start time of the bias phase Tv is the fourth time period Tn4; the length of the fourth time period Tn4 under the first mode N1 is the same as the length of the fourth time period Tn4 under the second mode N2.

[0103] Specifically, when the data writing frame T includes a fourth time period Tn4, which is the time period between the start of the data writing phase T2 and the start of the bias phase Tv, the length of the fourth time period Tn4 can be set to the same length under different modes, namely the first mode N1 and the second mode N2. Therefore, when the data writing module 13 is controlled to be turned on in the data writing phase T2 and the bias phase Tv by the scanning signal SP (or the first scanning signal S-P1 and the second scanning signal S-P2), the time interval between the effective pulses corresponding to the data writing phase T2 and the effective pulses corresponding to the bias phase Tv in the scanning signal SP (or the first scanning signal S-P1 and the second scanning signal S-P2) does not need to be changed with the mode switching. That is, there is no need to change the output of the scanning signal SP (or the first scanning signal S-P1 and the second scanning signal S-P2), which simplifies the driving method of the display panel and reduces the computing power of the driving chip that controls the output of the scanning signal SP (or the first scanning signal S-P1 and the second scanning signal S-P2), which is beneficial to the low cost of the display panel.

[0104] Optional, Figure 14 This is a driving timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention. Figure 15 This is a driving timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention, with reference to the figure. Figure 2 and Figure 14 or Figure 10 and Figure 15 As shown, in the same data write frame T, the time period between the start time of the data write phase T2 and the start time of the bias phase Tv is the fourth time period Tn4; the brightness of the display panel 10 in the first mode N1 is less than the brightness of the display panel 10 in the second mode N2; in the first mode N1, the length of the fourth time period Tn4 is t32; in the second mode N2, the length of the fourth time period Tn4 is t42; where t32 <t42。

[0105] The fourth time period Tn4 refers to the period between the start of the data writing phase T2 and the start of the bias phase Tv. During this time, the gate of the driving transistor M1 remains at the data signal Vdata, and the source and drain signals Vs / d can be the same as the initialization signal Vref1, or the same as the signal written during the light-emitting phase T of the previous frame. At this time, when the brightness of the display panel in the first mode is less than that in the second mode, the voltage V1 of the data signal Vdata in the first mode N1 will be greater than the voltage V2 of the data signal Vdata in the second mode N1. This results in a voltage difference of V1-Vs / d between the gate and the source / drain of the driving transistor M1 in the first mode N1, and V2-Vs / d between the gate and the source / drain of the driving transistor M1 in the fourth time period Tn4 of the second mode N2. V1-Vs / d is greater than V2-Vs / d. At this time, although the driving transistor M1 is initialized to different degrees according to the data signal written to the driving transistor M1 by setting the duration of the initialization phase Ta and / or the initialization write phase T1, the duration of the initialization phase Ta and / or the initialization write phase T1 is limited. Therefore, by making the length of the fourth time period Tn4 under the lower brightness of the first mode N1 shorter than the length of the fourth time period Tn4 under the higher brightness of the second mode N2, the bias effect of different data signals Vdata written on the gate of the driving transistor M1 can be better balanced, ensuring the display uniformity of the display panel 10.

[0106] Optional, Figure 16 This is a driving timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention. Figure 17 This is a driving timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention, for reference. Figure 2 and Figure 16 or Figure 10 and Figure 17 As shown, in the same data write frame T, the time period between the start time of the bias phase Tv and the start time of the light emission phase T3 is the first bias maintenance phase Tv1; the brightness of the display panel 10 in the first mode N1 is less than the brightness of the display panel 10 in the second mode N2; in the first mode N1, the length of the first bias maintenance phase Tv1 is t33; in the second mode N2, the length of the first bias maintenance phase Tv1 is t43; where t33 <t43。

[0107] The data writing frame T includes a first bias sustaining phase Tv1, which is the time period between the start of the bias sustaining phase Tv and the start of the light emission phase T3. During the first bias sustaining phase Tv1, a bias adjustment signal can also be provided to the source and / or drain of the driving transistor M1, ensuring that the voltage at the source and / or drain of the driving transistor M1 is consistent with the bias adjustment signal. This makes the voltage difference between the gate and the source and / or drain of the driving transistor M1 consistent with the difference between the data signal and the bias adjustment signal, thereby adjusting the bias state of the driving transistor M1. This improves the display uniformity of the display panel and ensures the display effect.

[0108] Specifically, for different brightness modes of the display panel, namely the first mode N1 and the second mode N2, there is a difference in the data signal Vdata written in the data writing stage T2 between the two modes. At this time, by setting the length of the first bias maintenance stage Tv1 under the first mode N1 to be less than the length of the first bias maintenance stage Tv1 under the second mode N2, that is, by increasing the bias adjustment time under the second mode N2, that is, increasing the time for the voltage difference between the gate and source of the driving transistor M1 in the second mode N2 to be maintained at the data signal Vdata and the bias signal Vobs, and relatively shortening the bias adjustment time under the first mode N1, that is, shortening the time for the voltage difference between the gate and source of the driving transistor M1 in the first mode N1 to be maintained at the data signal Vdata and the bias signal Vobs, the bias of the transistor caused by the voltage of the different data signals Vdata of the display panel is balanced. By differentiating the design of the first bias maintenance stage Tv1, it can be ensured that the bias degree of the driving transistor M1 in the first mode N1 is consistent with the bias degree of the driving transistor M1 in the second mode N2, so as to balance the different bias conditions caused by different data signals in the two modes, and realize targeted adjustment of the bias state of the driving transistor M1 in different working modes, which is beneficial to the display uniformity of the display panel in different working modes.

[0109] Optional, Figure 18 This is a driving timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention. Figure 19 This is a driving timing diagram of a pixel circuit in a display panel provided by an embodiment of the present invention, for reference. Figure 2 and Figure 18 Or mention 10 and Figure 19As shown, the frame time of the display panel 10 also includes at least one holding frame Tk; the holding frame Tk includes a bias phase Tv and a light emission phase T3; in the holding frame Tk, the time between the start time of the bias phase Tv and the start time of the light emission phase T3 is the second bias maintenance phase Tv2; the duration of the second bias maintenance phase Tv2 under the first mode N1 is the same as the duration of the second bias maintenance phase Tv2 under the second mode N2.

[0110] In general, the display panel 10 has a hold frame Tk at low or medium frequency. The second bias maintenance phase Tv2 in the hold frame Tk is the time period between the start of the bias phase Tv and the start of the light emission phase T3. By setting the second bias maintenance phase Tv2 in the hold frame Tk, the voltage difference between the gate of the driving transistor M1 and its source / drain can be maintained as the voltage difference between the data signal Vdata and the bias signal Vobs during the second bias maintenance phase Tv2. This is different from the voltage difference between the gate of the driving transistor M1 and its source / drain in the light emission phase T3, which is maintained as the voltage difference between the data signal Vdata and the positive power supply signal PVDD. The bias of the driving transistor M1 in the light emission phase T3 can be adjusted.

[0111] In different display modes of the display panel 10, namely the first mode N1 and the second mode N2, the duration of the second bias maintenance phase Tv2 can be the same or different, and can be set according to actual needs. When the duration of the second bias maintenance phase Tv2 is the same in the first mode N1 and the second mode N2, the duration of the scan signal SP (or the first scan signal S-P1 and the second scan signal S-P2) used to control the data writing module 13 to be turned on or off, and the time relative to the start time of the light emission phase T3, do not need to change with the mode switching, thereby reducing the driving capability of the driving chip that controls the output of the scan signal SP, which is beneficial to reducing the cost of the display panel.

[0112] In an alternative embodiment, reference continues. Figure 2 and Figure 18 or Figure 10 and Figure 19 As shown, in the first mode N1, the voltage of the bias signal Vobs provided by the bias stage T of the holding frame Tk is V12; in the second mode N2, the voltage of the bias signal Vobs provided by the bias stage T of the holding frame Tk is V22; where V12 = V22.

[0113] Specifically, in the first mode N1, the voltage of the bias signal Vobs provided by the bias stage T of the hold frame Tk is the same as the voltage of the bias signal Vobs provided by the bias stage T of the hold frame Tk in the second mode N2. That is, the bias signal Vobs can be the same, meaning that the whole can be adjusted using the same bias signal Vobs. This eliminates the need for the bias signal Vobs to change with mode switching, avoiding power consumption caused by switching the bias signal Vobs, thus contributing to the low power consumption of the display panel.

[0114] Based on the same inventive concept, embodiments of the present invention also provide a display device. Figure 20 This is a schematic diagram of a display device according to an embodiment of the present invention. The display device includes any of the display panels provided in the above embodiments. For example, refer to... Figure 20 The display device 1 includes a display panel 10. Therefore, the display device also has the beneficial effects of the display panel and array substrate in the above embodiments. The similarities can be understood with reference to the explanation of the display panel and array substrate above, and will not be repeated below.

[0115] The display device 1 provided in this embodiment of the invention can be Figure 17 The mobile phone shown can also be any electronic product with display function, including but not limited to the following categories: television, laptop, desktop monitor, tablet computer, digital camera, smart bracelet, smart glasses, in-vehicle display, industrial control equipment, medical display screen, touch interactive terminal, etc. The embodiments of the present invention do not make any special limitations on this.

[0116] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that, include: Pixel circuits and light-emitting elements; The pixel circuit includes a driving module, an initialization module, and a data writing module; The driving module includes a driving transistor; The driving module is used to selectively provide driving current to the light-emitting element; The operation of the pixel circuit includes a data writing stage and an initialization writing stage; in the data writing stage, the data writing module provides a data signal; in the initialization writing stage, the initialization module provides an initialization signal. One frame of the display panel includes at least a data writing frame; the data writing frame includes the initialization writing phase, the data writing phase, and the light emission phase. Within the same data write frame, the time period between the start time of the initialization write phase and the start time of the data write phase is the initialization phase; The display panel has a first mode and a second mode; the display brightness of the display panel in the first mode is different from that in the second mode. The length of the initialization phase in the first mode is different from the length of the initialization phase in the second mode, and / or the length of the initialization write phase in the first mode is different from the length of the initialization write phase in the second mode; The brightness of the display panel in the first mode is less than the brightness of the display panel in the second mode; The data write frame includes a non-light-emitting phase; the non-light-emitting phase includes the data write phase and the initialization write phase; within the same non-light-emitting phase, the time interval between the start time of the non-light-emitting phase and the start time of the initialization write phase is a first time interval; in the first mode, the length of the first time interval is t13; in the second mode, the length of the first time interval is t23; wherein, t23 <t13。 2. The display panel according to claim 1, characterized in that, In the first mode, the length of the initialization write phase is t11 and the length of the initialization phase is t12; in the second mode, the length of the initialization write phase is t21 and the length of the initialization phase is t22; wherein, t21>t11 and / or t22>t12.

3. The display panel according to claim 2, characterized in that, For the same data write frame, the time period between the end time of the initialization write phase and the start time of the data write phase is the second time period; In the first mode, the length of the second time period is t14; in the second mode, the length of the second time period is t24; wherein, when t21>t11 and t22>t12, t24 <t14。 4. The display panel according to claim 2, characterized in that, For the same data write frame, the time period between the end time of the initialization write phase and the start time of the data write phase is the second time period; In the first mode, the length of the second time period is t14; in the second mode, the length of the second time period is t24; wherein, when t21>t11 and t22>t12, t24=t14.

5. The display panel according to claim 1, characterized in that, In the first mode, the length of the initialization write phase is t11 and the length of the initialization phase is t12; in the second mode, the length of the initialization write phase is t21 and the length of the initialization phase is t22; wherein, t21>t11 and t22=t12.

6. The display panel according to claim 1, characterized in that, The operation of the pixel circuit also includes a bias stage; during the bias stage, the data writing module provides a bias signal.

7. The display panel according to claim 6, characterized in that, The data writing frame includes the bias phase; within the same data writing frame, the bias phase is located between the data writing phase and the light emission phase; For the same data write frame, the time period between the start time of the initialization phase and the start time of the offset phase is the third time period; In the first mode, the length of the third time period is t31; in the second mode, the length of the third time period is t41; wherein, t31 <t41。 8. The display panel according to claim 7, characterized in that, For the same data write frame, the time period between the start time of the data write phase and the start time of the offset phase is the fourth time period; The length of the fourth time period in the first mode is the same as the length of the fourth time period in the second mode.

9. The display panel according to claim 7, characterized in that, Within the same data write frame, the time period between the start time of the data write phase and the start time of the offset phase is the fourth time period; In the first mode, the length of the fourth time period is t32; in the second mode, the length of the fourth time period is t42; wherein, t32 <t42。 10. The display panel according to claim 7, characterized in that, Within the same data write frame, the time period between the start time of the bias phase and the start time of the emission phase is the first bias maintenance phase; In the first mode, the length of the first bias maintenance phase is t33; in the second mode, the length of the first bias maintenance phase is t43; wherein, t33 <t43。 11. The display panel according to claim 6, characterized in that, The display panel's frame time also includes at least one hold frame; the hold frame includes the bias phase and the emission phase; in the hold frame, the time between the start time of the bias phase and the start time of the emission phase is a second bias maintenance phase; The duration of the second bias maintenance phase in the first mode is the same as the duration of the second bias maintenance phase in the second mode.

12. The display panel according to claim 11, characterized in that, In the first mode, the voltage of the bias signal provided by the bias phase of the hold frame is V12; In the second mode, the voltage of the bias signal provided by the bias phase of the hold frame is V22; where V12 = V22.

13. The display panel according to claim 1, characterized in that, Within the same data writing frame, the time period between the start time of the data writing phase and the start time of the light emission phase is the data maintenance phase; The data maintenance phase in the first mode has the same length as the data maintenance phase in the second mode.

14. The display panel according to claim 1, characterized in that, Within the same data writing frame, the time period between the start time of the data writing phase and the start time of the light emission phase is the data maintenance phase; The length of the data maintenance phase in the first mode is different from that in the second mode.

15. The display panel according to claim 6, characterized in that, The data writing module includes a first transistor and a second transistor; The gate of the first transistor receives a first scan signal, the first electrode of the first transistor receives the data signal, and the second electrode of the first transistor is electrically connected to the driving module; during the data writing phase, the first scan signal controls the first transistor to turn on. The gate of the second transistor receives the second scan signal, the first terminal of the second transistor receives the bias signal, and the second terminal of the second transistor is electrically connected to the driving module; during the bias phase, the second scan signal controls the second transistor to turn on.

16. The display panel according to claim 15, characterized in that, In the first mode, the voltage of the bias signal is V11; in the second mode, the voltage of the bias signal is V21. Where V11 = V21.

17. A display device, characterized in that, include: The display panel according to any one of claims 1-16.

Images