Display panel and display device

Abstract

This invention relates to the field of display technology and discloses a display panel and a display device. The display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a driving module, a first light-emitting control module, and a second light-emitting control module. A first terminal of the first light-emitting control module is electrically connected to a first power signal terminal, and a second terminal of the first light-emitting control module is electrically connected to the driving module. A first terminal of the second light-emitting control module is electrically connected to the driving module, and a second terminal of the second light-emitting control module is electrically connected to the light-emitting element. One frame of the display panel includes a light-emitting phase and a non-light-emitting phase. The non-light-emitting phase includes a first phase and a second phase. In the first phase, both the first and second light-emitting control modules are off. In the second phase, both the first and second light-emitting control modules are off. This invention effectively improves the technical problem of image flickering in the prior art.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically, to a display panel and a display device. Background Technology

[0002] Electronic products use different refresh rates for display in different application scenarios. For example, in video or game mode, a higher refresh rate can be used to drive the display of dynamic images to ensure smoothness. Conversely, when displaying slow-motion or still images, a lower refresh rate can be used to reduce power consumption.

[0003] However, existing display panels suffer from display flickering issues. This flickering is particularly severe when the display panel shows images at a low refresh rate. Summary of the Invention

[0004] In view of this, the present invention provides a display panel and a display device to improve the technical problem of image flickering in the prior art.

[0005] This invention provides a display panel, comprising: a pixel circuit and a light-emitting element. The pixel circuit drives the light-emitting element to emit light. The pixel circuit includes a driving module, a first light-emitting control module, and a second light-emitting control module. A first terminal of the first light-emitting control module is electrically connected to a first power signal terminal, and a second terminal of the first light-emitting control module is electrically connected to the driving module. The first light-emitting control module responds to a first light-emitting control signal by providing a first power signal to the driving module. A first terminal of the second light-emitting control module is electrically connected to the driving module, and a second terminal of the second light-emitting control module is electrically connected to the light-emitting element. The second light-emitting control module responds to a second light-emitting control signal by providing a signal output by the driving module to the light-emitting element. One frame of the display panel includes a light-emitting phase and a non-light-emitting phase. The non-light-emitting phase includes a first phase and a second phase. In the first phase, both the first and second light-emitting control modules are turned off. In the second phase, both the first and second light-emitting control modules are turned on.

[0006] Based on the same idea, the present invention also provides a display device, including the display panel provided by the present invention.

[0007] Compared with the prior art, the display panel and display device provided by the present invention achieve at least the following beneficial effects:

[0008] In the display panel provided by this invention, the non-light-emitting stage includes a second stage. In the second stage, the first light-emitting control module is turned off under the control of the first light-emitting control signal, and the second light-emitting control module is turned on under the control of the second light-emitting control signal. At this time, the potential of the third node is pulled down by the potential of the fourth node. Since the driving module is turned on, the potential of the second node is correspondingly pulled down by the potential of the third node. At this time, the potential of the second node is less than the potential of the first power signal, and the difference between the potential of the second node and the potential of the first power signal is large. At the end of the second stage, the first light-emitting control module is turned on under the control of the first light-emitting control signal, and the first power signal is instantaneously charged into the second node, which can bias the driving transistor with a high voltage, so that the electrical properties of the driving transistor are restored. This optimizes the initial rise rate of the luminous brightness of the light-emitting element during the light-emitting stage, thereby improving the technical problem of image flickering in the prior art.

[0009] Of course, any product implementing this invention need not necessarily achieve all of the technical effects described above at the same time.

[0010] Other features and advantages of the invention will become clear from the following detailed description of exemplary embodiments of the invention with reference to the accompanying drawings. Attached Figure Description

[0011] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments of the invention and, together with their description, serve to explain the principles of the invention.

[0012] Figure 1 This is a partial cross-sectional view of a display panel provided by the present invention;

[0013] Figure 2 This is a schematic diagram of a pixel circuit provided by the present invention;

[0014] Figure 3 This is a circuit diagram of a pixel circuit provided by the present invention;

[0015] Figure 4 This invention provides a driving timing diagram;

[0016] Figure 5 This is another driving timing diagram provided by the present invention;

[0017] Figure 6 This is yet another driving timing diagram provided by the present invention;

[0018] Figure 7 This is yet another driving timing diagram provided by the present invention;

[0019] Figure 8 This is yet another driving timing diagram provided by the present invention;

[0020] Figure 9 Is with Figure 8 The simulation diagram corresponding to the driving timing shown is shown.

[0021] Figure 10 This is a comparison chart of the brightness curves of the display panel in this invention and the display panel in the prior art when they are working;

[0022] Figure 11 This is a plan view of a display panel provided by the present invention;

[0023] Figure 12 This is a plan view of a display device provided by the present invention. Detailed Implementation

[0024] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the invention.

[0025] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the invention or its application or use.

[0026] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0027] In all the examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0028] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0029] Figure 1 This is a partial cross-sectional view of a display panel provided by the present invention. Figure 2 This is a schematic diagram of a pixel circuit provided by the present invention. Figure 3 This is a circuit diagram of a pixel circuit provided by the present invention. Figure 4 This is a driving timing diagram provided by the present invention, for reference. Figures 1-4This embodiment provides a display panel, which includes a substrate 10, an array layer 20 and a display layer 30 located on one side of the substrate 10. The array layer 20 includes a plurality of pixel circuits 21, and the display layer 30 includes a plurality of light-emitting elements 31. Specifically, the light-emitting elements 31 may include organic light-emitting diodes (OLEDs) or inorganic light-emitting diodes (LEDs). The light-emitting elements 31 include a first electrode, a light-emitting layer, and a second electrode stacked together. In one embodiment, the first electrode is an anode and the second electrode is a cathode. Of course, in other embodiments of the present invention, the display panel may also include other structures. For example, an encapsulation layer may be provided on the side of the display layer 30 away from the substrate 10 to encapsulate and protect the light-emitting elements 31. Alternatively, when the display panel also has a touch function, the display panel may also include a touch layer. The display panel of this embodiment includes, but is not limited to, the above structures. This embodiment does not specifically limit the structure of the display panel; for specific understanding, please refer to the structure of display panels in related technologies.

[0030] It should be noted that the display panel provided in this embodiment can be an organic light-emitting diode (OLED) display panel. Those skilled in the art should understand that in other implementations of this invention, the display panel provided can also be a liquid crystal display (LCD), a micro LED display, a quantum dot display (QLED), electronic paper, or other types of panels or display components. This application does not limit the specific type; the choice depends on the actual situation.

[0031] Pixel circuit 21 is electrically connected to light-emitting element 31, and pixel circuit 21 is used to drive light-emitting element 31 to emit light. Specifically, pixel circuit 21 provides driving current to light-emitting element 31, and light-emitting element 31 displays a certain brightness according to the magnitude of driving current.

[0032] The pixel circuit 21 includes a driving module 211, a first light-emitting control module 212, and a second light-emitting control module 213.

[0033] The first end of the first light-emitting control module 212 is electrically connected to the first power signal terminal, and the second end of the first light-emitting control module 212 is electrically connected to the driving module 211. The first light-emitting control module 212 responds to the first light-emitting control signal Emit1 and provides the first power signal PVDD to the driving module 211.

[0034] The first end of the second light-emitting control module 213 is electrically connected to the driving module 211, and the second end of the second light-emitting control module 213 is electrically connected to the light-emitting element 31. The second light-emitting control module 213 responds to the second light-emitting control signal Emit2 by providing the signal output by the driving module 211 to the light-emitting element 31.

[0035] For details, please refer to [link / reference]. Figure 2 The control terminal of the driving module 211 is electrically connected to the first node N1, the first terminal of the driving module 211 is electrically connected to the second node N2, and the second terminal of the driving module 211 is electrically connected to the third node N3. The first terminal of the first light-emitting control module 212 is electrically connected to the first power signal terminal, which is electrically connected to the first power signal PVDD, which is at a high level. The second terminal of the first light-emitting control module 212 is electrically connected to the second node N2, and the control terminal of the first light-emitting control module 212 is electrically connected to the first light-emitting control signal Emit1. The first light-emitting control module 212 can be turned on under the control of the first light-emitting control signal Emit1, that is, the first light-emitting control module 212 responds to the first light-emitting control signal Emit1 by providing the first power signal PVDD to the second node N2. The first end of the second light-emitting control module 213 is electrically connected to the third node N3, and the second end of the second light-emitting control module 213 is electrically connected to the light-emitting element 31. Specifically, the second end of the second light-emitting control module 213 is electrically connected to the fourth node N4, the first electrode of the light-emitting element 31 is electrically connected to the fourth node N4, and the second electrode of the light-emitting element 31 is electrically connected to the second power supply signal PVEE. The second power supply signal PVEE is at a low level. The control end of the second light-emitting control module 213 is electrically connected to the second light-emitting control signal Emit2. The second light-emitting control module 213 can be turned on under the control of the second light-emitting control signal Emit2. That is, the second light-emitting control module 213 responds to the second light-emitting control signal Emit2 by providing the signal output by the drive module 211 to the light-emitting element 31.

[0036] Combination Figure 3 Schematic circuit diagram and Figure 4 The timing diagram illustrates that one frame of the display panel includes a light-emitting phase T1 and a non-light-emitting phase T2. The non-light-emitting phase T2 includes a first phase T21 and a second phase T22. In the first phase T21, the first light-emitting control module 212 is turned off and the second light-emitting control module 213 is turned off. In the second phase T22, the first light-emitting control module 212 is turned off and the second light-emitting control module 213 is turned on.

[0037] Specifically, one frame of the display panel includes a light-emitting phase T1 and a non-light-emitting phase T2. In the light-emitting phase T1, the first light-emitting control module 212 is turned on under the control of the first light-emitting control signal Emit1, and provides the first power signal PVDD to the second node N2. The second light-emitting control module 213 is turned on under the control of the second light-emitting control signal Emit2, and provides the driving current generated by the driving module 211 to the light-emitting element 31, so that the light-emitting element 31 emits light.

[0038] The non-light-emitting phase T2 includes a first phase T21 and a second phase T22. In the first phase T21, the first light-emitting control module 212 is turned off under the control of the first light-emitting control signal Emit1, and the second light-emitting control module 213 is turned off under the control of the second light-emitting control signal Emit2. In the second phase T22, the first light-emitting control module 212 is turned off under the control of the first light-emitting control signal Emit1, and the second light-emitting control module 213 is turned on under the control of the second light-emitting control signal Emit2. That is, in the non-light-emitting phase T2, at least one of the first light-emitting control module 212 and the second light-emitting control module 213 is in the off state. At this time, no driving current is supplied to the light-emitting element 31, and the light-emitting element 31 does not emit light. By setting the non-light-emitting phase T2 in one frame of the display panel, the duration of light emission in one frame of the display panel can be adjusted. That is, the duration of the non-light-emitting phase T2 in one frame of the display panel increases, thereby reducing the duration of the light-emitting phase T1 in one frame of the display panel. This allows for adjustment of the brightness of the displayed image, which is beneficial to improving the display effect.

[0039] When at least one of the first light-emitting control module 212 and the second light-emitting control module 213 is in the off state, no driving current can be supplied to the light-emitting element 31, and therefore the light-emitting element 31 does not emit light. When the first light-emitting control module 212 and the second light-emitting control module 213 are in the on state, the driving current generated by the driving module 211 can be supplied to the light-emitting element 31, and therefore the light-emitting element 31 emits light. In the initial stage of light emission from the light-emitting element 31, there is a brightness increase process, and the rate of brightness increase is related to the bias state of the driving transistor M1 in the driving module 211.

[0040] In the non-light-emitting stage T2, during the second stage T22, the first light-emitting control module 212 is turned off under the control of the first light-emitting control signal Emit1, and the second light-emitting control module 213 is turned on under the control of the second light-emitting control signal Emit2. At this time, the potential of the third node N3 is pulled down by the potential of the fourth node N4. Since the driving module 211 is turned on, the potential of the second node N2 is correspondingly pulled down by the potential of the third node N3. At this time, the potential of the second node N2 is less than the potential of the first power signal PVDD, and the difference between the potential of the second node N2 and the potential of the first power signal PVDD is large. At the end of the second stage T22, the first light-emitting control module 212 is turned on under the control of the first light-emitting control signal Emit1, and the first power signal PVDD is instantaneously charged into the second node N2, which can bias the driving transistor M1 with a high voltage, so that the electrical properties of the driving transistor M1 are restored. This optimizes the rise rate of the light-emitting element 31's initial light-emitting brightness during the light-emitting stage T1, thereby improving the technical problem of image flickering in the prior art.

[0041] It should be noted that, Figure 3 An exemplary illustration shows a pixel circuit 21 in the display panel that is a 7T1C pixel circuit. In other embodiments of the present invention, the pixel circuit 21 in the display panel may also be other types of pixel circuits, which will not be described in detail here.

[0042] Continue to refer to Figure 4 In some optional embodiments, the period from the end of the current first stage T21 to the start of the next first stage T21 includes at least one second stage T22.

[0043] Specifically, at least one second stage T22 is set between two adjacent first stages T21, thereby enabling a high-voltage bias to be applied to the driving transistor M1. For example, when a second stage T22 is set between two adjacent first stages T21, that is, after the end of the current first stage T21, there is a light-emitting stage T1; after the end of that light-emitting stage T1, there is a second stage T22; after the end of that second stage T22, there is another light-emitting stage T1; and after the end of that light-emitting stage T1, there is another first stage T21. Of course, Figure 3 The example shown only illustrates a second stage T22 between two adjacent first stages T21. In other embodiments of the present invention, two or more second stages T22 may also be set between two adjacent first stages T21, which can be set according to the display effect. The present invention will not elaborate on them here.

[0044] It should be noted that, Figure 4The example illustrates a period from the end of the current first stage T21 to the start of the next first stage T21, including a second stage T22. Of course, in other embodiments of the invention, the period from the end of the current first stage T21 to the start of the next first stage T21 may include two or more second stages T22. For example, refer to... Figure 5 , Figure 5 This invention provides another driving timing diagram. During the period from the end of the current first stage T21 to the start of the next first stage T21, two second stages T22 may be included. Specifically, when there are two or more second stages T22 during the period from the end of the current first stage T21 to the start of the next first stage T21, the driving transistor M1 can be biased with high voltage multiple times to improve the electrical recovery effect of the driving transistor M1. It is understood that the number of second stages T22 during the period from the end of the current first stage T21 to the start of the next first stage T21 can be set according to the display effect required by the display panel; this invention does not specifically limit this.

[0045] Continue to refer to Figure 4 In some alternative embodiments, the duration of the second stage T22 is shorter than the duration of the light emission stage T1.

[0046] Specifically, by setting a non-emissive phase T2 within a frame of the display panel, the duration of the luminous phase within that frame can be adjusted. That is, increasing the duration of the non-emissive phase T2 reduces the duration of the luminous phase T1, thereby adjusting the brightness of the displayed image. An excessively long non-emissive phase T2 will result in insufficient brightness of the displayed image. In this embodiment, the non-emissive phase T2 includes a first phase T21 and a second phase T22. The duration of the second phase T22 is W2, and the duration of the luminous phase T1 is W4. W2 is less than W4, meaning the duration of the second phase T22 can be less than the duration of the luminous phase T1. This means that while setting the second phase T22 to apply a high voltage bias to the driving transistor M1, the impact of the second phase T22 on the brightness of the displayed image is reduced.

[0047] It is understood that the duration of the non-light-emitting phase T2 and the duration of the light-emitting phase T1 can be specifically adjusted based on the target brightness of the display screen, which will not be elaborated upon here.

[0048] In some optional embodiments, the duration of the first stage T21 is W1, the duration of the second stage T22 is W2, and the duration of the non-luminescent stage is L1, wherein W1 / L1 ≥ W2 / L1, that is, in the non-luminescent stage, the duration of the second stage is less than or equal to the duration of the first stage. (Continue to refer to...) Figure 4 The duration of the first stage T21 is W1, the duration of the second stage T22 is W2, and the duration of the non-light-emitting stage is L1, where W1 / L1 > W2 / L1. That is, in the non-light-emitting stage, the duration of the second stage T22 is shorter than the duration of the first stage T21. In the prior art, only the first stage T21 is set within one frame of the display panel, without setting the second stage T22. That is, in the prior art, the brightness of the displayed image is adjusted based on the duration of the first stage T21. In this embodiment of the invention, the setting of the second stage T22 enables a high-voltage bias on the driving transistor M1. By setting the duration of the second stage T22 to be shorter than the duration of the first stage T21, i.e., a shorter duration of the second stage T22, the impact of the second stage T22 setting on the brightness of the displayed image on the display panel is reduced while still achieving a high-voltage bias on the driving transistor M1, thus facilitating the adjustment of the brightness of the displayed image.

[0049] Figure 6 This is another driving timing diagram provided by the present invention, see reference. Figure 6 The duration of the first stage T21 is W1, the duration of the second stage T22 is W2, and the duration of the non-emitting stage is L1. Where W1 / L1 = W2 / L1, meaning that in the non-emitting stage, the duration of the second stage T22 is equal to the duration of the first stage T21. This means that the invalid pulse width of the first emission control signal Emit1 in the second stage T22 is approximately the same as its invalid pulse width in the first stage T21. Therefore, compared to existing technologies, only the invalid pulse frequency of the first emission control signal Emit1 needs to be adjusted to achieve the setting of the second stage T22, which helps to reduce the difficulty of setting the first emission control signal Emit1.

[0050] Continue to refer to Figure 6 In some optional embodiments, the duration of the second stage T22 is W2, W2 = n * H, where n is an integer greater than or equal to 1, H is the single-line time, H = 1 / (N × f), f is the base frequency, and N is the number of pixel rows. Therefore, the invalid pulse width of the first light-emitting control signal Emit1 in the second stage T22 meets the minimum pulse width requirement of the shift register, thus enabling the first light-emitting control signal Emit1 provided to the pixel circuit 21 through the shift register to have invalid pulses in the second stage T22.

[0051] The fundamental frequency can be equal to the number of times the data signal Vdata is written into the gate of the driving transistor M1 in the pixel circuit 21 within 1 second.

[0052] Optionally, the base frequency is usually 30-120Hz, which is generally the refresh rate when browsing non-video web pages.

[0053] Continue to refer to Figure 3 In some optional embodiments, the driving module 211 includes a driving transistor M1, the gate of the driving transistor M1 is electrically connected to the first node N1, the source of the driving transistor M1 is electrically connected to the second node N2, and the drain of the driving transistor M1 is electrically connected to the third node N3.

[0054] The pixel circuit 21 also includes a data writing module 214, a compensation module 215, and a reset module 216. The data writing module 214 provides a data signal, the compensation module 215 compensates for the threshold voltage of the driving transistor M1, and the reset module 216 provides a reset signal to the gate of the driving transistor M1.

[0055] Specifically, the control terminal of the reset module 216 is electrically connected to the first control signal S1, the first terminal of the reset module 216 is electrically connected to the reset signal Vref, and the second terminal of the reset module 216 is electrically connected to the gate of the driving transistor M1. The control terminal of the data writing module 214 is electrically connected to the second control signal S2, the first terminal of the data writing module 214 is electrically connected to the data signal Vdata, and the second terminal of the data writing module 214 is electrically connected to the source of the driving transistor M1. The control terminal of the compensation module 215 is electrically connected to the second control signal S2, the first terminal of the compensation module 215 is electrically connected to the drain of the driving transistor M1, and the second terminal of the compensation module 215 is electrically connected to the gate of the driving transistor M1.

[0056] Figure 7 This is another driving timing diagram provided by the present invention, see reference. Figure 3 and Figure 7 The first stage T21 includes a signal adjustment stage t1. In the signal adjustment stage t1, the gate of the driving transistor M1 receives a preset signal and adjusts the gate potential of the driving transistor M1. The signal adjustment stage t1 includes M sub-signal adjustment stages t11, where M is an integer greater than or equal to 1.

[0057] Continue to refer to Figure 3 and Figure 7In some optional embodiments, during at least one sub-signal adjustment phase t11, the reset module 216 is activated, writing a reset signal Vref to the gate of the driving transistor M1. This sub-signal adjustment phase t11 occurs before the data writing module 214 is activated. Specifically, the control terminal of the reset module 216 is activated under the control of the first control signal S1, providing the reset signal Vref to the gate of the driving transistor M1 to reset the gate of the driving transistor M1. This ensures that in another sub-signal adjustment phase t11, the data writing module 214 is activated and can provide an accurate data signal Vdata to the gate of the driving transistor M1.

[0058] refer to Figure 3 and Figure 7 In some alternative embodiments, during at least one sub-signal adjustment stage t11, the data writing module 214 is turned on and provides a data signal Vdata to the gate of the driving transistor M1, thereby realizing the writing of the data signal Vdata to the gate of the driving transistor M1.

[0059] Specifically, during at least one sub-signal adjustment stage t11, the data writing module 214 is activated under the control of the second control signal S2. The data writing module 214 writes the data signal Vdata to the source of the driving transistor M1, turning on the driving transistor M1 and providing the signal from the source of the driving transistor M1 to its drain. The compensation module 215 is activated under the control of the second control signal S2, providing the signal from the drain of the driving transistor M1 to its gate. Subsequently, during the light emission stage T1, the first light emission control module 212 is activated under the control of the first light emission control signal Emit1, and the second light emission control module 213 is activated under the control of the second light emission control signal Emit2, thereby providing the driving current generated by the driving transistor M1 to the light-emitting element 31.

[0060] Continue to refer to Figure 3 and Figure 7 In some alternative embodiments, the signal adjustment phase t1 is located before the start time of the second phase T22 within one frame of the display panel.

[0061] Specifically, in at least one sub-signal adjustment stage t11 of the signal adjustment stage t1, the reset module 216 is turned on and writes a reset signal Vref to the gate of the driving transistor M1, thereby affecting the bias state of the driving transistor M1. This affects the rate of increase of the initial luminous brightness of the light-emitting element 31 in the light-emitting stage T1 after the end of the signal adjustment stage t1, resulting in a slower rate of increase of the initial luminous brightness of the light-emitting element 31 in the light-emitting stage T1 after the end of the signal adjustment stage t1.

[0062] Within one frame of the display panel, the signal adjustment phase t1 occurs before the start of the second phase T22. That is, before the start of the second phase T22, at least one sub-signal adjustment phase t11 can be set. In this sub-signal adjustment phase t11, the reset module 216 is activated, writing a reset signal Vref to the gate of the driving transistor M1, which affects the bias state of the driving transistor M1. After the end of this signal adjustment phase t1, the second phase T22 is set. In the second phase T22, the first light-emitting control module 212 is turned off under the control of the first light-emitting control signal Emit1, and the second light-emitting control module 213 is turned on under the control of the second light-emitting control signal Emit2. At this time, the potential of the third node N3 is pulled low by the potential of the fourth node N4. Since the driving module 211 is turned on, the potential of the second node N2 is correspondingly pulled low by the potential of the third node N3. At this time, the potential of the second node N2 is less than the potential of the first power signal PVDD, and the difference between the potential of the second node N2 and the potential of the first power signal PVDD is large. At the end of the second stage T22, the first light-emitting control module 212 is activated under the control of the first light-emitting control signal Emit1. The first power signal PVDD is instantaneously charged into the second node N2, thereby biasing the driving transistor M1 with a high voltage. This restores the electrical properties of the driving transistor M1 to its original state, effectively slowing down the initial rate of increase in brightness of the light-emitting element 31 in the light-emitting stage T1 after the end of the second stage T22. This makes the rate of increase in brightness of the light-emitting element 31 in the initial stage of light-emitting stage T1 after the end of the signal adjustment stage t1 and the light-emitting stage T1 after the end of the second stage T22 tend to be the same, thus improving the technical problem of image flickering in the prior art.

[0063] Continue to refer to Figure 3 and Figure 7 In some alternative embodiments, the first stage T21 includes a dimming stage D1, in which the data writing module 214 is turned off and the gate of the driving transistor M1 maintains the potential of the previous stage.

[0064] Specifically, the first stage T21 includes a dimming stage D1. In the dimming stage D1, the first light-emitting control module 212 is turned off under the control of the first light-emitting control signal Emit1, and the second light-emitting control module 213 is turned off under the control of the second light-emitting control signal Emit2. At this time, no driving current is supplied to the light-emitting element 31, and the light-emitting element 31 does not emit light. Also in the dimming stage D1, the data writing module 214 is turned off, and no data signal Vdata is written to the source of the driving transistor M1. Furthermore, the compensation module 215 is turned off, and the gate of the driving transistor M1 maintains the potential of the previous stage, generating a driving current under the potential control of the previous light-emitting stage T1. This ensures that the light-emitting brightness of the light-emitting element 31 is the same in each light-emitting stage T1.

[0065] By setting a dimming stage D1 within one frame of the display panel, the duration of the light-emitting stage T1 within that frame can be adjusted. Specifically, increasing the duration of the dimming stage D1 reduces the duration of the light-emitting stage T1, thereby adjusting the brightness of the displayed image and improving display quality. Optionally, one frame of the display panel may include multiple dimming stages D1 to adjust the brightness of the displayed image. It should be noted that... Figure 7 The illustration only shows two dimming stages D1. This embodiment of the invention does not limit the display panel frame time to include two dimming stages D1. For example, the number of dimming stages D1 can be set according to the specific time of a frame of the display panel. This invention does not make any specific limitation in this regard.

[0066] Figure 8 This is another driving timing diagram provided by the present invention, see reference. Figure 3 and Figure 8 In some optional embodiments, the non-light-emitting stage T2 further includes a third stage T23, in which the first light-emitting control module 212 is turned on and the second light-emitting control module 213 is turned off; wherein, the end time of the first stage T21 is the same as the start time of the third stage T23.

[0067] Specifically, in the third stage T23, the first light-emitting control module 212 is turned on under the control of the first light-emitting control signal Emit1, and the second light-emitting control module 213 is turned off under the control of the second light-emitting control signal Emit2. There is a parasitic capacitance between the signal line used to transmit the first light-emitting control signal Emit1 and the second node N2. The end time of the first stage T21 is the same as the start time of the third stage T23. Therefore, at the end time of the first stage T21 and the start time of the third stage T23, the first light-emitting control signal Emit1 changes from an invalid pulse signal to an effective pulse signal. Correspondingly, the potential of the second node N2 is coupled, and at this time, the potential of the second node N2 is different from the potential of the first power supply signal PVDD. In the third stage T23, the first light-emitting control module 212 is turned on under the control of the first light-emitting control signal Emit1, and the first power signal PVDD is instantaneously charged into the second node N2, thereby biasing the driving transistor M1 with a high voltage, so that the electrical properties of the driving transistor M1 are restored to the original state. This optimizes the initial light-emitting brightness rise rate of the light-emitting element 31 in the light-emitting stage T1 after the third stage T23, so as to improve the technical problem of image flickering in the prior art.

[0068] Figure 9 Is with Figure 8 The simulation diagram corresponding to the driving timing shown is for reference. Figure 3 , Figure 8 , Figure 9 According to Table 1, in this embodiment of the invention, in the third stage T23, the first light-emitting control module 212 is turned on under the control of the first light-emitting control signal Emit1, and the second light-emitting control module 213 is turned off under the control of the second light-emitting control signal Emit2. There is a parasitic capacitance between the signal line used to transmit the first light-emitting control signal Emit1 and the second node N2. The end time of the first stage T21 is the same as the start time of the third stage T23. Therefore, at the end time of the first stage T21 and the start time of the third stage T23, the first light-emitting control signal Emit1 changes from an invalid pulse signal to an effective pulse signal. Correspondingly, the potential of the second node N2 is coupled. At this time, the potential of the second node N2 is pulled down to 4.3V. In the third stage T23, the first light-emitting control module 212 is turned on under the control of the first light-emitting control signal Emit1, and the first power supply signal PVDD is instantaneously charged into the second node N2. The potential of the second node N2 is 4.6V, thereby allowing a high-voltage bias to be applied to the driving transistor M1.

[0069] In the second stage T22, the first light-emitting control module 212 is turned off under the control of the first light-emitting control signal Emit1, and the second light-emitting control module 213 is turned on under the control of the second light-emitting control signal Emit2. At this time, the potential of the third node N3 is pulled low by the potential of the fourth node N4. Since the driving module 211 is turned on, the potential of the second node N2 is correspondingly pulled low to 2.8V by the potential of the third node N3. At the end of the second stage T22, the first light-emitting control module 212 is turned on under the control of the first light-emitting control signal Emit1, and the first power supply signal PVDD is instantaneously charged into the second node N2, and the potential of the second node N2 is 4.6V, thereby biasing the driving transistor M1 with a high voltage.

[0070] Table 1

[0071]

[0072] Figure 10 This is a comparison chart of brightness curves when the display panel of this invention is working and when a display panel in the prior art is working. The horizontal axis represents time, and the vertical axis represents brightness. (Reference) Figure 10 By using the driving timing provided by this invention, namely by setting the second stage and the third stage, a high voltage bias can be achieved on the driving transistor. Compared with the prior art, the difference between the initial brightness rise rate of the light-emitting elements in each light-emitting stage in this invention is smaller, which effectively improves the technical problem of image flickering in the prior art.

[0073] Continue to refer to Figure 3 and Figure 8 In some alternative embodiments, at least one light-emitting stage T1 is included between the second stage T22 and the third stage T23.

[0074] Specifically, at least one light-emitting stage T1 is included between the second stage T22 and the third stage T23, thus avoiding the start of the second stage T22 occurring at the end of the third stage T23. Because in the third stage T23, the first light-emitting control module 212 is turned on under the control of the first light-emitting control signal Emit1, and the first power signal PVDD instantaneously charges the second node N2, causing a momentary on-state current to flow through the driving transistor M1. If the start of the second stage T22 occurs at the end of the third stage T23, and the second light-emitting control module 213 is turned on under the control of the second light-emitting control signal Emit2 at the start of the second stage T22, the momentary on-state current generated by the driving transistor M1 will flow to the light-emitting element 31, affecting the display effect of the display panel. (Continue to refer to...) Figure 3 and Figure 8In some optional embodiments, the duration of the third stage T23 is W3, W3 = m * H, where 1 ≤ m ≤ 3, H is the single-line time, H = 1 / (N × f), f is the base frequency, and N is the number of pixel rows. The invalid pulse width of the conventional second light-emitting control signal Emit2 is 4H. When the duration of the third stage T23 is set to 1-3H, the corresponding duration of the first light-emitting control signal Emit1 in the first stage T21 is greater than or equal to 1H. Thus, while setting the third stage T23, the invalid pulse width of the first light-emitting control signal Emit1 in the first stage T21 meets the minimum pulse width requirement of the shift register, thereby ensuring that the first light-emitting control signal Emit1 provided to the pixel circuit 21 through the shift register has an invalid pulse in the first stage T21.

[0075] The fundamental frequency can be equal to the number of times the data signal Vdata is written into the gate of the driving transistor M1 in the pixel circuit 21 within 1 second.

[0076] Optionally, the base frequency is usually 30-120Hz, which is generally the refresh rate when browsing non-video web pages.

[0077] Figure 11 This is a plan view of a display panel provided by the present invention, for reference. Figure 2 and Figure 11 In some optional embodiments, the display panel further includes a first shift register VSR1 and a second shift register VSR2, which are located on opposite sides of the display panel. The first shift register VSR1 provides a first light emission control signal Emit1 to the pixel circuit 21, and the second shift register VSR2 provides a second light emission control signal Emit2 to the pixel circuit 21.

[0078] Specifically, in the prior art, because the effective pulse widths of the first control signal S1 and the second control signal S2 are relatively small, in order to reduce the signal delay of the first control signal S1 and the second control signal S2 and improve display uniformity, the first shift register VSR1 and the second shift register VSR2 are usually set to simultaneously provide the first control signal S1 and the second control signal S2 to the pixel circuit 21. The first shift register VSR1 can be used to provide the first light-emitting control signal Emit1 to the pixel circuit 21 through the first light-emitting control signal E1, and the second shift register VSR2 can be used to provide the second light-emitting control signal Emit2 to the pixel circuit 21 through the second light-emitting control signal E2. This eliminates the need for additional shift registers and helps to reduce the bezel area.

[0079] Continue to refer to Figure 2 and Figure 6In some optional embodiments, the duration from the start time of the second stage T22 to the start time of the invalid pulse of the adjacent first light emission control signal Emit1 is equal to the duration from the start time of the second stage T22 to the start time of the invalid pulse of the adjacent second light emission control signal Emit2. That is, at the start time of the first stage T21, the start time of the invalid pulse of the first light emission control signal Emit1 is the same as the start time of the invalid pulse of the second light emission control signal Emit2.

[0080] Since at least one effective pulse exists in the first control signal S1 and at least one effective pulse exists in the second control signal S2 in at least one first stage T21, based on the limitation of reducing the effective pulses in the first control signal S1 and the effective pulses in the second control signal S2, the start time of the invalid pulse of the first light emission control signal Emit1 can be set to be the same as the start time of the invalid pulse of the second light emission control signal Emit2 at the start time of the first stage T21.

[0081] Of course, in other embodiments of the present invention, the start time of the first stage T21 may also be set to the start time of the invalid pulse of the first light emission control signal Emit1 or the start time of the invalid pulse of the second light emission control signal Emit2. That is, the start time of the invalid pulse of the first light emission control signal Emit1 and the start time of the invalid pulse of the second light emission control signal Emit2 may be different. The present invention will not elaborate further here.

[0082] Continue to refer to Figure 3 and Figure 8 In some alternative embodiments, the invalid pulse width of the first light emission control signal Emit1 is smaller than the invalid pulse width of the second light emission control signal Emit1.

[0083] Specifically, the width of an invalid pulse in the first light-emitting control signal Emit1 is less than the width of an invalid pulse in the second light-emitting control signal Emit2. Therefore, in the first stage T21, when the start time of the invalid pulse in the first light-emitting control signal Emit1 is the same as the start time of the invalid pulse in the second light-emitting control signal Emit2, the end time of the invalid pulse in the first light-emitting control signal Emit1 will be earlier than the end time of the invalid pulse in the second light-emitting control signal Emit2. At the end time of the invalid pulse in the first light-emitting control signal Emit1, the first light-emitting control signal Emit1 changes from an invalid pulse signal to a valid pulse signal. Correspondingly, the potential of the second node N2 is coupled, and at this time, the potential of the second node N2 is different from the potential of the first power supply signal PVDD. At the end of the invalid pulse of the second light emission control signal Emit2, that is, at the beginning of the valid pulse of the second light emission control signal Emit2, the first light emission control module 212 is turned on under the control of the first light emission control signal Emit1. The first power supply signal PVDD is instantaneously charged into the second node N2, thereby biasing the driving transistor M1 with a high voltage, so that the electrical properties of the driving transistor M1 are restored to the original state. This optimizes the initial light emission brightness rise rate of the light emission element 31 in the subsequent light emission stage T1, thereby improving the technical problem of image flickering in the prior art.

[0084] Continue to refer to Figure 3 and Figure 8 In some alternative embodiments, the effective pulse width of the first light emission control signal Emit1 is smaller than the effective pulse width of the second light emission control signal Emit2.

[0085] Specifically, in the first stage T21, when the start time of the invalid pulse of the first light-emitting control signal Emit1 is the same as the start time of the invalid pulse of the second light-emitting control signal Emit2, in the light-emitting stage T1 before the first stage T21, the end time of the valid pulse of the first light-emitting control signal Emit1 is the same as the end time of the valid pulse of the second light-emitting control signal Emit2. Since the width of a valid pulse of the first light-emitting control signal Emit1 is smaller than the width of a valid pulse of the second light-emitting control signal Emit2, there is at least one stage in which the first light-emitting control signal Emit1 is an invalid pulse and the second light-emitting control signal Emit2 is a valid pulse, that is, there is at least one second stage T22. The setting of the second stage T22 can bias the driving transistor M1 with a high voltage, so that the electrical properties of the driving transistor M1 are restored to the original state, thereby optimizing the rise rate of the brightness of the light-emitting element 31 in the initial stage of light emission in the light-emitting stage T1, so as to improve the technical problem of image flickering in the prior art.

[0086] Continue to refer to Figure 3 and Figure 8 In some optional embodiments, within one frame of the display panel, the first light emission control signal Emit1 includes i invalid pulses and the second light emission control signal Emit2 includes j invalid pulses, where i > j and i is an integer multiple of j.

[0087] Specifically, within one frame of the display panel, the number of invalid pulses in the first light-emitting control signal Emit1 is greater than the number of invalid pulses in the second light-emitting control signal Emit2, meaning the frequency of invalid pulses in the first light-emitting control signal Emit1 is greater than the frequency of invalid pulses in the second light-emitting control signal Emit2. Since in the first stage T21, when the start time of the invalid pulses in the first light-emitting control signal Emit1 is the same as the start time of the invalid pulses in the second light-emitting control signal Emit2, there must be at least one stage between two adjacent first stages T21 where the first light-emitting control signal Emit1 is an invalid pulse and the second light-emitting control signal Emit2 is a valid pulse. This means there is at least one second stage T22. Setting the second stage T22 can bias the driving transistor M1 with a high voltage, restoring the electrical properties of the driving transistor M1 to their original state. This optimizes the initial brightness increase rate of the light-emitting element 31 during the light-emitting stage T1, thereby improving the technical problem of image flickering in the prior art.

[0088] Meanwhile, since there is at least one second stage T22 between two adjacent first stages T21, and within one frame of the display panel, the number of invalid pulses in the first light emission control signal Emit1 is an integer multiple of the number of invalid pulses in the second light emission control signal Emit2, that is, the number of second stages T22 between any two adjacent first stages T21 is the same, that is, the number of invalid pulses in the first light emission control signal Emit1 between any two adjacent invalid pulses in the second light emission control signal Emit2 is the same, which helps to reduce the difficulty of setting the first light emission control signal Emit1.

[0089] In some alternative embodiments, please refer to Figure 12 , Figure 12 This is a plan view of a display device provided by the present invention. The display device 1000 provided in this embodiment includes the display panel 100 provided in the above embodiment of the present invention. Figure 12This embodiment uses a mobile phone as an example to illustrate the display device 1000. It is understood that the display device 1000 provided in this embodiment can also be other display devices 1000 with display functions, such as computers, televisions, and in-vehicle display devices. This invention does not impose specific limitations on these. The display device 1000 provided in this embodiment has the beneficial effects of the display panel 100 provided in this embodiment. For details, please refer to the specific descriptions of the display panel 100 in the above embodiments; these will not be repeated here.

[0090] As can be seen from the above embodiments, the display panel and display device provided by the present invention achieve at least the following beneficial effects:

[0091] In the display panel provided by this invention, the non-light-emitting stage includes a second stage. In the second stage, the first light-emitting control module is turned off under the control of the first light-emitting control signal, and the second light-emitting control module is turned on under the control of the second light-emitting control signal. At this time, the potential of the third node is pulled down by the potential of the fourth node. Since the driving module is turned on, the potential of the second node is correspondingly pulled down by the potential of the third node. At this time, the potential of the second node is less than the potential of the first power signal, and the difference between the potential of the second node and the potential of the first power signal is large. At the end of the second stage, the first light-emitting control module is turned on under the control of the first light-emitting control signal, and the first power signal is instantaneously charged into the second node, which can bias the driving transistor with a high voltage, so that the electrical properties of the driving transistor are restored. This optimizes the initial rise rate of the luminous brightness of the light-emitting element during the light-emitting stage, thereby improving the technical problem of image flickering in the prior art.

[0092] While specific embodiments of the invention have been described in detail by way of examples, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. Those skilled in the art should understand that modifications can be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. A display panel, characterized in that, include: A pixel circuit and a light-emitting element, wherein the pixel circuit is used to drive the light-emitting element to emit light; The pixel circuit includes a driving module, a first light-emitting control module, and a second light-emitting control module. The first terminal of the first light-emitting control module is electrically connected to the first power signal terminal, and the second terminal of the first light-emitting control module is electrically connected to the driving module. The first light-emitting control module responds to the first light-emitting control signal and provides the first power signal to the driving module. The first end of the second light-emitting control module is electrically connected to the driving module, and the second end of the second light-emitting control module is electrically connected to the light-emitting element. The second light-emitting control module responds to the second light-emitting control signal by providing the signal output by the driving module to the light-emitting element. One frame of the display panel includes a light-emitting phase and a non-light-emitting phase. The non-light-emitting phase includes a first phase and a second phase. In the first phase, the first light-emitting control module is turned off and the second light-emitting control module is turned off. In the second phase, the first light-emitting control module is turned off and the second light-emitting control module is turned on. The non-light-emitting stage also includes a third stage, in which the first light-emitting control module is turned on and the second light-emitting control module is turned off; wherein, the end time of the first stage is the same as the start time of the third stage.

2. The display panel according to claim 1, characterized in that, The period from the end of the current first phase to the start of the next first phase includes at least one second phase.

3. The display panel according to claim 1, characterized in that, The duration of the second stage is shorter than the duration of the light-emitting stage.

4. The display panel according to claim 1, characterized in that, The duration of the first stage is W1, the duration of the second stage is W2, and the duration of the non-luminescent stage is L1, wherein W1 / L1 ≥ W2 / L1.

5. The display panel according to claim 1, characterized in that, The duration of the second stage is W2, where W2 = n H, where n is an integer greater than or equal to 1, H is the single-line time, H=1 / (N×f), f is the basic frequency, and N is the number of pixel rows.

6. The display panel according to claim 1, characterized in that, The driving module includes a driving transistor; The first stage includes a signal adjustment stage, in which the gate of the driving transistor receives a preset signal to adjust the gate potential of the driving transistor. The signal adjustment stage includes M sub-signal adjustment stages, where M is an integer greater than or equal to 1.

7. The display panel according to claim 6, characterized in that, Within one frame of the display panel, the signal adjustment phase occurs before the start of the second phase.

8. The display panel according to claim 6, characterized in that, The display panel also includes a data writing module, which is activated during at least one of the sub-signal adjustment phases and provides a data signal to the gate of the driving transistor.

9. The display panel according to claim 8, characterized in that, The first stage includes a dimming stage, in which the data writing module is turned off and the gate of the driving transistor maintains the potential of the previous stage.

10. The display panel according to claim 9, characterized in that, The display panel's frame time includes multiple dimming stages.

11. The display panel according to claim 1, characterized in that, At least one luminescent stage is included between the second stage and the third stage.

12. The display panel according to claim 1, characterized in that, The duration of the third stage is W3, where W3 = m H, where 1 ≤ m ≤ 3, H is the single-line time, H=1 / (N×f), f is the basic frequency, and N is the number of pixel rows.

13. The display panel according to claim 1, characterized in that, The display panel further includes a first shift register and a second shift register, which are located on opposite sides of the display panel. The first shift register provides the first light emission control signal to the pixel circuit, and the second shift register provides the second light emission control signal to the pixel circuit.

14. The display panel according to claim 1, characterized in that, The width of an invalid pulse in the first light emission control signal is less than the width of an invalid pulse in the second light emission control signal.

15. The display panel according to claim 1, characterized in that, The effective pulse width of the first light emission control signal is less than the effective pulse width of the second light emission control signal.

16. The display panel according to claim 1, characterized in that, Within one frame of the display panel, the first light emission control signal includes i invalid pulses, and the second light emission control signal includes j invalid pulses, where i > j, and i is an integer multiple of j.

17. A display device, characterized in that, Includes the display panel as described in any one of claims 1-16.

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