Clock pass-through apparatus, method, and optical transport network device
By dynamically adjusting the number of data replications through a clock pass-through device, the high cost caused by the large number of dedicated clock chips in OTN equipment is solved, clock frequency pass-through is achieved, equipment costs are reduced, and compatibility is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHINA TELECOM CORP LTD TECHNOLOGY INNOVATION CENTER
- Filing Date
- 2023-07-07
- Publication Date
- 2026-07-24
AI Technical Summary
Existing OTN equipment requires a large number of dedicated clock chips when carrying multiple SDH optical interfaces, which increases costs.
A clock pass-through device is adopted, which dynamically adjusts the number of data replications through an ingress rate statistics module, a buffer module, a clock determination module, and an egress rate control module to achieve clock frequency pass-through and reduce dependence on dedicated clock chips.
It reduces the cost of OTN devices, improves device compatibility and adaptability, reduces the number of dedicated clock chips used, and saves PCB area and power consumption.
Smart Images
Figure CN116827870B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of optical network technology, and in particular to a clock pass-through device, method and optical transport network equipment. Background Technology
[0002] In the field of optical fiber communication, the original SDH system has gradually evolved into the OTN technology system. The OTN optical transport network has the ability to carry multiple services such as Ethernet, SDH, and E1.
[0003] Because optical interfaces in SDH communication systems require clock frequency pass-through functionality, mainstream OTN equipment manufacturers currently use dedicated clock chips to provide a reference clock for the SERDES of the SDH optical interface, thereby enabling clock pass-through for the SDH interface. Since the source and destination of each SDH optical interface service are different, each SDH optical interface requires a dedicated clock chip to track the clock frequency of the service source. When the number of SDH optical interfaces is large, the number of dedicated clock chips required in the hardware system increases significantly, leading to a substantial increase in the cost of access layer OTN equipment. Summary of the Invention
[0004] One object of this disclosure is to provide a clock frequency pass-through function for optical interfaces, reducing reliance on dedicated clock chips and lowering the cost of OTN equipment.
[0005] According to one aspect of some embodiments of this disclosure, a clock pass-through device is proposed, comprising: an ingress rate statistics module configured to count the ingress rate of a data stream from a service source based on a local clock, and update the ingress rate according to a predetermined first frequency; a cache module configured to cache data of the data stream and determine the amount of cache space already occupied; a clock determination module configured to multiply the frequency of a local crystal oscillator as a reference clock to obtain a multiplied clock; and an egress rate control module configured to read the data cached by the cache module, and copy the cached data bit by bit based on the multiplied clock before outputting it, wherein the number of copies is dynamically adjusted according to the ingress rate and the amount of cache space already occupied.
[0006] In some embodiments, the outgoing rate control module is configured to: determine the value of the token bucket based on the amount of data read, the amount of cache space already occupied in the cache module, and the incoming rate obtained by the incoming rate statistics module; determine the number of replications based on the value of the token bucket, wherein: when the value of the token bucket is less than a predetermined low threshold, the number of replications is the first replication count; when the value of the token bucket is greater than a predetermined high threshold, the number of replications is the second replication count; when the value of the token bucket is less than or equal to the predetermined high threshold and greater than or equal to the predetermined low threshold, the number of replications is the initial replication count; the first replication count > the initial replication count > the second replication count.
[0007] In some embodiments, the first number of copies is 1 greater than the initial number of copies, and the second number of copies is 1 less than the initial number of copies.
[0008] In some embodiments, the exit rate control module is configured to: initialize the token bucket to a predetermined initial value; add the entry rate counted by the entry rate statistics module to the token bucket at a predetermined second frequency; decrease the value of the token bucket by a predetermined deduction value each time bit data is read from the cache module; and set the token bucket to the predetermined initial value if the amount of cache space already occupied is greater than a predetermined first threshold or less than a predetermined second threshold.
[0009] In some embodiments, the export rate control module is further configured to: if the amount of cached space occupied is greater than a predetermined first threshold, continuously read cached data until the amount of cached space occupied is a predetermined standard value; if the amount of cached space occupied is less than a predetermined second threshold, stop reading cached data until the amount of cached space occupied is a predetermined standard value.
[0010] In some embodiments, the device conforms to at least one of the following: the clock determination module is configured to operate in STM-64 mode; the data bus width between the clock determination module and the output rate control module is 32 bits; the input rate statistics module is configured to count the total amount of valid data sent to the write interface of the cache module within a predetermined time, obtain the average value after counting a predetermined number of times, and determine the input rate.
[0011] In some embodiments, the clock pass-through device operates in STM-1 mode, the cache module has a cache depth of 64, a bit width of 1 bit, an initial copy count of 63, and reads 1 bit of data from the cache module each time, with a predetermined deduction value of 1.
[0012] In some embodiments, the clock pass-through device operates in STM-4 mode, the cache module has a cache depth of 64, a bit width of 4 bits, an initial copy count of 15, and reads 4 bits of data at a time from the cache module, with a predetermined deduction value of 4.
[0013] In some embodiments, the device further includes a mode adjustment module configured to switch the operating mode of the clock pass-through device, the operating modes including STM-1 and STM-4.
[0014] In some embodiments, the clock determination module is a Serdes TX module, including an input interface, an output interface, a reference clock receiving interface, and a frequency multiplier clock output interface, wherein: the reference clock receiving interface is connected to a crystal oscillator and configured to acquire a reference clock; the frequency multiplier clock output interface is connected to the output rate control module and the buffer module and configured to output a frequency multiplier clock; the input interface is connected to the output rate control module and configured to acquire a copied data stream output by the output rate control module; the output interface is configured to output a data stream according to the operating mode of the clock pass-through device based on the data stream from the input interface.
[0015] In some embodiments, the cache module is a FIFO module, including a write-side clock interface, a read-side clock interface, a cache input interface, a cache output interface, and an output interface for the amount of cache space occupied. Specifically: the write-side clock interface is connected to the clock output interface of the OTN device and is configured to write the data stream into the cache based on the clock output by the OTN device; the read-side clock interface is connected to the frequency multiplier clock output interface of the clock determination module and is configured to output the cached data based on the frequency multiplier clock output by the clock determination module; the cache input interface is configured to receive the input data stream; the cache output interface is configured to output the cached data to the output rate control module; and the output interface for the amount of cache space occupied is configured to output the amount of cache space occupied to the output rate control module.
[0016] In some embodiments, the output rate control module includes: a frequency multiplier clock input interface, an occupied buffer space input interface, an input rate input interface, a buffer read interface, and a data output interface, wherein: the frequency multiplier clock input interface is connected to the frequency multiplier clock output interface of the clock determination module and is configured to receive the frequency multiplier clock; the occupied buffer space input interface is connected to the occupied buffer space output interface of the buffer module and is configured to obtain the amount of occupied buffer space; the input rate input interface is configured to be connected to the input rate statistics module and is configured to receive the input rate; the buffer read interface is configured to be connected to the buffer output interface of the buffer module and is configured to read the data cached in the buffer module; and the data output interface is connected to the input interface of the clock determination module and is configured to output the bit-by-bit copied data to the clock determination module.
[0017] According to one aspect of some embodiments of this disclosure, an optical transport network device is proposed, including any of the clock pass-through devices described above.
[0018] According to one aspect of some embodiments of this disclosure, a clock pass-through method is proposed, comprising: statistically analyzing the ingress rate of a data stream from a service source based on a local clock, and updating the ingress rate according to a predetermined first frequency; caching data from the data stream and determining the amount of cached space already occupied; multiplying the frequency of a local crystal oscillator as a reference clock to obtain a multiplied clock; and reading data cached by a caching module, and copying the cached data bit by bit based on the multiplied clock before outputting it, wherein the number of copies is dynamically adjusted according to the ingress rate and the amount of cached space already occupied.
[0019] In some embodiments, reading data cached by the caching module and copying the cached data bit by bit based on a frequency multiplier clock and then outputting it includes: determining the value of the token bucket based on the amount of data read, the amount of cache space already occupied in the caching module, and the entry rate obtained by the entry rate statistics module; determining the number of copies based on the value of the token bucket, wherein: when the value of the token bucket is less than a predetermined low threshold, the number of copies is the first copy number; when the value of the token bucket is greater than a predetermined high threshold, the number of copies is the second copy number; when the value of the token bucket is less than or equal to the predetermined high threshold and greater than or equal to the predetermined low threshold, the number of copies is the initial copy number; the first copy number > the initial copy number > the second copy number; and copying the cached data bit by bit based on the number of copies and then outputting it.
[0020] In some embodiments, determining the value of the token bucket based on the amount of data read, the amount of cache space already occupied in the cache module, and the entry rate obtained by the entry rate statistics module includes: initializing the token bucket to a predetermined initial value; adding the entry rate counted by the entry rate statistics module to the token bucket at a predetermined second frequency; decreasing the value of the token bucket by a predetermined deduction value each time bit data is read from the cache module; and setting the token bucket to the predetermined initial value if the amount of cache space already occupied is greater than a predetermined first threshold or less than a predetermined second threshold.
[0021] In some embodiments, reading data cached by the cache module and copying the cached data bit by bit based on a frequency multiplier clock and then outputting it further includes: if the amount of cache space already occupied is greater than a predetermined first threshold, then continuously reading cached data until the amount of cache space already occupied is a predetermined standard value; if the amount of cache space already occupied is less than a predetermined second threshold, then stopping reading cached data until the amount of cache space already occupied is a predetermined standard value.
[0022] In some embodiments, the method further includes: switching the current operating mode, including STM-1 and STM-4. Attached Figure Description
[0023] The accompanying drawings, which are included to provide a further understanding of this disclosure and form part of this disclosure, illustrate exemplary embodiments of the present disclosure and are used to explain the disclosure, but do not constitute an undue limitation of the disclosure. In the drawings:
[0024] Figure 1 This is a schematic diagram of some embodiments of the clock transmission device disclosed herein.
[0025] Figure 2 These are schematic diagrams of other embodiments of the clock pass-through device of this disclosure.
[0026] Figures 3A-3C This is a schematic diagram of some embodiments of the buffer module in the clock pass-through device of this disclosure.
[0027] Figures 4A-4B This is a schematic diagram of some embodiments of the output rate control module in the clock pass-through device of this disclosure.
[0028] Figure 5 This is a schematic diagram of some embodiments of the clock determination module in the clock pass-through device of this disclosure.
[0029] Figure 6 This is a schematic diagram of some embodiments of the clock pass-through device of this disclosure for adjusting the service exit rate in STM-1 mode.
[0030] Figure 7 This is a schematic diagram of some embodiments of the optical transport network equipment disclosed herein.
[0031] Figure 8 This is a schematic diagram of some embodiments of uplink and downlink data transmission on an optical transport network according to the present disclosure.
[0032] Figure 9 This is a flowchart of some embodiments of the clock pass-through method disclosed herein. Detailed Implementation
[0033] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments.
[0034] Schematic diagrams of some embodiments of the clock pass-through device 10 disclosed herein are shown below. Figure 1 As shown.
[0035] The ingress rate statistics module 101 can count the ingress rate of the data stream from the service source based on the local clock and update the ingress rate according to a predetermined first frequency. In some embodiments, the ingress rate statistics module 101 counts the total amount of valid data sent to the write interface of the cache module within a predetermined time, and obtains the average value after a predetermined number of consecutive counts to determine the ingress rate. In some embodiments, the ingress rate statistics module 101 counts the ingress rate of the data stream from the service source in the current period at a predetermined period as the real-time ingress rate, and then takes the average of the ingress rates obtained in a predetermined number of consecutive periods to obtain the ingress rate, thereby avoiding the impact of accidental changes in the ingress rate on subsequent processing and improving the stability of the clock pass-through device. In some embodiments, the predetermined period can be 100ms, and the predetermined number of consecutive counts can be 16, that is, the ingress rate is updated once every 1600ms.
[0036] The cache module 102 can cache data from the data stream and determine the amount of cache space already occupied. In some embodiments, the cache module 102 is a FIFO (First Input First Output) memory. In some embodiments, when the clock pass-through device operates in STM-1 mode, the FIFO memory has a bit width of 1 bit; when the clock pass-through device operates in STM-4 mode, the FIFO memory has a bit width of 4 bits. In some embodiments, the cache module 102 can output the amount of cache space it has occupied.
[0037] The clock determination module 103 can multiply the local crystal oscillator as a reference clock to obtain a multiplied clock. In some embodiments, the clock determination module 103 can be a SerDes TX module, implemented by FPGA design tools. In some embodiments, the operating rate of the clock determination module 103 can be the rate corresponding to STM-64 mode, 9953.28 Mbps. In some embodiments, the bit width of the data bus connected to the clock determination module 103 and the output rate control module 104 can be 32 bits, then the clock frequency sent by the clock determination module 103 is 9953.28 / 32 = 311.04 MHz. In some embodiments, when the clock determination module 103 uses the local crystal oscillator as a reference clock, it obtains a multiplied clock by multiplying the frequency using the phase-locked loop inside the clock determination module 103, and uses the multiplied clock as the processing clock of the output rate control module 104 and the read-side clock of the cache module 102.
[0038] The output rate control module 104 can read the data cached by the cache module and copy the cached data bit by bit based on the frequency multiplication clock before outputting it. The number of copies is dynamically adjusted according to the input rate and the amount of cache space already occupied.
[0039] Such a device can copy the input data stream bit by bit based on a frequency multiplier clock and then output it. By changing the number of copies, the output rate can be finely adjusted to follow the input rate, reducing the dependence on a dedicated clock chip and helping to reduce the cost of OTN equipment.
[0040] In some embodiments, the exit rate control module 104 can determine the number of replications based on a token bucket mechanism. In some embodiments, the token bucket value can be determined based on the amount of data read, the amount of cache space already occupied in the cache module, and the entry rate obtained by the entry rate statistics module, and then the number of replications can be determined based on the token bucket value, wherein: when the token bucket value is less than a predetermined low threshold, the number of replications is the first replication count; when the token bucket value is greater than a predetermined high threshold, the number of replications is the second replication count; when the token bucket value is less than or equal to the predetermined high threshold and greater than or equal to the predetermined low threshold, the number of replications is the initial replication count; the first replication count > the initial replication count > the second replication count.
[0041] This method allows for the adjustment of the token bucket value based on the initial number of replications, the amount of data read, the ingress rate, and the amount of cached space already occupied. The number of replications is then adjusted based on the token bucket value, thus allowing for adjustment of the data stream's output rate. In some embodiments, the first replication count is one greater than the initial replication count, and the second replication count is one less than the initial replication count, thereby achieving a fine-tuned rate adjustment and improving the precision of the adjustment.
[0042] In some embodiments, when the clock pass-through device operates in STM-1 mode, the initial number of copies is 63 (i.e., 64 times per bit of data), then the first number of copies is 64 (i.e., 65 times per bit of data), and the second number of copies is 62 (i.e., 63 times per bit of data), achieving an adjustment with a precision of one-sixtieth of a bit. When the clock pass-through device operates in STM-1 mode, the initial number of copies is 15 (i.e., 16 times per bit of data), then the first number of copies is 16 (i.e., 17 times per bit of data), and the second number of copies is 14 (i.e., 15 times per bit of data), achieving an adjustment with a precision of one-sixteenth of a bit. Such a clock pass-through device can adjust the output rate with a precision of one-sixtieth of a bit or one-sixteenth of a bit in the corresponding operating mode, thereby achieving fine adjustments to the data transmission speed and reducing data jitter while achieving clock pass-through.
[0043] In some embodiments, the token bucket adjustment operation of the exit rate control module may include initializing the token bucket to a predetermined initial value, thereby providing a reference point for the control of the token bucket, which helps to determine the changes in the entry rate based on the absolute value of the token bucket.
[0044] In some embodiments, the adjustment operation of the token bucket by the exit rate control module may include: adding the entry rate counted by the entry rate statistics module to the token bucket at a predetermined second frequency, so that the entry rate can be intuitively reflected in the token bucket, and also facilitates the injection and deduction balance when deducting tokens.
[0045] In some embodiments, the token bucket adjustment operation of the outgoing rate control module may further include reducing the token bucket value by a predetermined deduction value each time bit data is read from the buffer module, so that the read and output data are visually reflected in the token bucket. When the token bucket value decreases below a predetermined low threshold, the output data transmission rate needs to be reduced by increasing the number of replications, thereby reducing the number of times information is output. Such a device can improve the sensitivity to changes in the incoming rate and improve the timeliness of the outgoing rate adjustment. In addition, the token injection rule is to inject the actual input bits of the SDH data stream at regular intervals; the token deduction rule is to deduct the corresponding tokens for every 1 bit (or 4 bits) read from the FIFO, thus achieving a balance between token injection and deduction.
[0046] In some embodiments, the token bucket adjustment operation of the exit rate control module may further include setting the token bucket to a predetermined initial value if the amount of occupied cache space is greater than a predetermined first threshold or less than a predetermined second threshold. In some embodiments, if the amount of occupied cache space is greater than the predetermined first threshold, the exit rate control module continuously reads cached data until the amount of occupied cache space reaches a predetermined standard value; if the amount of occupied cache space is less than the predetermined second threshold, the exit rate control module stops reading cached data until the amount of occupied cache space reaches the predetermined standard value. Such a device can determine the magnitude of the exit rate relative to the entry rate based on the change in the amount of occupied cache space, and effectively adjust the remaining space of the cache module by stopping and continuously reading cached data, ensuring the balance of data volume between input and output, and improving the operational stability of the device.
[0047] In some embodiments, the clock pass-through device further includes a mode adjustment module capable of switching the operating mode of the clock pass-through device, including STM-1 and STM-4. Such a device can improve compatibility and adaptability of the clock pass-through device to different OTN devices or application scenarios, which is beneficial for its widespread application.
[0048] Schematic diagrams of other embodiments of the clock pass-through device disclosed herein are shown below. Figure 2 As shown.
[0049] Services from the source STM-1 or STM-4 optical interface are carried and transmitted through various mapping methods such as AMP, BMP, and GMP into the OTN network. Upon arrival at the destination, the services are demapped using the corresponding mapping method, and then the service flow enters the OTN network. Figure 2 The clock pass-through processing device shown performs the processing. In this device, the input rate statistics module 201 performs rate statistics on the input STM-1 / STM-4 service data stream. The service data stream is input and stored in the buffer module, such as... Figure 2 As shown, the cache module is a FIFO memory 202. The clock determination module is implemented through a Serdes TX 203 on the FPGA chip. The Serdes TX 203 obtains a multiplied clock CLK311M04 based on the reference clock Refclk generated by the crystal oscillator through frequency multiplication. The multiplied clock CLK311M04 is sent to the FIFO memory 202 and the output rate control module 204 as the output clock of the FIFO memory; the output rate control module 204 reads the data cached in the FIFO memory 202, copies it based on the multiplied clock, and sends it to the Serdes TX 203 through the Serdes TX high-speed interface.
[0050] The clock pass-through device in the above embodiments allows OTN equipment to achieve clock frequency pass-through functionality for multiple STM-1 and STM-4 rate optical interfaces without using dedicated clock chips, while ensuring the clock frequency offset requirements of the SDH interface. Integrating such a device into cost-sensitive OTN access layer equipment, especially when the number of STM-1 and STM-4 optical interfaces to be supported is 4 or 8, saves 4 or 8 dedicated clock chips, significantly reducing product cost and power consumption, and increasing the competitiveness of access layer OTN equipment.
[0051] Schematic diagrams of some embodiments of the buffer module in the clock pass-through device disclosed herein are shown below. Figures 3A-3C As shown.
[0052] In some embodiments, such as Figure 3A As shown, the cache module 320 includes a write-side clock interface 321, a read-side clock interface 323, a cache input interface 322, a cache output interface 324, and an output interface 325 for the amount of cache space occupied.
[0053] The write-side clock interface 321 is connected to the clock output interface of the OTN device, and can write the data stream to the buffer based on the clock output by the OTN device.
[0054] The read-side clock interface 323 is connected to the frequency multiplier clock output interface of the clock determination module, and can buffer data based on the frequency multiplier clock output of the clock determination module.
[0055] The buffered input interface 322 can receive input data streams.
[0056] The buffer output interface 324 is connected to the output rate control module and can output buffered data to the output rate control module. In some embodiments, the output clock is matched with the multiplied clock input to the read-side clock interface 323. In some embodiments, the bit width of the buffer output interface 324 is 32 bits.
[0057] The occupied buffer space output interface 325 can output the occupied buffer space to the output rate control module.
[0058] In the clock pass-through device of the above embodiments, the cache module can cache the input data stream and obtain the read and write side clocks through different interfaces, thereby solving the problem of inconsistent read and write side clocks; the cache module outputs its real-time occupied cache space amount so that the outgoing rate control module can refer to this information to control the number of copies, so as to achieve the purpose of dynamically adjusting the output rate according to the business source.
[0059] In some embodiments, the cache module may be a FIFO memory.
[0060] In some embodiments, in STM-1 mode, the FIFO memory is as follows: Figure 3B As shown, the services of the STM-1 optical interface at the source end are demapped via AMP, BMP, or GMP methods, and then the data is sent to the buffer input interface DIN[0] of the FIFO memory. In some embodiments, the FIFO depth is 64 and the bit width is 1 bit in STM-1 mode, and the data stream from DIN[0] is sequentially written to the FIFO memory. In some embodiments, the FIFO memory also includes an input control interface WEN, which is used to control the opening and closing of the buffer input interface. In some embodiments, the write-side clock interface is connected to the demapping module of the OTN device to obtain the clock CLK_OTN sent by the OTN by the demapping module as the write-side clock.
[0061] The read-side clock interface obtains the multiplied clock CLK311M04 output by the clock determination module as the read-side clock. The FIFO memory outputs the cached data through the cache output interface DOUT[0]. In some embodiments, the FIFO memory also includes an output control interface REN for controlling the opening and closing of the cache output interface. The FIFO outputs USED[5:0] on the read side to indicate the amount of storage space used in the FIFO and sends it to the exit rate control module.
[0062] In some embodiments, in STM-4 mode, the FIFO memory is as follows: Figure 3CAs shown, the services of the STM-4 optical interface at the source end are demapped via AMP, BMP, or GMP methods, and then the data is sent to the buffer input interface DIN[3:0] of the FIFO memory. In some embodiments, the FIFO depth is 64 and the bit width is 4 bits in STM-4 mode, and the data stream from DIN[3:0] is sequentially written to the FIFO memory. In some embodiments, the FIFO memory also includes an input control interface WEN for controlling the opening and closing of the buffer input interface. In some embodiments, the write-side clock interface is connected to the demapping module of the OTN device to obtain the clock CLK_OTN sent by the OTN demapping module as the write-side clock.
[0063] The read-side clock interface obtains the multiplied clock CLK311M04 output by the clock determination module as the read-side clock. The FIFO memory outputs the cached data through the cache output interface DOUT[3:0]. In some embodiments, the FIFO memory also includes an output control interface REN for controlling the opening and closing of the cache output interface. The FIFO's read-side output USED[5:0] indicates the amount of storage space used in the FIFO and is sent to the exit rate control module.
[0064] In the clock pass-through device described in the above embodiments, its buffer module is applicable to both STM-1 and STM-4 modes, thereby expanding its applicability and facilitating its widespread application.
[0065] Schematic diagrams of some embodiments of the output rate control module in the clock pass-through device disclosed herein are shown below. Figures 4A-4B As shown.
[0066] In some embodiments, the output rate control module 440 includes: a frequency multiplier clock input interface 441, an occupied buffer space input interface 442, an input rate input interface 443, a buffer read interface 444, and a data output interface 445.
[0067] The frequency multiplier clock input interface 441 is connected to the frequency multiplier clock output interface of the clock determination module, and can receive the frequency multiplier clock. The occupied buffer space input interface 442 is connected to the occupied buffer space output interface of the buffer module, and is configured to obtain the amount of occupied buffer space. The entry rate input interface 443 is connected to the entry rate statistics module, and can receive the entry rate. The buffer read interface 444 is connected to the buffer output interface of the buffer module, and can read the data buffered in the buffer module. The data output interface 445 is connected to the input interface of the clock determination module, and can output the bit-by-bit copied data to the clock determination module.
[0068] In some embodiments, the outgoing rate control module designs a token bucket Token[31:0] to filter out the high-frequency jitter of the actual sending rate F[23:0] / F[25:0] of the service source as counted by the incoming rate statistics module, and then combines it with the number of buffer spaces used by the FIFO memory, USED[5:0], to control the sending rate of the data stream. Figure 4B ( Figure 4B In addition to the export rate control module, the system also includes a clock determination module (Serdes TX module). As shown, the 311.04MHz clock sent by the Serdes TX module serves as the processing clock for the export rate control module and the read-side clock for the FIFO. Under STM-64 rate settings, the data interface DATA[31:0] of the Serdes TX module has a bit width of 32 bits.
[0069] Generally speaking, when no frequency fine-tuning is required, since the Serdes TX module operates at a rate of 9953.28Mbps (STM-64), when the data stream to be transmitted is STM-1, each bit of the STM-1 data needs to be copied into 64 copies for transmission. That is, the 1 bit of data read from the FIFO is expanded into the same 64 bits and then sent out through the DATA[31:0] interface for 2 CLK311M04 clock cycles. When the data stream to be transmitted is STM-4, each bit of the STM-4 data needs to be copied into 16 copies for transmission. That is, 2 bits of the 4 bits read from the FIFO are expanded into 16 copies to form a 32-bit data and then sent out through the DATA[31:0] interface.
[0070] The clock pass-through device in the above embodiments can make the STM-1 or STM-4 data stream to be transmitted change slowly by finely adjusting the data transmission multiple on the FIFO read side when the SerdesTX module is working at the STM-64 rate. This achieves the purpose of slowly changing the transmitted data rate, ensuring that the transmitted data jitter is small and that the frequency is dynamically adjusted according to the service source, thus achieving the purpose of frequency pass-through and saving the use of a dedicated clock chip.
[0071] Schematic diagrams of some embodiments of the clock determination module in the clock pass-through device disclosed herein are shown below. Figure 5 As shown.
[0072] In some embodiments, the clock determination module 530 includes an input interface 531, an output interface 533, a reference clock receiving interface 532, and a frequency multiplication clock output interface 534.
[0073] The reference clock receiving interface 532 is connected to a crystal oscillator and can acquire a reference clock. The frequency multiplier clock output interface 534 is connected to the output rate control module and the buffer module and can output a frequency multiplier clock. The input interface 531 is connected to the output rate control module and can acquire the copied data stream output by the output rate control module. The output interface 532 can output a data stream according to the operating mode of the clock pass-through device based on the data stream from the input interface.
[0074] In some embodiments, the clock determination module 530 is generated by the FPGA design tool and operates at a rate of 9953.28 Mbps (STM-64). The data bus DATA[31:0] connected to the output rate control module has a bit width of 32 bits. Therefore, the clock frequency sent by the Serdes TX module is 9953.28 / 32 = 311.04 MHz. This clock is obtained by frequency multiplication of the internal phase-locked loop of the Serdes module with the local crystal oscillator as the reference clock. It is named CLK311M04 and is used as the processing clock of the output rate control module and the read-side clock of the FIFO.
[0075] Schematic diagrams of some embodiments of the clock pass-through device in STM-1 mode for adjusting the service egress rate are shown below. Figure 6 As shown.
[0076] The sequence read from the FIFO is: 0 1 … 1. At this time, the DATA[31:0] interface signals of the Serdes TX module are as follows:
[0077] 32'b0000-0000-0000-0000-0000-0000-0000-0000
[0078] 32'b0000-0000-0000-0000-0000-0000-0000-0000
[0079] 32'b1111-1111-1111-1111-1111-1111-1111-1111
[0080] 32'b1111-1111-1111-1111-1111-1111-1111-1111
[0081] …
[0082] 32'b1111-1111-1111-1111-1111-1111-1111-1111
[0083] 32'b1111-1111-1111-1111-1111-1111-1111-1111
[0084] When data transmission needs to be sped up, assuming the sequence read from the FIFO is 0 1 …, the number of copies of 0 read from the FIFO on the DATA[31:0] interface of the Serdes TX module is reduced to 63. The missing 1 bit of data on the DATA[31:0] bus is filled in by the 64 1s copied later. The signals are as follows:
[0085] 32'b0000-0000-0000-0000-0000-0000-0000-0000
[0086] 32'b0000-0000-0000-0000-0000-0000-0000-000 1
[0087] 32'b1111-1111-1111-1111-1111-1111-1111-1111
[0088] 32'b1111-1111-1111-1111-1111-1111-1111-111X
[0089] When data transmission needs to be slowed down, assuming the sequence read from the FIFO is 0 1 …, the DATA[31:0] interface signals of the Serdes TX module will be as follows:
[0090] 32'b0000-0000-0000-0000-0000-0000-0000-0000
[0091] 32'b0000-0000-0000-0000-0000-0000-0000-0000
[0092] 32'b 0 111-1111-1111-1111-1111-1111-1111-1111
[0093] 32'b1111-1111-1111-1111-1111-1111-1111-1111
[0094] 32'b1xxx-….
[0095] Under this data rate adjustment design method, the rate adjustment control accuracy is ±1 / 64, which is greater than the SDH optical interface clock frequency deviation of ±4.6PPM. By intermittently adjusting the rate, the requirement of tracking the source service clock and being better than ±4.6PPM can be achieved.
[0096] Schematic diagrams of some embodiments of the optical transport network device 70 disclosed herein. The optical transport network device 70 includes a clock pass-through device 700, which can be any of the types mentioned above.
[0097] Such optical transport network (OTN) equipment can copy the incoming data stream bit by bit based on a frequency-doubled clock before outputting it. By varying the number of copies, the output rate can be finely adjusted to follow the input rate, reducing reliance on dedicated clock chips and thus lowering the cost of OTN equipment. Furthermore, this device saves PCB area and power consumption, reduces the size of OTN box-type equipment, and makes the equipment more energy-efficient and environmentally friendly.
[0098] Schematic diagrams of some embodiments of uplink and downlink data transmission in the SDH service system of the optical transport network disclosed herein are shown below. Figure 8 As shown, services from the source STM-1 or STM-4 optical interface are transmitted through various mapping methods such as AMP, BMP, and GMP into the OTN network. Upon arrival at the destination, the services are demapped using the corresponding mapping method and then processed by the clock pass-through processing device disclosed herein. Finally, the services are transmitted through the high-speed interface Serdes TX of the FPGA chip. This enables clock frequency pass-through for multiple STM-1 and STM-4 rate optical interfaces without using a dedicated clock chip, while ensuring the clock frequency offset requirements of the SDH interface.
[0099] Flowcharts of some embodiments of the clock pass-through method disclosed herein are as follows: Figure 9 As shown.
[0100] In step 901, the ingress rate of the data stream from the service source is statistically analyzed based on the local clock, and the ingress rate is updated according to a predetermined first frequency. In some embodiments, the service interface rate F is statistically analyzed. Since the SDH standard specifies that the rate of STM-1 is 155.52 Mbps, the value of F in STM-1 is expected to be approximately 155.52 x 105 bps, which is converted to hexadecimal as ED4E00, requiring 24 bits to represent, i.e., F[23:0]; in STM-4 it is 4 times that of STM-1, requiring 26 bits to represent, i.e., F[25:0].
[0101] In step 902, the local crystal oscillator is used as a reference clock for frequency multiplication to obtain a frequency-multiplied clock.
[0102] In some embodiments, steps 901 and 902 are not sequential and can be executed in parallel.
[0103] In step 903, the data of the cached data stream is cached, and the amount of cache space already occupied is determined.
[0104] In step 904, the data cached by the cache module is read, and the cached data is copied bit by bit based on the frequency multiplication clock and then output. The number of copies is dynamically adjusted according to the input rate and the amount of cache space already occupied.
[0105] In some embodiments, taking STM-1 mode as an example, when no rate adjustment is required, 1 bit of data is read from DOUT[0] every 2 CLK311M04 clock cycles, and 32 copies are sent to the interface signal DATA[31:0] of the Serdes TX module every clock cycle. The transmission of 64 copies is completed in 2 clock cycles.
[0106] This method allows for the bit-by-bit copying of the input data stream based on a frequency-doubled clock, and the output rate can be finely adjusted to follow the input rate by changing the number of copies. This reduces the reliance on dedicated clock chips and helps to lower the cost of OTN devices.
[0107] In some embodiments, the current business mode can be set first, and the specific device parameters are shown in Table 1.
[0108] Table 1 STM-1 / 4 Mode Setting Parameter Definitions
[0109]
[0110] This method can be applied to STM-1 / 4 mode, expanding the scope of applications.
[0111] In some embodiments, in step 904 above, by using the token bucket control mechanism, the high-frequency jitter of F[23:0] / F[25:0] introduced by the large jitter during OTN demapping can be filtered out.
[0112] In some embodiments, the token bucket operates under two conditions: the useD[5:0] sent by the FIFO module and the entry rate indication F[23:0] / F[25:0] sent by the entry rate statistics module. The operating principle is as follows:
[0113] A. Initialization: Token = 32'h8000-0000;
[0114] B. When (USED[5:0]>=8)&&(USED[5:0]<=56), every 100ms Token=Token+F[23:0] or F[25:0];
[0115] When (USED[5:0]>56): Set Token=32'h8000-0000, and continuously read the FIFO until the FIFO returns to USED[5:0]=32;
[0116] When (USED[5:0]<8): Set Token=32'h8000-0000, stop reading FIFO until FIFO returns to USED[5:0]=32;
[0117] C. In STM-1 mode, for every 1 bit of data read from the FIFO, Token = Token - 1; in STM-4 mode, for every 4 bits of data read from the FIFO, Token = Token - 4.
[0118] D. When Token >= 32'hE000-0000, Token will no longer increase; when Token <= 32'h 2000-0000, Token will no longer decrease.
[0119] From the rules above, we can see that: the token injection rule injects the actual input bits of the SDH data stream every 100ms; the token deduction rule deducts the corresponding token for every 1 bit (or 4 bits) read from the FIFO. Therefore, the token injection and deduction are balanced.
[0120] In some embodiments, in order to enable the frequency information carried by the transmitted data to track the STM-1 or STM-4 data stream rate at the source end, it is necessary to dynamically adjust the transmitted data rate. The rules for rate adjustment are shown in Table 2.
[0121] Table 2 Rules for Rate Adjustment Based on Token Bucket
[0122]
[0123]
[0124]
[0125] Based on the methods in the above embodiments, it is possible to solve the problem of OTN access layer equipment carrying multiple SDH optical interfaces and providing clock frequency pass-through without using a dedicated clock chip, thereby reducing equipment costs; by setting a frequency multiplier clock in STM-64 mode, frequency tracking is transformed into adjusting the transmission speed of the data stream by adjusting the number of data stream transmissions (adjusting only 1 / 64 or 1 / 16 each time), thereby achieving tracking of the data source frequency; and by using a token bucket, the balance of data volume between input and output is ensured.
[0126] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a machine for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.
[0127] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.
[0128] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.
[0129] This concludes the detailed description of the present disclosure. To avoid obscuring the concept of the disclosure, some details known in the art have not been described. Those skilled in the art will fully understand how to implement the technical solutions disclosed herein based on the above description.
[0130] The methods and apparatus of this disclosure may be implemented in many ways. For example, they may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above-described order of steps for the methods is for illustrative purposes only, and the steps of the methods of this disclosure are not limited to the order specifically described above unless otherwise specifically stated. Furthermore, in some embodiments, this disclosure may also be implemented as a program recorded on a recording medium, the program including machine-readable instructions for implementing the methods according to this disclosure. Thus, this disclosure also covers recording media storing programs for performing the methods according to this disclosure.
[0131] It should be noted that the terms "first," "second," etc., used in the specification, claims, and drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0132] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure and not to limit them; although this disclosure has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications can still be made to the specific implementation of this disclosure or equivalent substitutions can be made to some technical features without departing from the spirit of the technical solutions of this disclosure, and all such modifications and substitutions should be covered within the scope of the technical solutions claimed in this disclosure.
Claims
1. A clock transmission device, comprising: The ingress rate statistics module is configured to count the ingress rate of the data stream from the service source based on the local clock, and update the ingress rate according to a predetermined first frequency; The caching module is configured to cache the data in the data stream and determine the amount of cache space already occupied. The clock determination module is configured to multiply the local crystal oscillator as a reference clock to obtain the multiplied clock. The output rate control module is configured to read the data cached by the cache module and copy the cached data bit by bit based on the frequency multiplier clock before outputting it. The number of copies is dynamically adjusted according to the input rate and the amount of cache space already occupied.
2. The apparatus according to claim 1, wherein, The export rate control module is configured as follows: The token bucket value is determined based on the amount of data read, the amount of cache space already occupied in the cache module, and the entry rate obtained by the entry rate statistics module. The number of replications is determined based on the value of the token bucket, where: If the value of the token bucket is less than a predetermined low threshold, the number of replications is the first replication count; If the value of the token bucket is greater than a predetermined high threshold, the number of replications is the second replication number; If the value of the token bucket is less than or equal to the predetermined high threshold and greater than or equal to the predetermined low threshold, the number of replications is the initial number of replications. The first number of replications > the initial number of replications > the second number of replications.
3. The apparatus according to claim 2, wherein, The first number of copies is 1 greater than the initial number of copies, and the second number of copies is 1 less than the initial number of copies.
4. The apparatus according to claim 2, wherein, The export rate control module is configured as follows: The token bucket is initialized to a predetermined initial value; The entry rate, as counted by the entry rate statistics module, is added to the token bucket at a predetermined second frequency. Each time bit data is read from the cache module, the value of the token bucket decreases by a predetermined deduction value; If the amount of cache space already occupied is greater than a predetermined first threshold, or the amount of cache space already occupied is less than a predetermined second threshold, then the token bucket is set to the predetermined initial value.
5. The apparatus according to claim 2, wherein, The export rate control module is also configured to: If the amount of cached space already occupied is greater than a predetermined first threshold, then the cached data is continuously read until the amount of cached space already occupied is a predetermined standard value; If the amount of cached space already occupied is less than a predetermined second threshold, then reading the cached data will stop until the amount of cached space already occupied reaches a predetermined standard value.
6. The apparatus according to any one of claims 1 to 5, wherein, The device meets at least one of the following criteria: The clock determination module is configured to operate in STM-64 mode; The data bus width between the clock determination module and the output rate control module is 32 bits; or The entry rate statistics module is configured to count the total amount of valid data sent to the write interface of the cache module within a predetermined time, and obtain the average value after counting a predetermined number of times to determine the entry rate.
7. The apparatus according to claim 4, wherein, The clock pass-through device operates in STM-1 mode. The cache module has a cache depth of 64, a bit width of 1 bit, an initial copy count of 63, and reads 1 bit of data from the cache module each time. The predetermined deduction value is 1.
8. The apparatus according to claim 4, wherein, The clock pass-through device operates in STM-4 mode. The cache module has a cache depth of 64, a bit width of 4 bits, an initial copy count of 15, and reads 4 bits of data at a time from the cache module. The predetermined deduction value is 4.
9. The apparatus according to claim 1, further comprising: The mode adjustment module is configured to switch the operating modes of the clock pass-through device, including STM-1 and STM-4.
10. The apparatus according to claim 1, wherein, The clock determination module is a Serdes TX module, including an input interface, an output interface, a reference clock receiving interface, and a frequency multiplication clock output interface, wherein: The reference clock receiving interface is connected to a crystal oscillator and is configured to acquire a reference clock. The frequency multiplier clock output interface is connected to the output rate control module and the buffer module, and is configured to output a frequency multiplier clock. The input interface is connected to the output rate control module and is configured to acquire the copied data stream output by the output rate control module; The output interface is configured to output a data stream according to the operating mode of the clock pass-through device, based on the data stream from the input interface.
11. The apparatus according to claim 10, wherein, The cache module is a FIFO module, including a write-side clock interface, a read-side clock interface, a cache input interface, a cache output interface, and an interface for outputting the amount of cache space already occupied, wherein: The write-side clock interface is connected to the clock output interface of the OTN device and is configured to write the data stream into the buffer based on the clock output by the OTN device. The read-side clock interface is connected to the frequency multiplier clock output interface of the clock determination module and is configured to buffer data based on the frequency multiplier clock output output by the clock determination module. The cached input interface is configured to receive an input data stream; The buffer output interface is configured to output buffered data to the exit rate control module; and The output interface for the amount of occupied cache space is configured to output the amount of occupied cache space to the exit rate control module.
12. The apparatus according to claim 10, wherein, The output rate control module includes: a frequency multiplier clock input interface, an occupied buffer space input interface, an input rate input interface, a buffer read interface, and a data output interface, wherein: The frequency multiplier clock input interface is connected to the frequency multiplier clock output interface of the clock determination module and is configured to receive the frequency multiplier clock. The input interface for occupied cache space is connected to the output interface for occupied cache space of the cache module and is configured to obtain the amount of occupied cache space. The ingress rate input interface is connected to the ingress rate statistics module and is configured to receive the ingress rate. The cache read interface is connected to the cache output interface of the cache module and is configured to read cached data in the cache module; The data output interface is connected to the input interface of the clock determination module and is configured to output the bit-by-bit copied data to the clock determination module.
13. An optical transmission network device, comprising the clock pass-through device according to any one of claims 1 to 12.
14. A clock pass-through method, comprising: The local crystal oscillator is used as a reference clock and its frequency is multiplied to obtain the multiplied clock. The ingress rate of the data stream from the service source is calculated based on the local clock, and the ingress rate is updated according to a predetermined first frequency. Cache the data in the data stream and determine the amount of cache space already occupied; and The data cached by the cache module is read, and the cached data is copied bit by bit based on the frequency multiplier clock before being output. The number of copies is dynamically adjusted according to the entry rate and the amount of cache space already occupied.
15. The method according to claim 14, wherein, The step of reading the data cached by the cache module and copying the cached data bit by bit based on the frequency multiplication clock and then outputting it includes: The token bucket value is determined based on the amount of data read, the amount of cache space already occupied in the cache module, and the entry rate obtained by the entry rate statistics module. The number of replications is determined based on the value of the token bucket, where: If the value of the token bucket is less than a predetermined low threshold, the number of replications is the first replication count; If the value of the token bucket is greater than a predetermined high threshold, the number of replications is the second replication number; If the value of the token bucket is less than or equal to the predetermined high threshold and greater than or equal to the predetermined low threshold, the number of replications is the initial number of replications. First replication count > Initial replication count > Second replication count; Based on the number of copies, the cached data is copied bit by bit and then output according to the frequency multiplication clock.
16. The method according to claim 15, wherein, The step of determining the token bucket value based on the amount of data read, the amount of cache space already occupied in the caching module, and the entry rate obtained by the entry rate statistics module includes: The token bucket is initialized to a predetermined initial value; The entry rate, as counted by the entry rate statistics module, is added to the token bucket at a predetermined second frequency. Each time bit data is read from the cache module, the value of the token bucket decreases by a predetermined deduction value; If the amount of cache space already occupied is greater than a predetermined first threshold, or the amount of cache space already occupied is less than a predetermined second threshold, then the token bucket is set to the predetermined initial value.
17. The method according to claim 15, wherein, The step of reading the data cached by the cache module and copying the cached data bit by bit based on the frequency multiplication clock and then outputting it further includes: If the amount of cached space already occupied is greater than a predetermined first threshold, then the cached data is continuously read until the amount of cached space already occupied is a predetermined standard value; If the amount of cached space already occupied is less than a predetermined second threshold, then reading the cached data will stop until the amount of cached space already occupied reaches a predetermined standard value.
18. The method according to any one of claims 14 to 17, further comprising: Switch the current working mode, which includes STM-1 and STM-4.