A multi-priority hardware timer in the field of real-time
By designing a multi-priority hardware timer, the problem that traditional timers cannot meet the high-precision timing and multi-priority scheduling requirements of real-time systems is solved, achieving efficient and flexible timer management and improving the real-time performance and reliability of the system.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NORTHEASTERN UNIV CHINA
- Filing Date
- 2023-07-03
- Publication Date
- 2026-06-30
AI Technical Summary
Traditional software and hardware timers cannot meet the needs of real-time systems for high-precision timing and multi-priority task scheduling, leading to system crashes, security vulnerabilities, and decreased scheduling performance.
Design a multi-priority hardware timer, including a timer unit and a priority control unit. Through a timing module, a comparison register, a priority configuration register, and an interrupt arbitration module, it realizes multi-task and multi-priority management, supports flexible timing modes and triggering methods, and dynamically adjusts the timer priority and time.
It improves the processing efficiency and real-time performance of the timer, avoids interference between low-priority tasks and high-priority tasks, enhances the reliability and security of the system, supports flexible configuration and expansion, and meets the needs of complex multi-tasking systems.
Smart Images
Figure CN116841617B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of real-time technology and relates to a multi-priority hardware timer in the real-time field. Background Technology
[0002] Real-time systems typically contain multiple tasks with different priorities and execution cycles. To ensure the system's real-time performance and reliability, strict task scheduling and control are essential. In this context, timers are a crucial tool, capable of triggering behaviors such as periodic tasks and delayed waiting. Traditional timers are mainly divided into software timers and hardware timers.
[0003] Traditional software timers are typically implemented in software, and their implementation generally follows these steps: A global variable `timer_counter` is defined to represent the timer counter, used to record the elapsed time since system startup, with an initial value of 0. A timer handler function `timer_isr` is defined to handle timer interrupts. This function triggers an interrupt when the timer reaches its set time, based on the timer's settings. A timer initialization function `timer_init` is defined to initialize timer-related parameters. This function needs to set parameters such as the timer's counting mode, counting rate, and timing interval, as well as the associated timer handler function `timer_isr`. During system initialization, the timer initialization function `timer_init` is called for initialization. During system runtime, the timer counter `timer_counter` continuously increments. When the timer counter reaches the set timing interval, a timer interrupt is triggered, executing the timer handler function `timer_isr`. Within the timer handler function `timer_isr`, specific processing is performed according to requirements. For example, the timer interrupt can be treated as an event, notifying relevant tasks to handle it.
[0004] Traditional software timers suffer from the following problems: Their accuracy is affected by factors such as system clock precision and operating system scheduling latency, failing to meet the high-precision timing requirements of real-time systems. They typically use data structures like linked lists and arrays to manage timers, requiring traversal of all timers for searching and processing, resulting in low efficiency. They are usually user-spaced; if the timer handling function has issues, it may lead to system crashes or security vulnerabilities. They generally only support fixed triggering methods and timing modes, lacking flexibility for expansion and customization. They typically only support a single priority, unable to differentiate the priorities of timers for different tasks, leading to the following problems: timer interrupts from low-priority tasks can interfere with the execution of high-priority tasks, affecting their response time. Priority inversion occurs, with lower-priority tasks responding before higher-priority tasks, which, from a scheduling perspective, is equivalent to lower-priority tasks preempting higher-priority tasks, impacting scheduling performance and real-time capabilities.
[0005] Traditional hardware timers typically consist of one or more counters, one or more comparators, and one or more interrupt controllers. Their implementation is as follows: Define one or more counter registers for counting. The counter is usually a fixed-length binary counter; when the counter overflows, an interrupt is generated. Define one or more comparator registers to set the timer's trigger time. When the counter value equals the comparator value, an interrupt is generated. Define an interrupt controller to control the triggering and handling of timer interrupts. The interrupt controller can receive interrupt signals from the counter and comparators and forward them to the processor. During system initialization, the timer's counting mode, counting rate, comparator setpoint, and other parameters are configured. During system operation, the timer counter continuously increments; when the counter value equals the comparator setpoint, the timer interrupt is triggered. In the timer interrupt handler function, relevant processing is performed according to specific needs. For example, the timer interrupt can be treated as an event, notifying relevant tasks to handle it.
[0006] Traditional hardware timers have the following problems: They typically only support a single priority level, lacking the ability to schedule and manage multiple priorities or differentiate between timers for different tasks. This makes them unsuitable for complex multitasking systems. Furthermore, traditional hardware timers usually require setting the trigger time during initialization, and once set, cannot be dynamically adjusted at runtime. This makes them ill-suited to handling dynamic system requirements. Summary of the Invention
[0007] To address the aforementioned technical problems, the present invention aims to provide a multi-priority hardware timer for real-time applications, which supports multiple tasks and multiple priorities, can distinguish between different tasks, supports multiple timing modes and triggering methods, and can meet the needs of different real-time tasks.
[0008] This invention provides a multi-priority hardware timer for real-time applications, comprising interconnected timer units and priority control units;
[0009] The timer unit includes: a timing module and multiple comparison registers connected to the timing module; the timing module and each comparison register constitute a hardware timer. After being enabled by the priority control unit, the timing module counts at a specific frequency. When the value in the timing module is greater than or equal to the value in the comparison register, the corresponding comparison register will generate a timing interrupt signal.
[0010] The priority control unit includes: an interrupt arbitration module, a low-priority mask register, a timer enable register, a timer ID register, and multiple priority configuration registers; the low-priority mask register is connected to multiple comparison registers, multiple priority configuration registers, and the interrupt arbitration module, respectively.
[0011] The timing enable register is used to enable the timing module; the priority configuration register is used to configure the priority of the corresponding comparison register according to the processor's instructions; the low priority mask register is used to mask the interrupt signals of low priority hardware timers; the interrupt arbitration module is used to arbitrate the interrupt signals of hardware timers, and after interrupt arbitration, the contents of the timer ID register are updated to the ID number of the highest priority hardware timer, and the interrupt signal of that hardware timer is forwarded to the processor.
[0012] Furthermore, when executing a high-priority task, the processor updates the low-priority mask register to the priority of the high-priority task, and all timer interrupt signals with a priority lower than that priority will be masked.
[0013] Furthermore, the processor assigns corresponding access addresses to the low-priority mask register, timer enable register, timer ID register, priority configuration register, and comparison register; among them, the priority configuration register and comparison register are addressed sequentially, and the hardware timer ID number is assigned starting from 0;
[0014] The processor reads and writes all registers of the multi-priority hardware timer according to the allocated access address through memory-mapped input / output.
[0015] Furthermore, the processor configures the hardware timer to different priorities by writing to the priority configuration register corresponding to the hardware timer, and dynamically adjusts the priority of the hardware timer at runtime; the highest bit of the priority configuration register is used to record whether the corresponding hardware timer is currently idle, and the remaining bits are used to record the priority of the corresponding hardware timer; if the hardware timer is idle, the interrupt signal generated by the hardware timer will also be masked by the low priority mask register.
[0016] Furthermore, the processor reads the ID number of the hardware timer stored in the Timer ID register to determine which task the timer interrupt belongs to.
[0017] Furthermore, when a task needs to request a hardware timer, the value of the priority configuration register corresponding to the first hardware timer is read in order of ID number. The availability of the corresponding hardware timer is determined by whether the highest bit of the priority configuration register is 0. If it is available, the allocation is successful, the highest bit of the priority configuration register is modified to 1, and the priority of the hardware timer is written to the priority configuration register. If it is not available, the priority configuration register corresponding to the next hardware timer is accessed and the determination is made again.
[0018] Furthermore, the timing module and each comparison register are read and written via memory-mapped input / output.
[0019] The multi-priority hardware timer for real-time applications of the present invention has at least the following beneficial effects:
[0020] 1. Compared with software timers, the multi-priority hardware timer of this invention has the characteristic of high precision. The timing precision of the timer can be configured according to the requirements, and the upper limit is only limited by the timing of the processor and the highest frequency of the hardware crystal oscillator.
[0021] 2. No need to search for and process timers. Timers are directly managed by the hardware, greatly improving timer processing efficiency.
[0022] 3. Supports multi-tasking and multi-priority, allowing differentiation of hardware timers for different tasks within the timer unit. Priority can be configured according to different task requirements, providing greater flexibility to adapt to various task demands. Hardware timers are categorized and managed according to priority; different priority hardware timers can be triggered independently. The interrupt arbitration module determines whether to respond to the corresponding hardware timer interrupt based on priority, and subsequently decides whether to execute the scheduling algorithm for scheduling and processing. This avoids interference from low-priority tasks to high-priority tasks and prevents potential issues such as slow system response or even deadlock, significantly improving system real-time performance and reliability.
[0023] 4. The software-level processing functions are implemented on the operating system kernel, which improves the processing efficiency of the timer and ensures the security of the system.
[0024] 5. It features flexible configuration and expansion capabilities. On the hardware side, it utilizes an accelerator-like implementation, offering flexibility and scalability. Users can customize and adjust the configuration according to their needs, and even add new functions. On the software side, it is even more flexible. Users can either use the timer directly or encapsulate it to design new timer libraries, fully leveraging the timer's features.
[0025] 6. The timer's timing and priority can be dynamically adjusted, avoiding the problems that exist with traditional hardware timers in this regard.
[0026] 7. The design of the timing enable register makes the actual multi-task configuration and execution more consistent with the assumptions made in theoretical research. That is, from the timeline perspective, it truly achieves the simultaneous release and execution of multiple tasks.
[0027] 8. Software timers require CPU resources to perform timing operations, while the multi-priority hardware timer of this invention is controlled by hardware and does not require CPU resources, allowing the CPU to focus on the execution of other tasks.
[0028] 9. The multi-priority hardware timer of the present invention is controlled by hardware and is not affected by software, which can achieve higher real-time performance and execute timing tasks more accurately.
[0029] 10. The multi-priority hardware timer of the present invention can better utilize system resources, effectively distinguish between high-priority tasks and low-priority tasks, reduce the interference of low-priority tasks on high-priority tasks, and improve the response speed of high-priority tasks. Attached Figure Description
[0030] Figure 1 This is a structural block diagram of a multi-priority hardware timer in the field of real-time applications according to the present invention;
[0031] Figure 2 This is a structural block diagram of the priority control unit of the present invention. Detailed Implementation
[0032] like Figure 1 and 2As shown, this invention discloses a multi-priority hardware timer for real-time applications, comprising interconnected timer units and priority control units. The timer unit includes a timing module and multiple comparison registers connected to the timing module. The timing module and each comparison register constitute a hardware timer. After being enabled by the priority control unit, the timing module counts at a specific frequency. When the value in the timing module is greater than or equal to the value in the comparison register, the corresponding comparison register generates a timing interrupt signal.
[0033] The priority control unit includes an interrupt arbitration module, a low-priority mask register, a timing enable register, a timer ID register, and multiple priority configuration registers. The low-priority mask register is connected to multiple comparison registers, multiple priority configuration registers, and the interrupt arbitration module. The timing enable register enables the timing module. The priority configuration register configures the priority of the corresponding comparison register according to the processor's instructions. The low-priority mask register masks the interrupt signals of low-priority hardware timers. The interrupt arbitration module arbitrates the interrupt signals of hardware timers, updates the timer ID register to the ID number of the highest-priority hardware timer after arbitration, and forwards the interrupt signal of that hardware timer to the processor.
[0034] In practice, the timing module and each comparison register are read and written through memory-mapped input / output.
[0035] In practice, when a high-priority task is being executed, the processor updates the low-priority mask register to the priority of the high-priority task, and all timer interrupt signals with a priority lower than that priority will be masked.
[0036] In specific implementation, the processor assigns corresponding access addresses to the low-priority mask register, timer enable register, timer ID register, priority configuration register, and comparison register; the priority configuration register and comparison register are addressed sequentially, and the ID number of the hardware timer is assigned starting from 0; the processor reads and writes all registers of the multi-priority hardware timer according to the assigned access addresses through memory-mapped input / output.
[0037] In practice, the processor configures the hardware timer to different priorities by writing to the priority configuration register corresponding to the hardware timer, and dynamically adjusts the priority of the hardware timer at runtime. The highest bit of the priority configuration register is used to record whether the corresponding hardware timer is currently idle, and the remaining bits are used to record the priority of the corresponding hardware timer. If the hardware timer is idle, the interrupt signal generated by the hardware timer will also be masked by the low priority mask register.
[0038] In practice, the ID number of the hardware timer stored in the Timer ID register is read by the processor to determine which task the timer interrupt belongs to. Example
[0039] When a task needs to request a hardware timer, the value of the priority configuration register corresponding to the first hardware timer is read in order of ID number. The most significant bit of the priority configuration register is checked to determine if the corresponding hardware timer is idle. If it is idle, the allocation is successful, the most significant bit of the priority configuration register is changed to 1, and the priority of the hardware timer is written to the priority configuration register. If it is not idle, the priority configuration register corresponding to the next hardware timer is accessed and the determination is made again.
[0040] After a task requests a timer, it can read the count value from the current timing module and calculate and configure the corresponding comparison register according to its timing requirements. For example, the timing module's counting frequency is... a (Hz), the current count value of the timer module x This task requires a timer. b (s), then will x + a × b The value can be written into the corresponding comparison register.
[0041] When multiple interrupt signals are generated by a timer unit within the same time period, the low-priority mask register first masks the interrupt signals from hardware timers with lower priorities. The remaining interrupt signals are then arbitrated by the priority control unit, which selects the highest-priority interrupt signal and sends it to the processor. The timer ID register is then updated with the ID number of the highest-priority hardware timer. The processor reads the ID number stored in the timer ID register, determines which task the hardware timer interrupt belongs to, and executes that task.
[0042] In practice, if a task wants to cancel a timer, it only needs to set the highest bit of the corresponding priority configuration register to 0.
[0043] In practice, at the start of task execution, the low-priority mask register can be configured to the priority of the task to mask all low-priority timer interrupts. This avoids interference from low-priority timer interrupts to the current task and also avoids priority inversion.
[0044] In practice, if the priority of a task needs to be adjusted during operation, the priority configuration register of the allocated hardware timer can be modified.
[0045] In practice, if the timer time needs to be adjusted during operation, the comparison register of the allocated hardware timer can be modified.
[0046] In practical implementation, some theoretical research requires the simultaneous release and execution of multiple periodic tasks. However, in reality, hardware timers are constantly running, leading to inconsistent release times for each task. By using a timer enable register, the timer can be activated only after all tasks have been created, thus satisfying the requirement for simultaneous release and execution of multiple tasks. This eliminates the errors inherent in simultaneous release and execution of multiple tasks in related theoretical research. Furthermore, the design of the timer enable register makes the use of timers more flexible for users.
[0047] The multi-priority hardware timer in the real-time field of the present invention mainly consists of a timer unit and a priority control unit. The timer unit is used for timing, and the priority control unit is used to enable the timing module in the timer unit, configure the priority, allocate the hardware timer, and shield the interrupt signal of the low-priority hardware timer.
[0048] The registers in a multi-priority hardware timer for real-time applications of this invention can be read and written via memory-mapped I / O (MMIO) or controlled via custom instructions.
[0049] The timing enable register design of this invention allows users to use timers more flexibly and can meet the needs of some research work.
[0050] The design of the low-priority mask register in this invention can mask the interrupt signals of low-priority hardware timers, thus avoiding interference from the interrupt signals of low-priority hardware timers to the current task and preventing priority inversion.
[0051] The priority configuration register of this invention can be used to configure the priority of a hardware timer. At the same time, the highest bit of the priority configuration register serves as the idle flag bit of the hardware timer, which can combine the idle flag modification operation and the priority allocation operation into a single operation.
[0052] The timer ID register design of this invention distinguishes between interrupts from different hardware timers. By reading this register, the interrupt handler can determine which task the interrupt belongs to. This design reduces the complexity of the hardware interface and makes the entire interrupt handling process simpler and more intuitive.
[0053] The multi-priority hardware timer of this invention performs each operation based on the current configuration of each register. Thanks to this implementation logic, the timer's priority and timing can be dynamically adjusted during runtime.
[0054] The above description is only a preferred embodiment of the present invention and is not intended to limit the ideas of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A multi-priority hardware timer in the field of real-time, characterized in that, This includes interconnected timer units and priority control units; The timer unit includes: a timing module and multiple comparison registers connected to the timing module; the timing module and each comparison register constitute a hardware timer. After being enabled by the priority control unit, the timing module counts at a specific frequency. When the value in the timing module is greater than or equal to the value in the comparison register, the corresponding comparison register will generate a timing interrupt signal. The priority control unit includes: an interrupt arbitration module, a low-priority mask register, a timer enable register, a timer ID register, and multiple priority configuration registers; the low-priority mask register is connected to multiple comparison registers, multiple priority configuration registers, and the interrupt arbitration module, respectively. The timing enable register is used to enable the timing module; the priority configuration register is used to configure the priority of the corresponding comparison register according to the processor's instructions; the low priority mask register is used to mask the interrupt signals of low priority hardware timers; the interrupt arbitration module is used to arbitrate the interrupt signals of hardware timers, and after interrupt arbitration, the contents of the timer ID register are updated to the ID number of the highest priority hardware timer, and the interrupt signal of that hardware timer is forwarded to the processor.
2. The multi-priority hardware timer in the field of real-time as claimed in claim 1, wherein, When a high-priority task is being executed, the processor updates the low-priority mask register to the priority of the high-priority task, and all timer interrupt signals with a priority lower than that priority will be masked.
3. The multi-priority hardware timer in the real-time domain as described in claim 1, characterized in that, The processor assigns corresponding access addresses to the low-priority mask register, timer enable register, timer ID register, priority configuration register, and comparison register; the priority configuration register and comparison register are addressed sequentially, and the hardware timer IDs are assigned starting from 0. The processor reads and writes all registers of the multi-priority hardware timer according to the allocated access address through memory-mapped input / output.
4. The multi-priority hardware timer in the real-time domain as described in claim 3, characterized in that, The processor configures the hardware timer to different priorities by writing to the priority configuration register corresponding to the hardware timer, and dynamically adjusts the priority of the hardware timer at runtime. The highest bit of the priority configuration register is used to record whether the corresponding hardware timer is currently idle, and the remaining bits are used to record the priority of the corresponding hardware timer. If the hardware timer is idle, the interrupt signal generated by the hardware timer will also be masked by the low priority mask register.
5. The multi-priority hardware timer in the real-time domain as described in claim 1, characterized in that, The ID number of the hardware timer stored in the Timer ID register is read by the processor to determine which task the timer interrupt belongs to.
6. The multi-priority hardware timer in the real-time domain as described in claim 3, characterized in that, When a task needs to request a hardware timer, the value of the priority configuration register corresponding to the first hardware timer is read in order of ID number. The most significant bit of the priority configuration register is checked to determine if the corresponding hardware timer is idle. If it is idle, the allocation is successful, the most significant bit of the priority configuration register is changed to 1, and the priority of the hardware timer is written to the priority configuration register. If it is not idle, the priority configuration register corresponding to the next hardware timer is accessed and the determination is made again.
7. The multi-priority hardware timer in the real-time domain as described in claim 1, characterized in that, The timing module and each comparison register are read and written via memory-mapped input / output.