System and method for computing the number of half-words in two block operands

Abstract

The present disclosure relates to systems and methods for computing a number product of half-words in two block operands. In one example, an apparatus comprises a plurality of memory controllers, a level two (L2) cache memory, and a processor having a plurality of cores, a core including circuitry to perform an operation corresponding to an instruction, the operation including multiplying eight 4-bit data elements of a 32-bit element of a row m of a first matrix with a respective data element of eight 4-bit data elements of a respective 32-bit element of a column n of a second matrix to generate eight products, and storing a 32-bit result data element at row m in an M row and column n in an N column of a third matrix, the 32-bit result data element to be based on an accumulation of the eight products generated for each of K 32-bit elements of row m of the first matrix with the 32-bit data elements corresponding to row m of the first matrix and column n of the second matrix.

Description

[0001] This is a divisional application. The parent application is entitled "System and Method for Calculating the Number Product of Half-Bytes in Two Block Operands", filed on December 28, 2018, with application number 201811620796.5. Technical Field

[0002] The field of this invention generally relates to computer processor architecture, and more specifically to systems and methods for calculating the number product of nibbles in two block operands. Background Technology

[0003] Matrices are becoming increasingly important in many computational tasks such as machine learning and other batch data processing. Attached Figure Description

[0004] The invention is illustrated in the figures by way of example rather than limitation, wherein like reference numerals indicate similar elements, and wherein:

[0005] Figure 1A An example of a configured block is illustrated;

[0006] Figure 1B An example of a configured block is illustrated;

[0007] Figure 2 Several examples of matrix storage are shown;

[0008] Figure 3 An example of a system that utilizes a matrix (block) to operate an accelerator is illustrated;

[0009] Figure 4 and Figure 5 Different embodiments of how to use a matrix operation accelerator to share memory are shown;

[0010] Figure 6 An example of using a block-based matrix multiplication accumulation operation (“TMMA”) is illustrated;

[0011] Figure 7 An example is illustrated of a subset of the iterative execution of chained fused multiplication-accumulation instructions;

[0012] Figure 8 An example is illustrated of a subset of the iterative execution of chained fused multiplication-accumulation instructions;

[0013] Figure 9 An example is illustrated of a subset of the iterative execution of chained fused multiplication-accumulation instructions;

[0014] Figure 10 An example is illustrated of a subset of the iterative execution of chained fused multiplication-accumulation instructions;

[0015] Figure 11 An example of a power-of-two sized SIMD implementation according to an embodiment is shown, wherein the accumulator uses an input size larger than that to the input of the multiplier;

[0016] Figure 12 An example of a system utilizing a matrix manipulation circuit is illustrated;

[0017] Figure 13 An example of a processor core pipeline that supports matrix operations using blocks is illustrated;

[0018] Figure 14 An example of a processor core pipeline that supports matrix operations using blocks is illustrated;

[0019] Figure 15 Examples of matrices represented in row-major and column-major order are shown;

[0020] Figure 16 Examples of using matrices (blocks) are shown;

[0021] Figure 17 An example of how to use a matrix (block) is shown;

[0022] Figure 18 This illustrates support for block usage configuration according to an embodiment;

[0023] Figure 19 An example of a description of the matrix (block) to be supported is shown;

[0024] Figures 20(A)-(D) illustrate examples of (one or more) registers;

[0025] Figure 21 An exemplary execution of the TILELOADQPAIR instruction is illustrated;

[0026] Figure 22 An example of a processor executing the TILELOADQPAIR instruction is illustrated;

[0027] Figure 23 A more detailed description of the execution of the TILELOADQPAIR instruction is provided;

[0028] Figure 24A This is exemplary pseudocode describing an embodiment of a processor executing the TILELOADQPAIR instruction;

[0029] Figure 24B This is exemplary pseudocode describing an embodiment of the auxiliary functions used by the processor to execute the TILELOADQPAIR instruction;

[0030] Figures 25A-25B This is a block diagram illustrating a general vector-friendly instruction format and its instruction template according to embodiments of the present invention;

[0031] Figure 25A This is a block diagram illustrating a general vector-friendly instruction format and its Class A instruction template according to embodiments of the present invention;

[0032] Figure 25B This is a block diagram illustrating a general vector-friendly instruction format and its Class B instruction template according to embodiments of the present invention;

[0033] Figure 26A This is a block diagram illustrating an exemplary specific vector-friendly instruction format according to an embodiment of the present invention;

[0034] Figure 26B This is a block diagram illustrating a specific vector-friendly instruction format that constitutes a full opcode field according to an embodiment of the present invention;

[0035] Figure 26C This is a block diagram illustrating a specific vector-friendly instruction format of a field constituting a register index field according to an embodiment of the present invention;

[0036] Figure 26D This is a block diagram illustrating a specific vector-friendly instruction format that constitutes an amplification operation field according to an embodiment of the present invention;

[0037] Figure 27 This is a block diagram of a register architecture according to an embodiment of the present invention;

[0038] Figure 28A This is a block diagram illustrating both an exemplary ordered pipeline and an exemplary register renaming and unordered release / execution pipeline according to embodiments of the present invention;

[0039] Figure 28B This is a block diagram illustrating both an exemplary ordered architecture core embodiment and an exemplary register renaming, out-of-order release / execution architecture core to be included in a processor according to embodiments of the present invention;

[0040] Figure 29A -B illustrates a more specific example of an ordered core architecture, which will be one of several logical blocks in the chip (including other cores of the same type and / or different types);

[0041] Figure 29A This is a block diagram of a single processor core, its connection to the on-die interconnect network, and a local subset of its secondary (L2) cache, according to an embodiment of the present invention.

[0042] Figure 29BAccording to an embodiment of the present invention Figure 29A An expanded diagram of a portion of the processor core;

[0043] Figure 30 This is a block diagram of a processor according to an embodiment of the present invention. The processor may have more than one core, may have an integrated memory controller, and may have an integrated graphics device.

[0044] Figures 31-34 This is a block diagram of an exemplary computer architecture;

[0045] Figure 31 A block diagram of a system according to an embodiment of the present invention is shown;

[0046] Figure 32 This is a block diagram of a first, more specific, exemplary system according to an embodiment of the present invention;

[0047] Figure 33 This is a block diagram of a second, more specific, exemplary system according to an embodiment of the present invention;

[0048] Figure 34 This is a block diagram of a System-on-Chip (SoC) according to an embodiment of the present invention; and

[0049] Figure 35 This is a block diagram illustrating the use of a software instruction converter to convert binary instructions in a source instruction set into binary instructions in a target instruction set, according to an embodiment of the present invention. Detailed Implementation

[0050] Numerous specific details are set forth in the following description. However, it should be understood that embodiments of the invention can be practiced without these specific details. In other instances, well-known circuits, structures, and techniques have not been shown in detail so as not to obscure the understanding of this description.

[0051] References to "an embodiment," "embodiment," "example embodiment," etc., in this specification indicate that the described embodiment may include a particular feature, structure, or characteristic, but not every embodiment may necessarily include that particular feature, structure, or characteristic. Furthermore, these phrases do not necessarily refer to the same embodiment. Additionally, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is claimed that implementing such a feature, structure, or characteristic in conjunction with other embodiments, whether explicitly described or not, is within the knowledge of those skilled in the art.

[0052] In many mainstream processors, processing matrices is a difficult and / or instruction-intensive task. For example, the rows of a matrix might be placed into multiple packed data (e.g., SIMD or vector) registers and then operated on individually. For instance, depending on the data size, adding two 8x2 matrices might require loading or aggregating into four packed data registers. A first addition is then performed with the packed data registers corresponding to the first row of each matrix, and a second addition is performed with the packed data registers corresponding to the second row of each matrix. The resulting packed data registers are then distributed back into memory. While this approach might be acceptable for small matrices, it is generally unacceptable for larger matrices.

[0053] I. High-level Discussion

[0054] This document describes mechanisms for supporting matrix operations in computer hardware such as central processing units (CPUs), graphics processing units (GPUs), and accelerators. Matrix operations utilize two-dimensional (2-D) data structures representing one or more packed regions of memory, such as registers. Throughout this description, these 2-D data structures are referred to as tiles. Note that a matrix can be smaller than a tile (using less than the entire tile) or utilize multiple tiles (the matrix is ​​larger than the size of any single tile). Throughout this description, a matrix (tile) language is used to indicate operations performed using tiles that affect the matrix; whether the matrix is ​​larger than any single tile is generally irrelevant.

[0055] Each block can be operated on using various operations, such as those detailed herein and including but not limited to: matrix (block) multiplication, block addition, block subtraction, block diagonalization, block zeroing, block transpose, block dot product, block broadcasting, block row broadcasting, block column broadcasting, block multiplication, block multiplication and accumulation, block shifting, etc. Furthermore, support for operators such as scaling and / or biasing can be used in conjunction with these operations or to support future non-numerical applications, such as OpenCL "local memory," data compression / decompression, etc.

[0056] Storage components (such as memory (non-volatile and volatile), registers, caches, etc.) are arranged into blocks with different horizontal and vertical dimensions. For example, a block can have a horizontal dimension of 4 (e.g., 4 rows in a matrix) and a vertical dimension of 8 (e.g., 8 columns in a matrix). Typically, the horizontal dimension is related to the element size (e.g., 2-bit, 4-bit, 8-bit, 16-bit, 32-bit, 64-bit, 128-bit, etc.). Multiple data types (single-precision floating-point, double-precision floating-point, integers, etc.) can be supported.

[0057] A. Exemplary use of configured blocks

[0058] In some embodiments, block parameters can be configured. For example, a given block can be configured to provide block options. Exemplary block options include, but are not limited to: the number of rows in the block, the number of columns in the block, whether the block is VALID (valid), and whether the block consists of a pair of blocks of equal size.

[0059] Figure 1A An example of a configured block configuration is illustrated. As shown, four 1kB blocks, block 0104, block 1106, block 2108, and block 3110, are stored on 4kB application memory 102. In this example, these four blocks are not composed of pairs and each has elements arranged in rows and columns. Blocks 0104 and 1106 have 4-byte elements (e.g., single-precision data) with K rows and N columns, where K equals 8 and N = 32. Blocks 2108 and 3110 have 8-byte elements (e.g., double-precision data) with K rows and N / 2 columns. Since double-precision operands are twice the width of single-precision operands, this configuration is consistent with a palette for providing block options, thus providing at least four names with a total storage of at least 4kB. In operation, load and store operations can be used to load blocks from memory and store blocks into memory. Depending on the instruction encoding scheme used, the amount of available application memory, as well as the size, number, and configuration of available blocks, will vary.

[0060] Figure 1B An example of a configured block configuration is illustrated. As shown, two pairs of 1kB blocks are stored on 4kB application memory 122: the first pair is block t4L 124 and block t4R 126, and the second pair is block t5L 128 and block t5R 130. As shown, the block pairs are divided into left and right blocks. In other embodiments, the block pairs are divided into even and odd blocks. In this example, each of the four blocks has elements arranged in rows and columns. Blocks t4L 124 and t4R 126 have 4-byte elements (e.g., single-precision data) with K rows and N columns, where K equals 8 and N equals 32. Blocks t5L 128 and t5R 130 have 8-byte elements (e.g., double-precision data) with K rows and N / 2 columns. Since double-precision operands are twice the width of single-precision operands, this configuration is consistent with the tray and is used to provide block options, thereby providing at least two names with a total storage of at least 4kB. Figure 1A The four blocks each use four names to name a 1kB block, while Figure 1BThe two pairs of blocks can be specified using two names. In some embodiments, the block instruction accepts the names of the paired blocks as operands. Load and store operations can be used to load blocks from memory and store blocks into memory. The amount of available application memory, as well as the size, number, and configuration of available blocks, will vary depending on the instruction encoding scheme used.

[0061] In some embodiments, block parameters are definable. For example, a "tray" is used to provide block options. Exemplary options include, but are not limited to, the number of block names, the number of bytes in a storage row, the number of rows and columns in the block, etc. For example, the maximum "height" (number of rows) of a block can be defined as:

[0062] Maximum number of rows in a block = Schematic storage / (Number of tray names * Number of bytes per row).

[0063] Accordingly, the application can be programmed such that the fixed use of the name will be able to utilize different storage sizes across implementation methods.

[0064] Block configuration (“TILECONFIG”) directives are used to configure blocks, where specific block usage is defined in the selected tray. This declaration includes the number of block names to be used, the number of rows and columns requested for each name (block), and, in some embodiments, the requested data type for each block. In some embodiments, a consistency check is performed during the execution of the TILECONFIG directive to determine its compliance with tray entry constraints.

[0065] B. Exemplary Block Storage Type

[0066] Figure 2 Several examples of matrix storage are illustrated. In (A), blocks are stored in memory. As shown, each "row" consists of four packed data elements. To move to the next "row," a stride value is used. Note that rows can be stored contiguously in memory. When block storage does not map the row width of the underlying memory array, stride memory access allows access to one row and then the next.

[0067] Loading blocks from memory and storing blocks into memory is typically a step-by-step access from application memory to a packed data line. In some embodiments, the exemplary TILELOAD and TILESTORE instructions, or other instruction references to application memory as TILE operands in load-op instructions, are restartable to handle (up to) 2*page fault lines, unmasked floating-point exceptions, and / or per-instruction interrupts.

[0068] In (B), the matrix is ​​stored in a block of registers, such as packed data registers (Single Instruction, Multiple Data (SIMD), or vector registers). In this example, the block covers three physical registers. Typically, contiguous registers are used; however, this is not always the case.

[0069] In (C), the matrix is ​​stored in a block of non-register memory accessible by the fused multiply-accumulate (FMA) circuitry used in block operations. This memory may be internal to or adjacent to the FMA. Additionally, in some embodiments discussed below, this memory may be used for data elements rather than entire rows or blocks.

[0070] Support parameters for the TMMA architecture are reported via CPUID. In some embodiments, the information list includes maximum height and maximum SIMD size. Configuring the TMMA architecture requires specifying the size of each block, the element size of each block, and the tray identifier. This configuration is performed by executing the TILECONFIG directive.

[0071] Successful execution of the TILECONFIG instruction enables subsequent TILE operators. The TILERELEASEALL instruction clears the block configuration and disables TILE operations (until the next TILECONFIG instruction is executed). In some embodiments, XSAVE, XSTORE, etc., are used for context switching when using blocks. In some embodiments, two XCR0 bits are used in XSAVE, one for TILECONFIG metadata and one corresponding to the actual block payload data.

[0072] TILECONFIG can not only configure block usage but also set status variables indicating that the program is located in the code region of a configured block. Implementation examples may include constraints on other instructions that can be used with block regions, such as not using existing register sets.

[0073] The TILERELEASEALL command is typically used to exit a block region. It requires no parameters and can immediately invalidate all blocks (indicating that the data no longer needs to be saved or restored) and clear the internal state corresponding to the block region.

[0074] In some embodiments, block operations will zero out any rows and columns that exceed the size specified by the block configuration. For example, when writing each row, the block operation will zero out data that exceeds the configured number of columns (factoring in terms of element size). For example, in the case of a 64-byte row and a block configured with 10 rows and 12 columns, an operation to write FP32 elements will write output / result data in 12*4 bytes to each of the first 10 rows, and zero out the remaining 4*4 bytes in each row. The block operation will also completely zero out any rows after the first 10 configured rows. When using a 1K block with 64-byte rows, there will be 16 rows, so in this example, the last 6 rows will also be zeroed out.

[0075] In some embodiments, when loading data, context recovery (e.g., XRSTOR) forces data exceeding the configured rows for a block to be maintained at zero. If no valid configuration exists, all rows are zeroed. The XRSTOR for block data can load garbage in columns exceeding those configured columns. It should be impossible for the XRSTOR to clear columns exceeding the configured number because there is no element width associated with the block configuration.

[0076] Context saving (e.g., XSAVE) exposes the entire TILE (block) storage area when writing it to memory. If XRSTOR loads garbage data into the rightmost part of a block, that data will be saved via XSAVE. XSAVE will write zeros for any lines exceeding the number specified for each block.

[0077] In some embodiments, block instructions are restartable. Memory access operations allow for restarting after a page fault. Computation instructions handling floating-point operations also allow for unmasked floating-point exceptions, where exception masking is controlled by control and / or status registers.

[0078] To support restart instructions after these events, the instructions store information in the boot register, which is detailed below.

[0079] II. Matrix (Block) Operating System

[0080] A. Exemplary Hardware Support

[0081] Figure 3An embodiment of a system utilizing a matrix (block) manipulation accelerator is illustrated. In this illustration, the host processor / processing system 301 transmits commands 311 (e.g., matrix manipulation operations such as arithmetic or matrix manipulation operations, or load and store operations) to a matrix manipulation accelerator 307. However, this is shown in this manner only for discussion purposes. As detailed later, the accelerator 307 may be part of a processing core. Typically, commands 311, as block manipulation operator instructions, refer to blocks as register-register (“reg-reg”) or register-memory (“reg-mem”) formats. Other commands such as TILESTORE, TILELOAD, TILECONFIG, etc., do not perform data manipulation on blocks. Commands may be decoded instructions (e.g., micro-operations) or macro instructions for processing by the accelerator 307.

[0082] In this example, the coherent memory interface 303 is coupled to the host processor / processing system 301 and the matrix operation accelerator 307, allowing them to share memory. Figure 4 and Figure 5 Different embodiments of how to use a matrix operation accelerator to share memory are shown. For example... Figure 4 As shown, the host processor 401 and the matrix operation accelerator circuit 405 share the same memory 403. Figure 5 An example is illustrated where the host processor 501 and the matrix operation accelerator 505 do not share memory but can access each other's memory. For example, processor 501 can access block memory 507 and utilize its host memory 503 as usual. Similarly, matrix operation accelerator 505 can access host memory 503 but more often uses its own memory 507. Note that these memories can be of different types.

[0083] In some embodiments, the matrix operation accelerator 307 includes a plurality of FMAs 309 coupled to a data buffer 305 (in some embodiments, one or more of these buffers 305 are stored in an FMA of a grid as shown). The data buffers 305 buffer blocks loaded from memory and / or blocks to be stored into memory (e.g., using block load or block store instructions). The data buffers may be, for example, a plurality of registers. Typically, these FMAs are arranged as a grid of linked FMAs 309s capable of reading and writing blocks. In this example, the matrix operation accelerator 307 is to perform a matrix multiplication operation using blocks T0, T1, and T2. At least one of the blocks is contained in an FMA grid 309. In some embodiments, all blocks in the operation are stored in an FMA grid 309. In other embodiments, only a subset is stored in an FMA grid 309. As shown, T1 is contained while T0 and T2 are not. Note that A, B, and C refer to the matrices of these blocks, which may or may not occupy the entire space of the blocks.

[0084] Figure 6 An example of using a block-based matrix multiplication accumulation operation (“TMMA”) is illustrated.

[0085] The number of rows in the matrix (block A 601) matches the number of serial (chained) FMAs that include computational delays. The implementation is free to recycle on grids with smaller heights, but the computation remains unchanged.

[0086] The source / destination vectors originate from a block with N rows (block C 605), and the grid of FMA 611 performs N vector matrix operations to obtain the complete instruction for the matrix multiplication of the block. Block B 603 is another vector source and provides "broadcast" terms to FMA in each stage.

[0087] In operation, in some embodiments, the elements of matrix B (stored in block B 603) are scattered across a rectangular grid of FMAs. Matrix B (stored in block A 601) transposes the elements in its rows to match the column size of the rectangular grid of the FMAs. At each FMA in the grid, the elements of A and B are multiplied and added to the addend of the input (from above in the diagram), and the sum of the outputs is passed to the next row of the FMA (or the final output).

[0088] The latency of a single step is proportional to K (the row height of matrix B), and the associated TMMA typically has enough source-destination rows (in a single block or across blocks) to hide this latency. Implementations can also segment the SIMD (packed data element) size M (the row height of matrix A) across time steps, but this only changes the constant multiplied by K. When the program specifies a K smaller than the maximum value listed in TMACC, implementations are free to implement this using "masking" or "early outs."

[0089] The latency of the entire TMMA is proportional to N*K. The repetition rate is proportional to N. The number of MACs for each TMMA instruction is N*K*M.

[0090] Figure 7 An embodiment of a subset of the iterative execution of a chained fused multiply-accumulate instruction is illustrated. Specifically, this illustrates the execution circuitry for iteratively executing the position of a packaged data element at the destination. In this embodiment, the chained fused multiply-accumulate operates on a signed source, where the accumulator is 2 x the input data size.

[0091] The first signed source (source 1701) and the second signed source (source 2703) each have four packed data elements. Each of these packed data elements stores signed data such as floating-point data. The third signed source (source 3709) has two packed data elements, each of which stores signed data. The sizes of the first and second signed sources 701 and 703 are half the size of the third signed source (initial value or previous result) 709. For example, the first and second signed sources 701 and 703 can have 32-bit packed data elements (e.g., single-precision floating-point), while the third signed source 709 can have 64-bit packed data elements (e.g., double-precision floating-point).

[0092] This example only shows the positions of the two most valid packed data elements from the first and second signed sources 701 and 703, and the most valid packed data element from the third signed source 709. Of course, other packed data element positions will also be processed.

[0093] As illustrated, packaged data elements are processed in pairs. For example, multiplier circuit 705 multiplies the data at the most valid packaged data element locations of the first and second signed sources 701 and 703, and multiplier circuit 707 multiplies the data at the second most valid packaged data element locations of the first and second signed sources 701 and 703. In some embodiments, these multiplier circuits 705 and 707 are reused for other packaged data element locations. In other embodiments, additional multiplier circuitry is used to enable parallel processing of packaged data elements. In some contexts, parallel execution is performed using a channel of size 709 with a signed third source. Adder circuit 711 is used to add the results of each of the multiplications.

[0094] (Using a different adder 713 or the same adder 711) the sum of the multiplication results is added to the data at the position of the most valid packed data element from the signed source 3709.

[0095] Finally, the result of the second addition is stored in the signed destination 715 in the packed data element position corresponding to the packed data element position used from the signed third source 709, or the result of the second addition is passed to the next iteration, if there is a next iteration. In some embodiments, a write mask is applied to the storage such that the storage occurs if the corresponding write mask (bit) is set, and does not occur if it is not set.

[0096] Figure 8 An embodiment of a subset of the iterative execution of a chained fused multiply-accumulate instruction is illustrated. Specifically, this illustrates the execution circuitry for iteratively executing the position of a packaged data element at the destination. In this embodiment, the chained fused multiply-accumulate operates on a signed source, where the accumulator is 2 x the input data size.

[0097] The first signed source (source 1801) and the second signed source (source 2803) each have four packed data elements. Each of these packed data elements stores signed data such as integer data. The third signed source (source 3809) has two packed data elements, each of which stores signed data. The sizes of the first and second signed sources 801 and 803 are half the size of the third signed source 809. For example, the first and second signed sources 801 and 803 can have 32-bit packed data elements (e.g., single-precision floating-point), and the third signed source 809 can have 64-bit packed data elements (e.g., double-precision floating-point).

[0098] This example only shows the positions of the two most valid packed data elements from the first and second signed sources 801 and 803, and the most valid packed data element from the third signed source 809. Of course, other packed data element positions will also be processed.

[0099] As illustrated, packed data elements are processed in pairs. For example, multiplier circuit 805 multiplies the data at the most valid packed data element positions of the first and second signed sources 801 and 803, and multiplier circuit 807 multiplies the data at the second most valid packed data element positions of the first and second signed sources 801 and 803. In some embodiments, these multiplier circuits 805 and 807 are reused for other packed data element positions. In other embodiments, additional multiplier circuitry is used to enable parallel processing of packed data elements. In some contexts, parallel execution is performed using channels of size 809 with a signed third source (initial value or result of previous iterations). An adder / saturation circuit 813 is used to add the result of each of the multiplications to the signed third source 809.

[0100] When the addition results in an excessively large value, the adder / saturation (accumulator) circuit 813 preserves the sign of the operand. Specifically, saturation evaluation occurs on the infinite-precision result between the multiplexed sum and the write to the destination or the next iteration. When the accumulator 813 is floating-point and the input is an integer, the sum of the products and the floating-point accumulator input value are converted to an infinite-precision value (a fixed-point number with hundreds of digits), the multiplication result is added to the third input, and a single rounding to the actual accumulator type is performed.

[0101] Unsigned saturation means that the output value is restricted to the maximum unsigned number (all 1s) for the width of the element. Signed saturation means that the value is restricted to the range between the minimum negative number and the maximum positive number for the width of the element (e.g., for a byte, the range is from -128 (=-2^7) to 127 (=2^7-1)).

[0102] The saturation check and the result of the addition are either stored in the signed result 815 in the packed data element position corresponding to the position of the packed data element used from the signed third source 809, or the saturation check and the result of the addition are passed to the next iteration, if there is a next iteration. In some embodiments, a write mask is applied to the storage such that the storage occurs if the corresponding write mask (bit) is set, and does not occur if it is not set.

[0103] Figure 9An embodiment of a subset of the iterative execution of a chained fused multiply-accumulate instruction is illustrated. Specifically, this illustrates the execution circuitry for iteratively executing the position of a packaged data element at the destination. In this embodiment, the chained fused multiply-accumulate operates on both signed and unsigned sources, where the accumulator is 4 x the input data size.

[0104] The first signed source (source 1901) and the second unsigned source (source 2903) each have four packed data elements. Each of these packed data elements contains data such as floating-point or integer data. The third signed source (initial value or result 915) has packed data elements in which signed data is stored. The sizes of the first and second sources 901 and 903 are one-quarter of the size of the third signed source 915. For example, the first and second sources 901 and 903 may have 16-bit packed data elements (e.g., words), while the third signed source 915 may have 64-bit packed data elements (e.g., double-precision floating-point or 64-bit integers).

[0105] This illustration shows the four most valid packed data element positions for the first and second sources 901 and 903, as well as the most valid packed data element position for the third signed source 915. Other packed data element positions, if any, will also be processed.

[0106] As illustrated, the packed data elements are processed in groups of four. For example, multiplier circuit 905 multiplies the data from the most significant packed data element positions of the first and second sources 901 and 903, multiplier circuit 907 multiplies the data from the second most significant packed data element positions of the first and second sources 901 and 903, multiplier circuit 909 multiplies the data from the third most significant packed data element positions of the first and second sources 901 and 903, and multiplier circuit 910 multiplies the data from the least significant packed data element positions of the first and second sources 901 and 903. In some embodiments, the signed packed data elements of the first source 901 are sign-extended, and the unsigned packed data elements of the second source 903 are zero-extended before multiplication.

[0107] In some embodiments, these multiplier circuits 905-910 are reused for other locations of packed data elements. In other embodiments, additional multiplier circuitry is used to enable parallel processing of packed data elements. In some contexts, parallel execution is performed using a channel of size 915 with a signed third source. An adder circuit 911 is used to add the results of each of the multiplications.

[0108] (Using a different adder 913 or the same adder 911) the sum of the multiplication results is added to the data at the position of the most valid packed data element from the signed source 3915.

[0109] Finally, the result 919 of the second addition is either stored in the signed destination of the packed data element position corresponding to the packed data element position used from the signed third source 915, or the result 919 of the second addition is passed to the next iteration. In some embodiments, a write mask is applied to the storage such that the storage occurs if the corresponding write mask (bit) is set, and does not occur if it is not set.

[0110] Figure 10 An embodiment of a subset of the iterative execution of a chained fused multiply-accumulate instruction is illustrated. Specifically, this illustrates the execution circuitry for iteratively executing the position of a packaged data element at the destination. In this embodiment, the chained fused multiply-accumulate operates on both signed and unsigned sources, where the accumulator is 4 x the input data size.

[0111] The first signed source (source 11001) and the second unsigned source (source 21003) each have four packed data elements. Each of these packed data elements stores data such as floating-point or integer data. The third signed source (initial or previous result 1015) has packed data elements in which signed data is stored. The sizes of the first and second sources 1001 and 1003 are one-quarter of the size of the third signed source 1015. For example, the first and second sources 1001 and 1003 may have 16-bit packed data elements (e.g., words), while the third signed source 1015 may have 64-bit packed data elements (e.g., double-precision floating-point or 64-bit integers).

[0112] This illustration shows the four most valid packed data element positions for the first and second sources 1001 and 1003, as well as the most valid packed data element position for the third signed source 1015. Other packed data element positions, if any, will also be processed.

[0113] As illustrated, the packed data elements are processed in groups of four. For example, multiplier circuit 1005 multiplies the data from the most significant packed data element positions of the first and second sources 1001 and 1003, multiplier circuit 1007 multiplies the data from the second most significant packed data element positions of the first and second sources 1001 and 1003, multiplier circuit 1009 multiplies the data from the third most significant packed data element positions of the first and second sources 1001 and 1003, and multiplier circuit 1011 multiplies the data from the least significant packed data element positions of the first and second sources 1001 and 1003. In some embodiments, the signed packed data elements of the first source 1001 are sign-extended, and the unsigned packed data elements of the second source 1003 are zero-extended before multiplication.

[0114] In some embodiments, these multiplier circuits 1005-1011 are reused for other packed data element locations. In other embodiments, additional multiplier circuitry is used to enable parallel processing of packed data elements. In some contexts, parallel execution is performed using a channel with the size of a signed third source 1015. An adder / saturation circuit 1013 is used to add the sum of the multiplication results to the data from the most valid packed data element location of the signed source 31015.

[0115] When the addition yields a value that is too large or too small for signed saturation, the adder / saturation (accumulator) circuit 1013 preserves the sign of the operand. Specifically, saturation evaluation occurs on the infinite-precision result between the multiplexed addition and the write to the destination. When the accumulator 1013 is floating-point and the input is an integer, the sum of the products and the floating-point accumulator input value are converted to an infinite-precision value (a fixed-point number with hundreds of digits), the multiplication result is added to the third input, and a single rounding to the actual accumulator type is performed.

[0116] The saturation check and the result of the addition 1019 are either stored in a signed destination corresponding to the location of the packed data element used from the signed third source 1015, or the saturation check and the result of the addition 1019 are passed to the next iteration. In some embodiments, a write mask is applied to the storage such that the storage occurs if the corresponding write mask (bit) is set, and does not occur if it is not set.

[0117] Figure 11 An example of a SIMD implementation of a power of 2 according to an embodiment is illustrated, wherein the accumulator uses an input size larger than the input to the multiplier. Note that the source and accumulator values ​​(to the multiplier) can be signed or unsigned values. For an accumulator with an input size of 2X (in other words, the accumulator input value is twice the size of the packed data element of the source), Table 1101 illustrates different configurations. For a source of size byte, the accumulator uses a word or a 16-bit half-precision floating-point (HPFP) value. For a source of size word, the accumulator uses a 32-bit integer or a 32-bit single-precision floating-point (SPFP) value. For a source of size SPFP or a 32-bit integer, the accumulator uses a 64-bit integer or a 64-bit double-precision floating-point (DPFP) value.

[0118] For an accumulator with an input size of 4X (in other words, the accumulator input value is four times the size of the packed data element of the source), Table 1103 illustrates different configurations. For sources of size byte, the accumulator uses a 32-bit integer or a 32-bit single-precision floating-point (SPFP) value. In some embodiments, for sources of size word, the accumulator uses a 64-bit integer or a 64-bit double-precision floating-point (DPFP) value.

[0119] For an accumulator with an input size of 8X (in other words, the accumulator input value is eight times the size of the source's packed data element), Table 1105 illustrates different configurations. For sources of bytes in size, the accumulator uses 64-bit integers.

[0120] As implied above, the matrix operation circuitry can be included in the core or used as an external accelerator. Figure 12 An embodiment of a system utilizing matrix operation circuitry is illustrated. In this embodiment, multiple entities are coupled to a ring interconnect 1245.

[0121] Multiple cores 1201, 1203, 1205, and 1207 provide non-block-based instruction support. In some embodiments, matrix operation support 1251 is provided in core 1203, and in other embodiments, matrix operation circuitry 1211 and 1213 are accessible on a ring interconnect 1245.

[0122] Additionally, one or more memory controllers 1223-1225 are provided to communicate with memories 1233 and 1231 on behalf of core and / or matrix operation circuitry.

[0123] Figure 13 An embodiment of a processor core pipeline supporting matrix operations using blocks is illustrated. Branch prediction and decoding circuitry 1303 performs branch prediction, instruction decoding, and / or both of the instructions from instructions stored in instruction store 1301. For example, the instructions detailed herein may be stored in instruction store. In some embodiments, separate circuitry is used for branch prediction, and in some embodiments, microcode 1305 is used to decode at least some instructions into one or more micro-operations, microcode entry points, microinstructions, other instructions, or other control signals. Branch prediction and decoding circuitry 1303 can be implemented using a variety of different mechanisms. Examples of suitable mechanisms include, but are not limited to, lookup tables, hardware implementations, programmable logic arrays (PLAs), microcode read-only memory (ROM), etc.

[0124] Branch prediction and decoding circuitry 1303 is coupled to rename / allocator circuitry 1307, which in some embodiments is coupled to scheduler circuitry 1309. In some embodiments, these circuits provide register renaming, register allocation, and / or scheduling functionality by performing one or more of the following: 1) renaming logical operand values ​​to physical operand values ​​(e.g., a register alias table in some embodiments), 2) assigning status bits and flags to decoded instructions, and 3) scheduling decoded instructions for execution on execution circuitry outside the instruction pool (e.g., using a reserved station in some embodiments).

[0125] Scheduler circuitry 1309 represents any number of different schedulers, including reservation stations, central instruction windows, etc. Scheduler circuitry 1309 is coupled to or includes one or more physical register files 1315. Each of the one or more physical register files 1315 represents one or more physical register files, where different physical register files store one or more different data types, such as scalar integers, scalar floating-point numbers, packed integers, packed floating-point numbers, vector integers, vector floating-point numbers, status (e.g., instruction pointer, which is the address of the next instruction to be executed), blocks, etc. In one embodiment, physical register files 1315 include vector register circuitry, write mask register circuitry, and scalar register circuitry. These register circuitry can provide architectural vector registers, vector mask registers, and general-purpose registers. One or more physical register files 1315 are overlapped by retirement circuitry 1317 to illustrate various ways in which register renaming and out-of-order execution can be implemented (e.g., using one or more reorder buffers and one or more retirement register files; using one or more future files, one or more history buffers and one or more retirement register files; using register mapping and register pools; etc.). Retirement circuitry 1317 and one or more physical register files 1315 are coupled to one or more execution circuitry 1311.

[0126] Although register renaming is described in the context of out-of-order execution, it should be understood that register renaming can be used in ordered architectures. While the illustrated processor embodiments may also include separate instruction and data cache units and a shared L2 cache unit, alternative embodiments may have a single internal cache for both instructions and data, such as, for example, a Level 1 (L1) internal cache or a multi-level internal cache. In some embodiments, the system may include a combination of internal caches and external caches located outside the core and / or processor. Alternatively, all caches may be located outside the core and / or processor.

[0127] Execution circuitry 1311 comprises one or more execution circuits 1321, 1323, and 1327, and one or more memory access circuits 1325. Execution circuits 1321, 1323, and 1327 perform various operations (e.g., shift, addition, subtraction, multiplication) and operations on various types of data (e.g., scalar floating-point, packed integer, packed floating-point, vector integer, vector floating-point). While some embodiments may include multiple execution units dedicated to a particular function or group of functions, other embodiments may include a single execution unit or multiple execution units that perform all functions. Scalar circuitry 1321 performs scalar operations, vector / SIMD circuitry 1323 performs vector / SIMD operations, and matrix operation circuitry 1327 performs the matrix (block) operations detailed herein.

[0128] As an example, the exemplary register renaming, out-of-order release / execution core architecture can implement the pipeline as follows: 1) The instruction fetch circuit performs the fetch and length decoding phase; 2) The branch and decode circuit 1303 performs the decoding phase; 3) The rename / allocator circuit 1307 performs the allocation and rename phases; 4) The scheduler circuit 1309 performs the scheduling phase; 5) The physical register files and memory units coupled to or included in the scheduler circuit 1309 and the rename / allocation circuit 1307 perform the register read / memory read phase; the execution circuit 1311 performs the execution phase; 6) The memory units and physical register file units perform the write-back / memory write phase; 7) Various units may involve exception handling phases; and 8) The retirement unit and physical register file units perform the commit phase.

[0129] The core may support one or more instruction sets (e.g., the x86 instruction set (with some extensions added in newer versions); the MIPS instruction set of MIPS Technologies, Sunnyvale, California; the ARM instruction set of ARM Holdings, Sunnyvale, California (with optional additional extensions such as NEON)), including one or more instructions described herein. In one embodiment, core 1390 includes logic for supporting packaged data instruction set extensions (e.g., AVX1, AVX2), thereby allowing the use of packaged data to perform operations used by many multimedia applications.

[0130] It should be understood that a core can support multithreading (executing two or more sets of operations or threads in parallel), and can do so in various ways, including time-sliced ​​multithreading, concurrent multithreading (where a single physical core provides a logical core for each of the threads being concurrently multithreaded by the physical core), or combinations thereof (e.g., time-slice extraction and decoding followed by subsequent concurrent multithreading, such as in...). (like in hyper-threading technology).

[0131] Figure 14 An embodiment of a processor core pipeline supporting matrix operations using blocks is illustrated. Branch prediction and decoding circuitry 1403 performs branch prediction, instruction decoding, and / or both of the instructions from instructions stored in instruction store 1401. For example, the instructions detailed herein may be stored in instruction store. In some embodiments, separate circuitry is used for branch prediction, and in some embodiments, microcode 1405 is used to decode at least some instructions into one or more micro-operations, microcode entry points, microinstructions, other instructions, or other control signals. Branch prediction and decoding circuitry 1403 can be implemented using a variety of different mechanisms. Examples of suitable mechanisms include, but are not limited to, lookup tables, hardware implementations, programmable logic arrays (PLAs), microcode read-only memory (ROM), etc.

[0132] Branch prediction and decoding circuitry 1403 is coupled to rename / allocator circuitry 1407, which in some embodiments is coupled to scheduler circuitry 1409. In some embodiments, these circuits provide register renaming, register allocation, and / or scheduling functionality by performing one or more of the following: 1) renaming logical operand values ​​to physical operand values ​​(e.g., a register alias table in some embodiments), 2) assigning status bits and flags to decoded instructions, and 3) scheduling decoded instructions for execution on execution circuitry outside the instruction pool (e.g., using a reserved station in some embodiments).

[0133] Scheduler circuitry 1409 represents any number of different schedulers, including reservation stations, central instruction windows, etc. Scheduler circuitry 1409 is coupled to or includes one or more physical register files 1415. Each of the one or more physical register files 1415 represents one or more physical register files, where different physical register files store one or more different data types, such as scalar integers, scalar floating-point numbers, packed integers, packed floating-point numbers, vector integers, vector floating-point numbers, status (e.g., instruction pointer, which is the address of the next instruction to be executed), blocks, etc. In one embodiment, physical register files 1415 include vector register circuitry, write mask register circuitry, and scalar register circuitry. These register circuitry can provide architectural vector registers, vector mask registers, and general-purpose registers. One or more physical register files 1415 are overlapped by retirement circuitry 1417 to illustrate various ways in which register renaming and out-of-order execution can be implemented (e.g., using one or more reorder buffers and one or more retirement register files; using one or more future files, one or more history buffers and one or more retirement register files; using register mapping and register pools; etc.). Retirement circuitry 1417 and one or more physical register files 1415 are coupled to one or more execution circuitry 1411.

[0134] Although register renaming is described in the context of out-of-order execution, it should be understood that register renaming can be used in ordered architectures. While the illustrated processor embodiments may also include separate instruction and data cache units and a shared L2 cache unit, alternative embodiments may have a single internal cache for both instructions and data, such as, for example, a Level 1 (L1) internal cache or a multi-level internal cache. In some embodiments, the system may include a combination of internal caches and external caches located outside the core and / or processor. Alternatively, all caches may be located outside the core and / or processor.

[0135] The execution circuit 1411 is a set of one or more execution circuits 1427 and a set of one or more memory access circuits 1425. The execution circuits 1427 perform the matrix (block) operations detailed herein.

[0136] As an example, the exemplary register renaming, out-of-order release / execution core architecture can implement the pipeline as follows: 1) The instruction fetch circuit performs the fetch and length decoding phase; 2) The branch and decode circuit 1403 performs the decoding phase; 3) The rename / allocator circuit 1407 performs the allocation and rename phases; 4) The scheduler circuit 1409 performs the scheduling phase; 5) The physical register files and memory units coupled to or included in the scheduler circuit 1409 and the rename / allocation circuit 1407 perform the register read / memory read phase; the execution circuit 1411 performs the execution phase; 6) The memory units and physical register file units perform the write-back / memory write phase; 7) Various units may involve exception handling phases; and 8) The retirement unit and physical register file units perform the commit phase.

[0137] The core may support one or more instruction sets (e.g., the x86 instruction set (with some extensions added in newer versions); the MIPS instruction set of MIPS Technologies, Sunnyvale, California; the ARM instruction set of ARM Holdings, Sunnyvale, California (with optional additional extensions such as NEON)), including one or more instructions described herein. In one embodiment, core 1490 includes logic for supporting packaged data instruction set extensions (e.g., AVX1, AVX2), thereby allowing the use of packaged data to perform operations used by many multimedia applications.

[0138] It should be understood that a core can support multithreading (executing two or more sets of operations or threads in parallel), and can do so in various ways, including time-sliced ​​multithreading, concurrent multithreading (where a single physical core provides a logical core for each of the threads being concurrently multithreaded by the physical core), or combinations thereof (e.g., time-slice extraction and decoding followed by subsequent concurrent multithreading, such as in...). (like in hyper-threading technology).

[0139] B. Layout

[0140] Throughout this description, row-major data layout is used to represent data. Column-major users should translate the terminology according to their preference. Figure 15 Examples of matrices represented in row-major and column-major order are shown. As shown in the figure, matrix A is a 2×3 matrix. When this matrix is ​​stored in row-major order, the data elements in a row are consecutive. When this matrix is ​​stored in column-major order, the data elements in a column are consecutive. A T *B T =(BA) T This is a well-known matrix property, where the superscript T indicates transpose. Reading column-major data as row-major data causes the matrix to appear as a transpose matrix.

[0141] In some embodiments, row-major semantics are utilized in the hardware, and column-major data is used to exchange operand order, resulting in a transpose of the matrix, but which is a correct, untransposed matrix for subsequent column-major reads from memory.

[0142] For example, if there are two column-major matrices to be multiplied, then:

[0143] abgik ag+bh ai+bj ak+bl

[0144] cd* hjl= cg+dh cl+dj ck+dl

[0145] ef eg+fh ei+fj ek+fl

[0146] (3×2) (2x3) (3x3)

[0147] The input matrix will be stored in a (column-major) linear memory, such as:

[0148] acebdf

[0149] and

[0150] ghi jk l

[0151] Reading those matrices in row-major order with dimensions of 2x3 and 3x2, they will be displayed as:

[0152] ace and gh

[0153] bdfij

[0154] kl

[0155] Change the order and perform matrix multiplication:

[0156] ghace ag+bh cg+dh eg+fh

[0157] ij * bdf= ai+bj ci+dj ei+fj

[0158] kl ak+bl ck+d lek+fl

[0159] The transpose matrix is ​​output and can then be stored in row-major order:

[0160] ag+bh cg+dh eg+fh ai+bj ci+dj ei+fj ak+bl ck+dl ek+fl

[0161] And it is used in subsequent column-major calculations; it is a correct non-transpose matrix:

[0162]

[0163] III. Exemplary Use

[0164] Figure 16 An example of matrix (block) usage is illustrated. In this example, matrix C 1601 comprises two blocks, matrix A 1603 comprises one block, and matrix B 1605 comprises two blocks. The diagram shows an example of the inner loop of the algorithm used to compute matrix multiplication. In this example, two result blocks tmm0 and tmm1 from matrix C 1601 are used to accumulate intermediate results. A block (tmm2) from matrix A 1603 is reused twice when it is multiplied by the two blocks from matrix B 1605. The pointers used to load the new A block and the two new B blocks are in the direction indicated by the arrows. The outer loop, not shown, adjusts the pointer used for block C.

[0165] The exemplary code shown includes the use of block configuration instructions, which are executed to configure block usage, load blocks, load a loop for processing blocks, store blocks in memory, and release block usage.

[0166] Figure 17 An example of the use of a matrix (block) is illustrated. At 1701, block usage is configured. For example, the TILECONFIG instruction is executed to configure block usage, including setting the number of rows and columns for each block. Typically, at least one matrix (block) is loaded from memory at 1703. At 1705, at least one matrix (block) operation is performed using the matrix (block). At 1707, at least one matrix (block) is stored out of memory, and a context switch may occur at 1709.

[0167] IV. Exemplary Configuration

[0168] A. Block configuration hardware support

[0169] As discussed above, block usage typically needs to be configured before use. For example, it may not be necessary to use all rows and columns completely. In some embodiments, not configuring these rows and columns not only saves power, but the configuration can be used to determine whether the operation will produce errors. For example, if M and L are not the same, matrix multiplication of the form (N×M)*(L*N) will generally not work.

[0170] In some embodiments, block support must be configured before using a matrix that utilizes blocks. This includes configuring the number of rows and columns per block, the blocks to be used, etc. The TILECONFIG instruction is an improvement to the computer itself because it provides support for configuring the computer to use a matrix accelerator (either as part of a processor core or as an external device). Specifically, execution of the TILECONFIG instruction causes the configuration to be retrieved from memory and applied to the matrix (block) settings within the matrix accelerator.

[0171] i. Block Usage Configuration

[0172] Figure 18 Support for configurations for block usage according to an embodiment is illustrated. Memory 1801 contains a description 1803 of the matrices (blocks) to be supported.

[0173] The execution circuitry 1811 of the processor / core 1805 stores various aspects of the block description 1803 into the block configuration 1817. The block configuration 1817 details which blocks for the tray are configured (the number of rows and columns in each block) and the markers indicating that the matrix support is in use. Specifically, the instruction execution resource 1811 is configured to use blocks as specified in the block configuration 1817. The instruction execution resource may also include machine-specific registers or configuration registers to indicate block usage. Additional values, such as "in use" and "starting value," are also set. The block configuration 1817 utilizes one or more registers 1819 to store block usage and configuration information.

[0174] Figure 19 An example of a description of the matrix (block) to be supported is shown. This is the description to be stored when the STTILECFG instruction is executed. In this example, each field is one byte. In byte [0], tray ID 1901 is stored. The tray ID is used to index tray table 1813, which stores the number of bytes in the block associated with that ID and the number of bytes per row in the block, as defined by the configuration.

[0175] Byte 1 stores the value 1903 to be stored in the "startRow" register, and byte 2 stores the value 1905 to be stored in the "startP" register. To support restart instructions after these events, the instructions store information in these registers. The startRow value indicates the row to be used for restarting. The startP value indicates the in-row position to be stored when the operation is used, and in some embodiments, indicates the lower half of the row (in the lower block of the pair) or the upper half of the row (in the upper block of the pair). Generally, the position in the row (column) is not required.

[0176] In the event of TILECONFIG and STTILECFG exceptions, successful execution of matrix (block) instructions will set both startRow and startP to zero.

[0177] At any time before an interrupted matrix (block) instruction is restarted, the software is responsible for resetting the startRow and startP values ​​to zero. For example, an unmasked floating-point exception handler might decide to complete the operation in the software and change the program counter value to another instruction, typically the next instruction. In this case, the software exception handler must reset the startRow and startP values ​​from the exception provided to it by the operating system before it can continue program execution. Subsequently, the operating system will reload those values ​​using recovery instructions.

[0178] Byte 3 indicates the pair of storage blocks (1b per block) 1907.

[0179] Bytes 16-17 store the number of rows (1913) and columns (1915) for block 0, and bytes 18-19 store the number of rows and columns for block 1, and so on. In other words, each 2-byte group specifies the number of rows and columns for a block. If block parameters are not specified using 2-byte groups, they should have a value of zero. Specifying block parameters for more blocks than the implementation limit or tray limit will result in a failure. Unconfigured blocks are set to an initial state with 0 rows and 0 columns.

[0180] Finally, the configuration in memory usually ends with a delimiter, such as several consecutive bytes all being zero.

[0181] ii. Exemplary blocks and block configuration storage

[0182] Figures 20(A)-(D) illustrate examples of register(s) 1819. Figure 20(A) illustrates multiple registers 1819. As shown, each block (TMM0 2001...TMMN 2003) has a separate register for each register storing the row and column size of that particular block. StartP and StartRow are stored in separate registers 2011 and 2013. One or more status registers 2015 (e.g., TILES_CONFIGURED = 1) are set to indicate that the block is configured for use.

[0183] Figure 20(B) illustrates multiple registers 1819. As shown, each block has separate registers for its rows and columns. For example, TMM0 row configuration 2021, TMM0 column configuration 2023, StartP, and StartRow are stored in separate registers 2011 and 2013. One or more status registers 2015 (e.g., TILES_CONFIGURED = 1) are set to indicate that the block is configured for use.

[0184] Figure 20(C) illustrates a single register 1819. As shown, this register stores block configurations (rows and columns of each block) 2031, StartP 2011, and StartRow 2013, which are stored in a single register as a packed data register. One or more status registers 2015 (e.g., TILES_CONFIGURED = 1) are set to indicate that the block is configured for use.

[0185] Figure 20(D) illustrates multiple registers 1819. As shown, a single register stores block configurations (rows and columns of each block) 2031. StartP and StartRow are stored in separate registers 2011 and 2013. One or more status registers 2015 (e.g., TILES_CONFIGURED = 1) are set to indicate that a block is configured for use.

[0186] Other combinations can be envisioned, such as combining the start registers into individual registers in which they are shown separately, and so on.

[0187] B.TDP4BIT

[0188] A common matrix operation is dot product, such as the dot product between elements of two blocks stored in a set of registers or in memory. This article details the TDP4BIT instruction and an embodiment of its execution. The TDP4BIT instruction is an improvement on the computer itself because it provides support for performing dot product between elements of two matrices within a single matrix (block). Specifically, the execution of the TDP4BIT instruction performs a dot product between elements of a first source matrix (block) and a second source matrix (block) and stores the result in a destination matrix (block). The size of the data elements to be loaded can vary depending on the instruction and block support. Exemplary sizes include, but are not limited to, 16-bit, 32-bit, 64-bit, 128-bit, 256-bit, etc. However, the TDP4BIT instruction operates on nibbles within a four-word element. In some embodiments, elements in rows of the destination matrix (block) that do not have corresponding columns in the source matrix (block) are zeroed out.

[0189] I. Exemplary Execution

[0190] Figure 21 An exemplary execution of the TDP4BIT instruction is illustrated. The TDP4BIT instruction format includes fields for the opcode and identifiers for a first source, a second source, and a destination. Each identifier identifies a matrix (block) where the PAIR parameter is set to FALSE. The identified destination matrix (block) has M rows and N columns. The identified first source matrix (block) has M rows and K columns, and the identified second source matrix (block) has K rows and N columns. As shown in the figure, the execution circuit 2108 receives the decoded TDP4BIT instruction 2102. In some embodiments, the execution circuit 2108 uses the FMA grid 2110 to perform K processes on each element (M, N) of the identified destination matrix 2118. The process includes multiplying each half-byte of the double-word element (M, K) of the identified first source matrix by the corresponding half-byte of the double-word element (K, N) of the identified second source matrix using multipliers 2112A-H to generate eight products; and accumulating the previous contents of the double-word elements (M, N) of the identified destination matrix using accumulator 2114 and saturating the eight products using saturation circuit 2116.

[0191] In some embodiments, multipliers 2112A-H perform all multiplications in parallel. In some embodiments, multipliers 2112A-H perform all multiplications serially over one or more additional cycles.

[0192] In some embodiments, the execution circuit 2108 periodically saves its state so that, in the event of a failure during operation, the execution circuit 2108 can resume execution after the failure is resolved and continue execution from where it stopped. In such embodiments, the saved state includes one or more of row pointers, block pointers, byte pointers, and element pointers to identify the current destination block element being loaded.

[0193] As detailed above, the source and destination matrices (blocks) can be loaded into a register set, a location in memory, or other storage accessible to the execution circuitry. However, as shown in the figure, the identified source and destination matrices (blocks) are stored in a register set.

[0194] As shown in the figure, instruction 2102 includes the TDP4BIT opcode, the destination block identifier "tdest", and the first and second source block identifiers "tsrc1" and "tsrc2".

[0195] In some embodiments, a matrix (block) is configured to use only a subset of the possible rows and columns. For example, a matrix (block) may have up to 16 rows and columns available, but only 4 of each are used. Typically, each matrix (block) is configured by executing configuration instructions before it is used.

[0196] II. (One or more) Exemplary instruction formats

[0197] An embodiment of the format used for the TDP4BIT instruction is TDP4BIT tdest, tsrc1, tsrc2. In some embodiments, TDP4BIT is the opcode mnemonic for the instruction, where "4BIT" indicates operation on a 4-bit data nibble. In some embodiments, the tdest field is an R / M value (such as...) Figure 25A -B of 2546), the tsrc1 field is Figure 25A -B REG 2544. In some embodiments, the TDP4BIT opcode includes an indicator, such as a [U,S] prefix or suffix, to indicate whether each of the identified first and second sources is signed or unsigned.

[0198] In some embodiments, the instruction encoding includes proportional-indexed-base (SIB) type memory addressing operands, which indirectly identify multiple indexed destination locations in memory (e.g., Figure 25A -B field 2550). In one embodiment, the SIB memory operand may include encoding that identifies a base address register. The contents of the base address register may represent a base address in memory, used to calculate the address of a specific destination location in memory. For example, the base address may be the address of a first location in a potential destination location block for extended vector instructions. In one embodiment, the SIB memory operand may include encoding that identifies an index register. Each element of the index register may specify an index or offset value that can be used to calculate the address of the corresponding destination location within a potential destination location block based on the base address. In one embodiment, the SIB memory operand may include encoding that specifies a scaling factor to be applied to each index value when calculating the corresponding destination address. For example, if a scaling factor of 4 is encoded in the SIB memory operand, each index value obtained from an element in the index register may be multiplied by 4 and then added to the base address to calculate the destination address.

[0199] In one embodiment, a SIB-type memory operand of the form vm32{x, y, z} can identify a vector array of memory operands specified using SIB-type memory addressing. In this example, a common base address register, a constant scaling factor, and a vector index register containing individual elements (each of which is a 32-bit index value) are used to specify the array of memory addresses. The vector index register can be a 128-bit register (e.g., XMM) register (vm32x), a 256-bit register (e.g., YMM) register (vm32y), or a 512-bit register (e.g., ZMM) register (vm32z). In another embodiment, a SIB-type memory operand of the form vm64{x, y, z} can identify a vector array of memory operands specified using SIB-type memory addressing. In this example, a common base address register, a constant scaling factor, and a vector index register containing individual elements (each of which is a 64-bit index value) are used to specify the array of memory addresses. The vector index register can be a 128-bit register (e.g., XMM) register (vm64x), a 256-bit register (e.g., YMM) register (vm64y), or a 512-bit register (e.g., ZMM) register (vm64z).

[0200] III. (One or more) Exemplary Execution Methods

[0201] Figure 22 An example of a processor executing a TDP4BIT instruction is illustrated. The instruction is fetched at 2201. For example, a TDP4BIT instruction is fetched, which has fields for an opcode, a destination identifier for identifying an M×N destination matrix, a first source identifier for identifying an M×K first source matrix, and a second source identifier for identifying a K×N second source matrix, each of which contains a double-word element. In some embodiments, the instruction is fetched from an instruction cache via fetch circuitry. The opcode of the TDP4BIT instruction indicates the execution of the packing number product of the element positions of the identified first and second source matrices (blocks). The source matrices contain double-word elements, each of which is divided into eight logical 4-bit nibbles.

[0202] The extracted instruction is decoded at 2203. For example, the extracted TDP4BIT instruction is decoded using a decoding circuit such as that detailed in this article.

[0203] The execution of the decoded instruction is scheduled at 2205 (as needed). This step is optional in the range that it may occur at different times or not at all (as indicated by its dashed boundary).

[0204] At 2207, the decoded TDP4BIT instruction is executed by execution circuitry (hardware) such as those detailed herein. For a TDP4BIT instruction, this execution is performed K times on each element (M, N) of the identified destination matrix, causing the execution circuitry to execute the decoded instruction. This process includes generating eight products by multiplying each nibble of the double-word element (M, K) of the identified first source matrix by the corresponding nibble of the double-word element (K, N) of the identified second source matrix; and saturating these eight products by summing them with the previous contents of the double-word element (M, N) of the identified destination matrix. In some embodiments, the instruction is committed or retired at 2209, a step that is optional (as indicated by its dashed boundary) within a range where it may occur at different times or not at all.

[0205] Figure 23 A more detailed description of the execution of the TDP4BIT instruction is illustrated below. Typically, this is implemented by execution circuitry such as those detailed above.

[0206] At 2302, extract the TDP4BIT instruction, which has fields for the opcode and first source, second source, and destination identifiers. Each identifier is used to identify the matrix (block) where the PAIR parameter is set to FALSE.

[0207] At 2304, determine if all of the following conditions are true, in which case a fault is generated at 2306 regardless of any one or more errors detected.

[0208] When all error checks at 2304 pass, the execution circuit at 2308 performs the process K times for each element (M, N) of the identified destination matrix to execute the remaining blocks of the process. At 2310, the execution circuit produces eight products by multiplying each nibble of the double-word element (M, K) of the identified first source matrix by the corresponding nibble of the double-word element (K, N) of the identified second source matrix, and saturates these eight products with the previous contents of the double-word element (M, N) of the identified destination matrix. At 2312, N is incremented, and if there are any more columns, execution returns to 2308 to process the next column. Otherwise, at 2314, K is incremented, and if there are any more Ks, execution returns to 2308 to process the next K. Otherwise, at 2316, M is incremented, and if there are any more rows, execution returns to 2308 to process the next M. Otherwise, the process ends.

[0209] IV. Exemplary Pseudocode

[0210] Figure 24AThis is exemplary pseudocode describing an embodiment of a processor executing the TDP4BIT instruction. As shown in pseudocode 2400, the TDP4BIT instruction includes the opcode TDP4BIT, a destination matrix (block) identifier “tdest” for identifying an M×N destination matrix (block), a first source matrix (block) identifier “tsrc1” for identifying an M×K first source matrix (block), and a second source matrix (block) identifier “tsrc2” for identifying a K×N second source matrix (block).

[0211] In some embodiments, each of the identified first source, second source, and destination matrices is represented using a set of registers and one of a plurality of memory locations.

[0212] As shown in the figure, if any of the error checks fails, pseudocode 2400 first causes the execution circuitry to generate a fault. For example, if any of tdest, tsrc1, and tsrc2 sets the PAIR parameter to TRUE, a fault will be generated.

[0213] Pseudocode 2400 further defines the "extend_src" macro to perform sign extension on signed source data values ​​or zero extension on unsigned source data values. If both source data values ​​are unsigned, pseudocode 2400 further defines the "saturation_fn" macro to perform unsigned saturation, and if any one or both of the source data values ​​are signed, then signed saturation is performed. For signed saturation, when a single result exceeds the range of a signed double-word integer (i.e., greater than 7FFF_FFFFH or less than 8000_0000H), the saturated value 7FFF_FFFFH or 8000_0000H is written to the destination operand, respectively. For unsigned saturation, when a single result value exceeds the range of an unsigned double word (i.e., greater than FFFF_FFFFH), the saturated unsigned double-word integer value FFFF_FFFFH is stored in the double-word destination.

[0214] Pseudocode 2400, when executed by the processor, causes the processor to compute the dot product of two double-word operands—each double-word operand containing eight 4-bit (nibble) elements—as well as double-word accumulation and saturation. As explained above, the 4-bit elements are either signed or unsigned, and saturation is signed if either operand is signed. Pseudocode 2400 causes the processor to execute multiple nested for loops to perform a process K times for each element (M, N) of the identified destination matrix, the process comprising producing eight products by multiplying each signed-expanded or zero-expanded nibble of the double-word elements (M, K) of the identified first source matrix by the corresponding signed-expanded or zero-expanded nibble of the double-word elements (K, N) of the identified second source matrix. The result of each nibble multiplication is stored in the double-word tprod[b], thus preserving precise accuracy. Pseudocode 2400 further causes the processor to accumulate these eight products with the previous contents of the double-word elements (M, N) of the identified destination matrix and saturate them (signed or unsigned). Pseudocode 2400 causes the processor to zero out any remaining configured rows of the destination matrix (block) and reset the pointer for the next call to the function.

[0215] In some embodiments, the execution circuit saves the state after performing the process on each element (M, N) of the identified destination matrix, and in the event of a failure, continues execution using the saved state after recovering from the failure, wherein the state includes at least destination matrix row pointers and destination matrix element pointers.

[0216] Figure 24B These are exemplary pseudocode examples describing an embodiment of the auxiliary functions used by the processor to execute the TDP4BIT instruction. Pseudocode 2450 defines the function "write_row_and_zero(treg, r, data, nbytes)". Pseudocode 2452 defines the function "zero_upper_rows(treg, r)". Pseudocode 2454 defines the function "zero_tileconfig_start()".

[0217] Figure 24A and Figure 24B The pseudocode in the document is a self-compiled file that uses the function and variable names it includes.

[0218] Other examples

[0219] Example 1 provides a processor including: a decoding circuit for decoding a block multiplication instruction having fields for an opcode, a destination identifier for identifying an M×N destination matrix, a first source identifier for identifying an M×K first source matrix, and a second source identifier for identifying a K×N second source matrix, each of the matrices containing a double-word element; and an execution circuit for executing the decoded instruction by performing a process K times on each element (M, N) of the identified destination matrix, the process including: generating eight products by multiplying each half-byte of the double-word element (M, K) of the identified first source matrix by the corresponding half-byte of the double-word element (K, N) of the identified second source matrix; and saturating the eight products by accumulating the previous contents of the double-word element (M, N) of the identified destination matrix.

[0220] Example 2 includes the essence of the exemplary processor of Example 1, wherein the execution circuitry further generates a fault in the event of a fault condition, the fault condition including any one or more of the following: one or more of the identified first and second source matrices have a PAIR parameter set to TRUE; one or more of the identified first and second source matrices have a VALID parameter not set to TRUE; the identified destination matrix has a number of rows different from the number of rows of the identified first source matrix; the identified destination matrix has a number of columns different from the number of columns of the identified second source matrix; and one or more of the identified first, second, and destination matrices have a size exceeding a maximum size, the size including the number of rows and columns of the matrix.

[0221] Example 3 includes the essence of the exemplary processor of Example 1, wherein the execution circuitry further performs sign expansion or zero expansion on each half-byte being multiplied based on the sign of the half-byte.

[0222] Example 4 includes the essence of the exemplary processor of Example 1, wherein the saturation includes signed saturation or unsigned saturation, depending on the sign of the eight products.

[0223] Example 5 includes the essence of the exemplary processor of Example 1, wherein the result of each half-byte multiplication is stored in a double-word register.

[0224] Example 6 includes the substance of an exemplary processor of any of Examples 1-5, wherein M is one of 2, 4, 8, and 16, N is one of 2, 4, 8, 16, and 32, and K is one of 1, 2, 4, 8, and 16.

[0225] Example 7 includes the essence of an exemplary processor of any of Examples 1-5, wherein the execution circuit saves a state after performing the process on each element (M, N) of the identified destination matrix, and in the event of a failure, continues to execute the K processes using the saved state after recovering from the failure; wherein the state includes at least a destination matrix row pointer and a destination matrix element pointer.

[0226] Example 8 includes the essence of an exemplary processor of any of Examples 1-5, wherein the identified first and second source matrices are each represented using a set of registers and one of a plurality of memory locations.

[0227] Example 9 includes the essence of an exemplary processor of any of Examples 1-5, wherein the identified destination matrix is ​​represented using a set of registers and one of a plurality of memory locations.

[0228] Example 10 includes the essence of an exemplary processor of any of Examples 1-5, wherein the opcode further indicates whether each of the first and second source matrices contains signed or unsigned elements.

[0229] Example 11 provides a method comprising: decoding a block multiplication instruction via a decoding circuit, the block multiplication instruction having fields for an opcode, a destination identifier for identifying an M×N destination matrix, a first source identifier for identifying an M×K first source matrix, and a second source identifier for identifying a K×N second source matrix, each of the matrices containing a double-word element; and executing the decoded instruction via an execution circuit by performing a process K times on each element (M, N) of the identified destination matrix, the process comprising: generating eight products by multiplying each nibble of the double-word element (M, K) of the identified first source matrix by the corresponding nibble of the double-word element (K, N) of the identified second source matrix; and saturating the eight products by accumulating the previous contents of the double-word element (M, N) of the identified destination matrix.

[0230] Example 12 includes the essence of the exemplary method of Example 11, further comprising: generating a fault via the execution circuitry when a fault condition occurs, the fault condition including any one or more of the following: one or more of the identified first and second source matrices have a PAIR parameter set to TRUE; one or more of the identified first and second source matrices have a VALID parameter not set to TRUE; the identified destination matrix has a number of rows different from the number of rows of the identified first source matrix; the identified destination matrix has a number of columns different from the number of columns of the identified second source matrix; and one or more of the identified first, second, and destination matrices have a size exceeding a maximum size, the size including the number of rows and columns of the matrix.

[0231] Example 13 includes the essence of the exemplary method of Example 11, further including: performing sign expansion or zero expansion on each half-byte being multiplied based on the sign of the half-byte by the execution circuitry.

[0232] Example 14 includes the essence of the exemplary method of Example 11, wherein the saturation includes signed saturation or unsigned saturation, depending on the sign of the eight products.

[0233] Example 15 includes the essence of the exemplary method of Example 11, further including: storing the result of each multiplication of the half-byte in the double-word register via the execution circuitry.

[0234] Example 16 includes the substance of an exemplary method of any of Examples 11-15, wherein M is one of 2, 4, 8, and 16, N is one of 2, 4, 8, 16, and 32, and K is one of 1, 2, 4, 8, and 16.

[0235] Example 17 includes the essence of an exemplary method of any of Examples 11-15, further comprising: saving a state after performing the process on each element (M, N) of the identified destination matrix, and, in the event of a failure, continuing to perform the K processes using the saved state after recovering from the failure; wherein the state includes at least destination matrix row pointers and destination matrix element pointers.

[0236] Example 18 includes the essence of an exemplary method of any of Examples 11-15, wherein the identified first and second source matrices are each represented using a set of registers and one of a plurality of memory locations.

[0237] Example 19 includes the essence of an exemplary method of any of Examples 11-15, wherein the identified destination matrix is ​​represented using a set of registers and one of a plurality of memory locations.

[0238] Example 20 includes the essence of an exemplary method of any of Examples 11-15, wherein the opcode further indicates whether each of the first and second source matrices contains signed or unsigned elements.

[0239] Example 21 provides a system comprising: a memory and a processor, the processor including: decoding circuitry for decoding block multiplication instructions having fields for an opcode, a destination identifier for identifying an M×N destination matrix, a first source identifier for identifying an M×K first source matrix, and a second source identifier for identifying a K×N second source matrix, each of the matrices containing a double-word element; and execution circuitry for executing the decoded instructions by performing a process K times on each element (M, N) of the identified destination matrix, the process comprising: generating eight products by multiplying each nibble of the double-word element (M, K) of the identified first source matrix by the corresponding nibble of the double-word element (K, N) of the identified second source matrix; and saturating the eight products by accumulating the previous contents of the double-word elements (M, N) of the identified destination matrix.

[0240] Example 22 includes the essence of the exemplary system of Example 21, wherein the execution circuitry further generates a fault in the event of a fault condition, the fault condition including any one or more of the following: one or more of the identified first and second source matrices have a PAIR parameter set to TRUE; one or more of the identified first and second source matrices have a VALID parameter not set to TRUE; the identified destination matrix has a number of rows different from the number of rows of the identified first source matrix; the identified destination matrix has a number of columns different from the number of columns of the identified second source matrix; and one or more of the identified first, second, and destination matrices have a size exceeding a maximum size, the size including the number of rows and columns of the matrix.

[0241] Example 23 includes the essence of the exemplary system of Example 21, wherein the execution circuitry further performs sign expansion or zero expansion on each half-byte being multiplied based on the sign of the half-byte.

[0242] Example 24 includes the essence of the exemplary system of Example 21, wherein the saturation includes signed saturation or unsigned saturation, depending on the sign of the eight products.

[0243] Example 25 includes the essence of the exemplary system of Example 21, wherein the result of each half-byte multiplication is stored in a double-word register.

[0244] Example 26 includes the essence of an exemplary system of any of Examples 21-25, wherein M is one of 2, 4, 8, and 16, N is one of 2, 4, 8, 16, and 32, and K is one of 1, 2, 4, 8, and 16.

[0245] Example 27 includes the essence of an exemplary system of any of Examples 21-25, wherein the execution circuit saves a state after performing the process on each element (M, N) of the identified destination matrix, and in the event of a failure, continues to execute the K processes using the saved state after recovering from the failure; wherein the state includes at least a destination matrix row pointer and a destination matrix element pointer.

[0246] Example 28 includes the essence of an exemplary system of any of Examples 21-25, wherein the identified first and second source matrices are each represented using a set of registers and one of a plurality of memory locations.

[0247] Example 29 includes the essence of an exemplary system of any of Examples 21-25, wherein the identified destination matrix is ​​represented using a set of registers and one of a plurality of memory locations.

[0248] Example 30 includes the essence of an exemplary system of any of Examples 21-25, wherein the opcode further indicates whether each of the first and second source matrices contains signed or unsigned elements.

[0249] Example 31 provides a non-transitory machine-readable medium containing instructions that, when executed by a processor, cause the processor to: decode a block multiplication instruction via decoding circuitry, the block multiplication instruction having fields for an opcode, a destination identifier for an M×N destination matrix, a first source identifier for an M×K first source matrix, and a second source identifier for a K×N second source matrix, each of the matrices containing a double-word element; and execute the decoded instruction via execution circuitry by performing a process K times on each element (M, N) of the identified destination matrix, the process comprising: generating eight products by multiplying each nibble of the double-word element (M, K) of the identified first source matrix by the corresponding nibble of the double-word element (K, N) of the identified second source matrix; and saturating the eight products by accumulating the previous contents of the double-word elements (M, N) of the identified destination matrix.

[0250] Example 32 includes the substance of the exemplary non-transitory machine-readable medium of Example 31, further comprising instructions that, when executed by the processor, cause the processor to: generate a fault through the execution circuitry when a fault condition occurs, the fault condition including any one or more of the following: one or more of the identified first and second source matrices have a PAIR parameter set to TRUE; one or more of the identified first and second source matrices have a VALID parameter not set to TRUE; the identified destination matrix has a number of rows different from the number of rows in the identified first source matrix; the identified destination matrix has a number of columns different from the number of columns in the identified second source matrix; and one or more of the identified first, second, and destination matrices have a size exceeding a maximum size, the size including the number of rows and columns of the matrix.

[0251] Example 33 includes the substance of the exemplary non-transitory machine-readable medium of Example 31, further comprising instructions that, when executed by the processor, cause the processor to: perform sign expansion or zero expansion on each half-byte being multiplied based on the sign of the half-byte via the execution circuitry.

[0252] Example 34 includes the substance of an exemplary non-transitory machine-readable medium of Example 31, wherein the saturation includes signed saturation or unsigned saturation, depending on the sign of the eight products.

[0253] Example 35 includes the substance of the exemplary non-transitory machine-readable medium of Example 31, further comprising instructions that, when executed by the processor, cause the processor to: store the result of each multiplication of a half-byte in a double-word register via the execution circuitry.

[0254] Example 36 includes the substance of an exemplary non-transitory machine-readable medium of any of Examples 31-35, wherein M is one of 2, 4, 8, and 16, N is one of 2, 4, 8, 16, and 32, and K is one of 1, 2, 4, 8, and 16.

[0255] Example 37 includes the substance of an exemplary non-transitory machine-readable medium of any of Examples 31-35, further comprising instructions that, when executed by the processor, cause the processor to: save a state after performing the process on each element (M, N) of the identified destination matrix, and, in the event of a failure, continue to perform the K processes using the saved state after recovering from the failure; wherein the state includes at least destination matrix row pointers and destination matrix element pointers.

[0256] Example 38 includes the substance of an exemplary non-transitory machine-readable medium of any of Examples 31-35, wherein the identified first and second source matrices are each represented using a set of registers and one of a plurality of memory locations.

[0257] Example 39 includes the substance of an exemplary non-transitory machine-readable medium of any of Examples 31-35, wherein the identified destination matrix is ​​represented using a set of registers and one of a plurality of memory locations.

[0258] Example 40 includes the substance of an exemplary non-transitory machine-readable medium of any of Examples 31-35, wherein the opcode further indicates whether each of the first and second source matrices contains signed or unsigned elements.

[0259] Example 41 provides an apparatus comprising: a plurality of memory controllers; a secondary (L2) cache memory coupled to the plurality of memory controllers; and a processor coupled to the plurality of memory controllers and coupled to the L2 cache memory, the processor having a plurality of cores, each core including circuitry for executing operations corresponding to instructions to instruct: a first matrix having M rows × K columns of 32-bit elements, each 32-bit element having eight 4-bit data elements; a second matrix having K rows × N columns of 32-bit elements, each 32-bit element having eight 4-bit data elements; and a third matrix having M rows × N columns; the instructions having a first indicator for indicating whether the 4-bit data elements of the first matrix are signed or unsigned, and a first indicator for indicating whether the 4-bit data elements of the second matrix are signed or unsigned. The data element is a second indicator of whether it is signed or unsigned. The operation includes: for each row m in the M rows of the first matrix and for each column n in the N columns of the second matrix: for each of the K 32-bit elements of row m of the first matrix: multiplying eight 4-bit data elements of the 32-bit element of row m of the first matrix with the corresponding data element of the eight 4-bit data elements of the corresponding 32-bit element of column n of the second matrix to generate eight products; and storing the 32-bit result data element in row m in the M rows and column n in the N columns of the third matrix, the 32-bit result data element being based on the sum of the eight products generated for each of the K 32-bit elements of row m of the first matrix and the 32-bit data elements corresponding to row m of the first matrix and column n of the second matrix.

[0260] Example 42 includes the essence of the exemplary apparatus of Example 41, wherein the operation further includes performing saturation to generate the 32-bit result data element.

[0261] Example 43 includes the essence of the exemplary apparatus of Example 42, wherein performing saturation includes performing signed saturation.

[0262] Example 44 includes the essence of the exemplary device of Example 41, wherein K is 4.

[0263] Example 45 includes the essence of the exemplary device of Example 44, wherein M is one of 2, 4, 8 and 16.

[0264] Example 46 includes the essence of the exemplary apparatus of Example 41, wherein a first matrix is ​​to be stored in a plurality of registers of the processor, and wherein a second matrix is ​​to be stored in a plurality of registers of the processor.

[0265] Example 47 includes the substance of the exemplary device of Example 41, and further includes an interconnect interface coupled to the processor.

[0266] Example 48 includes the substance of the exemplary device of Example 41, and further includes a bus controller interface coupled to the processor.

[0267] Example 49 includes the essence of the exemplary device of Example 41, wherein the core includes a graphics core.

[0268] Example 50 includes the essence of the exemplary device of Example 41, wherein the core includes a heterogeneous graphics core.

[0269] Example 51 includes the essence of the exemplary device of Example 41, and further includes an instruction converter for converting the instructions into one or more instructions of different instruction sets executable by the core.

[0270] Example 52 includes the essence of the exemplary device of Example 41, wherein a 4-bit data element of one of the first and second matrices is signed, while a 4-bit data element of the other of the first and second matrices is unsigned.

[0271] Example 53 provides an apparatus comprising: circuitry for receiving an instruction to instruct: a first matrix having M rows × K columns of 32-bit elements, each 32-bit element having eight 4-bit data elements; a second matrix having K rows × N columns of 32-bit elements, each 32-bit element having eight 4-bit data elements; and a third matrix having M rows × N columns; the instruction having a first indicator for indicating whether the 4-bit data elements of the first matrix are signed or unsigned, and a second indicator for indicating whether the 4-bit data elements of the second matrix are signed or unsigned; and execution circuitry for performing an operation corresponding to the instruction, including: targeting the M rows of the first matrix... For each row m of the first matrix, and for each column n of the N columns of the second matrix: for each of the K 32-bit elements of row m of the first matrix: multiply eight 4-bit data elements of the 32-bit element of row m of the first matrix with the corresponding data element of the corresponding 32-bit element of column n of the second matrix to generate eight products; and store the 32-bit result data element in row m of the M rows and column n of the N columns of the third matrix, the 32-bit result data element being based on the sum of the eight products generated for each of the K 32-bit elements of row m of the first matrix and the 32-bit data elements corresponding to row m of the first matrix and column n of the second matrix.

[0272] Example 54 provides an apparatus comprising: an instruction converter for converting a first instruction into one or more other instructions, the first instruction indicating: a first matrix having M rows × K columns of 32-bit elements, each 32-bit element having eight 4-bit data elements; a second matrix having K rows × N columns of 32-bit elements, each 32-bit element having eight 4-bit data elements; and a third matrix having M rows × N columns; the instructions having a first indicator for indicating whether the 4-bit data elements of the first matrix are signed or unsigned, and a second indicator for indicating whether the 4-bit data elements of the second matrix are signed or unsigned; and execution circuitry for performing an operation corresponding to the first instruction, including... For each row m in the M rows of the first matrix, and for each column n in the N columns of the second matrix: For each of the K 32-bit elements of row m of the first matrix: multiply eight 4-bit data elements of the 32-bit element of row m of the first matrix with the corresponding data element of the eight 4-bit data elements of the corresponding 32-bit element of column n of the second matrix to generate eight products; and store the 32-bit result data element in row m in the M rows and column n in the N columns of the third matrix, the 32-bit result data element being based on the sum of the eight products generated for each of the K 32-bit elements of row m of the first matrix and the 32-bit data elements corresponding to row m of the first matrix and column n of the second matrix.

[0273] Example 55 provides a method comprising: using multiple memory controllers to access memory; storing data in a secondary (L2) cache memory; and processing the data with a processor having multiple cores, including executing operations corresponding to instructions indicating: a first matrix having M rows × K columns of 32-bit elements, each 32-bit element having eight 4-bit data elements; a second matrix having K rows × N columns of 32-bit elements, each 32-bit element having eight 4-bit data elements; and a third matrix having M rows × N columns; the instructions having a first indicator indicating whether the 4-bit data elements of the first matrix are signed or unsigned, and a second indicator indicating whether the 4-bit data elements of the second matrix are signed or unsigned. The operation includes: for each row m in the M rows of the first matrix and for each column n in the N columns of the second matrix: for each of the K 32-bit elements of row m of the first matrix: multiplying eight 4-bit data elements of the 32-bit element of row m of the first matrix with the corresponding data element of the eight 4-bit data elements of the corresponding 32-bit element of column n of the second matrix to generate eight products; and storing the 32-bit result data element in row m in the M rows and column n in the N columns of the third matrix, the 32-bit result data element being the sum of the eight products generated for each of the K 32-bit elements of row m of the first matrix and the 32-bit data elements corresponding to row m of the first matrix and column n of the second matrix.

[0274] Example 56 includes the essence of the exemplary method of Example 55, wherein the operation further includes performing saturation to generate the 32-bit result data element.

[0275] Example 57 includes the essence of the exemplary method of Example 56, wherein performing saturation includes performing signed saturation.

[0276] Example 58 includes the essence of the exemplary method of Example 55, where K is 4.

[0277] Example 59 includes the essence of the exemplary method of Example 55, wherein M is one of 2, 4, 8, and 16.

[0278] Example 60 includes the essence of the exemplary method of Example 55, further including accessing a first matrix from a plurality of registers of the processor, and accessing a second matrix from a plurality of registers of the processor.

[0279] Example 61 includes the essence of the exemplary method of Example 55, wherein the core includes a heterogeneous graphics core.

[0280] Example 62 includes the essence of the exemplary method of Example 55, further including converting the instructions into one or more instructions of a different set of instructions executable by the core.

[0281] Example 63 includes the essence of the exemplary method of Example 55, wherein a 4-bit data element of one of the first and second matrices is signed, while a 4-bit data element of the other of the first and second matrices is unsigned.

[0282] Example 64 provides a machine-readable medium having instructions that, when executed, cause the machine to perform an exemplary method of one of Examples 55 to 63.

[0283] Example 65 provides an apparatus that includes components for performing an exemplary method of one of Examples 55 to 63.

[0284] V. Detailed Exemplary Systems, Processors, and Simulations

[0285] This article details examples of the hardware, software, etc., used to execute the above instructions. For example, the following description details various aspects of instruction execution, including various pipeline stages such as fetch, decode, schedule, execute, and retire.

[0286] Instruction set

[0287] An instruction set may include one or more instruction formats. A given instruction format may define, among other things, fields (e.g., number of bits, bit positions) and / or one or more other data fields (e.g., mask) for specifying the operation to be performed (e.g., opcode) and the operand(s) to which the operation is to be performed. Some instruction formats are further decomposed by defining instruction templates (or subformats). For example, an instruction template of a given instruction format may be defined as having different subsets of the fields of the instruction format (the included fields are typically in the same order, but because fewer fields are included, at least some have different bit positions) and / or be defined as having given fields interpreted in different ways. Thus, each instruction of an ISA is represented using a given instruction format (and, if defined, one of the given instruction templates of that instruction format) and includes fields for specifying the operation and operands. For example, an exemplary ADD instruction has a specific opcode and instruction format, which includes an opcode field for specifying the opcode and an operand field for selecting operands (source 1 / destination and source 2); and the appearance of this ADD instruction in the instruction stream will have specific content in the operand field for selecting specific operands. A set of SIMD extensions called Advanced Vector Extensions (AVX) (AVX1 and AVX2) and using the Vector Extensions (VEX) encoding scheme have been published and / or disclosed (see, for example, the September 2014...). See the 64 and IA-32 architecture software developer's manual; and also see the October 2014 edition. (Advanced Vector Extension Programming Reference).

[0288] Exemplary instruction format

[0289] Implementations of the instructions(s) described herein may be embodied in various formats. Furthermore, exemplary systems, architectures, and pipelines are detailed below. Implementations of the instructions(s) may be executed in such systems, architectures, and pipelines, but are not limited to those detailed herein.

[0290] General Vector-Friendly Instruction Format

[0291] A vector-friendly instruction format is an instruction format suitable for vector instructions (e.g., having certain fields specifically for vector operations). Although an embodiment in which both vector and scalar operations are supported through a vector-friendly instruction format has been described, alternative embodiments use only vector operations within the vector-friendly instruction format.

[0292] Figures 25A-25B This is a block diagram illustrating a general vector-friendly instruction format and its instruction template according to embodiments of the present invention. Figure 25A This is a block diagram illustrating a general vector-friendly instruction format and its Class A instruction template according to embodiments of the present invention; while Figure 25B This is a block diagram illustrating a general vector-friendly instruction format and its Class B instruction template according to an embodiment of the present invention. Specifically, the general vector-friendly instruction format 2500 defines Class A and Class B instruction templates, both of which include a no-memory-access 2505 instruction template and a memory-access 2520 instruction template. In the context of vector-friendly instruction formats, the term generally refers to an instruction format not bound to any particular instruction set.

[0293] Although the following embodiments of the invention will be described, the vector-friendly instruction format in these embodiments supports the following: a 64-byte vector operand length (or size) with a 32-bit (4-byte) or 64-bit (8-byte) data element width (or size) (and thus, a 64-byte vector consists of 16 double-word elements or alternatively 8 quad-word elements); a 64-byte vector operand length (or size) with a 16-bit (2-byte) or 8-bit (1-byte) data element width (or size); and 32-bit (4-byte), 64-bit (8-byte), 16-bit (2-byte), 64-bit (8-byte), 16-bit (2-byte), 64-byte (8 ... 32-byte vector operand lengths (or sizes) with 32-bit (2-byte) or 8-bit (1-byte) data element widths (or sizes); and 16-byte vector operand lengths (or sizes) with 32-bit (4-byte), 64-bit (8-byte), 16-bit (2-byte), or 8-bit (1-byte) data element widths (or sizes); however, alternative embodiments may support more, fewer, and / or different vector operand sizes (e.g., 256-byte vector operands) with more, fewer, or different data element widths (e.g., 128-bit (16-byte) data element widths).

[0294] Figure 25A The Class A instruction modules include: 1) within the No Memory Access 2505 instruction template, showing the No Memory Access, Full Rounding Control Type Operation 2510 instruction template and the No Memory Access, Data Transformation Type Operation 2515 instruction template; and 2) within the Memory Access 2520 instruction template, showing the Memory Access, Temporary 2525 instruction template and the Memory Access, Non-Temporary 2530 instruction template. Figure 25B The B-type instruction modules include: 1) within the no-memory access 2505 instruction template, showing the no-memory access, write mask control, partial rounding control type operation 2512 instruction template and the no-memory access, write mask control, vsize type operation 2517 instruction template; and 2) within the memory access 2520 instruction template, showing the memory access, write mask control 2527 instruction template.

[0295] The General Vector Friendly Command Format 2500 includes the following: Figures 25A-25B The following fields are listed in the order shown in the example.

[0296] Format field 2540 – A specific value in this field (instruction format identifier value) uniquely identifies the vector-friendly instruction format and therefore the occurrence of the instruction in the instruction stream in the vector-friendly instruction format. Accordingly, this field is optional in the sense that it is not required for instruction sets that only have a general vector-friendly instruction format.

[0297] Basic operation field 2542 – its content distinguishes different basic operations.

[0298] Register index field 2544—its contents specify the location of the source and destination operands (whether they are in registers or memory) directly or through address generation. These include enough bits to select N registers from a PxQ (e.g., 32x512, 16x128, 32x1024, 64x1024) register file. While in one embodiment N can be up to three source and one destination registers, alternative embodiments can support more or fewer source and destination registers (e.g., up to two sources, where one of these sources also acts as a destination; up to three sources, where one of these sources also acts as a destination; up to two sources and one destination).

[0299] Modifier field 2546—its contents distinguish between the appearance of instructions specifying a general vector instruction format for memory access and those not specifying memory access; that is, it distinguishes between the no-memory-access 2505 instruction template and the memory-access 2520 instruction template. Memory access operations read and / or write to the memory hierarchy (in some cases using values ​​in registers to specify the source and / or destination addresses), while non-memory access operations do not read and / or write to the memory hierarchy (e.g., the source and destination are registers). Although in one embodiment, this field also selects between three different methods for performing memory address calculations, alternative embodiments may support more, fewer, or different methods for performing memory address calculations.

[0300] The augmented operation field 2550 distinguishes which of several different operations to be performed in addition to the basic operation. This field is context-specific. In one embodiment of the invention, this field is divided into a category field 2568, an α field 2552, and a β field 2554. The augmented operation field 2550 allows a common set of operations to be performed in a single instruction, rather than in two, three, or four instructions.

[0301] The scaling field 2560—its contents allow for the generation of memory addresses (e.g., for using 2...). 比例 The index field content is scaled (generated from the index and base address).

[0302] The offset field 2562A—its contents are used as part of the memory address generation (e.g., for memory addresses using 2...). 比例 *Address generation of index + base address + offset.

[0303] The displacement factor field 2562B (note that the juxtaposition of displacement field 2562A directly on displacement factor field 2562B indicates that one or the other is being used) – its contents are used as part of the address generation; it specifies the displacement factor to be scaled by the size (N) of the memory access, where N is the number of bytes in the memory access (e.g., for a 2... 比例 *Address generation from index + base address + scaled displacement). Redundant low-order bits are ignored, and therefore the displacement factor field content is multiplied by the total memory operand size (N) to generate the final displacement to be used in calculating the effective address. The value of N is determined by the processor hardware at runtime based on the full opcode field 2574 (described later herein) and the data manipulation field 2554C. The displacement field 2562A and the displacement factor field 2562B are optional in the sense that they are not used in the No Memory Access 2505 instruction template, and / or different embodiments may implement only one of them or neither.

[0304] The data element width field 2564—its content distinguishes which of the multiple data element widths to use (in some embodiments for all instructions; in other embodiments for only some instructions). This field is optional in the sense that it is not needed if only one data element width is supported and / or some aspect of the opcode is used to support the data element width.

[0305] The write mask field 2570—its content controls, based on the position of each data element, whether that position in the destination vector operand reflects the result of the base operation and the augmentation operation. Type A instruction templates support merge write masking, while Type B instruction templates support both merge write masking and zero-out write masking. When merging, the vector mask allows any set of elements in the destination to be protected from being updated during the execution of any operation (specified by the base operation and the augmentation operation); in another embodiment, the old value of each element in the destination is preserved, where the corresponding mask bit has 0. In contrast, when zeroing, the vector mask allows any set of elements in the destination to be zeroed during the execution of any operation (specified by the base operation and the augmentation operation); in one embodiment, when the corresponding mask bit has a value of 0, the element in the destination is set to 0. A subset of this functionality is the ability to control the vector length of the performed operation (i.e., the span of the modified elements, from first to last); however, the modified elements are not necessarily contiguous. Therefore, the write mask field 2570 allows for partial vector operations, including load, store, arithmetic, logical, etc. Although an embodiment of the invention has been described in which the content of the write mask field 2570 is selected to contain one of a plurality of write mask registers to be used (and thus the content of the write mask field 2570 indirectly identifies the mask to be performed), alternative embodiments may instead or additionally allow the content of the mask write field 2570 to directly specify the mask to be performed.

[0306] The immediate number field 2572—its contents allow for the specification of an immediate number. This field is optional in the sense that it does not exist in implementations of a generic vector-friendly format that does not support immediate numbers, and it does not exist in instructions that do not use immediate numbers.

[0307] Category field 2568 – Its content distinguishes between instructions in different categories. (See reference) Figure 25A -B indicates that the content of this field selects between type A and type B instructions. Figure 25A In -B, rounded rectangles are used to indicate the presence of a specific value in a field (e.g., in...). Figure 25A -B represents category A (2568A) and category B (2568B) of category field 2568, respectively.

[0308] Type A Instruction Template

[0309] In the case of the Class A non-memory access 2505 instruction template, the α field 2552 is interpreted as the RS field 2552A, the content of which distinguishes which of the different amplification operation types to be performed (for example, rounding type operation 2510 and data transformation type operation 2515 instruction templates specify rounding 2552A.1 and data transformation 2552A.2 respectively), while the β field 2554 distinguishes which of the specified type of operation to be performed. In the non-memory access 2505 instruction template, the scaling field 2560, the displacement field 2562A, and the displacement scaling field 2562B are not present.

[0310] No memory access instruction template - full rounding control type operation

[0311] In the instruction template of operation 2510 with no memory access and full round control, the β field 2554 is interpreted as a round control field 2554A, the contents of which provide static rounding. Although in the embodiments described in this invention, the round control field 2554A includes a suppress all floating-point exception (SAE) field 2556 and a round operation control field 2558, alternative embodiments may support encoding these two concepts into the same field or having only one or the other of these concepts / fields (e.g., only the round operation control field 2558).

[0312] SAE field 2556 – its content distinguishes whether exception event reporting is disabled; when the content of SAE field 2556 indicates that suppression is enabled, a given instruction will not report any kind of floating-point exception flag and will not trigger any floating-point exception handler.

[0313] The rounding operation control field 2558 distinguishes which of a set of rounding operations to perform (e.g., round up, round down, round to zero, and round to nearest). Therefore, the rounding operation control field 2558 allows the rounding mode to be changed based on each instruction. In one embodiment of the invention, where the processor includes a control register for specifying the rounding mode, the content of the rounding operation control field 2550 overwrites that register value.

[0314] No memory access instruction template – Data transformation type operation

[0315] In the instruction template 2515 of the no-memory-access data transformation type operation, the β field 2554 is interpreted as the data transformation field 2554B, the contents of which distinguish which of the multiple data transformations to be performed (e.g., no data transformation, mixing, broadcasting).

[0316] In the case of Class A memory access instruction template 2520, field α2552 is interpreted as eviction hint field 2552B, the content of which distinguishes which eviction hint to use (in... Figure 25A In this context, temporary 2525 instruction templates and non-temporary 2530 instruction templates are specified as temporary 2552B.1 and non-temporary 2552B.2, respectively. The β field 2554 is interpreted as the data manipulation field 2554C, whose content distinguishes which of the multiple data manipulation operations (also known as primitives) to be performed (e.g., no manipulation; broadcast; source upcast; and destination downcast). The memory access 2520 instruction template includes a scaling field 2560 and optionally a displacement field 2562A or a displacement scaling field 2562B.

[0317] Vector memory instructions, with translation support, perform vector loading from memory and vector storage to memory. For regular vector instructions, vector memory instructions transfer data from / to memory element by element, where the actual element transferred is determined by the contents of the vector mask selected as the write mask.

[0318] Memory access instruction template - temporary

[0319] Temporary data is data that may be quickly reused to benefit from caching. However, this is a hint, and different processors may implement it in different ways, including ignoring the hint entirely.

[0320] Memory access instruction template - non-temporary

[0321] Non-temporary data is data that is unlikely to be reused soon to benefit from the L1 cache and should be given eviction priority. However, this is a hint, and different processors may implement it in different ways, including ignoring the hint entirely.

[0322] Type B Instruction Template

[0323] In the case of the B-type instruction template, the α field 2552 is interpreted as the write mask control (Z) field 2552C, the content of which distinguishes whether the write mask controlled by the write mask field 2570 should be merged or zeroed.

[0324] In the case of the Class B non-memory access 2505 instruction template, a portion of the β field 2554 is interpreted as the RL field 2557A, the contents of which distinguish which of the different amplification operation types to be performed (e.g., rounding 2557A.1 and vector length (VSIZE) 2557A.2 are specified for the no-memory access, write mask control, partial rounding control type operation 2512 instruction template and the no-memory access, write mask control, VSIZE type operation 2517 instruction template, respectively), while the remaining portion of the β field 2554 distinguishes which of the specified types of operations to be performed. In the no-memory access 2505 instruction template, the scaling field 2560, the displacement field 2562A, and the displacement scaling field 2562B are not present.

[0325] In the instruction template 2510 of the no memory access, write mask control, partial rounding control type operation, the remainder of the β field 2554 is interpreted as the rounding operation field 2559A and exception event reporting is disabled (the given instruction does not report any kind of floating-point exception flag and does not raise any floating-point exception handler).

[0326] Rounding operation control field 2559A—like rounding operation control field 2558, its contents distinguish which of a set of rounding operations to perform (e.g., round up, round down, round to zero, and round to nearest). Therefore, rounding operation control field 2559A allows the rounding mode to be changed based on each instruction. In one embodiment of the invention, where the processor includes a control register for specifying the rounding mode, the contents of rounding operation control field 2550 overwrite that register value.

[0327] In the instruction template 2517 for no memory access, write mask control, and VSIZE type operation, the remainder of the β field 2554 is interpreted as the vector length field 2559B, the contents of which distinguish which of the multiple data vector lengths to be executed (e.g., 128, 256, or 512 bytes).

[0328] In the case of the Class B memory access 2520 instruction template, a portion of the β field 2554 is interpreted as a broadcast field 2557B, the content of which distinguishes whether a broadcast-type data manipulation operation is to be performed, while the remainder of the β field 2554 is interpreted as a vector length field 2559B. The memory access 2520 instruction template includes a scaling field 2560, and optionally a displacement field 2562A or a displacement scaling field 2562B.

[0329] Regarding the general vector-friendly instruction format 2500, a full opcode field 2574 is shown, comprising a format field 2540, a basic operation field 2542, and a data element width field 2564. While one embodiment is shown in which the full opcode field 2574 includes all of these fields, in embodiments that do not support all of them, the full opcode field 2574 includes fewer than all of these fields. The full opcode field 2574 provides the operation code (opcode).

[0330] The augmentation operation field 2550, the data element width field 2564, and the write mask field 2570 allow these features to be specified on a per-instruction basis in a generic vector-friendly instruction format.

[0331] The combination of a write mask field and a data element width field creates typed instructions because they allow masks to be applied based on different data element widths.

[0332] The various instruction templates found within classes A and B are advantageous in different situations. In some embodiments of the invention, different processors or different cores within a processor may support only class A, only class B, or both classes. For example, a high-performance general-purpose out-of-order core intended for general-purpose computing may support only class B, a core intended primarily for graphics and / or scientific (throughput) computing may support only class A, and a core intended for both may support both (of course, a core having templates and instructions from both classes, but not all templates and instructions from both classes, is within the scope of the invention). Moreover, a single processor may include multiple cores, all of which support the same class or different cores supporting different classes. For example, in a processor with separate graphics and general-purpose cores, one of the graphics cores intended primarily for graphics and / or scientific computing may support only class A, while one or more of the general-purpose cores may be a high-performance general-purpose core with out-of-order execution and register renaming intended for general-purpose computing that supports only class B. Another processor without a separate graphics core may include one or more general-purpose ordered or out-of-order cores supporting both class A and class B. Of course, features from one category can also be implemented in another category in different embodiments of the invention. Programs written in high-level languages ​​will be arranged (e.g., just-in-time or statically compiled) into a variety of different executable forms, including: 1) forms having only instructions for executing one or more categories supported by the target processor; or 2) forms having alternative routines written using different combinations of instructions from all categories and having selection routines for control flow code executed based on instructions supported by the processor currently executing the code.

[0333] Exemplary Vector-Friendly Instruction Format

[0334] Figure 26AThis is a block diagram illustrating an exemplary vector-friendly instruction format according to an embodiment of the present invention. Figure 26A A specific vector-friendly instruction format 2600 is shown, which is specific in that it specifies the position, size, interpretation, and field order, as well as the meaning of the values ​​used for some of those fields. This specific vector-friendly instruction format 2600 can be used to extend the x86 instruction set, and therefore some of the fields are similar to or the same as those used in existing x86 instruction sets and their extensions (e.g., AVX). The format maintains consistency with prefix-coded fields, real opcode byte fields, MOD R / M fields, SIB fields, shift fields, and immediate numeric fields of existing x86 instruction sets with extensions. Fields from Figure 25 are illustrated, where... Figure 26A The fields are mapped to the fields from Figure 25.

[0335] It should be understood that although embodiments of the invention have been described with reference to a specific vector-friendly instruction format 2600 in the context of a general vector-friendly instruction format 2500 for illustrative purposes, the invention is not limited to that specific vector-friendly instruction format 2600, except where stated. For example, the general vector-friendly instruction format 2500 is intended for a wide variety of possible sizes for various fields, while the specific vector-friendly instruction format 2600 is shown as a field with a specific size. By a specific example, although the data element width field 2564 is exemplified as a single field in the specific vector-friendly instruction format 2600, the invention is not limited thereto (that is, the general vector-friendly instruction format 2500 intends other sizes for the data element width field 2564).

[0336] The General Vector Friendly Command Format 2500 includes the following: Figure 26A The following fields are listed in the order shown in the example.

[0337] The EVEX prefix (bytes 0-3) 2602 — it is encoded in four-byte format.

[0338] Format field 2540 (EVEX byte 0, bits [7:0]) — The first byte (EVEX byte 0) is format field 2540 and it contains 0x62 (a unique value used in one embodiment of the invention to distinguish vector-friendly instruction formats).

[0339] The second to fourth bytes (EVEX bytes 1-3) include multiple bit fields that provide specific capabilities.

[0340] The REX field 2605 (EVEX byte 1, bits [7-5]) consists of the EVEX.R bit field (EVEX byte 1, bits [7]-R), the EVEX.X bit field (EVEX byte 1, bits [6]-X), and the 2557BEX byte 1, bits [5]-B. The EVEX.R, EVEX.X, and EVEX.B bit fields provide the same functionality as the corresponding VEX bit fields and are encoded using supplementary 1 form, i.e., ZMM0 is encoded as 1111B and ZMM15 is encoded as 0000B. As is known in the art, the other fields of the instruction encode the next three bits of the register index (rrr, xxx, and bbb) so that Rrrr, Xxxx, and Bbbb can be formed by adding EVEX.R, EVEX.X, and EVEX.B.

[0341] REX′ field 2610 — This is the first part of REX′ field 2610 and is the EVEX.R′ bit field (EVEX byte 1, bit [4]-R′) used for upper 16 or lower 16 encoding of the extended 32 register set. In one embodiment of the invention, this bit, along with the other bits indicated below, is stored in a bit-inverted format to distinguish it from the BOUND instruction (in the well-known x8632 bit mode), whose actual opcode byte is 62, but the value of 11 in the MOD field is not accepted in the MOD R / M field (described below); an alternative embodiment of the invention does not store this bit and the other bits indicated below in an inverted format. A value of 1 is used for lower 16 register encoding. In other words, R′Rrrr is formed by combining EVEX.R′, EVEX.R, and other RRRs from other fields.

[0342] Opcode mapping field 2615 (EVEX byte 1, bits [3:0]-mmmm) — its contents encode the implicit leading opcode byte (0F, 0F 38 or 0F 3).

[0343] The data element width field is 2564 (EVEX bytes 2, bits [7]-W) – indicated by the label EVEX.W. EVEX.W is used to define the granularity (size) of the data type (32-bit data element or 64-bit data element).

[0344] EVEX.vvvv 2620 (EVEX byte 2, bits [6:3] -vvvv) — The function of EVEX.vvvv can include the following: 1) EVEX.vvvv encodes the first source register operand specified in inverted (Supplement 1) form and is valid for instructions with two or more source operands; 2) EVEX.vvvv encodes the destination register operand specified in Supplement 1 form for some vector shift; or 3) EVEX.vvvv does not encode any operands, the field is reserved and should contain 1111b. Therefore, the EVEX.vvvv field 2620 encodes the four lower-order bits of the first source register specifier stored in inverted (Supplement 1) form. Depending on the instruction, additional different EVEX bit fields are used to extend the specifier size to 32 registers.

[0345] EVEX.U 2568 Category field (EVEX byte 2, bit [2]-U) — If EVEX.U = 0, it indicates class A or EVEX.U0; if EVEX.U = 1, it indicates class B or EVEX.U1.

[0346] The prefix-encoded field 2625 (EVEX byte 2, bits [1:0]-pp) provides additional bits for the underlying operation field. Besides supporting legacy SSE instructions in EVEX prefix format, this also has the benefit of compressing the SIMD prefix (instead of requiring a byte to represent the SIMD prefix, the EVEX prefix only requires 2 bits). In one embodiment, to support legacy SSE instructions using SIMD prefixes (66H, F2H, F3H) in both legacy and EVEX prefix formats, these legacy SIMD prefixes are encoded into a SIMD prefix-encoded field; and extended to the legacy SIMD prefix at runtime before being provided to the PLA for the decoder (so the PLA can execute both legacy and EVEX formats of these legacy instructions without modification). While newer instructions can use the contents of the EVEX prefix-encoded field directly as opcode extensions, some embodiments allow different meanings to be specified via these legacy SIMD prefixes for consistency by extending them in a similar manner. Alternative embodiments can redesign the PLA to support 2-bit SIMD prefix encoding and therefore do not require extension.

[0347] The α field 2552 (EVEX byte 3, bit [7]-EH; also known as EVEX.EH, EVEX.rs, EVEX.RL, EVEX.WriteMaskControl, and EVEX.N; also denoted as α) — as previously described, this field is context-specific.

[0348] β field 2554 (EVEX byte 3, bits [6:4] - SSS, also known as EVEX.S) 2-0 EVEX.r 2-0 ,EVEX.rr1,EVEX.LL0,EVEX.LLB; also exemplified by β β β) — as previously described, this field is context-specific.

[0349] REX′ field 2610 — This is the remainder of the REX′ field and is the EVEX.V′ bit field (EVEX byte 3, bit [3] — V′) that can be used to encode the upper 16 or lower 16 of the extended 32 register set. This bit is stored in bit-inverted format. The lower 16 registers are encoded using the value 1. In other words, V′VVVV is formed by combining EVEX.V′ and EVEX.vvvv.

[0350] Write mask field 2570 (EVEX byte 3, bits [2:0]-kkk) – as previously described, its content specifies the index of the register in the write mask register. In one embodiment of the invention, the specific value EVEX.kkk = 000 has the special behavior of implying that no write mask is used for a particular instruction (this can be implemented in a variety of ways, including using a write mask hardwired to all one or hardware that bypasses the masking hardware).

[0351] The actual opcode field 2630 (byte 4) is also known as the opcode byte. This field specifies the portion of the opcode.

[0352] The MOD R / M field 2640 (byte 5) includes the MOD field 2642, the Reg field 2644, and the R / M field 2646. As previously described, the content of the MOD field 2642 distinguishes between memory access and non-memory access operations. The function of the Reg field 2644 can be summarized in two cases: encoding the destination register operand or the source register operand, or treating it as an opcode extension and not used to encode any instruction operand. The function of the R / M field 2646 can include encoding the instruction operand that references a memory address, or encoding the destination register operand or the source register operand.

[0353] The Proportional, Index, Base (SIB) byte (byte 6) – as previously described, the contents of the Proportional field 2550 are used for memory address generation. SIB.xxx 2654 and SIB.bbb2656 – the contents of these fields have been previously discussed regarding register indices Xxxx and Bbbb.

[0354] Displacement field 2562A (bytes 7-10) — When MOD field 2642 contains 10, bytes 7-10 are displacement field 2562A, and it works in the same way as the old 32-bit displacement (disp32) and works at the byte granularity.

[0355] Byte 7 (disp8) is the shift factor segment 2562B – when MOD field 2642 contains 0s and 1s, byte 7 is the shift factor segment 2562B. This field is located in the same position as the 8-bit shift (disp8) of the older x86 instruction set, which operates at byte granularity. Because disp8 is sign-extended, it can be addressed only between offsets of -128 and 127 bytes; for a 64-byte cache line, disp8 uses 8 bits that can be set to only four truly useful values: -128, -64, 0, and 64; because a larger range is often required, disp32 is used; however, disp32 requires 4 bytes. The shift factor segment 2562B is a reinterpretation of disp8 compared to disp8 and disp32; when using the shift factor segment 2562B, the actual shift is determined by multiplying the contents of the shift factor segment by the size (N) of the memory operand access. This type of shift is called disp8*N. This reduces the average instruction length (a single byte used for displacement, but with a much larger range). This compressed displacement is based on the assumption that the effective displacement is a multiple of the granularity of memory accesses, and therefore redundant low-order bit encoding of address offsets is unnecessary. In other words, the displacement is replaced by the old x86 instruction set 8-bit displacement with digital segment 2562B. Therefore, the displacement is encoded with digital segment 2562B in the same way as the x86 instruction set 8-bit displacement (so the ModRM / SIB encoding rules remain unchanged), with the only exception being that disp8 is overloaded to disp8*N. In other words, there is no change in the encoding rules or encoding length, but only in the interpretation of the displacement values ​​by the hardware (which requires scaling the size of the memory operand to obtain byte-level address offsets). Immediate segment 2572 operates as previously described.

[0356] Full opcode field

[0357] Figure 26B This is a block diagram illustrating the fields constituting a specific vector-friendly instruction format 2600 of the full opcode field 2574 according to an embodiment of the present invention. Specifically, the full opcode field 2574 includes a format field 2540, a basic operation field 2542, and a data element width (W) field 2564. The basic operation field 2542 includes a prefix encoding field 2625, an opcode mapping field 2615, and a real opcode field 2630.

[0358] Register index field

[0359] Figure 26C This is a block diagram illustrating the fields of a specific vector-friendly instruction format 2600 constituting register index field 2544 according to an embodiment of the present invention. Specifically, register index field 2544 includes REX field 2605, REX′ field 2610, MODR / M.reg field 2644, MODR / Mr / m field 2646, VVVV field 2620, xxx field 2654, and bbb field 2656.

[0360] Amplification operation field

[0361] Figure 26D This is a block diagram illustrating the fields of a specific vector-friendly instruction format 2600 constituting the amplification operation field 2550 according to an embodiment of the present invention. When the category (U) field 2568 contains 0, it means EVEX.U0 (Class A 2568A); when it contains 1, it means EVEX.U1 (Class B 2568B). When U = 0 and the MOD field 2642 contains 11 (meaning no memory access operation), the α field 2552 (EVEX byte 3, bit [7]-EH) is interpreted as the rs field 2552A. When the rs field 2552A contains a1 (rounded 2552A.1), the β field 2554 (EVEX byte 3, bit [6:4]-SSS) is interpreted as the rounding control field 2554A. The rounding control field 2554A includes a one-bit SAE field 2556 and a two-bit rounding operation field 2558. When rs field 2552A contains 0 (data transformation 2552A.2), β field 2554 (EVEX byte 3, bits [6:4]-SSS) is interpreted as a three-bit data transformation field 2554B. When U = 0 and MOD field 2642 contains 00, 01, or 10 (meaning a memory access operation), β field 2552 (EVEX byte 3, bits [7]-EH) is interpreted as an eviction hint (EH) field 2552B, and β field 2554 (EVEX byte 3, bits [6:4]-SSS) is interpreted as a three-bit data manipulation field 2554C.

[0362] When U = 1, α field 2552 (EVEX byte 3, bit [7]-EH) is interpreted as write mask control (Z) field 2552C. When U = 1 and MOD field 2642 contains 11 (meaning no memory access operation), a portion of β field 2554 (EVEX byte 3, bit [4]-S0) is interpreted as RL field 2557A; when it contains 1 (rounded to 2557A.1), the remainder of β field 2554 (EVEX byte 3, bit [6-5]-S0) is interpreted as RL field 2557A. 2-1The remainder of the β field 2554 (EVEX byte 3, bit [6-5]-S) is interpreted as a rounding operation field 2559A, while when the RL field 2557A contains 0 (VSIZE2557.A2), the remainder of the β field 2554 (EVEX byte 3, bit [6-5]-S) is interpreted as a rounding operation field 2559A, and when the RL field 2557A contains 0 (VSIZE2557.A2), the remainder of the β field 2554 is interpreted as a rounding operation field 2559A, while when the RL field 2557A contains 0 (VSIZE2557.A2), the remainder of the β field 2554 (EVEX byte 3, bit [6-5]-S) is interpreted as a rounding operation field 2559A, and when the RL field 2 2-1 ) is interpreted as a vector length field 2559B (EVEX byte 3, bits [6-5]-L 1-0 When U=1 and MOD field 2642 contains 00, 01, or 10 (meaning a memory access operation), β field 2554 (EVEX byte 3, bits [6:4]-SSS) is interpreted as vector length field 2559B (EVEX byte 3, bits [6:5]-L). 1-0 ) and broadcast field 2557B (EVEX byte 3, bit [4]-B).

[0363] Exemplary Register Architecture

[0364] Figure 27 This is a block diagram of a register architecture 2700 according to an embodiment of the present invention. In the illustrated embodiment, there are 32 vector registers 2710 with a width of 512 bits; these registers are referred to as zmm0 to zmm31. The lower 256 bits of the next 16 zmm registers overwrite registers ymm0-16. The lower 128 bits of the next 16 zmm registers (the lower 128 bits of the ymm registers) overwrite registers xmm0-15. As illustrated in the table below, this particular vector-friendly instruction format 2600 operates on these overwritten register files:

[0365]

[0366] In other words, the vector length field 2559B is selected between a maximum length and one or more other shorter lengths, each of which is half the length of the preceding length; and instruction templates without the vector length field 2559B operate on the maximum vector length. Furthermore, in one embodiment, the Class B instruction template of the specific vector-friendly instruction format 2600 operates on packed or scalar single / double-precision floating-point data and packed or scalar integer data. Scalar operations are performed at the lowest-order data element positions in the zmm / ymm / xmm registers; according to an embodiment, higher-order data element positions are either on the left or zeroed out, as they are before the instruction.

[0367] Write mask register 2715—In the illustrated embodiment, there are eight write mask registers (k0 to k7), each 64 bits in size. In an alternative embodiment, write mask register 2715 is 16 bits in size. As previously described, in one embodiment of the invention, the vector mask register k0 cannot be used as a write mask; when the encoding that would normally indicate k0 is used as the write mask, it selects a hardwired 0xFFFF write mask, effectively disabling write masking for that instruction.

[0368] General Purpose Register 2725 — In the illustrated embodiment, there are sixteen 64-bit general purpose registers used together with the existing x86 addressing modes for addressing memory operands. These registers are referred to by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 through R15.

[0369] Scalar floating-point stack register file (x87 stack) 2745 (also known as MMX packed integer plane register file 2750) — In the illustrated embodiment, this x87 stack is an octal stack used to perform scalar floating-point operations on 32 / 64 / 80-bit floating-point data using x87 instruction set extensions; while the MMX registers are used to perform operations on 64-bit packed integer data and to hold operands for some operations performed between the MMX and XMM registers.

[0370] Alternative embodiments of the present invention may use wider or narrower registers. Furthermore, alternative embodiments of the present invention may use more, fewer, or different register files and registers.

[0371] Exemplary core architectures, processors, and computer architectures

[0372] Processor cores can be implemented in different ways and in different processors for different purposes. For example, such core implementations may include: 1) a general-purpose ordered core intended for general-purpose computing; 2) a high-performance general-purpose unordered core intended for general-purpose computing; and 3) a dedicated core intended primarily for graphics and / or scientific (throughput) computing. Different processor implementations may include: 1) a CPU comprising one or more general-purpose ordered cores intended for general-purpose computing and / or one or more general-purpose unordered cores intended for general-purpose computing; and 2) a coprocessor comprising one or more dedicated cores intended primarily for graphics and / or scientific (throughput) computing. Such different processors result in different computer system architectures, which may include: 1) a coprocessor on a separate chip from the CPU; 2) a coprocessor on a separate die in the same package as the CPU; 3) a coprocessor on the same die as the CPU (in which case such a coprocessor is sometimes referred to as dedicated logic (such as integrated graphics and / or scientific (throughput) logic), or a dedicated core); and 4) a system-on-a-chip that may include the CPU (sometimes referred to as application cores or application processors), the aforementioned coprocessors, and additional functionality on the same die. The following describes an exemplary core architecture, followed by a description of exemplary processors and computer architectures.

[0373] Exemplary core architecture

[0374] Block diagram of ordered and disordered kernels

[0375] Figure 28A This is a block diagram illustrating both an exemplary ordered pipeline and an exemplary register renaming and unordered release / execution pipeline according to embodiments of the present invention. Figure 28B This is an exemplary embodiment of an ordered architecture core according to embodiments of the present invention, and a block diagram illustrating both exemplary register renaming and out-of-order release / execution of the architecture core to be included in the processor. Figure 28A The solid boxes in -B exemplify ordered pipelines and ordered cores, while the optional additional items in the dashed boxes exemplify register renaming, out-of-order release / execution pipelines, and cores. Since ordered aspects are a subset of out-of-order aspects, the out-of-order aspects will be described.

[0376] exist Figure 28A In the processor pipeline 2800, there are fetch phase 2802, length decoding phase 2804, decoding phase 2806, allocation phase 2808, renaming phase 2810, scheduling (also known as dispatch or issue) phase 2812, register read / memory read phase 2814, execution phase 2816, write-back / memory write phase 2818, exception handling phase 2822, and commit phase 2824.

[0377] Figure 28BThe processor core 2890 is shown, which includes a front-end unit 2830 coupled to an execution engine unit 2850, and both units are coupled to a memory unit 2870. Core 2890 can be a Reduced Instruction Set Computing (RISC) core, a Complex Instruction Set Computing (CISC) core, a Very Long Instruction Word (VLIW) core, or a hybrid or alternative core type. Alternatively, core 2890 can be a dedicated core, such as, for example, a network or communication core, a compression engine, a coprocessor core, a general-purpose computing graphics processing unit (GPGPU) core, a graphics core, etc.

[0378] Front-end unit 2830 includes branch prediction unit 2832 coupled to instruction cache unit 2834, which is coupled to instruction translation lookup buffer (TLB) 2836, which is coupled to instruction fetch unit 2838, which is coupled to decoding unit 2840. Decoding unit 2840 (or decoder) can decode instructions and generate one or more micro-operations, microcode entry points, microinstructions, other instructions, or other control signals as output, which are decoded from, or otherwise reflect, or derived from, the original instructions. Decoding unit 2840 can be implemented using various mechanisms. Examples of suitable mechanisms include, but are not limited to, lookup tables, hardware implementations, programmable logic arrays (PLAs), microcode read-only memory (ROM), etc. In one embodiment, core 2890 includes microcode ROM or other medium storing microcode for certain macro instructions (e.g., in decoding unit 2840 or otherwise within front-end unit 2830). The decoding unit 2840 is coupled to the rename / allocator unit 2852 in the execution engine unit 2850.

[0379] Execution engine unit 2850 includes a rename / allocator unit 2852, which is coupled to retirement unit 2854 and a set of one or more scheduler units 2856. The scheduler units 2856 represent any number of different schedulers, including reservation stations, central instruction windows, etc. The scheduler units 2856 are coupled to one or more physical register file units 2858. Each of the physical register file units 2858 represents one or more physical register files, where different physical register files store one or more different data types, such as scalar integers, scalar floating-point numbers, packed integers, packed floating-point numbers, vector integers, vector floating-point numbers, status (e.g., an instruction pointer as the address of the next instruction to be executed), etc. In one embodiment, the physical register file units 2858 include vector register units, write mask register units, and scalar register units. These register units can provide architectural vector registers, vector mask registers, and general-purpose registers. One or more physical register file units 2858 are overlapped by retirement units 2854 to illustrate various ways in which register renaming and out-of-order execution can be implemented (e.g., using one or more reorder buffers and one or more retirement register files; using one or more future files, one or more history buffers, and one or more retirement register files; using register mappings and register pools, etc.). Retirement units 2854 and one or more physical register file units 2858 are coupled to one or more execution clusters 2860. Execution clusters 2860 include a set of one or more execution units 2862 and a set of one or more memory access units 2864. Execution units 2862 can perform various operations (e.g., shift, addition, subtraction, multiplication) and various data types (e.g., scalar floating-point, packed integer, packed floating-point, vector integer, vector floating-point). While some embodiments may include several execution units dedicated to a particular function or set of functions, other embodiments may include only one or more execution units that perform all functions. One or more scheduler units 2856, one or more physical register file units 2858, and one or more execution clusters 2860 are shown as possibly multiple, because some embodiments create separate pipelines for certain data / operation types (e.g., scalar integer pipelines, scalar floating-point / packed integer / packed floating-point / vector integer / vector floating-point pipelines, and / or memory access pipelines, each having its own scheduler unit, one or more physical register file units, and / or execution clusters—and in the case of separate memory access pipelines, some embodiments are implemented in which only the execution cluster of that pipeline has one or more memory access units 2864).It should also be understood that, in the case of using separate pipelines, one or more of these pipelines may be unordered releases / executions while the rest are ordered.

[0380] The memory access unit 2864 is coupled to memory unit 2870, which includes a data TLB unit 2872. The data TLB unit 2872 is coupled to data cache unit 2874, which is coupled to level 2 (L2) cache unit 2876. In one exemplary embodiment, memory access unit 2864 may include a load unit, a memory address unit, and a memory data unit, each of which is coupled to the data TLB unit 2872 in memory unit 2870. Instruction cache unit 2834 is further coupled to level 2 (L2) cache unit 2876 in memory unit 2870. L2 cache unit 2876 is coupled to one or more other levels of cache and ultimately coupled to main memory.

[0381] By way of example, the exemplary register renaming, out-of-order release / execution core architecture can implement pipeline 2800 as follows: 1) Instruction fetch 2838 performs fetch and length decoding stages 2802 and 2804; 2) Decoding unit 2840 performs decoding stage 2806; 3) Rename / allocator unit 2852 performs allocation stage 2808 and rename stage 2810; 4) (one or more) scheduler unit 2856 performs scheduling stage 2812; 5) (one or more) physical register file unit 2858 and memory unit 2870 perform register read / memory read stage 2814; execution cluster 2860 performs execution stage 2816; 6) memory unit 2870 and (one or more) physical register file unit 2858 perform write-back / memory write stage 2818; 7) various units may be involved in exception handling stage 2822; and 8) retirement unit 2854 and (one or more) physical register file unit 2858 perform commit stage 2824.

[0382] Core 2890 may support one or more instruction sets (e.g., the x86 instruction set (with some extensions added in newer versions); the MIPS instruction set of MIPS Technologies, Sunnyvale, California; the ARM instruction set of ARM Holdings, Sunnyvale, California (with optional additional extensions such as NEON)), including one or more instructions described herein. In one embodiment, Core 2890 includes logic for supporting packaged data instruction set extensions (e.g., AVX1, AVX2), thereby allowing the use of packaged data to perform operations used by a variety of multimedia applications.

[0383] It should be understood that a core can support multithreading (execution of two or more parallel sets of operations or threads) and can do so in various ways, including time-slice multithreading, simultaneous multithreading (where a single physical core provides a logical core for each of the threads that are being multithreaded simultaneously), or combinations thereof (e.g., time-slice extraction and decoding followed by simultaneous multithreading, such as in...). (like in hyper-threading technology).

[0384] Although register renaming is described in an out-of-order execution scenario, it should be understood that register renaming can be used in ordered architectures. While the illustrated processor embodiments also include separate instruction and data cache units 2834 / 2874 and a shared L2 cache unit 2876, alternative embodiments may have a single internal cache for both instructions and data, such as, for example, a Level 1 (L1) internal cache or a multi-level internal cache. In some embodiments, the system may include a combination of internal caches and external caches located outside the core and / or processor. Alternatively, all caches may be located outside the core and / or processor.

[0385] Specific Exemplary Ordered Core Architecture

[0386] Figure 29A -B illustrates a more specific exemplary ordered core architecture block diagram, where the core will be one of several logic blocks in the chip (including other cores of the same type and / or different types). The logic blocks communicate through a high-bandwidth interconnect network (e.g., a ring network) with certain fixed-function logic, memory I / O interfaces, and other necessary I / O logic (depending on the application).

[0387] Figure 29A This is a block diagram of a single processor core according to an embodiment of the invention, its connection to the on-die interconnect network 2902, and a local subset 2904 of its Level 2 (L2) cache. In one embodiment, the instruction decoder 2900 supports the x86 instruction set with Packed Data Instruction Set Extensions. The L1 cache 2906 allows low-latency access to cache memory in scalar and vector units. Although (for design simplification) in one embodiment scalar unit 2908 and vector unit 2910 use separate register sets (scalar register 2912 and vector register 2914, respectively) and data transferred between them is written to memory and then read back from the Level 1 (L1) cache 2906, alternative embodiments of the invention may use different methods (e.g., using a single register set or including a communication path that allows data transfer between two register files without write-and-read-back).

[0388] The local subset 2904 of the L2 cache is part of the global L2 cache, which is divided into separate local subsets for each processor core. Each processor core has a direct access path to its own local subset 2904 of the L2 cache. Data read by a processor core is stored in its L2 cache subset 2904 and can be accessed quickly, in parallel with other processor cores accessing their own local L2 cache subsets. Data written by a processor core is stored in its own L2 cache subset 2904 and is evicted from other subsets if necessary. A ring network ensures the consistency of shared data. This ring network is bidirectional to allow agents such as processor cores, L2 caches, and other logical blocks to communicate with each other within the chip. Each ring data path is 1024 bits wide in each direction.

[0389] Figure 29B This is according to an embodiment of the present invention. Figure 29A An expanded diagram of the processor core. Figure 29B This includes L1 data cache 2906A (part of L1 cache 2904) and further details regarding vector unit 2910 and vector register 2914. Specifically, vector unit 2910 is a 16-wide vector processing unit (VPU) (see 16-wide ALU 2928) that executes one or more of integer instructions, single-precision float instructions, and double-precision float instructions. The VPU supports mixing register inputs using mixing unit 2920, performing value conversions using value conversion units 2922A-B, and copying memory inputs using copy unit 2924. Write mask register 2926 allows prediction of the resulting vector writes.

[0390] Figure 30 This is a block diagram of a processor 3000 according to an embodiment of the present invention, which may have more than one core, may have an integrated memory controller, and may have an integrated graphics device. Figure 30 The solid-line box in the diagram illustrates a processor 3000 having a single core 3002A, a system agent 3010, and a group of one or more bus controller units 3016, while the dashed-line box represents an alternative processor 3000 having multiple cores 3002A-N, a group of one or more integrated memory controller units 3014 in the system agent units 3010, and dedicated logic 3008.

[0391] Therefore, different implementations of processor 3000 may include: 1) a CPU with dedicated logic 3008 integrating graphics and / or scientific (throughput) logic (which may include one or more cores), and cores 3002A-N being one or more general-purpose cores (e.g., general-purpose ordered cores, general-purpose unordered cores, or a combination of both); 2) a coprocessor with cores 3002A-N, which are a large number of dedicated cores primarily used for graphics and / or scientific (throughput); and 3) a coprocessor with cores 3002A-N, which are a large number of general-purpose ordered cores. Thus, processor 3000 can be a general-purpose processor, a coprocessor, or a dedicated processor, such as, for example, a network or communication processor, a compression engine, a graphics processor, a GPGPU (General-Purpose Graphics Processing Unit), a high-throughput multi-integrated-core (MIC) coprocessor (including 30 or more cores), an embedded processor, etc. The processor can be implemented on one or more chips. The processor 3000 may be part of one or more substrates, or the processor 3000 may be implemented on one or more substrates using any of a variety of process technologies, such as, for example, BiCMOS, CMOS or NMOS.

[0392] The memory hierarchy includes one or more levels of cache within the core, a set of one or more shared cache units 3006, and external memory (not shown) coupled to the set of integrated memory controller units 3014. The set of shared cache units 3006 may include one or more intermediate-level caches, such as Level 2 (L2), Level 3 (L3), Level 4 (L4), or other levels of cache, Last Level Cache (LLC), and / or combinations thereof. While in one embodiment the integrated graphics logic 3008 (which is an example of dedicated logic and is also referred to herein as dedicated logic), the set of shared cache units 3006, and the system proxy units 3010 / (one or more) of the integrated memory controller units 3014 are interconnected based on a ring interconnect unit 3012, alternative embodiments may use any number of known techniques to interconnect such units. In one embodiment, consistency is maintained between one or more cache units 3006 and cores 3002A-N.

[0393] In some embodiments, one or more of the cores 3002A-N are capable of multithreading. System agent 3010 includes those components that coordinate and operate the cores 3002A-N. System agent unit 3010 may include, for example, a power control unit (PCU) and a display unit. The PCU may be, or include, the logic and components required to regulate the power state of the cores 3002A-N and the integrated graphics logic 3008. The display unit is used to drive one or more externally connected displays.

[0394] In terms of the instruction set architecture, cores 3002A-N can be homogeneous or heterogeneous; that is, two or more cores of 3002A-N can execute the same instruction set, while other cores can execute only a subset of that instruction set or execute different instruction sets.

[0395] Exemplary computer architecture

[0396] Figures 31-34 This is a block diagram of an exemplary computer architecture. Other system designs and configurations known in the field of laptops, desktop computers, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, microcontrollers, cellular phones, portable media players, handheld devices, and various other electronic devices are also suitable. In general, a wide variety of systems or electronic devices capable of incorporating processors and / or other execution logic as disclosed herein are generally suitable.

[0397] Now for reference Figure 31 A block diagram of a system 3100 according to an embodiment of the present invention is shown. System 3100 may include one or more processors 3110, 3115 coupled to a controller hub 3120. In one embodiment, the controller hub 3120 includes a graphics memory controller hub (GMCH) 3190 and an input / output hub (IOH) 3150 (which may be on a separate chip); the GMCH 3190 includes memory and a graphics controller, to which a memory 3140 and a coprocessor 3145 are coupled; the IOH 3150 couples an input / output (I / O) device 3160 to the GMCH 3190. Alternatively, one or both of the memory and the graphics controller are integrated within the processor (as described herein), with the memory 3140 and the coprocessor 3145 directly coupled to the processor 3110 and the controller hub 3120 on a single chip with the IOH 3150.

[0398] exist Figure 31 The optional nature of the additional processor 3115 is indicated by a dashed line. Each processor 3110, 3115 may include one or more of the processing cores described herein and may be a version of processor 3000.

[0399] The memory 3140 may be, for example, dynamic random access memory (DRAM), phase-change memory (PCM), or a combination of both. For at least one embodiment, the controller hub 3120 communicates with one or more processors 3110, 3115 via a multipoint bus 3195, such as a front-side bus (FSB), a point-to-point interface (such as a fast path interconnect (QPI)), or a similar connection.

[0400] In one embodiment, the coprocessor 3145 is a dedicated processor, such as, for example, a high-throughput MIC processor, a network or communication processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, and so on. In one embodiment, the controller hub 3120 may include an integrated graphics accelerator.

[0401] In terms of the metric spectrum including advantages such as architecture, microarchitecture, thermal properties, and power consumption characteristics, there can be various differences between physical resources 3110 and 3115.

[0402] In one embodiment, processor 3110 executes instructions that control general-type data processing operations. Embedded within these instructions may be coprocessor instructions. Processor 3110 identifies these coprocessor instructions as types to be executed by an attached coprocessor 3145. Therefore, processor 3110 sends these coprocessor instructions (or control signals representing coprocessor instructions) to coprocessor 3145 on a coprocessor bus or other interconnect. One or more coprocessors 3145 receive and execute the received coprocessor instructions.

[0403] Now for reference Figure 32 A block diagram of a first, more specific, exemplary system 3200 according to an embodiment of the present invention is shown. Figure 32 As shown, the multiprocessor system 3200 is a point-to-point interconnect system and includes a first processor 3270 and a second processor 3280 coupled via a point-to-point interconnect 3250. Each of processors 3270 and 3280 may be a version of processor 3000. In one embodiment of the invention, processors 3270 and 3280 are processors 3110 and 3115, respectively, and coprocessor 3238 is coprocessor 3145. In another embodiment, processors 3270 and 3280 are processor 3110 and coprocessor 3145, respectively.

[0404] Processors 3270 and 3280 are shown as including integrated memory controller (IMC) units 3272 and 3282, respectively. Processor 3270 also includes point-to-point (PP) interfaces 3276 and 3278 as part of its bus controller unit; similarly, the second processor 3280 includes PP interfaces 3286 and 3288. Processors 3270 and 3280 can exchange information via point-to-point (PP) interface 3250 using PP interface circuits 3278 and 3288. Figure 32 As shown, IMC 3272 and 3282 couple the processor to the corresponding memory, namely memory 3232 and memory 3234, which may be portions of the main memory locally attached to the corresponding processor.

[0405] Processors 3270 and 3280 can exchange information with chipset 3290 via point-to-point interface circuits 3276, 3294, 3286, and 3298 through separate PP interfaces 3252 and 3254. Chipset 3290 can optionally exchange information with coprocessor 3238 via high-performance interface 3292. In one embodiment, coprocessor 3238 is a dedicated processor, such as, for example, a high-throughput MIC processor, a network or communication processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, etc.

[0406] A shared cache (not shown) may be included in either processor or outside of both processors, or connected to the processors via a PP interconnect, such that if the processors are put into a low-power mode, the local cache information of either or both processors may be stored in the shared cache.

[0407] Chipset 3290 can be coupled to first bus 3216 via interface 3296. In one embodiment, first bus 3216 may be a peripheral component interconnect (PCI) bus, or a bus such as PCI Fast Bus or another third-generation I / O interconnect bus, but the scope of the invention is not limited thereto.

[0408] like Figure 32As shown, various I / O devices 3214 can be coupled to a first bus 3216 and a bus bridge 3218, which couples the first bus 3216 to a second bus 3220. In one embodiment, one or more additional processors 3215, such as a coprocessor, a high-throughput MIC processor, a GPGPU, an accelerator (such as, for example, a graphics accelerator or digital signal processing (DSP) unit), a field-programmable gate array, or any other processor, are coupled to the first bus 3216. In one embodiment, the second bus 3220 may be a low pin count (LPC) bus. Various devices can be coupled to the second bus 3220, including, for example, a keyboard and / or mouse 3222, a communication device 3227, and a storage unit 3228, such as a disk drive or other mass storage device, which in one embodiment may include instructions / code and / or data 3230. Furthermore, audio I / O 3224 can be coupled to the second bus 3216. Note that other architectures are also possible. For example, as Figure 32 As an alternative to point-to-point architecture, the system can implement multi-point bus or other similar architectures.

[0409] Now for reference Figure 33 The diagram shows a block diagram of a second, more specific, exemplary system 3300 according to an embodiment of the present invention. Figure 32 and 33 Similar elements in the figures have similar reference numerals, and from Figure 33 The middle part is omitted Figure 32 certain aspects in order to avoid ambiguity Figure 33 Other aspects.

[0410] Figure 33 For example, processors 3270 and 3280 may include integrated memory and I / O control logic (“CL”) 3372 and 3382, respectively. Therefore, CL 3372 and 3382 include an integrated memory controller unit and I / O control logic. Figure 33 For example, not only are memories 3232 and 3234 coupled to CLs 3272 and 3282, but I / O device 3314 is also coupled to control logic 3272 and 3282. Legacy I / O device 3315 is coupled to chipset 3290.

[0411] Now for reference Figure 34 A block diagram of a SoC 3400 according to an embodiment of the present invention is shown. Figure 30 Similar components in the diagram have similar reference numerals. Furthermore, the dashed box is an optional feature on more advanced SoCs. Figure 34In this embodiment, one or more interconnect units 3402 are coupled to: an application processor 3410, which includes a set of one or more cores 3002A-N comprising cache units 3004A-N and one or more shared cache units 3006; a system proxy unit 3010; one or more bus controller units 3016; one or more integrated memory controller units 3014; a set of one or more coprocessors 3420, which may include integrated graphics logic, an image processor, an audio processor, and a video processor; a static random access memory (SRAM) unit 3430; a direct memory access (DMA) unit 3432; and a display unit 3440 for coupling to one or more external displays. In one embodiment, the one or more coprocessors 3420 are dedicated processors, such as, for example, network or communication processors, compression engines, GPGPUs, high-throughput MIC processors, embedded processors, and so on.

[0412] Embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementations. Embodiments of the invention may be implemented as computer programs or program code that execute on a programmable system comprising at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0413] Applications such as Figure 32 Program code such as code 3230, as illustrated herein, is used to input instructions to perform the functions described herein and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, the processing system includes any system having a processor, such as, for example, a digital signal processor (DSP), a microcontroller, an application-specific integrated circuit (ASIC), or a microprocessor.

[0414] The program code can be implemented in a high-level programming language or an object-oriented programming language to communicate with the processing system. If desired, it can also be implemented in assembly language or machine language. In fact, the mechanisms described in this paper are not limited to any particular programming language. In any case, the language can be a compiled language or an interpreted language.

[0415] One or more aspects of at least one embodiment can be implemented by representative instructions representing various logics within a processor, stored on a machine-readable medium, which, when read by a machine, cause the machine to manufacture logic to implement the techniques described herein. Such a representation, known as an "IP core," can be stored on a tangible machine-readable medium and supplied to various customers or manufacturing facilities for loading into manufacturing machines that actually manufacture the logic or processor.

[0416] Such machine-readable storage media may include, without limitation, arrangements of non-transitory tangible articles made or formed by a machine or device, including storage media such as hard disks, any other type of disk (including floppy disks, optical disks, compact disc read-only memory (CD-ROM), compact disc rewritable device (CD-RW), and magneto-optical disks), semiconductor devices (such as read-only memory (ROM), random access memory (RAM) (such as dynamic random access memory (DRAM), static random access memory (SRAM)), erasable programmable read-only memory (EPROM), flash memory, electrically erasable programmable read-only memory (EEPROM), phase-change memory (PCM)), magnetic cards or optical cards, or any other type of media suitable for storing electronic instructions.

[0417] Accordingly, embodiments of the invention also include a non-transitory tangible machine-readable medium containing instructions or design data (such as a hardware description language (HDL)) that defines the architectures, circuits, devices, processors, and / or system features described herein. Such embodiments may also be referred to as program products.

[0418] Simulation (including binary translation, code transformation, etc.)

[0419] In some cases, an instruction translator can be used to translate instructions from a source instruction set into a target instruction set. For example, an instruction translator can translate (e.g., using static binary translation, including dynamic binary translation with dynamic compilation), transform, emulate, or otherwise translate instructions into one or more other instructions to be processed by the kernel. Instruction translators can be implemented in software, hardware, firmware, or a combination thereof. Instruction translators can be on-processor, off-processor, or partially on-processor and partially off-processor.

[0420] Figure 35 This is a block diagram illustrating the use of a software instruction converter to convert binary instructions in a source instruction set into binary instructions in a target instruction set, according to an embodiment of the present invention. In the illustrated embodiment, the instruction converter is a software instruction converter; however, alternatively, the instruction converter may be implemented in software, firmware, hardware, and various combinations thereof. Figure 35A program in the form of a high-level language 3502 can be compiled using an x86 compiler 3504 to generate x86 binary code 3506, which can be natively executed by a processor 3516 having at least one x86 instruction set core. A processor 3516 having at least one x86 instruction set core means any processor that can substantially perform the same function as an Intel processor having at least one x86 instruction set core by mutually compatiblely executing or otherwise processing the following: (1) a substantial portion of the instruction set of the Intel x86 instruction set core or (2) a version of object code for an application or other software targeted to run on an Intel processor having at least one x86 instruction set core, in order to substantially achieve the same result as an Intel processor having at least one x86 instruction set core. An x86 compiler 3504 means a compiler operable to generate x86 binary code 3506 (e.g., object code), which can be executed on a processor 3516 having at least one x86 instruction set core with or without additional linking processing. Similarly, Figure 35 A program in the form of a high-level language 3502 is shown to be compiled using a replacement instruction set compiler 3508 to generate replacement instruction set binary code 3510, which can be natively executed by a processor 3514 that does not have at least one x86 instruction set core (e.g., a processor with a core that executes the MIPS instruction set of MIPS Technologies, Sunnyvale, California, and / or the ARM instruction set of ARM Holdings, Sunnyvale, California). An instruction converter 3512 is used to translate the x86 binary code 3506 into code that can be natively executed by a processor 3514 that does not have an x86 instruction set core. This translated code is likely not identical to the replacement instruction set binary code 3510, as instruction converters capable of doing so are difficult to manufacture; however, the translated code will perform general operations and consist of instructions from the replacement instruction set. Therefore, the instruction converter 3512 represents software, firmware, hardware, or a combination thereof that allows a processor or other electronic device without an x86 instruction set processor or core to execute the x86 binary code 3506 through emulation, simulation, or any other process.

Claims

1. An apparatus comprising: Multiple storage controllers; Secondary (L2) cache memory coupled to the plurality of memory controllers; as well as A processor coupled to the plurality of memory controllers and coupled to the L2 cache memory, the processor having a plurality of cores, each core including circuitry for executing operations corresponding to instructions indicating: a first matrix having M rows × K columns of 32-bit elements, each 32-bit element having eight 4-bit data elements; A second matrix with K rows × N columns of 32-bit elements, where each 32-bit element has eight 4-bit data elements; And a third matrix having M rows × N columns; the instructions have a first indicator for indicating whether the 4-bit data elements of the first matrix are signed or unsigned, and a second indicator for indicating whether the 4-bit data elements of the second matrix are signed or unsigned, the operation including: For each row m in the M rows of the first matrix, and for each column n in the N columns of the second matrix: For each of the K 32-bit elements in row m of the first matrix: Multiply the eight 4-bit data elements of the 32-bit element in row m of the first matrix with the corresponding data elements of the eight 4-bit data elements of the corresponding 32-bit element in column n of the second matrix to generate eight products. as well as The 32-bit result data element is stored in row m of the M rows and column n of the N columns of the third matrix. The 32-bit result data element is based on the sum of eight products generated for each of the K 32-bit elements of the first matrix row m and the 32-bit data elements corresponding to the first matrix row m and the second matrix column n.

2. The apparatus according to claim 1, wherein, The operation further includes performing saturation to generate the 32-bit result data element.

3. The apparatus according to claim 2, wherein, Execution saturation includes execution signed saturation.

4. The apparatus according to claim 1, wherein, K is 4.

5. The apparatus according to claim 4, wherein, M is one of 2, 4, 8, and 16.

6. The apparatus according to claim 1, wherein, The first matrix is ​​to be stored in multiple registers of the processor, and the second matrix is ​​to be stored in multiple registers of the processor.

7. The apparatus of claim 1, further comprising an interconnect interface coupled to the processor.

8. The apparatus of claim 1, further comprising a bus controller interface coupled to the processor.

9. The apparatus according to claim 1, wherein, The kernel includes a graphics kernel.

10. The apparatus according to claim 1, wherein, The core includes heterogeneous graphic cores.

11. The apparatus of claim 1, further comprising an instruction converter for converting the instructions into one or more instructions of different instruction sets executable by the core.

12. The apparatus according to claim 1, wherein, One of the first and second matrices has a signed 4-bit data element, while the other of the first and second matrices has an unsigned 4-bit data element.

13. An apparatus comprising: The circuit to receive the instruction indicates: a first matrix having M rows × K columns of 32-bit elements, each 32-bit element having eight 4-bit data elements; A second matrix with K rows × N columns of 32-bit elements, where each 32-bit element has eight 4-bit data elements; And a third matrix having M rows × N columns; the instructions have a first indicator for indicating whether the 4-bit data elements of the first matrix are signed or unsigned, and a second indicator for indicating whether the 4-bit data elements of the second matrix are signed or unsigned; as well as An execution circuit, which performs an operation corresponding to the instruction, including: For each row m in the M rows of the first matrix, and for each column n in the N columns of the second matrix: For each of the K 32-bit elements in row m of the first matrix: Multiply the eight 4-bit data elements of the 32-bit element in row m of the first matrix with the corresponding data elements of the eight 4-bit data elements of the corresponding 32-bit element in column n of the second matrix to generate eight products. as well as The 32-bit result data element is stored in row m of the M rows and column n of the N columns of the third matrix. The 32-bit result data element is based on the sum of eight products generated for each of the K 32-bit elements of the first matrix row m and the 32-bit data elements corresponding to the first matrix row m and the second matrix column n.

14. An apparatus comprising: An instruction converter that translates a first instruction into one or more other instructions, the first instruction indicating: a first matrix having M rows × K columns of 32-bit elements, each 32-bit element having eight 4-bit data elements; A second matrix with K rows × N columns of 32-bit elements, where each 32-bit element has eight 4-bit data elements; And a third matrix having M rows × N columns; the instructions have a first indicator for indicating whether the 4-bit data elements of the first matrix are signed or unsigned, and a second indicator for indicating whether the 4-bit data elements of the second matrix are signed or unsigned; as well as An execution circuit, which performs an operation corresponding to the first instruction, including: For each row m in the M rows of the first matrix, and for each column n in the N columns of the second matrix: For each of the K 32-bit elements in row m of the first matrix: Multiply the eight 4-bit data elements of the 32-bit element in row m of the first matrix with the corresponding data elements of the eight 4-bit data elements of the corresponding 32-bit element in column n of the second matrix to generate eight products. as well as The 32-bit result data element is stored in row m of the M rows and column n of the N columns of the third matrix. The 32-bit result data element is based on the sum of eight products generated for each of the K 32-bit elements of the first matrix row m and the 32-bit data elements corresponding to the first matrix row m and the second matrix column n.

15. A method comprising: Use multiple storage controllers to access the memory; Data is stored in the Level 2 (L2) cache memory; as well as Processing data with a processor having multiple cores involves executing operations corresponding to instructions that indicate: a first matrix having M rows × K columns of 32-bit elements, each 32-bit element having eight 4-bit data elements; A second matrix with K rows × N columns of 32-bit elements, where each 32-bit element has eight 4-bit data elements; And a third matrix having M rows × N columns; the instruction has a first indicator indicating whether the 4-bit data elements of the first matrix are signed or unsigned, and a second indicator indicating whether the 4-bit data elements of the second matrix are signed or unsigned, the operation including: For each row m in the M rows of the first matrix, and for each column n in the N columns of the second matrix: For each of the K 32-bit elements in row m of the first matrix: Multiply the eight 4-bit data elements of the 32-bit element in row m of the first matrix with the corresponding data elements of the eight 4-bit data elements of the corresponding 32-bit element in column n of the second matrix to generate eight products. as well as The 32-bit result data element is stored in row m of row M and column n of column N of the third matrix. The 32-bit result data element is the sum of eight products generated based on each of the K 32-bit elements of row m of the first matrix and the 32-bit data elements corresponding to row m of the first matrix and column n of the second matrix.

16. The method according to claim 15, wherein, The operation further includes performing saturation to generate the 32-bit result data element.

17. The method according to claim 16, wherein, Execution saturation includes execution signed saturation.

18. The method according to claim 15, wherein, K is 4.

19. The method according to claim 15, wherein, M is one of 2, 4, 8, and 16.

20. The method of claim 15, further comprising accessing a first matrix from a plurality of registers of the processor, and accessing a second matrix from a plurality of registers of the processor.

21. The method according to claim 15, wherein, The core includes heterogeneous graphic cores.

22. The method of claim 15, further comprising converting the instructions into one or more instructions of a different instruction set executable by the core.

23. The method according to claim 15, wherein, One of the first and second matrices has a signed 4-bit data element, while the other of the first and second matrices has an unsigned 4-bit data element.

24. A machine-readable medium having instructions that, when executed, cause the machine to perform the method according to any one of claims 15 to 23.

25. An apparatus comprising components for performing the method according to any one of claims 15 to 23.

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