A communication chip and electronic device
By integrating the user identification module and communication module within the system-in-package and setting up circuitry to prevent backflow of current, the problems of resource waste and complexity in existing technologies are solved, resulting in a reduction in the number of pins and improved security, thereby enhancing product competitiveness.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHINA MOBILE M2M
- Filing Date
- 2022-03-23
- Publication Date
- 2026-07-24
AI Technical Summary
In existing technologies, wireless communication chips and user identification modules in system-in-package (SIP) structures each need to retain 10 independent functional ports, resulting in resource waste and increased circuit board complexity. In particular, fewer pins are more competitive in low-cost applications.
By integrating the user identification module and the communication module into a system-in-package (SIPP), and by setting up a first circuit to connect the first and second pins, current backflow is prevented, reducing the number of pins to 6, thereby improving security and integration.
This effectively reduces the number of pins in communication chip packaging, lowers costs, improves security and integration, and enhances product competitiveness.
Smart Images
Figure CN116864495B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of wireless technology, and in particular to a communication chip and electronic device. Background Technology
[0002] With the rapid development of IoT technology, more and more IoT terminals are connecting to the Internet. Each IoT terminal requires not only a wireless communication chip for communication but also a user identification module that provides network access authentication and identity verification functions. To reduce the size of the solution board, more and more manufacturers are adopting a system-in-package (SIP) architecture to encapsulate the user identification module within the wireless communication chip.
[0003] In existing technologies, to preserve the initialization writing of personalized data to the user identification module by the issuing device after chip packaging, five independent functional ports (power port, ground port, clock port, data port, and reset port) are required. Simultaneously, the wireless communication chip also needs to retain the same five independent functional ports for board-level connectivity. For some low-cost applications, fewer pins on the chip result in lower operating costs; therefore, it is necessary to further reduce the number of pins occupied by the SIP-structured user identification module. Summary of the Invention
[0004] The purpose of this invention is to provide a communication chip and electronic device to avoid the problems of wasted resources in the SIP structure or the complex circuit board design of the communication chip in the prior art.
[0005] To achieve the above objectives, embodiments of the present invention provide a communication chip, comprising: a user identification module located within a system-in-package (SIP) structure; and a communication module located within the SIP structure and connected to the user identification module;
[0006] The user identification module includes at least one first pin, and the communication module includes at least one second pin, wherein the at least one first pin and the at least one second pin are connected correspondingly.
[0007] A first circuit is provided between the first target pin and the second target pin connected to the first target pin. Both the first target pin and the second target pin are non-power supply terminals and are non-grounded terminals.
[0008] Optionally, the first pin and the corresponding second pin are connected via a first trace within the SIP structure.
[0009] Optionally, when both the first pin and the second pin include a power port, a ground port, a clock port, a data port, and a reset port,
[0010] The ground port of the first pin is connected to the ground port of the second pin and is encapsulated into the first pin of the SIP structure;
[0011] The clock port of the first pin is connected to the clock port of the second pin, and is encapsulated into the second pin of the SIP structure;
[0012] The data port of the first pin is connected to the data port of the second pin, and is encapsulated into the third pin of the SIP structure;
[0013] The reset port of the first pin is connected to the reset port of the second pin and is encapsulated into the fourth pin of the SIP structure;
[0014] The power port of the first pin is packaged into the fifth pin of the SIP structure;
[0015] The power port of the second pin is packaged into the sixth pin of the SIP structure.
[0016] Optionally, the first circuit is provided between the clock port of the first pin and the clock port of the second pin, between the data port of the first pin and the data port of the second pin, and between the reset port of the first pin and the reset port of the second pin.
[0017] Optionally, the first circuit includes: a power supply port, a ground port, a first signal port, and a second signal port;
[0018] Between the power supply port and the grounding port are provided a driving circuit, a first protection circuit, and a second protection circuit.
[0019] A preset resistor is provided between the first signal port and the second signal port;
[0020] The power port and the second signal port are also respectively connected to a substrate voltage control circuit.
[0021] The first signal port is also connected to the first pin and the corresponding second pin.
[0022] Optionally, the driving circuit includes:
[0023] P-drive elements and N-drive elements;
[0024] The P-driving element is connected to the power port, the N-driving element is connected to the ground port, and the connection point between the P-driving element and the N-driving element is connected to the first signal port.
[0025] The P-driving element is also connected to the substrate voltage control circuit.
[0026] Optionally, the first protection circuit includes:
[0027] First PMOS transistor, first NMOS transistor, and second NMOS transistor;
[0028] The first PMOS transistor is connected to the power supply port, the first NMOS transistor is connected to the ground port, and the connection point between the first PMOS transistor and the first NMOS transistor is connected to the first end of the preset resistor.
[0029] The second NMOS transistor is connected to the ground port and the second end of the preset resistor, respectively;
[0030] The first PMOS transistor is also connected to the substrate voltage control circuit.
[0031] Optionally, the second protection circuit includes:
[0032] The second PMOS transistor, the third PMOS transistor, the third NMOS transistor, and the fourth NMOS transistor;
[0033] The second PMOS transistor and the third PMOS transistor are connected in series, the second PMOS transistor is connected to the power supply port, and the third PMOS transistor is connected to the second signal port;
[0034] The third NMOS transistor and the fourth NMOS transistor are connected in series, the third NMOS transistor is connected to the second signal port, and the fourth NMOS transistor is connected to the ground port;
[0035] The second PMOS transistor or the third PMOS transistor is also connected to the substrate voltage control circuit.
[0036] Optionally, the substrate voltage control circuit includes:
[0037] The fourth PMOS transistor, the fifth PMOS transistor, the sixth PMOS transistor, and the substrate voltage port;
[0038] The substrate voltage port is connected to the P driving element, the first PMOS transistor, and the second PMOS transistor, respectively.
[0039] The substrate voltage port is also connected to the fourth PMOS transistor, the fifth PMOS transistor, and the sixth PMOS transistor, respectively;
[0040] The fourth PMOS transistor is connected to the power supply port and the second signal port, respectively.
[0041] The sixth PMOS transistor is connected to the power supply port and the second signal port respectively;
[0042] The fifth PMOS transistor is connected to both the power supply port and the fourth PMOS transistor.
[0043] To achieve the above objectives, embodiments of the present invention also provide an electronic device, the electronic device including the communication chip as described in any of the preceding claims.
[0044] The beneficial effects of the above-described technical solution of the present invention are as follows:
[0045] The communication chip provided in this embodiment of the invention includes: a user identification module located within a system-in-package (SIP) structure; and a communication module located within the SIP structure and connected to the user identification module. Here, the user identification module and the communication module are integrated into a single communication chip, avoiding resource waste during communication chip packaging. The user identification module includes at least one first pin, and the communication module includes at least one second pin, with the at least one first pin and the at least one second pin correspondingly connected. A first circuit is provided between the first target pin and the second target pin corresponding to the first target pin. Both the first target pin and the second target pin are non-power supply terminals and non-grounded terminals. This first circuit prevents current backflow into the communication chip, improving the safety of the communication chip. Attached Figure Description
[0046] Figure 1 This is one of the structural schematic diagrams of the communication chip provided in the embodiments of the present invention;
[0047] Figure 2 This is a second schematic diagram of the structure of the communication chip provided in an embodiment of the present invention;
[0048] Figure 3 This is a schematic diagram of the structure of the first circuit provided in an embodiment of the present invention;
[0049] Figure 4 This is a schematic diagram of the substrate voltage provided in an embodiment of the present invention. Detailed Implementation
[0050] To make the technical problems, technical solutions and advantages of the present invention clearer, a detailed description will be given below in conjunction with the accompanying drawings and specific embodiments.
[0051] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of the invention. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments.
[0052] In the description of the embodiments of the present invention, "inner" and "outer" refer to the structure itself. It should be understood that these directional terms are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the present invention.
[0053] Before introducing the technical solutions of the embodiments of the present invention, the relevant technologies will be explained first.
[0054] In related technologies, the SiP (System-in-Package) architecture typically encapsulates the communication module and the user identification chip together. Since the user identification chip needs to have its personalized data written to it via a dedicated device after encapsulation, the package needs to reserve five dedicated functional ports for data writing. Simultaneously, the communication module also needs to reserve five signal ports for connection via board-level traces on the product's solution board or module. Thus, the SiP architecture will have at least ten signal ports. Specifically, to allow for the initialization of personalized data writing to the user identification module by the issuing device after chip encapsulation, five independent functional ports (VDD, GND, CLK, DATA, RST) are reserved. The baseband chip also needs to reserve the same five independent functional ports for board-level connection, thus requiring a total of ten pins on the chip package.
[0055] However, for some low-cost applications, fewer pins on a chip result in lower operating costs. Even with the same number of pins, supporting more functions enhances competitiveness. Therefore, it is necessary to further reduce the complexity of SIP architecture design and the waste of SIP resources in order to control the number of pins occupied by communication chips.
[0056] like Figure 1 As shown, an optional embodiment of the present invention provides a communication chip, including: a user identification module 11 located within a system-in-package (SIP) structure 10; and a communication module 12 located within the SIP structure 10 and connected to the user identification module 11.
[0057] In this embodiment of the invention, as the size of communication devices becomes smaller and the functions integrated into communication devices become more and more numerous, the size of communication modules also needs to become smaller and smaller. In this way, the user identification module 11 and the communication module 12 can be integrated into the SIP structure 10.
[0058] The user identification module 11 includes at least one first pin, and the communication module 12 includes at least one second pin, with the at least one first pin and the at least one second pin being connected accordingly.
[0059] A first circuit is provided between the first target pin and the second target pin connected to the first target pin. Both the first target pin and the second target pin are non-power supply terminals and are non-grounded terminals.
[0060] In this embodiment, the first target pin is one of the at least one first pin, and the second target pin is one of the at least one second pin. The function of the first circuit is to prevent current backflow into the user identification module 11 or the communication module 12, thereby improving the security of the communication chip. The communication module may consist of a main chip, an RF front-end, etc., but is not limited to a main chip and an RF front-end.
[0061] Optionally, the first pin and the corresponding second pin are connected via a first trace within the SIP structure 10.
[0062] In this embodiment, the first trace is, for example, a substrate trace or a bonding wire. The first pin and the corresponding second pin are packaged together within the SIP structure 10 via the first trace, thereby improving integration and further reducing the size of the IoT terminal on the PCB board. The mechanical reliability of the connection between the first pin and the corresponding second pin is greatly improved, and an absolute one-to-one match is achieved, significantly enhancing security.
[0063] In one specific embodiment, such as Figure 2 As shown, when both the first pin and the second pin include a power supply port (VDD), a ground port (GND), a clock port (CLK), a data port (DATA), and a reset port (RST),
[0064] The GND port of the first pin is connected to the GND_M port of the second pin (not shown in the figure) and is encapsulated into the first pin of the SIP structure 10;
[0065] The CLK port of the first pin is connected to the CLK_M port of the second pin (not shown in the figure) and is encapsulated into the second pin of the SIP structure 10;
[0066] The DATA port of the first pin is connected to the DATA_M port of the second pin (not shown in the figure) and is encapsulated into the third pin of the SIP structure 10;
[0067] The RST port of the first pin is connected to the RST_M port of the second pin (not shown in the figure) and is encapsulated into the fourth pin of the SIP structure 10;
[0068] The VDD port of the first pin is encapsulated into the fifth pin of the SIP structure 10;
[0069] The VDD_M port of the second pin is encapsulated into the sixth pin of the SIP structure 10.
[0070] In this embodiment, the first pin includes a VDD port, a GND port, a CLK port, a DATA port, and an RST port, and the second pin includes a VDD_M port, a GND_M port, a CLK_M port, a DATA_M port, and an RST_M port. Here, the VDD port is connected to the VDD_M port, the GND port is connected to the GND_M port, the CLK port is connected to the CLK_M port, the DATA port is connected to the DATA_M port, and the RST port is connected to the RST_M port.
[0071] The GND port of the first pin and the GND_M port of the second pin (not shown in the figure) are encapsulated into the first pin of the SIP structure 10, i.e., the GND pin of the SIP structure 10; the CLK port of the first pin and the CLK_M port of the second pin (not shown in the figure) are encapsulated into the second pin of the SIP structure 10, i.e., the CLK pin of the SIP structure 10; the DATA port of the first pin and the DATA_M port of the second pin (not shown in the figure) are encapsulated into the second pin of the SIP structure 10. The three pins are the DATA pin of the SIP structure 10; the RST port of the first pin and the RST_M port of the second pin (not shown in the figure) are encapsulated into the fourth pin of the SIP structure 10, i.e., the RST pin of the SIP structure 10; the VDD port of the first pin is encapsulated into the fifth pin of the SIP structure 10, i.e., the VDD pin of the SIP structure 10; the VDD_M port of the second pin is encapsulated into the sixth pin of the SIP structure 10, i.e., the VDD_M pin of the SIP structure 10.
[0072] The present invention connects the four pins of the user identification module to the four pins of the communication module on the same pin of the package (excluding the power port), reducing the number of chip pins required from 10 to 6. This allows the functionality achieved by the existing 10-pin solution to be accomplished with only 6 pins, significantly reducing the number of pins required during packaging. This reduces the cost of using communication chip products and improves product competitiveness.
[0073] Optionally, the first circuit is provided between the clock port of the first pin and the clock port of the second pin, between the data port of the first pin and the data port of the second pin, and between the reset port of the first pin and the reset port of the second pin.
[0074] In this embodiment, a double bonding method is used to connect the pins of the user identification module 11 and the pins of the communication module 12 to the same pin of the SIP structure, including the four ports CLK, DATA, RST, and GND. To achieve this simplified connection, the ports on the communication module 12 need to have backflow prevention functionality. Therefore, a first circuit is provided in the above-mentioned structure to prevent current from flowing back into the wireless communication chip through these ports when the user identification module 11 is powered on while the communication module 12 is powered off, thus preventing damage to the chip.
[0075] In one specific embodiment, such as Figure 3 As shown, the first circuit includes: a power supply port (VDD power supply), a ground port (GND terminal), a first signal port (PAD terminal), and a second signal port (PADIN terminal).
[0076] Between the power supply port and the grounding port are provided a driving circuit, a first protection circuit, and a second protection circuit.
[0077] A preset resistor R is provided between the first signal port and the second signal port;
[0078] The power port and the second signal port are also respectively connected to a substrate voltage control circuit.
[0079] The first signal port (PAD end) is also connected to the first pin and the corresponding second pin.
[0080] The power supply VDD_M of the communication module and the power supply VDD of the user identification module are connected to different pins. Since the power supply carries a large current, it is not possible to add backflow protection. Therefore, the connection is made at the board level after the user identification module completes the personalized data writing.
[0081] In this embodiment, the driving circuit is used to drive the communication chip to work, the first protection circuit is an electrostatic discharge (ESD) protection circuit, the second protection circuit is a pull-up protection circuit or a pull-down protection circuit, the substrate voltage control circuit is used to provide the substrate voltage, and the preset resistor R is used to filter out voltage noise input through the PAD terminal.
[0082] Optionally, the driving circuit includes:
[0083] P-drive elements and N-drive elements;
[0084] The P-driving element is connected to the power port, the N-driving element is connected to the ground port, and the connection point between the P-driving element and the N-driving element is connected to the first signal port (PAD terminal).
[0085] The P-driving element is also connected to the substrate voltage control circuit.
[0086] In this embodiment, the P driving element is preferably a PMOS transistor, and the N driving element is preferably an NMOS transistor. The input signal drives the P driving element and the N driving element through the first signal port (PAD terminal). That is, when there is an external input signal at the PAD terminal, the substrate voltage of the first PMOS transistor is the PAD terminal voltage. There is no equivalent diode that can conduct between the power supply port (VDD power supply) and the PAD terminal, that is, there is no return current between the power supply voltage terminal and the PAD terminal.
[0087] It should be noted that MOS is an abbreviation for MOSFET. MOSFET stands for Metal-Oxide-Semiconductor Field-Effect Transistor. Field-effect transistors are divided into PMOS (P-channel) and NMOS (N-channel) transistors, both belonging to the insulated-gate field-effect transistor category.
[0088] Optionally, the first protection circuit includes:
[0089] First PMOS transistor MP1, first NMOS transistor MN1, and second NMOS transistor MN2;
[0090] The first PMOS transistor MP1 is connected to the power supply port, the first NMOS transistor MN1 is connected to the ground port, and the connection point between the first PMOS transistor MP1 and the first NMOS transistor MN1 is connected to the first end of the preset resistor R.
[0091] The second NMOS transistor MN2 is connected to the ground port and the second end of the preset resistor R, respectively;
[0092] The first PMOS transistor MP1 is also connected to the substrate voltage control circuit.
[0093] In this embodiment, the first end of the preset resistor R is the first signal port (PAD end), and the second end of the preset resistor R is the second signal port (PADIN end). Here, three ESD protection circuits are designed: a first ESD protection circuit composed of the power supply port, the first PMOS transistor MP1, and the first signal port (PAD end); a second ESD protection circuit composed of the first signal port (PAD end), the first NMOS transistor MN1, and the ground port; and a third ESD protection circuit composed of the second signal port (PADIN end), the second NMOS transistor MN2, and the ground port. The first, second, and third ESD protection circuits are all used for electrostatic discharge and preventing backflow of current.
[0094] Optionally, the second protection circuit includes:
[0095] The second PMOS transistor MP2, the third PMOS transistor MP3, the third NMOS transistor MN3, and the fourth NMOS transistor MN4;
[0096] The second PMOS transistor MP2 and the third PMOS transistor MN3 are connected in series; the second PMOS transistor MP2 is connected to the power supply port; and the third PMOS transistor MP3 is connected to the second signal port (PADIN terminal).
[0097] The third NMOS transistor MN3 and the fourth NMOS transistor MN4 are connected in series, the third NMOS transistor MN3 is connected to the second signal port (PADIN terminal), and the fourth NMOS transistor MN4 is connected to the ground port;
[0098] The second PMOS transistor MP2 or the third PMOS transistor MP3 is also connected to the substrate voltage control circuit.
[0099] In this embodiment, the second PMOS transistor MP2 and the third PMOS transistor MN3 are connected in series, the second PMOS transistor MP2 is connected to the power supply port, and the third PMOS transistor MP3 is connected to the second signal port (PADIN terminal), together forming a pull-up control circuit; the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are connected in series, the third NMOS transistor MN3 is connected to the second signal port (PADIN terminal), and the fourth NMOS transistor MN4 is connected to the ground port, together forming a pull-down control circuit; wherein, the function of both the pull-up control circuit and the pull-down control circuit is to protect the circuit.
[0100] Here, "up" refers to a high-level signal, and "down" refers to a low-level signal. A pull-up signal connects to the power supply via the second PMOS transistor MP2 and the third PMOS transistor MP3, typically used for clock and data signals. A pull-down signal connects to ground via the third NMOS transistor MN3 and the fourth NMOS transistor MN4, typically used for protection signals. The main purpose of pull-up and pull-down control circuits is to prevent interference and increase circuit stability.
[0101] Without pull-up resistors, clock and data signals are prone to errors. After all, the CPU of a communication chip has limited power, and providing high-level signals is somewhat difficult when supporting many bus lines. If these signals are pulled down to a certain voltage by load or interference, the CPU cannot correctly receive information and issue instructions, and can only repeatedly reset and restart. Without pull-down resistors, the protection circuit is highly susceptible to external interference, causing the CPU to mistakenly believe that the protected object has a problem and take protective action, resulting in false protection.
[0102] In one specific embodiment, such as Figure 4 As shown, the substrate voltage control circuit includes:
[0103] The fourth PMOS transistor, the fifth PMOS transistor, the sixth PMOS transistor, and the substrate voltage port;
[0104] The substrate voltage port is connected to the P driving element, the first PMOS transistor, and the second PMOS transistor, respectively.
[0105] The substrate voltage port is also connected to the fourth PMOS transistor MP4, the fifth PMOS transistor MP5, and the sixth PMOS transistor MP6, respectively.
[0106] The fourth PMOS transistor MP4 is connected to the power supply port (VDD power supply) and the second signal port (PADIN terminal), respectively.
[0107] The sixth PMOS transistor MP6 is connected to the power supply port (VDD power supply) and the second signal port (PADIN terminal) respectively;
[0108] The fifth PMOS transistor MP5 is connected to the power supply port (VDD power supply) and the fourth PMOS transistor MP4, respectively.
[0109] In this embodiment, regardless of whether power is available, the fourth PMOS transistor MP4, the fifth PMOS transistor MP5, and the sixth PMOS transistor MP6 all need to be connected to the highest potential; otherwise, leakage current may easily occur due to PN junction conduction. This requires a substrate selection substrate voltage control circuit to adjust the substrate voltage.
[0110] comprehensive Figure 3 and Figure 4 As shown, when the power supply is normal, the output terminal drive transistor PMOS transistor ( Figure 4 The substrate of all PMOS transistors is connected to the power supply. When the VDD power supply is turned off, there is no power and the PAD terminal is at a high voltage. At this time, the substrate voltage control circuit adjusts the substrate voltage at the substrate voltage terminal to the PAD voltage.
[0111] The substrate voltage control circuit, in addition to controlling the substrate voltage at the substrate voltage terminal, also controls the PMOS transistor ( Figure 3 and Figure 4 The gate of all PMOS transistors also requires adjustment by the substrate voltage control circuit, achieved through switching logic timing. PMOS driver transistors ( Figure 3 and Figure 4 The gate of all PMOS transistors is connected to a high level by default for ESD protection. When the power supply is active, the gate is connected to the power supply; when the power supply is not active, but the PAD terminal is active, the switching logic circuit, i.e., the first circuit, will cause the PMOS transistor ( Figure 3 and Figure 4 The gate of all PMOS transistors is connected to the PAD. When the PMOS transistor ( Figure 3 and Figure 4 When all PMOS transistors in the circuit are used for output drive capability selection, the drive capability can only be configured through additional logic circuitry to select the high or low gate voltage, provided that the VDD power supply is powered.
[0112] In this scenario, the NMOS driver transistor ( Figure 3 All NMOS transistors have their substrates and gates grounded by default, so there is no leakage problem.
[0113] According to an embodiment of the present invention, the communication module can be a wireless communication chip for realizing the wireless communication function of Internet of Things (IoT) devices. It can be a communication chipset of any one or multiple modes, such as 2G, 4G, 5G, NB-IoT, or eMTC.
[0114] In one embodiment of the present invention, the communication module includes at least a baseband chip, and may also include other chips such as an application processor, a power management chip, and a memory chip.
[0115] In summary, because the communication module is in a power-off state during the personalized data writing process of the user identification module issuing device, leakage current paths exist between CLK and CLK_M, RST and RST_M, and DATA and DATA_M. Therefore, in the design of the communication chip, the first signal port (PAD end) of these three signal ports needs to have reverse current protection and ensure that the leakage current of these three ports is minimal when the communication module is powered off and the user identification module is powered on. In the design of the communication chip, the reverse current protection PAD circuit, i.e., the first circuit, with the structure described above, is used to ensure that no leakage current occurs and the chip is not damaged when the communication chip is powered off.
[0116] Embodiments of the present invention also provide an electronic device, the electronic device comprising the communication chip as described in any of the preceding claims.
[0117] It should be noted that the electronic devices of the present invention all include the structure of any of the above-mentioned communication chips and can achieve the corresponding technical effects, which will not be elaborated here.
[0118] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.
Claims
1. A communication chip, characterized in that, include: The user identification module is located within a system-in-package (SIP) structure. And a communication module, located within the SIP structure and connected to the user identification module; The user identification module includes at least one first pin, and the communication module includes at least one second pin, wherein the at least one first pin and the at least one second pin are connected correspondingly. A first circuit is provided between the first target pin and the second target pin connected to the first target pin. Both the first target pin and the second target pin are non-power supply terminals and are non-grounded terminals. The first target pin is one of the at least one first pin, and the second target pin is one of the at least one second pin. The first circuit is used to prevent current from flowing back into the user identification module or the communication module. The first circuit includes: a power supply port, a ground port, a first signal port, and a second signal port; a driving circuit, a first protection circuit, and a second protection circuit are provided between the power supply port and the ground port; a preset resistor is provided between the first signal port and the second signal port; the power supply port and the second signal port are also respectively connected to a substrate voltage control circuit; wherein, the first signal port is also respectively connected to the first pin and the corresponding second pin.
2. The communication chip according to claim 1, characterized in that, The first pin and the corresponding second pin are connected through a first trace within the SIP structure.
3. The communication chip according to claim 1, characterized in that, When both the first pin and the second pin include a power port, a ground port, a clock port, a data port, and a reset port, The ground port of the first pin is connected to the ground port of the second pin and is encapsulated into the first pin of the SIP structure; The clock port of the first pin is connected to the clock port of the second pin, and is encapsulated into the second pin of the SIP structure; The data port of the first pin is connected to the data port of the second pin, and is encapsulated into the third pin of the SIP structure; The reset port of the first pin is connected to the reset port of the second pin and is encapsulated into the fourth pin of the SIP structure; The power port of the first pin is packaged into the fifth pin of the SIP structure; The power port of the second pin is packaged into the sixth pin of the SIP structure.
4. The communication chip according to claim 3, characterized in that, The first circuit is respectively provided between the clock port of the first pin and the clock port of the second pin, between the data port of the first pin and the data port of the second pin, and between the reset port of the first pin and the reset port of the second pin.
5. The communication chip according to claim 1, characterized in that, The driving circuit includes: P-drive elements and N-drive elements; The P-driving element is connected to the power port, the N-driving element is connected to the ground port, and the connection point between the P-driving element and the N-driving element is connected to the first signal port. The P-driving element is also connected to the substrate voltage control circuit.
6. The communication chip according to claim 5, characterized in that, The first protection circuit includes: First PMOS transistor, first NMOS transistor, and second NMOS transistor; The first PMOS transistor is connected to the power supply port, the first NMOS transistor is connected to the ground port, and the connection point between the first PMOS transistor and the first NMOS transistor is connected to the first end of the preset resistor. The second NMOS transistor is connected to the ground port and the second end of the preset resistor, respectively; The first PMOS transistor is also connected to the substrate voltage control circuit.
7. The communication chip according to claim 6, characterized in that, The second protection circuit includes: The second PMOS transistor, the third PMOS transistor, the third NMOS transistor, and the fourth NMOS transistor; The second PMOS transistor and the third PMOS transistor are connected in series, the second PMOS transistor is connected to the power supply port, and the third PMOS transistor is connected to the second signal port; The third NMOS transistor and the fourth NMOS transistor are connected in series, the third NMOS transistor is connected to the second signal port, and the fourth NMOS transistor is connected to the ground port; The second PMOS transistor or the third PMOS transistor is also connected to the substrate voltage control circuit.
8. The communication chip according to claim 7, characterized in that, The substrate voltage control circuit includes: The fourth PMOS transistor, the fifth PMOS transistor, the sixth PMOS transistor, and the substrate voltage port; The substrate voltage port is connected to the P driving element, the first PMOS transistor, and the second PMOS transistor, respectively. The substrate voltage port is also connected to the fourth PMOS transistor, the fifth PMOS transistor, and the sixth PMOS transistor, respectively; The fourth PMOS transistor is connected to the power supply port and the second signal port, respectively. The sixth PMOS transistor is connected to the power supply port and the second signal port respectively; The fifth PMOS transistor is connected to both the power supply port and the fourth PMOS transistor.
9. An electronic device, characterized in that, The electronic device includes a communication chip as described in any one of claims 1 to 8.