Harmonic rejection receiver

Abstract

A radio frequency (RF) receiver is described, the RF receiver comprising: a plurality of analog mixing circuits including circuits for down-converting an input RF signal; a plurality of analog combining and scaling circuits operably connected to the analog mixing circuits and for generating a plurality of intermediate signals; a digital combining and scaling circuit operably connected to the analog combining and scaling circuits, the digital combining and scaling circuit comprising: in-phase signal component (I) circuitry for performing a first combining and scaling operation on a set of two or more of the plurality of intermediate signals to generate an in-phase signal component of a baseband signal; quadrature phase signal component (Q) circuitry for performing a second combining and scaling operation on another set of two or more of the plurality of intermediate signals to generate a quadrature phase signal component (Q) of the baseband signal.

Description

Technical Field

[0001] This invention generally relates to harmonic suppression receivers, and more particularly to radio frequency N-phase receivers. Background Technology

[0002] In a heterodyne wireless receiver, the wireless signal is multiplied or mixed with a local oscillator (LO) signal to produce a lower-frequency received signal, which is then filtered and processed to extract the information or message signal. In a direct-conversion receiver, the LO frequency is equal to the center frequency of the wireless signal, and the wireless signal is mixed with two versions of the LO signal, each 90 degrees out of phase. These two mixed signals are used to generate the in-phase (I) and quadrature-phase (Q) components of the received signal. In modern receivers, these two components of the received signal are generated in the analog domain, allowing subsequent digital processing circuitry to distinguish between received signals with frequencies higher than the LO signal and received signals with frequencies lower than the LO signal.

[0003] Mixers are typically implemented as simple metal-oxide-semiconductor field-effect transistor (MOSFET) switches or “passive” mixers. In this case, the LO signal behaves much like a square wave or pulse train signal, and is therefore rich in higher-order harmonics. Just as the fundamental frequency of the LO signal is mixed with the desired wireless signal to produce the required low-frequency signal for processing, these higher-order harmonics of the LO signal can also be mixed with higher-frequency interference signals whose frequencies are close to the harmonics of the desired wireless signal. Summary of the Invention

[0004] Typically, the first innovative aspect of the subject matter described in this specification can be embodied in a radio frequency (RF) receiver comprising: a plurality of analog mixer circuits, each mixer circuit including circuitry for down-converting an input RF signal by combining i) an input radio frequency (RF) signal with ii) a local oscillator (LO) signal, the LO signal being phase-shifted by a specified phase relative to the input RF signal to obtain a phase-shifted signal; a plurality of analog combining and scaling circuits operatively connected to the analog mixer circuits for generating a plurality of intermediate signals, wherein each analog combining and scaling circuit is used to scale and combine the plurality of phase-shifted signals using a first set of analog scaling factors to generate a corresponding intermediate signal; a converter for converting each of the plurality of intermediate signals from the plurality of combining and scaling circuits from analog to digital; and a digital combining and scaling circuit operatively connected to the analog combining and scaling circuits, the digital combining and scaling circuit including: an in-phase signal divider... A quantity (I) circuit is used to perform a first combination and scaling operation on a group of two or more intermediate signals from the plurality of intermediate signals to generate an in-phase signal component of the baseband signal; a quadrature phase signal component (Q) circuit is used to perform a second combination and scaling operation on another group of two or more intermediate signals from the plurality of intermediate signals to generate a quadrature phase signal component (Q) of the baseband signal, wherein the first combination and scaling operation includes multiplying each signal in the group of two or more intermediate signals from the plurality of intermediate signals by a first set of digital scaling factors, and the second combination and scaling operation includes multiplying each signal in the group of two or more intermediate signals from the plurality of intermediate signals by a second set of digital scaling factors.

[0005] In some implementations, the receiver includes: a first mixer circuit for down-converting the input RF signal by combining i) an input radio frequency (RF) signal with ii) a local oscillator (LO) signal, wherein the local oscillator signal is phase-shifted by a first specified phase to obtain a first phase-shifted signal; a second mixer circuit for i) down-converting the input RF signal by combining i) the input RF signal with ii) the local oscillator (LO) signal, wherein the local oscillator signal is phase-shifted by a second specified phase relative to the LO signal to obtain a second phase-shifted signal; and a third mixer circuit for down-converting the input RF signal by combining i) the input RF signal with ii) the local oscillator (LO) signal, wherein the local oscillator signal is phase-shifted by a third specified phase relative to the LO signal to obtain a third phase-shifted signal.

[0006] In some examples, the second phase-shifted signal is phase-shifted by 60 degrees relative to the first phase-shifted signal, and the third phase-shifted signal is phase-shifted by 120 degrees relative to the first phase-shifted signal.

[0007] In some implementations, the RF receiver includes: a first combining and scaling circuit for scaling each of two or more phase-shift signals in a first group of a plurality of phase-shift signals using a first set of scaling factors, and combining the first group of phase-shift signals to generate a first intermediate signal; and a second combining and scaling circuit for scaling each of two or more phase-shift signals in a second group of the plurality of phase-shift signals using a second set of scaling factors, and combining the second group of phase-shift signals to generate a second intermediate signal.

[0008] In some implementations, the scaling factor is a rational number.

[0009] In some implementations, generating the first intermediate signal includes adding a first phase-shift signal and a second phase-shift signal from the plurality of phase-shift signals, wherein a first scaling factor of the first phase-shift signal is a positive integer and a second scaling factor of the second phase-shift signal is a positive integer.

[0010] In some examples, generating the second intermediate signal includes adding a first phase-shift signal and a third phase-shift signal from the plurality of phase-shift signals, wherein a third scaling factor of the first phase-shift signal is a positive integer and a fourth scaling factor of the third phase-shift signal is a negative integer.

[0011] In some examples, generating the in-phase signal component (I) of the baseband signal includes: multiplying the first intermediate signal by a first digital scaling factor and multiplying the second digital signal by a second digital scaling factor, wherein the first digital scaling factor and the second digital scaling factor include non-integers; and adding the first intermediate signal and the second intermediate signal.

[0012] In some examples, the first digital scaling factor and the second digital scaling factor are

[0013] In some examples, generating the quadrature phase signal component (Q) of the baseband signal includes: multiplying the first intermediate signal by a third digital scaling factor and multiplying the second digital signal by a fourth digital scaling factor, wherein the third and fourth digital scaling factors include non-integers; and subtracting the resulting second intermediate signal from the resulting [scaled] first intermediate signal.

[0014] In some examples, the third digital scaling factor and the fourth digital scaling factor are

[0015] In some implementations, the RF receiver includes a fourth mixer circuit for downconverting the input RF signal by combining i) the input radio frequency (RF) signal with ii) the local oscillator (LO) signal, wherein the local oscillator signal is phase-shifted by a fourth specified phase relative to the input RF signal to obtain a fourth phase-shifted signal.

[0016] In some examples, the second phase-shift signal, the third phase-shift signal, and the fourth phase-shift signal are offset by 45 degrees, 90 degrees, and 135 degrees relative to the first phase-shift signal, respectively.

[0017] In some implementations, the analog combination and scaling circuit includes a plurality of resistors, each of which has an equal value.

[0018] In some implementations, the digital combination and scaling circuitry includes a floating-point multiplier.

[0019] In some implementations, the analog mixer circuit is implemented using one or more MOFSET switches.

[0020] In some implementations, the floating-point multiplier performs one or more bitwise operations.

[0021] The above and other embodiments may each optionally include one or more features described herein, individually or in combination. One embodiment includes all combined features.

[0022] The mixing of LO harmonics with these interfering wireless signals can generate low-frequency interference signals, thereby obscuring the desired signal and reducing the sensitivity performance of the receiver. Therefore, it may be desirable for wireless receivers to have mixers that suppress or reject harmonic mixing.

[0023] One exemplary approach is known as an N-phase receiver. One way to implement an N-phase receiver is to create more LO phases and apply them to an additional mixer, then create a weighted sum of the outputs of these mixers in a manner that reduces the amplitude of the harmonic mixing components.

[0024] However, implementing an N-phase receiver can increase costs and may require a significant amount of die area. Each N-phase requires multiple complete analog signal paths and associated analog-to-digital (AD) conversion circuitry. Alternatively, the signals are combined in the analog domain with resistors or other components that may be inconvenient to implement.

[0025] The subject matter described in this specification can be implemented in specific embodiments to achieve one or more of the following advantages. For example, in some implementations, by utilizing one or more innovative harmonic suppression receiver configurations described herein, components and techniques can facilitate the generation of in-phase and quadrature components of the received signal with high accuracy, low power, and small die area. The innovative harmonic suppression receiver effectively suppresses the effects of these interfering signals.

[0026] As described in further detail below, in some examples, one or more harmonic suppression receivers described herein can leverage the strengths of both the analog and digital signal processing domains. For example, in the analog domain, a simple gain combination of mixer outputs can be used to reduce the signal path early in the intermediate frequency processing series. Precise scaling of the signal amplitude is left to the digital domain. Thus, the desired I / Q pair of the signal can be extracted with greater accuracy, but at a lower cost using a more analog summing method.

[0027] Detailed description of one or more embodiments of the subject matter of this specification is set forth in the accompanying drawings and detailed description. Other features, aspects, and advantages of the subject matter will become apparent from the detailed description, the accompanying drawings, and the claims. Attached Figure Description

[0028] Figure 1 This is a block diagram of an exemplary wireless communication system.

[0029] Figure 2 A block diagram illustrating exemplary details of a wireless device that can implement the methods and teachings of the present invention.

[0030] Figures 3A to 3C A diagram of an exemplary 8-phase receiver.

[0031] Figure 4 The phase diagrams for the I and Q components of an 8-phase receiver are shown.

[0032] Figures 5A to 5B A diagram of an exemplary 6-phase receiver.

[0033] Figure 6 The phase diagrams for the I and Q components of a 6-phase receiver are shown.

[0034] Figure 7 A diagram of an exemplary N-phase receiver according to the present invention.

[0035] Figure 8 A diagram illustrating an exemplary combination and scaling circuit.

[0036] Figure 9 A diagram of an exemplary digital combination and scaling circuit.

[0037] In the various figures, the same reference numerals and names indicate the same elements. Detailed Implementation

[0038] Figure 1 This is a block diagram of an exemplary wireless communication system 100 including a wireless device 110 capable of communicating with one or more wireless communication networks. The one or more wireless communication networks that the wireless device 110 is capable of communicating with may include, but are not limited to, one or more cellular or wireless wide area networks (WWANs), one or more wireless local area networks (WLANs), one or more wireless personal area networks (WPANs), or combinations thereof.

[0039] exist Figure 1 In the example, wireless device 110 communicates with at least one WWAN via at least one base station 120 and with at least one WLAN via at least one access point 130. At least one base station 120 can support bidirectional communication with wireless devices within its respective coverage area 122. Similarly, at least one access point 130 can support bidirectional communication with wireless devices within its respective coverage area 132.

[0040] In some implementations, at least one WWAN associated with at least one base station 120 can be a fifth-generation (5G) network in other generations and types of networks. In these implementations, at least one base station 120 can be a 5G base station that uses orthogonal frequency-division multiplexing (OFDM) and / or non-OFDM and a transmission time interval (TTI) shorter than 1 ms (e.g., 100 or 200 microseconds) to communicate with wireless devices, such as wireless device 110. For example, at least one base station 120 can take one of several device forms, such as a base transceiver station (BTS), Node-B (NodeB), evolved NodeB (eNB), next-generation (fifth) generation (5G) NodeB (gNB), home NodeB, home eNodeB, site controller, access point, or wireless router, or a server, router, switch, or other processing entity with wired or wireless networks. Additionally, as... Figure 1 As shown, wireless device 110 is used to communicate with one or more personal area network (PAN) devices / systems 130 (e.g., via one or more WPANs) Or radio frequency identification (RFID) systems and equipment for communication.

[0041] System 100 may use multi-channel access functionality, including a scheme in which at least one base station 120 and wireless device 110 are used to implement Long Term Evolution (LTE), LTE Advanced (LTE-A), and / or LTE Multimedia Broadcast Multicast Service (MBMS). In other implementations, at least one base station 120 and wireless device 110 are used to implement UMTS, HSPA, or HSPA+ standards and protocols. Of course, other multiple access schemes and wireless protocols may also be used. In some examples, one or more such access schemes and wireless protocols may correspond to standards that impose RF power amplifier linearity requirements.

[0042] In order to communicate with at least one or both of base station 120 and access point 130, wireless device 110 may include similar or equivalent features referenced below. Figure 2One or more transmitter and receiver components, described in further detail, to support multiple communications with different types of access points, base stations and other wireless communication devices.

[0043] Although Figure 1 An example of a communication system is shown, but it is possible to... Figure 1 Various modifications can be made. For example, the communication system 100 can be configured in any suitable way, including any number of wireless devices, base stations, access points, networks, or other components.

[0044] The following text is for reference only. Figures 2 to 9 Examples of transmitter components and RF power amplifiers that can be used in wireless device 110 and other similar devices are described in further detail. Although Figure 1 An example of a communication system is shown, but it is possible to... Figure 1 Various modifications can be made. For example, the communication system 100 can be configured in any suitable way, including any number of wireless devices, base stations, access points, networks, or other components.

[0045] Figure 2 A block diagram illustrating exemplary details of a wireless device 110 that can implement the methods and teachings of the present invention is provided. The wireless device 110 may be a mobile phone, or in other examples, other devices such as a desktop computer, laptop computer, tablet computer, handheld computing device, automotive computing device, and / or other computing device. As shown, the wireless device 110 is illustrated as including at least one transmitter 210, at least one receiver 220, memory 230, at least one processor 240, and at least one input / output device 260. Only one transmitter and one receiver are shown here, but in many embodiments, multiple transmitters and receivers are included to simultaneously support multiple communications of different types. Each transmitter may incorporate the innovations of the present invention.

[0046] Processor 240 can perform various processing operations on wireless device 110. For example, processor 240 can perform signal encoding, data processing, power control, input / output processing, or enable wireless device 110 to operate within system 100 (… Figure 1 Any other functions operating within the processor. Processor 240 may include any suitable processing or computing device for performing one or more operations. For example, processor 240 may include a microprocessor, microcontroller, digital signal processor, field-programmable gate array, or application-specific integrated circuit, or a combination of these devices.

[0047] Transmitter 210 is used to modulate data or other content and to filter and amplify the output radio frequency (RF) signal for transmission by at least one antenna 250A. Transmitter 210 can also be used to amplify, filter, and down-convert baseband or intermediate frequency signals into RF signals before they are provided to antenna 250A for transmission. Transmitter 210 may include any suitable structure for generating RF signals for wireless transmission. See below for reference. Figure 2 The components 212 to 218 shown further describe additional aspects of the transmitter 210 in detail.

[0048] Receiver 220 can be used to demodulate data or other content received in the input RF signal by at least one antenna 250B. Receiver 220 can also be used to amplify, filter, and down-convert the RF signal received through antenna 250B to an intermediate frequency (IF) or baseband frequency signal before converting it to digital form and processing it. Receiver 220 may include any suitable structure for processing signals received wirelessly.

[0049] Each of antennas 250A and 250B may include any suitable structure for transmitting and / or receiving wireless RF signals. In some implementations, antennas 250A and 250B may be implemented as a single antenna, which can be used to transmit and receive RF signals.

[0050] It should be understood that one or more transmitters 210 may be used in wireless device 110, one or more receivers 220 may be used in wireless device 110, and one or more antennas 250 may be used in wireless device 110. For example, in one embodiment, device 110 includes at least three transmitters 210 and receivers 220 for use via This allows communication via personal area networks (LANs), WiFi networks such as IEEE 802.11-based networks, and cellular networks. Each of these protocol transceivers (transmitter 210 and receiver 220) can employ the concepts of this invention. Although shown as separate blocks or components, at least one transmitter 210 and at least one receiver 220 can be combined into a transceiver. Therefore, a single block of transceiver can be shown instead of... Figure 2 The transmitter 210 and the receiver 220 are separate blocks.

[0051] In addition, the wireless device 110 includes one or more input / output devices 260. The input / output devices 260 facilitate interaction with the user. Each input / output device 260 includes any suitable structure for providing or receiving information from the user, such as a speaker, microphone, keypad, keyboard, display, or touchscreen.

[0052] Additionally, the wireless device 110 includes at least one memory 230. The memory 230 stores instructions and data used, generated, or collected by the wireless device 110. For example, the memory 230 may store software or firmware instructions executed by one or more processors 240, as well as data used to reduce or eliminate interference in the input signal. Each memory 230 includes any suitable one or more volatile and / or non-volatile storage and retrieval devices. Any suitable type of memory can be used, such as random access memory (RAM), read-only memory (ROM), hard disk, optical disk, subscriber identity module (SIM) card, memory stick, secure digital (SD) memory card, etc.

[0053] In some implementations, transmitter 210 may include signal processing circuitry 212, modulation circuitry 214, RF front-end 217, power amplifier 216, and at least one filter 218. Signal processing circuitry 212 may include one or more circuits for processing signals received as input (e.g., from processor 240). For example, signal processing circuitry 212 may include a digital-to-analog (D / A) converter that converts the digital input (e.g., from processor 240) into an analog signal, then provides the analog signal to a low-pass filter that filters the analog signal and provides the filtered analog signal to modulation circuitry 214. In addition to receiving the filtered analog signal from signal processing circuitry 212, modulation circuitry 214 also receives signals from local oscillator 215 and modulates or adjusts the frequency of the signal, for example, modulating or adjusting it from a first frequency to a second frequency higher than the first frequency. For example, modulation circuit 214 may include a mixer that upconverts the filtered analog signal from a relatively low frequency (e.g., the baseband frequency, or an intermediate frequency (IF) offset from the baseband frequency) to a relatively high frequency RF signal. Therefore, the signal from local oscillator 215 is used as the carrier signal in transmitter 210. Furthermore, as... Figure 2As shown, transmitter 210 includes RF front-end 217, which includes amplification and filtering circuitry that filters and amplifies the RF signal before it is supplied to power amplifier 216.

[0054] The RF signal from RF front-end 217 is then amplified by power amplifier 216 and filtered by at least one filter 218, and then provided as the output of transmitter 210 to at least one antenna 250A for wireless transmission. Although Figure 2 The diagram shows filter 218 downstream of power amplifier 216, but in some implementations, filter 218 can be upstream of power amplifier 216. In this case, the RF signal from RF front end 217 is first filtered by at least one filter 218, then amplified by power amplifier 216, and then provided as the output of transmitter 210 to at least one antenna 250A for wireless transmission.

[0055] Figures 3A to 3C This is a schematic diagram of an exemplary 8-phase receiver.

[0056] Conventional quadrature (i.e., four-phase) receivers utilize mixers driven by four-phase local oscillators (LOs) (0, 90, 180, 270 degrees) to generate "in-phase (I-channel)" and "quadrature-phase (Q-channel)" baseband signals. The mixer is a passive MOS switching mixer, whose operation causes one or more LOs to behave as near-square wave pulse trains. Therefore, in direct-conversion or zero-IF receivers, the mixer has a relatively large RF-to-baseband gain at the fundamental and harmonic frequencies of the LO signal. Typically, the gain at the fundamental frequency of the LO is the desired output. Preferably, the response caused by the harmonics of the LO is suppressed as an unwanted source of interference. For example, in the case of a conventional receiver, the mixer's RF-to-baseband gain at the third harmonic of the LO is only 9.5 dB lower than the gain at the desired fundamental frequency of the LO.

[0057] An N-phase receiver can be implemented to create additional phases of the LO and apply them to an additional mixer, creating a weighted sum of the outputs of these mixers in a manner that reduces the amplitude of the harmonic-dependent mixing components.

[0058] The implementation of various existing N-phase receiver technologies will be described below.

[0059] Figure 3A and 3B This is a schematic diagram of an exemplary 8-phase receiver 300, in which the signals are scaled and combined entirely in the analog domain.

[0060] The 8-phase receiver 300 includes four mixer circuits 302 whose outputs are phase-shifted signals generated by mixing the input baseband RF signal with a signal from a local oscillator, such as signals with phase shifts of 0 / 180, 45 / 225, 90 / 270, and 135 / 315 degrees. The 8-phase receiver also includes four post-mixer transconductance (Gm) amplifiers 304 (for clarity, Figure 3A (Only one path is marked in the image). Receiver 300 includes analog and digital sections (not shown). Gm amplifier 304 is used to generate a weighted sum of the phase-shift mixer output signal. The weighting coefficient is a scaling factor used to produce the correct vector summation, resulting in harmonic suppression. This approach requires precise control of the weighting coefficients through design or calibration to achieve a high level of harmonic suppression.

[0061] Figure 3B This is a schematic diagram of another exemplary 8-phase receiver 310. As in the previous implementation, the mixer circuit 312 outputs a phase-shifted signal, such as a 0 / 180, 45 / 225, 90 / 270, or 135 / 315 degree phase shift, generated by mixing the input baseband RF signal with a signal from a local oscillator. The mixer circuit is implemented together with multiple Gm amplifiers 314. However, several weighting coefficients are shown in this figure, including an irrational number, such as √2. Even on the same IC, it is difficult to achieve irrational number ratios in analog integrated circuit components and maintain matching on the IC or across multiple signal paths. That is, scaling factors can be created using ratios of resistors of different sizes. Using resistors of different sizes, for example, resistors that are not in a rational number ratio to each other (e.g., 1500Ω, 750Ω, 2250Ω), can cause difficulties in IC layout and design. Mismatched weighting coefficients can adversely affect the receiver's harmonic suppression, thereby reducing the effectiveness of harmonic suppression.

[0062] Figure 3C This is a schematic diagram of another exemplary 8-phase receiver 320. (Compared to...) Figure 3A and 3B Compared to receivers 300 and 310, the 8-phase receiver 320 performs the combination and scaling of signals from the mixer circuit 322 entirely in the digital domain. In the digital domain, the weighting coefficients can be controlled more precisely. However, combining and scaling signals in the digital domain requires additional analog baseband signal path circuitry 324 and an analog-to-digital converter 326 (one path for each of the 0 / 180, 45 / 225, 90 / 270, and 135 / 315 signals). Therefore, a significant increase in die area is required.

[0063] Figure 4The phase diagrams for the I and Q components of the 8-phase receiver are shown. The fundamental signal 400 of the I and Q components can be generated by the vector sum of the four phase-shifted signals output from the mixer circuit, i.e. and To suppress the third harmonic signal 402, the vector sum of the harmonic signals should be zero, i.e. and However, as mentioned above, when the scaling factor is an irrational number, for example... At that time, it is difficult to maintain a consistent match on integrated circuits.

[0064] To reduce system costs, some exemplary receivers can use fewer phases.

[0065] Figures 5A to 5B A diagram of an exemplary 6-phase receiver.

[0066] Figure 5A This is a schematic diagram of a first exemplary 6-phase receiver 500.

[0067] The 6-phase receiver 500 includes: three mixer circuits 502 for outputting three phase-shifted signals (0 / 180, 60 / 240, 120 / 300); and a post-mixer amplifier and a summer 504 for combining each signal output from the mixer circuits 502 to generate I-channel and Q-channel signals. However, in this system, several scaling factors include irrational numbers, such as √3, which, as mentioned above, are difficult to implement in analog integrated circuit components and maintain matching of integrated circuit (IC) components.

[0068] Figure 5B This is a schematic diagram of another exemplary 6-phase receiver 510. Similar to the above. Figure 3C The 6-phase receiver 510 performs the combination and scaling of signals from the mixer circuit 512 entirely in the digital domain. In the digital domain, the weighting coefficients can be controlled more precisely. However, combining and scaling signals in the digital domain requires additional analog baseband signal path circuitry 514 and an analog-to-digital converter 316 (each of the three phase-shifted signals has its own path). Therefore, a significant increase in die area is required.

[0069] Figure 6 The diagram shows the phase diagrams of the I and Q components of a 6-phase receiver. For the third harmonic, the phase of each phasor is shifted by a factor of 3 compared to the fundamental mixer output. Therefore, the 0-degree phasor remains at 0 degrees for the third harmonic, while the 60-degree phasor shifts to 180 degrees, and the 120-degree phasor shifts to 360 degrees. Using the same weighting coefficients in the summation, it can be seen that the resulting baseband signal is completely suppressed under the third harmonic. The fundamental signal 600 of the I and Q components can be generated by the vector sum of the three phase signals, i.e. and To suppress the third harmonic signal 602, the vector sum of the harmonic signals should be zero, i.e. and However, as mentioned above, when the scaling factor is an irrational number, for example... At that time, it is difficult to maintain a consistent match on integrated circuits.

[0070] Figure 7 A diagram of an exemplary N-phase receiver 700 according to the present invention.

[0071] In the N-phase receiver 700, the in-phase (I) and quadrature-phase (Q) signal components of the incoming signal are separated for processing. (See above reference...) Figures 3A to 3C In the harmonic suppression receivers described in 5A to 5B, the combination or interpolation of multiphase mixer output paths can be accomplished either by using complex and finite-precision non-integer summing weights in the analog domain, or by performing the summation entirely in the digital domain, sacrificing the need for a full analog processing path and A / D for each mixer phase.

[0072] In the N-phase receiver 700, in the early stages of the IF signal processing series, a simple combination of unit, integer, or rational gain from the mixer output is used in the analog domain to reduce the number of signal paths. Precise scaling and further combination of the signal are then performed in the digital domain. This document describes the N-phase receiver 700 with reference to a 6-phase embodiment; however, other embodiments are also possible, such as 8-phase.

[0073] The input signal is processed in the analog domain to produce a set of intermediate analog output signals, which are then manipulated in the digital domain to produce the desired I / Q pair. The number of intermediate analog signals and the weighting values ​​applied to the mixer output signal to produce the analog intermediate signals can be selected to reduce cost and improve robustness to mismatches with resistors or other analog components. Subsequent ADC and digital circuitry ultimately convert the analog signal into the desired I / Q receiver output signal pair. Simple analog weighting functions and trivial coefficients, such as those based on integers and / or rational numbers, make the cheaper analog domain circuitry more robust to mismatches, while irrational weighting coefficients are left to the digital domain, where the desired accuracy can be more easily achieved. Therefore, the desired I / Q pair of the signal can be extracted with higher accuracy than conventional analog summing methods but at a lower cost than digital summing methods.

[0074] The radio frequency (RF) receiver 700 includes a plurality of analog mixer circuits 702, each mixer circuit combining i) an input radio frequency (RF) signal with ii) a local oscillator (LO) signal, which is phase-shifted by a specified phase relative to the input RF signal (i.e., the input RF signal received at input 706) to obtain a phase-shifted signal.

[0075] Each analog mixer circuit can be a passive or switched mixer implemented using one or more MOFSET switches. Each mixer circuit 702 is driven by the LO signal. For example, mixer circuit 702 can be gated by the LO signal and is considered to be on during the peak voltage period of the LO signal and off during the minimum voltage period of the LO signal. A low noise amplifier (LNA) 704 can be added before the analog mixer circuit 702 to enhance the input RF signal and overcome the conversion losses in the analog mixer circuit 702. The local oscillator (LO) signal can be generated by a voltage controlled oscillator (VCO) or other suitable type of oscillator. The local oscillator is typically a single local oscillator with additional circuitry to generate multiple LO phases, but the input to each of the multiple mixer circuits 702 can be a signal from a separate local oscillator.

[0076] In some implementations, the mixer multiplies the input RF signal by a complex sinusoidal LO signal. The fundamental frequency of the LO is mixed with the input RF frequency to produce a low-frequency baseband signal or intermediate frequency (IF) signal for processing. The output frequency is determined by the frequency of the LO signal mixed with the input RF. Switching mixers can approximate an ideal sine wave with a signal that behaves very much like a square wave or pulse train signal, and is therefore rich in higher-order harmonics. Aliasing around the third, fifth, and seventh harmonics is common. The harmonics of the LO signal can also be mixed with higher-frequency interfering RF signals whose frequencies are close to the harmonics of the desired RF signal. The mixing of LO harmonics with interfering radio signals produces low-frequency interference, which reduces the receiver's sensitivity and obscures the desired signal.

[0077] Each of the multiple analog mixer circuits 702 is used to down-convert the received RF signal to an intermediate frequency (IF) signal with a phase shift relative to the first local oscillator signal. The phase-shifted signal can be generated by acquiring the first local oscillator signal and applying a phase shift to generate the desired signal. For example, the phase-shifted signal can be referenced above... Figure 4and Figure 6 One of the signals described. Then, the phase-shifted signals can be combined and scaled to eliminate higher-order harmonics in the output signal.

[0078] Multiple phase-shift signals output from the analog mixer circuit 702 can be input to multiple analog combination and scaling circuits 708, for example, Figure 8 The diagram illustrates an analog combination and scaling circuit. Multiple combination and scaling circuits 708 are each used to scale each of two or more phase-shifted signals from a set of multiple phase-shifted signals using a first set of scaling factors, and to combine the set of phase-shifted signals to generate an intermediate frequency (IF) signal. For example, each of the multiple input phase-shifted signals can be input to the combination and scaling circuit 708. Each combination and scaling circuit in the multiple combination and scaling circuits 708 may include one or more resistors or transconductors or other amplification devices for appropriately scaling the input signal. The amplitudes of the resistors or amplification components may be equal, or these resistors or amplification components may have rational or integer ratios. The multiple combination and scaling circuits may also include operational amplifiers for combining the signals. The scaling factor is a rational number, such as an integer, which can be implemented in the analog section of the circuit using a simple combination of resistors, thus making it easier to maintain small resistor mismatches.

[0079] Each analog combination and scaling circuit in the multiple combination and scaling circuits 708 includes multiple resistors, transconductors, or other amplifying components. In some implementations, each of the multiple resistors, transconductors, or other amplifying components has an equal value; in other implementations, the resistors, transconductors, or other amplifying components may have integer and / or rational ratio relationships.

[0080] For example, in a six-phase receiver, generating a first intermediate frequency (IF) signal A may include, for instance, adding a first phase-shift signal to a second phase-shift signal from a plurality of phase-shift signals, wherein a first scaling factor of the first phase-shift signal is a positive integer and a second scaling factor of the second phase-shift signal is a positive integer. For example, generating a second intermediate frequency (IF) signal B may include adding a first phase-shift signal to a third phase-shift signal from a plurality of phase-shift signals, wherein a third scaling factor of the first phase-shift signal is a positive integer and a fourth scaling factor of the third phase-shift signal is a negative integer. For example, the first intermediate signal A can be calculated as A = (1*P0) + (1*P... 60 In this case, the scaling factor for each intermediate signal is a positive integer. The second intermediate signal B can be generated according to = (1*P0) + (-1*P0). 120The scaling factor is generated, meaning it can be a positive or negative integer. In each case, scaling can be achieved through a simple combination of resistors, transconductors, or other amplifying components. Each signal path may include several additional circuits, including, for example, channel filters, such as channel filters 710 and 712, and additional low-noise amplifiers 714 and 716, such as transimpedance amplifiers. In some implementations, the channel filter may be a low-pass filter, for example, an RC filter or similar filter used for anti-aliasing before analog-to-digital conversion.

[0081] Converters (such as analog-to-digital converters (ADCs) 718 and 720) are used to convert each of multiple intermediate signals from multiple combinational and scaling circuits from analog to digital. Figure 7 In the diagram, each signal path is shown with a separate ADC (ADC 718 and ADC 720); however, a single ADC can receive input from multiple signal paths. For example, the ADC can be implemented in series with a multiplexer / demultiplexer to convert signals from each input signal path. Each ADC can have the same resolution, where the choice of resolution depends on the dynamic range of the input signals and / or the required conversion time. In some implementations, each ADC is a 12-bit ADC. In other implementations, 8-bit, 16-bit, or other suitable ADCs can be used.

[0082] Digital combination and scaling circuit 722, for example, as follows Figure 9 The digital combination and scaling circuit shown includes an in-phase signal component (I) circuit 724, which performs a first combination and scaling operation on a group of two or more intermediate signals from a plurality of intermediate signals to generate an in-phase signal component of the baseband signal. The digital combination and scaling circuit 722 also includes a quadrature phase signal component (Q) circuit 726, which performs a second combination and scaling operation on another group of two or more intermediate frequency (IF) signals from a plurality of intermediate frequency (IF) signals to generate a quadrature phase signal component (Q) of the baseband signal.

[0083] The first combination and scaling operation includes multiplying each of two or more intermediate signals in a set of multiple intermediate signals by a first set of digital scaling factors, and the second combination and scaling operation includes multiplying each of two or more intermediate signals in a set of multiple intermediate signals by a second set of digital scaling factors.

[0084] For example, in a six-phase embodiment, the in-phase signal component (I) of the baseband signal includes: multiplying a first intermediate signal A by a first digital scaling factor and multiplying a second digital signal B by a second digital scaling factor, wherein the first and second digital scaling factors include any real numbers; and adding the first intermediate signal A and the second intermediate signal B, for example, the first and second digital scaling factors can be 1 / 2. Therefore, the in-phase (I) signal component is formed by... Given that A is a first intermediate signal and B is a second intermediate signal B, generating the quadrature phase signal component (Q) of the baseband signal includes: multiplying the first intermediate signal A by a third digital scaling factor and multiplying the second digital signal B by a fourth digital scaling factor, where the third and fourth digital scaling factors include any real numbers; and subtracting the second intermediate signal B from the first intermediate signal A. For example, the third and fourth digital scaling factors could be... An approximation of the value. Therefore, the quadrature (Q) phase of the baseband signal components is determined by... Provided.

[0085] In some implementations, the in-phase (I) signal component circuit 724 and the quadrature-phase (Q) signal component circuit 726 are one or more floating-point units (FPUs), and combination and scaling operations are performed using appropriate bitwise operations. In other implementations, the in-phase (I) signal component circuit 724 and the quadrature-phase (Q) signal component circuit 726 are implemented using one or more FPGAs optimized to perform floating-point arithmetic.

[0086] In some implementations, receiver 700 may be a six-phase receiver, including first, second, and third mixer circuits 702 for combining i) an input radio frequency (RF) signal with ii) a phase-shifted local oscillator (LO) signal to generate down-converted phase-shifted signals. Here, the first down-converted phase-shifted signal is generated by mixing the input RF signal with a first LO signal, which is phase-shifted by a first specified phase (in some implementations, the first specified phase can be 0 degrees). The second and third specified phases of the input LO signal are phase-shifted relative to the first phase-shifted LO signal to obtain second and third phase-shifted LO signals. The output of the second mixer is a second down-converted phase-shifted signal phase-shifted by 60 degrees relative to the first down-converted phase-shifted signal, and the output of the third mixer is a third down-converted phase-shifted signal phase-shifted by 120 degrees relative to the first down-converted phase-shifted signal.

[0087] In some implementations, receiver 700 may be an eight-phase receiver, and the plurality of mixer circuits 702 further include a fourth mixer circuit for combining i) the input radio frequency (RF) signal with ii) a local oscillator (LO) signal, which is phase-shifted by a third specified phase relative to the input RF signal to obtain a fourth phase-shifted signal. In the eight-phase receiver implementation, the second, third, and fourth output signals are shifted by 45 degrees, 90 degrees, and 135 degrees relative to the first phase-shifted signal, respectively.

[0088] In some implementations, the multiple combination circuits 708 may include a first combination and scaling circuit, which is used to scale each of two or more phase-shift signals in a first group of multiple phase-shift signals using a first set of scaling factors, and to combine the first group of phase-shift signals to generate a first intermediate signal A. The multiple combination circuits 708 may also include a second combination and scaling circuit, which is used to scale each of two or more phase-shift signals in a second group of multiple phase-shift signals using a second set of scaling factors, and to combine the second group of phase-shift signals to generate a second intermediate signal B.

[0089] In some implementations of the N-phase receiver 700, including a six-phase receiver, generating the first intermediate signal A may, for example, include adding a first phase-shift signal and a second phase-shift signal from a plurality of phase-shift signals, wherein a first scaling factor of the first phase-shift signal is a positive integer and a second scaling factor of the second phase-shift signal is a positive integer. A second intermediate signal B is then generated.

[0090] The in-phase signal component (I) of the baseband signal includes: multiplying the first intermediate signal A by a first digital scaling factor and multiplying the second digital signal by a second digital scaling factor, wherein the first and second digital scaling factors include any real numbers; and adding the first intermediate signal A and the second intermediate signal B.

[0091] Figure 8This diagram illustrates an example of an analog combination and scaling circuit, such as analog combination and scaling circuit 708. Each local oscillator (e.g., first local oscillator 802, second local oscillator 804, and third local oscillator 806) combines an input radio frequency (RF) signal with a first local oscillator (LO) signal, which is phase-shifted by a specified phase relative to the input RF signal to obtain a phase-shifted down-converted signal. Each local oscillator produces a first output and a second output. The first output is the sum of the frequencies between the local oscillator's frequency and the input signal's frequency, and the second output is the frequency difference between the local oscillator's frequency and the input signal's frequency. The output signals are time-dependent voltages and can be combined and scaled, as described in further detail below.

[0092] like Figure 8 As shown, the phase-shifted down-converted signal from the first local oscillator 802 is input to the first amplifier 808. The phase-shifted down-converted signal from the second local oscillator 804 is input to the second amplifier 810. The phase-shifted down-converted signal from the third local oscillator 806 is input to the third amplifier 812.

[0093] The first intermediate signal A can be generated by combining the outputs of the first amplifier 808 and the second amplifier 810. Since each resistor (814 to 820) in the signal path has the same value, each phase-shifted down-converted signal is scaled by the same value (e.g., 1). These signals are then input to the fourth amplifier 822 to obtain the combined intermediate signal A = (1*P0) + (1*P 60 ). Among them, P0 and P 60 These are down-converted signals with phase shifts from the second local oscillator 804 and the first local oscillator 802, respectively.

[0094] The second intermediate signal B can be generated by combining the output of the second amplifier 810 with the inverted output of the third amplifier 812. As before, each resistor (824 to 830) in the signal path can be selected (e.g., matched with the same value) such that each signal component is scaled by the same value. These signals are used as inputs to the fifth amplifier 832, according to B = (1*P0) + (-1*P...). 120 The output is the intermediate signal B of the second combination. In each case, scaling can be achieved through a simple combination of resistors, transconductors, or other amplifying components. Where P0 and P... 120 These are down-converted signals with phase shifts from the second local oscillator 804 and the third local oscillator 806, respectively.

[0095] Figure 8The diagram shows a first dummy load resistor 834 across the first amplifier 808 and a second dummy load resistor 836 across the third amplifier 812. The resistors compensate for the fact that the signal path of the second local oscillator 804 includes an additional amplifier. The dummy load ensures accuracy but can be omitted for applications requiring lower precision.

[0096] Back Figure 7 The intermediate signals A and B output by the analog combination and scaling circuit can be converted from analog to digital by other circuits, including channel filters such as channel filters 710 and 712, additional low-noise amplifiers such as transimpedance amplifiers 714 and 716, and converters such as analog-to-digital converters (ADCs) 718 and 720.

[0097] Figure 9 This is an example of a digital combination and scaling circuit, such as the 722 digital combination and scaling circuit. Intermediate signal A is input to the first low-pass filter 902. Intermediate signal B is passed to the second low-pass filter 904.

[0098] The outputs of each of the first low-pass filter 902 and the second low-pass filter 904 are combined using a first combination operation 906 (e.g., a summation operation 906) and a first multiplication operation 908 to obtain the in-phase signal component I, as described in further detail below. The in-phase (I) signal component is... Given, where A is the first intermediate signal and B is the second intermediate signal B.

[0099] The outputs of each of the first low-pass filter 902 and the second low-pass filter 904 are combined using a second combination operation 910 and a second multiplication operation 912 to obtain the quadrature phase signal component Q. Each of the first combinational operation 906 and the second combinational operation 910, and each of the first multiplication operation 908 and the second multiplication operation 912, can be performed using a multi-bit adder, an arithmetic logic unit, a floating-point unit, other suitable integrated circuits, or combinations thereof. For example, each of these operations can be performed as a bitwise operation in a floating-point unit.

[0100] While this specification includes numerous specific implementation details, these details should not be construed as limiting the scope of any invention or the scope of the claimed protection, but rather as descriptions of features that may be characteristic of particular embodiments of a particular invention. In the context of a single embodiment, certain features described herein may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually in multiple embodiments or in any suitable sub-combination. Furthermore, although features may be described above as acting in certain combinations, or even initially claimed, in some cases one or more features from the claimed combination may be removed from that combination, and the claimed combination may be for sub-combinations or variations thereof.

[0101] Similarly, although the accompanying drawings depict operations in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or sequentially, or requiring the execution of all the operations shown to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the above embodiments should not be construed as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together into a single software product or packaged into multiple software products.

[0102] Furthermore, without departing from the scope of the invention, the technologies, systems, subsystems, and methods described and illustrated as discrete or separate in the various embodiments may be combined or integrated with other systems, modules, technologies, or methods. Other items shown or described as coupled to each other, or directly coupled, or communicating with each other may be indirectly coupled or communicated through some interface, device, or intermediate component, electrically, mechanically, or otherwise. Other examples of variations, substitutions, and alterations can be determined by those skilled in the art and may be exemplified without departing from the spirit and scope disclosed herein.

[0103] For the purposes of this document, a connection can be a direct connection or an indirect connection (e.g., through one or more other components). In some cases, when a component is said to be connected or coupled to another component, that component may be directly connected to the other component or indirectly connected to the other component through an intermediate component. When a component is said to be directly connected to another component, there is no intermediate component between that component and the other component. If two devices are directly or indirectly connected so that they can transmit electronic signals between them, then they are “communicating.”

[0104] Specific embodiments of this subject matter have been described. Other embodiments are within the scope of the appended claims. For example, the operations described in the claims can be performed in a different order and still achieve the desired result. For example, the processes depicted in the drawings do not necessarily require execution in the specific order shown to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous.

Claims

1. A radio frequency (RF) receiver, characterized in that, include: Multiple analog mixer circuits, each analog mixer circuit including: A circuit for downconverting an input radio frequency (RF) signal by combining i) an input radio frequency (RF) signal with ii) a local oscillator (LO) signal, wherein the local oscillator signal is phase-shifted by a specified phase relative to the input RF signal to obtain a phase-shifted signal; Multiple analog combination and scaling circuits are operatively connected to the analog mixer circuit and used to generate multiple intermediate signals, wherein each analog combination and scaling circuit is used to generate a corresponding intermediate signal by scaling multiple phase-shift signals using a first set of analog scaling factors, wherein the first set of analog scaling factors are rational numbers; A converter for converting each of the plurality of intermediate signals from analog to digital; A digital combination and scaling circuit, operatively connected to the converter and used to generate in-phase (I) and quadrature-phase (QP) components of the baseband signal, wherein the digital combination and scaling circuit includes: An in-phase signal component (I) circuit is used to perform a first combination and scaling operation on a group of two or more intermediate signals from the plurality of intermediate signals to generate the in-phase signal (I) component of the baseband signal. A quadrature phase signal component (Q) circuit is used to perform a second combination and scaling operation on another set of two or more intermediate signals from the plurality of intermediate signals to generate the quadrature phase signal component (Q) of the baseband signal. The first combination and scaling operation includes multiplying each of the two or more intermediate signals in the group of the plurality of intermediate signals by a first set of digital scaling factors, and the second combination and scaling operation includes multiplying each of the two or more intermediate signals in the group of the plurality of intermediate signals by a second set of digital scaling factors, wherein the first set of digital scaling factors includes non-integers and the second set of digital scaling factors includes irrational numbers.

2. The RF receiver according to claim 1, characterized in that, The plurality of analog mixer circuits include: A first mixer circuit is used to downconvert the input radio frequency (RF) signal by combining i) an input radio frequency (RF) signal with ii) a local oscillator (LO) signal, wherein the local oscillator signal is phase-shifted by a first specified phase to obtain a first phase-shifted signal; The second mixer circuit is used to i) downconvert the input radio frequency (RF) signal by combining the input radio frequency (RF) signal with the local oscillator (LO) signal, wherein the local oscillator signal is phase-shifted by a second specified phase relative to the first phase-shift signal to obtain a second phase-shift signal; The third mixer circuit is used to down-convert the input radio frequency (RF) signal by combining i) the input radio frequency (RF) signal with ii) the local oscillator (LO) signal, wherein the local oscillator signal is phase-shifted by a third specified phase relative to the first phase-shift signal to obtain a third phase-shift signal.

3. The RF receiver according to claim 2, characterized in that: The second phase-shifted signal is phase-shifted by 60 degrees relative to the first phase-shifted signal; The third phase-shifted signal is phase-shifted by 120 degrees relative to the first phase-shifted signal.

4. The RF receiver according to claim 3, characterized in that, Multiple analog combination and scaling circuits include: The first combination and scaling circuit is used to scale each of two or more phase shift signals in a first group of multiple phase shift signals using a first group of analog scaling factors, and to combine the first group of phase shift signals to generate a first intermediate signal. The second combination and scaling circuit is used to scale each of two or more phase shift signals in a second group of the plurality of phase shift signals using a second group of analog scaling factors, and to combine the second group of phase shift signals to generate a second intermediate signal.

5. The RF receiver according to claim 4, characterized in that, Generating the first intermediate signal includes adding the first phase-shift signal and the second phase-shift signal from the plurality of phase-shift signals, wherein the first analog scaling factor of the first phase-shift signal is a positive integer, and the second analog scaling factor of the second phase-shift signal is a positive integer.

6. The RF receiver according to any one of claims 4 to 5, characterized in that, Generating the second intermediate signal includes adding the first phase shift signal and the third phase shift signal among the plurality of phase shift signals, wherein the third analog scaling factor of the first phase shift signal is a positive integer and the fourth analog scaling factor of the third phase shift signal is a negative integer.

7. The RF receiver according to claim 6, characterized in that, Generating the in-phase signal component (I) of the baseband signal includes: multiplying the first intermediate signal by a first digital scaling factor and multiplying the second intermediate signal by a second digital scaling factor, wherein the first digital scaling factor and the second digital scaling factor include non-integers; and adding the first intermediate signal and the second intermediate signal.

8. The RF receiver according to claim 7, characterized in that, The first digital scaling factor and the second digital scaling factor are .

9. The RF receiver according to claim 8, characterized in that, Generating the quadrature phase signal component (Q) of the baseband signal includes: multiplying the first intermediate signal by a third digital scaling factor and multiplying the second intermediate signal by a fourth digital scaling factor, wherein the first digital scaling factor and the second digital scaling factor include non-integers; and subtracting the second intermediate signal from the first intermediate signal.

10. The RF receiver according to claim 9, characterized in that, The third digital scaling factor and the fourth digital scaling factor are .

11. The RF receiver according to any one of claims 2 to 5, characterized in that, The system includes a fourth mixer circuit for down-converting the input radio frequency (RF) signal by combining i) the input RF signal with ii) the local oscillator (LO) signal, wherein the local oscillator signal is phase-shifted by a fourth specified phase relative to the first phase-shift signal to obtain a fourth phase-shift signal.

12. The RF receiver according to claim 11, characterized in that, The second phase-shift signal, the third phase-shift signal, and the fourth phase-shift signal are offset by 45 degrees, 90 degrees, and 135 degrees respectively relative to the first phase-shift signal.

13. The RF receiver according to any one of claims 1-5, characterized in that, The analog combination and scaling circuit includes multiple resistors, and each of the multiple resistors has an equal value.

14. The RF receiver according to any one of claims 1-5, characterized in that, The digital combination and scaling circuitry includes a floating-point multiplier.

15. The RF receiver according to any one of claims 1-5, characterized in that, The analog mixer circuit is implemented using one or more MOFSET switches.

16. The RF receiver according to claim 14, characterized in that, The floating-point multiplier performs one or more bitwise operations.

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