Display panel and display device

Abstract

The application discloses a display panel and a display device. The working process of a pixel circuit in the display panel comprises a first data refresh period, a data adjustment stage, and a second data refresh period arranged in sequence. The data adjustment stage comprises T1 first sub-data adjustment stages and T2 second sub-data adjustment stages arranged in sequence. The number of data write frames in the first sub-data adjustment stage is greater than the number of data write frames in the second sub-data adjustment stage, and the number of hold frames in the first sub-data adjustment stage is less than the number of hold frames in the second sub-data adjustment stage. Therefore, the unstable situation of the input signal of the driving transistor caused by the first data refresh period can be quickly reversed before the second data refresh period, so that the flicker phenomenon of the picture observed by the human eye during the display picture switching can be avoided.

Description

[0001] This application is a divisional application of the patent filed on September 14, 2021, with application number 202111074968.5 and invention title: Display Panel and Display Device. Technical Field

[0002] This invention belongs to the field of display technology, and particularly relates to a display panel and a display device. Background Technology

[0003] Currently, display panels have permeated all aspects of people's daily lives, serving as interactive display modules for various devices for users to view. When a display panel is running, its pixel units are driven and controlled, causing the screen content to constantly switch. However, during these screen switching events, a flickering phenomenon that is perceptible to the human eye can easily occur. Summary of the Invention

[0004] This invention provides a display panel and a display device that can avoid the problem of screen flickering that can be observed by the human eye when switching display screens.

[0005] This application provides a display panel, including:

[0006] Pixel circuitry and light-emitting element; the pixel circuitry includes a driving transistor, which is used to provide driving current to the light-emitting element.

[0007] The frame refresh frequency of the pixel circuit is F1, the frame refresh period is S1, and the frame includes a data writing frame or a holding frame.

[0008] The data refresh frequency of the pixel circuit is F2, F2≤F1, and the data refresh period is S2;

[0009] A data refresh cycle includes S2 / S1 frames, and each S2 / S1 frame includes at least one data write frame and r hold frames, where r ≥ 0; where,

[0010] The working process of the pixel circuit includes a first data refresh cycle, a data adjustment stage, and a second data refresh cycle set in sequence. The data adjustment stage includes a first data adjustment stage and a second data adjustment stage set in sequence.

[0011] The first data adjustment phase includes T1 first sub-data adjustment phases set sequentially. Each first sub-data adjustment phase includes m1 data write frames and n1 hold frames, where T1≥1, m1≥0, n1≥0, and m1+n1≥1.

[0012] The second data adjustment phase includes T2 sequentially set second sub-data adjustment phases, each sub-data adjustment phase comprising m2 data write frames and n2 hold frames, where T2≥1, m2≥0, n2≥0, and m2+n2≥1;

[0013] m1≥m2, n1<n2<r.

[0014] This application also provides a display device, including the display panel described above.

[0015] Compared with the prior art, the display panel and display device provided in this application embodiment have a first data adjustment stage and a second data adjustment stage sequentially arranged between the first data refresh cycle and the second data refresh cycle. The first data adjustment stage includes T1 first sub-data adjustment stages, and the second data adjustment stage includes T2 second sub-data adjustment stages. The number of data-written frames in the first sub-data adjustment stage is greater than or equal to the number of data-written frames in the second sub-data adjustment stage, and the number of held frames in the first sub-data adjustment stage is less than the number of held frames in the second sub-data adjustment stage. Therefore, before the second data refresh cycle, the instability of the drive transistor input signal caused by the first data refresh cycle in the low-frequency drive mode can be quickly reversed, thereby avoiding screen flickering observable by the human eye during display screen switching. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the pixel circuit structure of the display panel involved in the present invention;

[0018] Figure 2 This is a schematic diagram of the existing working process of the pixel circuit in the display panel when the data refresh rate is 1Hz;

[0019] Figure 3 It is a graph showing the time-brightness change when the display screen changes from grayscale value 0 to grayscale value 255 at a data refresh rate of 1Hz.

[0020] Figure 4 This is a schematic diagram of the pixel circuit operation process in a display panel according to an embodiment of the present invention;

[0021] Figure 5 yes Figure 4 A parameter table related to the operation of the mid-pixel circuit;

[0022] Figure 6 This is a schematic diagram of the pixel circuit operation process in a display panel according to another embodiment of the present invention;

[0023] Figure 7 yes Figure 6 A parameter table related to the operation of the mid-pixel circuit;

[0024] Figure 8 This is a schematic diagram of the pixel circuit operation process in a display panel according to another embodiment of the present invention;

[0025] Figure 9 yes Figure 8 A parameter table related to the operation of the mid-pixel circuit;

[0026] Figure 10 This is a schematic diagram of the pixel circuit operation process in a display panel according to another embodiment of the present invention;

[0027] Figure 11 yes Figure 10 A parameter table related to the operation of the mid-pixel circuit;

[0028] Figure 12 It is a parameter table involving the operation of the pixel circuit under two different data refresh frequencies;

[0029] Figure 13 This is a schematic diagram of a display device provided in this application.

[0030] In the attached diagram: pixel circuit 10, data writing frame 11, holding frame 12, data signal line Data, light-emitting element L, driving transistor T, data refresh cycle S2, first data refresh cycle 20, second data refresh cycle 40, data adjustment stage 30, first data adjustment stage 31, second data adjustment stage 32, third data adjustment stage 33, first sub-data adjustment stage 311, second sub-data adjustment stage 321, and third sub-data adjustment stage 331. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0032] It should be noted that the terms "upper," "lower," "left," and "right," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the purpose of description, not indicating or implying that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this patent. The terms "first" and "second" are used only for the purpose of description and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features. "A plurality of" means two or more, unless otherwise explicitly specified. In addition, the terms "horizontal," "vertical," and "suspended," etc., do not indicate that the component is required to be absolutely horizontal or suspended, but can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal than "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0033] It should also be noted that, unless otherwise explicitly specified and limited, the terms "set up," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0034] To illustrate the technical solution of this application, the following detailed description is provided in conjunction with specific drawings and embodiments.

[0035] With the development of display technology, display panels are widely used in electronic devices such as mobile phones, laptops, and computers. (See also...) Figure 1 , Figure 1 This is a schematic diagram of the pixel circuit structure of the display panel involved in the present invention. The display panel may include a light-emitting element L and a pixel circuit 10.

[0036] The aforementioned light-emitting element L can be an LED (Light-Emitting Diode), an OLED (Organic Electroluminescence Display), or others.

[0037] The pixel circuit 10 described above is connected to the data signal line L1, which is used to transmit the data signal Vdata. The pixel circuit 10 may include a driving transistor T0, whose gate receives the data signal Vdata. The driving transistor T0 is used to provide driving current to the light-emitting element L.

[0038] The aforementioned driving transistor T0 can be an oxide semiconductor transistor, specifically an IGZO (Indium Gallium Zinc Oxide) transistor, or a silicon transistor, specifically an LTPS (Low Temperature Poly-Silicon) transistor, or others.

[0039] in addition, Figure 1 The pixel circuit shown also includes a data writing transistor T1 controlled by control signal S1, used to selectively provide a data signal Vdata; a compensation transistor T2 controlled by control signal S2, used to compensate for the threshold voltage Vth of the driving transistor; light emission control transistors T3 and T4 controlled by light emission control signal EM, used to selectively allow the light-emitting element to enter the light emission stage; a reset transistor T5 controlled by control signal S3, used to provide a reset signal to the gate of the driving transistor T0; and an initialization transistor T6 controlled by control signal S4, used to provide an initialization signal to the anode of the light-emitting element L.

[0040] exist Figure 1 In pixel circuits, reducing power consumption has always been a research hotspot, leading to the development of various power-saving methods. Among these, reducing the data refresh rate can significantly reduce power consumption in certain situations; this low-data-signal driving method is called low-frequency driving mode, where the data refresh rate can be as low as 1Hz.

[0041] Please refer to the following: Figure 1 and Figure 2 ,in Figure 2 This is a schematic diagram of the operation of the pixel circuit 10 when the data refresh frequency is 1Hz. A single data refresh cycle S2 includes one data write frame 11 and multiple hold frames 12. During the data write frame 11, the data signal Vdata is written to the gate of the driving transistor T via the data signal line L1. The main difference between the hold frame 12 and the data write frame 11 is that, in the hold frame 12, the data voltage written in the previous data write frame 11 is retained, and no new data voltage is written. That is, in the hold frame 12, the data signal line L1 does not write the data signal Vdata to the gate of the driving transistor T.

[0042] However, due to the data refresh timing settings of hold frame 12 and data write frame 11, there are many hold frames 12 between the data write frames 11 of two adjacent data refresh cycles S2, resulting in a longer hold time for the same gray level.

[0043] Since the light-emitting element L is in the light-emitting stage at this time, the driving transistor T operates in a non-saturated state. This state lasts for a long time, which causes the drain current Id-gate voltage Vg curve of the driving transistor T to shift, and in turn causes the threshold voltage Vth of the driving transistor T to drift. The longer frame 12 lasts, the more obvious the shift of the threshold voltage Vth becomes.

[0044] The deviation of the threshold voltage Vth of the driving transistor T0 may cause the data signal Vdata received by the gate of the driving transistor T0 to be unstable, and the data signal Vdata is the decisive factor in determining the driving current required by the light-emitting element L.

[0045] Therefore, when the display panel transitions from one data refresh cycle S2 to a new data refresh cycle S2 and the grayscale changes, the large interval between the data write frames 11 of two adjacent data refresh cycles S2 and the numerous hold frames 12 cause the output drive current to be unstable, resulting in the light-emitting element L failing to reach the expected brightness in subsequent refresh cycles.

[0046] Only after several data refresh cycles S2 does the brightness of the light-emitting element L slowly reach the expected brightness. However, in low-frequency drive mode, one data refresh cycle S2 takes a long time, and the total time after several data refresh cycles S2 is also long. Therefore, the phenomenon that the light-emitting brightness does not reach the expected brightness can be easily observed by the human eye, and is reflected in the human eye as a flickering phenomenon.

[0047] For example, see Figure 3 , Figure 3 This is a graph showing the time-brightness change when the display changes from grayscale value 0 to grayscale value 255 at a data refresh rate of 1Hz. Figure 1 and Figure 3 As shown, the grayscale transition phase of the display screen needs to last for 3 seconds. During this transition phase, the actual light-emitting element L of the pixel circuit 10 does not reach the expected brightness, and the human eye can observe the flickering phenomenon of the display screen.

[0048] It should be noted that, Figures 2-3 The example given is a data refresh rate of 1Hz, which illustrates the problems with the display panel in low-frequency mode. This does not mean that such problems only occur when the data refresh rate is 1Hz. The inventors of this application have found that when the data refresh rate is low, such as below 30Hz, the flickering problem in the example above is more likely to occur, and the solution provided in this application is needed to improve it.

[0049] To address the issue of visually perceptible flickering on the display panel caused by excessively long hold frames 12 between data write frames 11 in adjacent data refresh cycles S2, in Figure 1 and Figure 2 Based on the existing technical solution, this application redesigns the working process of the pixel circuit 10 of the display panel.

[0050] See Figure 4 , Figure 4 This is a schematic diagram of the operation process of a pixel circuit in a display panel according to an embodiment of the present invention. The operation process of the pixel circuit 10 includes a first data refresh cycle 20, a data adjustment stage 30, and a second data refresh cycle 40, which are set sequentially. The configuration of the holding frame 12 and the data write frame 11 can be consistent within the first data refresh cycle 20 and the second data refresh cycle 40, and the data refresh timing of the holding frame 12 and the data write frame 11 can also be set consistently.

[0051] That is, both the first data refresh cycle 20 and the second data refresh cycle 40 can include frames S2 / S1. Each frame S2 / S1 includes at least one data write frame 11 and r hold frames 12, where r ≥ 0. Here, S1 is the frame refresh cycle of the pixel circuit 10, corresponding to a frame refresh frequency F1, where F1 is the reciprocal of S1. S2 is the data refresh cycle S2 of the pixel circuit 10, corresponding to a data refresh frequency F2, where F2 is the reciprocal of S2.

[0052] It should be noted here that in the concept of frame refresh frequency, a frame is calculated based on the minimum period of a light-emitting phase, and a frame includes a data write frame and a hold frame; in the concept of data refresh frequency, data refresh is calculated based on the minimum period of the data write signal, and a data refresh cycle may include at least one data write frame and several hold frames.

[0053] As stated above, without the data adjustment phase 30, the S2 / S1 value is large, and the r value is also large, resulting in a large interval between the data write frame 11 of one data refresh cycle S2 and the data write frame 11 of the next data refresh cycle S2, which maintains the frame 12. Therefore, a data adjustment phase 30 can be set between the first data refresh cycle 20 and the second data refresh cycle 40. This data adjustment phase 30 includes a first data adjustment phase 31 and a second data adjustment phase 32 set sequentially.

[0054] Please see also Figure 1 , Figure 4 and Figure 5 , Figure 5 yes Figure 4 A parameter table is involved in the operation of the pixel circuit. The first data adjustment stage 31 includes T1 first sub-data adjustment stages 311 set in sequence. The first sub-data adjustment stage 311 includes m1 data writing frames 11 and n1 holding frames 12, T1≥1, and m1≥0, n1≥0, m1+n1≥1.

[0055] The second data adjustment stage 32 includes T2 second sub-data adjustment stages 321 set in sequence. The second sub-data adjustment stage 321 includes m2 data write frames 11 and n2 hold frames 12, T2≥1, and m2≥0, n2≥0, m2+n2≥1; where m1≥m2, n1<n2<r.

[0056] It should be noted that, Figure 5 The specific values ​​in the diagrams below are merely illustrative embodiments, and the values ​​of each parameter are not necessarily limited to these. In other embodiments, the aforementioned parameters T1, T2, m1, n1, r, etc., can be selected as appropriate, and all are within the scope of protection of this application.

[0057] It is understandable that by setting a data adjustment phase 30 between the first data refresh cycle 20 and the second data refresh cycle 40, the data adjustment phase 30 includes T1 first sub-data adjustment phases 311 and T2 second sub-data adjustment phases 321 set sequentially. The data write frames 11 and hold frames 12 within the first sub-data adjustment phases 311 and 321 satisfy the relationship m1≥m2, n1<n2<r. This allows the number of data write frames 11, m1, to be relatively large during the first data adjustment phase 31. In other words, during this phase, through multiple data write refreshes, the instability of the input signal of the driving transistor T0 caused by the offset of the threshold voltage Vth of the driving transistor T0 in the first data refresh cycle 20 can be reversed as quickly as possible.

[0058] The larger the number of data frames m1 written to frame 11 and the smaller the number of holding frames n1, the faster this rapid reversal process. In an optional example, when the number of holding frames n1 in the first data adjustment stage 31 is much smaller than the total number r of holding frames 12 in a data refresh cycle S2, the time of this process can be shortened even more. Therefore, the design of the first data adjustment stage 31 and the second data adjustment stage 32, and the number of data frames 11 and holding frames 12 therein satisfying a certain relationship, can avoid the data refresh process when the human eye observes that the light emission brightness has not reached the expected brightness, thereby solving the problem of screen flickering observed by the human eye when the display screen switches.

[0059] Furthermore, the number m1 of data writing frames 11 in the first sub-data adjustment stage 311 is set to be greater than or equal to the number m2 of data writing frames 11 in the second sub-data adjustment stage 321, and the number n1 of holding frames 12 in the first sub-data adjustment stage 311 is less than the number n2 of holding frames 12 in the second sub-data adjustment stage 321. This is mainly because after writing data signals to the gate of the driving transistor T through m1 rapid times, if the second data refresh cycle 40 is suddenly entered, the number of holding frames 12 will increase sharply. At this time, during the first few holding frames 12 of the second data refresh cycle 40, the state of the driving transistor T0 is still unstable, and the flickering phenomenon that can be observed by the human eye will occur again.

[0060] Therefore, by setting a second data adjustment stage 32, the number of holding frames 12 is increased compared to the number of holding frames 12 in the first data adjustment stage 31. After the state buffer of the driving transistor T is adjusted, the second data refresh cycle 40 is entered. That is, during the sequential setting from the first data adjustment stage 31 to the second data adjustment stage 32, the number of holding frames 12 gradually increases from n1 to n2, thereby avoiding the drastic change in the amount of data in the holding frames 12 from the first data adjustment stage 31 directly to the second data refresh cycle 40, which would cause the driving transistor T0 to become unstable and cause flickering.

[0061] Please continue reading Figures 1 to 5 In an optional example, the data adjustment phase 30 may be set between the first data refresh cycle 20 and the second data refresh cycle 40 when the brightness of the light-emitting element L is less than that of the light-emitting element L in the second data refresh cycle 40.

[0062] It should be noted that the display brightness is lower in the first data refresh cycle 20 and higher in the second data refresh cycle 40, which is actually a transition from low grayscale to high grayscale. Especially when the difference in display brightness between the first data refresh cycle 20 and the second data refresh cycle 40 is significant, the grayscale transition process takes a longer time. Figure 3 As shown, this can easily lead to a flickering effect that is visible to the human eye. Therefore, in this situation, it is particularly important to shorten the grayscale transition time. This problem can be effectively solved by setting the aforementioned data adjustment stage 30 during the transition from low to high grayscale.

[0063] It should also be noted that, in another optional example, if the brightness of the light-emitting element L is greater than or equal to the brightness of the light-emitting element L in the second data refresh cycle 40, the aforementioned data adjustment phase 30 may not be provided between the first data refresh cycle 20 and the second data refresh cycle 40. This avoids flickering being observed by the human eye while saving power consumption of the display panel.

[0064] In another alternative example, the number of the first sub-data adjustment stages 311 can be greater than the number of the second sub-data adjustment stages 321, i.e., T1>T2.

[0065] Based on the foregoing analysis, the function of the first data adjustment stage 31 is to shorten the grayscale conversion time. The number of data written to frame 11 in the first sub-data adjustment stage 311 is relatively large, and the number of frames 12 held in the first sub-data adjustment stage 311 is relatively small. If the number of the first sub-data adjustment stage 311 is relatively large, the number of data refreshes in the first data adjustment stage 31 can be increased, the refresh frequency can be increased, and the grayscale conversion time can be kept as short as possible.

[0066] It should be noted that the main function of the second data adjustment stage 32 is to ensure a smooth transition in the number of holding frames 12 from small to large. Therefore, the number T2 of the second sub-data adjustment stages 321 does not need to be large; it is only necessary to smoothly adjust the state of the driving transistor T0. Therefore, the number T1 of the first sub-data adjustment stages 311 is greater than the number T2 of the second sub-data adjustment stages 321.

[0067] For example, please refer to the following: Figures 4 to 7 , Figure 6 This is a schematic diagram of the pixel circuit operation process in a display panel according to another embodiment of the present invention. Figure 7 yes Figure 6 A parameter table related to the operation of the mid-pixel circuit. Figure 4 and Figure 5 The quantity T2 of the second sub-data adjustment stage 321 shown is 4. Of course, T2 can also be any other value smaller than the quantity T1 of the first sub-data adjustment stage 311, for example, T2 could be 3. Figure 6 and Figure 7 The number T2 of the second sub-data adjustment stage 321 shown is 2, which is less than the number T1 of the first sub-data adjustment stage. Optionally, the number T1 of the first sub-data adjustment stage 311 can also be a positive integer multiple of the number T2 of the second sub-data adjustment stage 321, that is, T1 and T2 also satisfy the following relationship: T1=k×T2, where k is a positive integer.

[0068] For example, Figures 4 to 7 In this case, k = T1 / T2 = 2.

[0069] By reducing the number of sub-data adjustment stages 311 to 321 in multiples during the data adjustment stage 30, the accelerated reversal adjustment function of the first sub-data adjustment stage 311 is guaranteed, while the smooth transition function of the second sub-data adjustment stage 321 is also guaranteed.

[0070] Furthermore, based on this, the relationship between the total number of frames in the first sub-data adjustment stage 311 and the second sub-data adjustment stage 321 can be set as (m2+n2)=k×(m1+n1). Combined with T1=k×T2, it can be guaranteed that T1×(m1+n1)=T2×(m2+n2), that is, the total number of frames input in the first data adjustment stage 31 is equal to the total number of frames input in the second data adjustment stage 32.

[0071] Still with Figure 4 and Figure 5 As shown in the example, the total number of frames in the first sub-data adjustment stage 311 is (m1+n1)=1, and the number of the first sub-data adjustment stages 311 is T1=8; the total number of frames in the second sub-data adjustment stage 321 is (m2+n2)=2, and the number of the second sub-data adjustment stages 321 is T2=4. That is, at this time, k=(m2+n2) / (m1+n1)=2 / 1=2, T1×(m1+n1)=T2×(m2+n2)=8.

[0072] Or, see Figure 6 and Figure 7 The total number of frames in the first sub-data adjustment stage 311 shown is (m1+n1)=2, and the number of the first sub-data adjustment stages 311 is T1=4. The total number of frames in the second sub-data adjustment stage 321 is (m2+n2)=4, and the number of the second sub-data adjustment stages 321 is T2=2. That is, at this time, k=(m2+n2) / (m1+n1)=4 / 2=2, T1×(m1+n1)=T2×(m2+n2)=8.

[0073] This configuration ensures that the total number of input frames in each data adjustment stage 30 is equal, and that the adjustment time of the driving transistor T is the same in each data adjustment stage 30. This avoids situations where the time in some data adjustment stages 30 is too long and the time in others is too short, resulting in an uneven transition state of the driving transistor T0, thus avoiding flickering problems that can be observed by the human eye.

[0074] Please continue reading. Figure 4 and Figure 5 In another embodiment, the number m1 of data writing frames 11 in the first sub-data adjustment stage 311 is 1, and the number n1 of holding frames 12 in the first sub-data stage is 0. That is, at this time, T1 first sub-data adjustment stages 311 continuously write data without interruption by holding frames 12, which can shorten the driving transistor T time as much as possible, thereby significantly reducing the flickering phenomenon that can be observed by the human eye.

[0075] Please continue reading. Figures 4 to 7Furthermore, the number of data writing frames 11 and holding frames 12 in the second sub-data adjustment stage 321 can be limited. Specifically, the number of data writing frames 11 in the second sub-data adjustment stage 321 can be m2 = 1, and the number of holding frames 12 can be n2 ≥ 1. Alternatively, in other embodiments, the number of data writing frames 11 in the second sub-data adjustment stage 321 can be m2 > 1, and the number of holding frames 12 can be n2 ≥ m2. In practice, the relationship between the number of data writing frames 11 and holding frames 12 in the second sub-data adjustment stage 321 can be determined based on the magnitude of n2.

[0076] When m2 = 1 and n2 ≥ 1, in the actual pixel circuit 10 during the T2 second sub-data adjustment stage 321, after writing a data signal to the gate of the driving transistor T with one data write frame 11, there are several hold frames 12, and then the next data write frame 11 is written. This approach is suitable when n2 is relatively small. It allows writing one data write frame 11 first, then writing a hold frame 12, and then immediately entering another data write frame 11, making the data write frames 11 and hold frames 12 evenly distributed, which is beneficial for timely stabilization of the state of the driving transistor T0.

[0077] When m2 > 1 and n2 ≥ m2, for example, m2 = 2 = n2, in the actual pixel circuit 10 during the T2 second sub-data adjustment stages 321, the number of data frames written to frame 11 is followed by the number of hold frames 12. This approach is suitable when n2 is large, because if one frame of data is written to frame 11 first, followed by a relatively long hold frame 12, the hold frame 12 time will be long, causing the threshold voltage Vth of the driving transistor T to shift, resulting in the recurrence of flickering. Therefore, by first inputting multiple data frames to frame 11 and then inputting multiple hold frames 12, the state of the driving transistor T can be guaranteed.

[0078] Please refer to the following: Figure 1 , Figure 8 and Figure 9 , Figure 8 This is a schematic diagram of the pixel circuit operation process in a display panel according to another embodiment of the present invention. Figure 9 yes Figure 8 A parameter table is involved in the operation of the intermediate pixel circuit. During this operation, the data adjustment stage 30 also includes a third data adjustment stage 33. Between the first data refresh cycle 20 and the second data refresh cycle 40, the first data adjustment stage 31, the second data adjustment stage 32, and the third data adjustment stage 33 are sequentially set.

[0079] The third data adjustment stage 33 includes T3 third sub-data adjustment stages 331 set in sequence. The third sub-data adjustment stage 331 includes m3 data write frames 11 and n3 hold frames 12, T3≥1, and m3≥0, n3≥0, m3+n3≥1; where m2≥m3, n2<n3<r.

[0080] This embodiment sets a third data adjustment stage 33 after the first data adjustment stage 31 and the second data adjustment stage 32. Compared to the data write frame 11 and hold frame 12 in the second sub-data adjustment stage 321, the number of data write frames 11 in the third sub-data adjustment stage 331 of the third data adjustment stage 33 is reduced, while the number of hold frames 12 is increased. This more closely resembles the combination of hold frames 12 and data write frames 11 in the second data refresh cycle 40, thus making the transition from the second data adjustment stage 32 to the second data refresh cycle 40 smoother.

[0081] Based on this, the difference in the total number of frames between two adjacent sub-data adjustment stages 30 can also be limited, that is, the frame difference d1 between the third sub-data adjustment stage 331 and the second sub-data adjustment stage 321 is greater than the frame difference d2 between the second sub-data adjustment stage 321 and the first sub-data adjustment stage 311.

[0082] Where d1=(m3+n3)-(m2+n2) and d2=(m2+n2)-(m1+n1).

[0083] Continue with Figure 8 and Figure 9 Taking d1 as an example, where d1 = (1+3) - (1+1) = 2, d2 = (1+1) - (1+0) = 1, and d1 > d2.

[0084] By designing the total frame count difference as described above, the number of frames 12 can be gradually increased from the first data adjustment stage 31 to the third data adjustment stage 33. This is because the purpose of the first data adjustment stage 31 is to achieve rapid input data writing to frame 11, so the number of frames 12 n1 held in the first sub-data adjustment stage 311 is generally small. The second data adjustment stage 32 and other adjustment stages, such as the third data adjustment stage 33, are used to solve the problem of a smooth transition between the fast refresh stage and the second data refresh cycle 40.

[0085] When the period of the second data refresh cycle 40 is large, the span of the smooth transition is large. Therefore, setting d1 = (m3 + n3) - (m2 + n2) > d2 = (m2 + n2) - (m1 + n1) can appropriately increase the span of the number of hold frames 12 in the transition phase, so as to quickly switch to the second data refresh cycle 40.

[0086] The relationship between the total number of frames in two adjacent sub-data adjustment stages 30 can also be limited proportionally, that is, the ratio d3 of the total number of frames in the third sub-data adjustment stage 331 to the total number of frames in the second sub-data adjustment stage 321 is equal to the ratio d4 of the total number of frames in the second sub-data adjustment stage 321 to the total number of frames in the first sub-data adjustment stage 311.

[0087] In mathematical terms, it would be:

[0088] d3=(m3+n3) / (m2+n2)=d4=(m2+n2) / (m1+n1)≥1.

[0089] Continue with Figure 8 and Figure 9 Let's take an example to illustrate, where,

[0090] d3=(1+3) / (1+1)=d4=(1+1) / (1+0)=2.

[0091] The total number of frames in the sub-data adjustment phase 30 changes in a proportional manner. On the one hand, this allows for a larger range of variation in the number of frames 12. On the other hand, it avoids significant gaps in the change process, making the state change process of the driving transistor T more uniform and preventing drastic changes.

[0092] Please refer to the following: Figure 1 , Figures 8 to 9 In the data adjustment stage 30 shown in the figure, the quantity T1 of the first sub-data adjustment stage 311 is greater than the quantity T2 of the second sub-data adjustment stage 321, and the quantity T2 of the second sub-data adjustment stage 321 is greater than or equal to the quantity T3 of the third sub-data adjustment stage 331.

[0093] The number T1 of the first sub-data adjustment stage 311 is greater than the number T2 of the second sub-data adjustment stage 321 because the function of the first data adjustment stage 31 is to refresh quickly, while the function of the second data adjustment stage 32 is to smooth the transition.

[0094] Generally speaking, the number T1 of the first sub-data adjustment stage 311 is required to be relatively large in order to ensure that the state of the driving transistor T0 can be quickly refreshed to normal.

[0095] If the number T2 of the second sub-data adjustment phase 321 is smaller, the total number of frames of the data adjustment phase 30 can be reduced, thus avoiding the data adjustment phase 30 from taking too long.

[0096] The reason why the number T2 of the second sub-data adjustment stage 321 is greater than or equal to the number T3 of the third sub-data adjustment stage 331 is that the number n3 of the holding frames 12 in the third sub-data adjustment stage 331 is relatively large, and the total number (m3+n3) of the holding frames 12 and the data writing frames 11 in a single third sub-data adjustment stage 331 is relatively large. If T3 is relatively large, it will lead to an excessively large total number of frames in the third data adjustment stage 33, making the data adjustment stage 30 too long. Therefore, setting the number T3 of the third sub-data adjustment stage 331 to be less than or equal to the number T2 of the second sub-data adjustment stage 321 can prevent the data adjustment stage 30 from being too long.

[0097] Please continue reading. Figure 1 , Figures 8 to 9 In another embodiment, the difference between the quantity T2 of the second sub-data adjustment stage 321 and the quantity T1 of the first sub-data adjustment stage 311 can be set to a relationship with the difference between the quantity T3 of the third sub-data adjustment stage 331 and the quantity T2 of the second sub-data adjustment stage 321, i.e., T1-T2 > T2-T3. Figure 8 and Figure 9 In, T1-T2=4>T2-T3=2.

[0098] As can be seen from the foregoing, the functions of the first sub-data adjustment stage 311 are different from those of the second sub-data adjustment stage 321 and the third sub-data adjustment stage 331.

[0099] It is understandable that when setting the number of sub-data adjustment stages, the difference between the number T1 of the first sub-data adjustment stage 311 and the number T2 of the second sub-data adjustment stage 321 can be large, while the difference between the number T2 of the second sub-data adjustment stage 321 and the number T3 of the third sub-data adjustment stage 331 can be small.

[0100] While ensuring that the state of the driving transistor T0 can be quickly refreshed to normal, a smooth transition is ensured from the data adjustment phase 30 to the second data refresh cycle 40, and the data adjustment phase 30 does not take up too much time.

[0101] In another optional example, the quantity ratios of the first sub-data adjustment stage 311 and the second sub-data adjustment stage 321 can be set proportionally, as can the quantity ratio of the second sub-data adjustment stage 321 to the third sub-data adjustment stage 331, i.e., T1 / T2 = T2 / T3. For example, please continue to see Figure 1 , Figures 8 to 9 , where T1 / T2=8 / 4=T2 / T3=4 / 2.

[0102] By making the ratio of the quantities of adjacent sub-data adjustment stages equal, the quantity T1 of the first sub-data adjustment stage 311, the quantity T2 of the second sub-data adjustment stage 321, and the quantity T3 of the third sub-data adjustment stage 331 can decrease more rapidly, and large or small discontinuities in the middle can be avoided, so that the transition layer can transition evenly.

[0103] Please continue reading. Figure 8 and 9 Based on the sequentially set first data adjustment stage 31, second data adjustment stage 32, and third data adjustment stage 33 in the data adjustment stage 30, the total number of frames in each stage can be kept consistent, i.e., T1×(m1+n1)=T2×(m2+n2)=T3×(m3+n3). Figure 11 In this process, the total number of frames in each data adjustment phase of 30 is 8.

[0104] It is understandable that keeping the total number of frames in each data adjustment phase 30 consistent ensures that the state adjustment time of the driving transistor T is consistent in each data adjustment phase 30. This avoids situations where the time is too long in some phases and too short in others, causing the driving transistor T to have different state times and thus leading to instability.

[0105] In yet another optional example, see Figures 8 to 11 , Figure 10 This is a schematic diagram of the pixel circuit operation process in a display panel according to another embodiment of the present invention. Figure 11 yes Figure 10 A parameter table related to the operation of the pixel circuit. In the first sub-data adjustment stage 311, the number of data written to frame 11 is m1 = 1, while maintaining the number of frames 12 n1 ≥ 0; in the second sub-data adjustment stage 321, the number of data written to frame 11 is m2 = 1, while maintaining the number of frames 12 n2 ≥ 1; in the third sub-data adjustment stage 331, the number of data written to frame 11 is m3 > 1, and n3 ≥ m3. Wherein, Figure 8 and Figure 9 As shown, m1 = 1, n1 = 0; m2 = 1, n2 = 1; m3 = 1, n3 = 3, which satisfies the above size relationship. Figure 10 and Figure 11 As shown, m1 = 1, n1 = 0; m2 = 1, n2 = 1; n3 = 2, m3 = 2, which also satisfies the above size relationship.

[0106] It is understandable that when switching from the first data adjustment stage 31 to the second data adjustment stage 32, n1 and n2 of the holding frame 12 are still relatively small. Therefore, a data writing frame 11 can be written first, and then the holding frame 12 can be written. Then, the data writing frame 11 is entered again, so that the data writing frame 11 and the holding frame 12 are evenly distributed, which is conducive to timely stabilizing the state of the driving transistor T.

[0107] When the second data adjustment stage 32 switches to the third data adjustment stage 33, the number of holding frames 12 gradually increases. The number n3 of the third sub-data adjustment stage 331 is relatively large. Therefore, by first inputting multiple data to write to frame 11 and then inputting multiple holding frames 12, the state of the driving transistor T can be guaranteed.

[0108] It should also be noted that, please refer to Figure 1 , Figure 4 , Figure 6 and Figure 12 , Figure 12 This is a parameter table related to the operation of the pixel circuit under two different data refresh rates. Based on Figure 1 In another alternative example of the structure shown, the operation of the pixel circuit 10 includes a first data refresh frequency F21 and a second data refresh frequency F22, wherein F21 < F22 < F1.

[0109] See Figure 1 and Figure 4 When the pixel circuit 10 operates at the first data refresh frequency F21, the first data adjustment stage 31 includes T11 first sub-data adjustment stages 311 arranged in sequence, and the second data adjustment stage 32 includes T12 second sub-data adjustment stages 321 arranged in sequence.

[0110] See Figure 1 and Figure 6 When the pixel circuit 10 operates at the second data refresh frequency F22, the first data adjustment stage 31 includes T21 sequentially arranged first sub-data adjustment stages 311, and the second data adjustment stage 32 includes T22 sequentially arranged second sub-data adjustment stages 321; wherein...

[0111] T11 > T21, and / or, T12 > T22.

[0112] It should be noted that the first data refresh frequency F21 and the second data refresh frequency F22 can be two different low frequencies, where F21 < F22. When the pixel circuit 10 operates at the corresponding data refresh frequency, the relatively higher data refresh frequency F22 results in a relatively shorter holding frame 12 duration for adjacent data refresh cycles S2. The offset of the threshold voltage Vth of the driving transistor T0 gate is not as severe as when operating at the first data refresh frequency F21. Therefore, when setting the number of holding frames 12, the number of holding frames 12 in the first sub-data adjustment stage 311 can be less than the number of holding frames 12 in the first sub-data adjustment stage 311 at the relatively lower data refresh frequency F21.

[0113] When the pixel circuit 10 operates at the second data refresh frequency F22, the number of the first sub-data adjustment stages 311 can also be appropriately smaller than the number of the first sub-data adjustment stages 311 when operating at the first data refresh frequency F21, so as to save the time of the data adjustment stage 30.

[0114] In contrast, when the pixel circuit 10 operates at the first data refresh frequency F21, the number of first sub-data adjustment stages 311 is relatively large, thereby ensuring that the state of the driving transistor T0 can be quickly and completely adjusted.

[0115] By adapting the number of holding frames 12 and the number of sub-data adjustment stages 30 in the data adjustment stage 30 when the pixel circuit 10 is operating at different data refresh frequencies, the time of the data adjustment stage 30 can be flexibly adjusted, while also avoiding flickering phenomena that can be observed by the human eye.

[0116] Please refer to Figure 1 , Figure 4 , Figure 6 and Figure 12 ,in Figure 4 This is a schematic diagram of the operation of the pixel circuit 10 at the first data refresh frequency F21, wherein the difference between the number n2 of the number of holding frames 12 in the second sub-data adjustment stage 321 and the number n1 of the number of holding frames 12 in the first sub-data adjustment stage 311 is R1. R1 can be 1-0=1.

[0117] in Figure 6 When the pixel circuit 10 operates at the second data refresh frequency F22, the difference between the number m2 of held frames 12 in the second sub-data adjustment stage 321 and the number m1 of held frames 12 in the first sub-data adjustment stage 311 is R2. Where R1 > R2. R2 can be 3 - 1 = 2, in which case R2 = 2 > R1 = 1.

[0118] As can be seen from the foregoing description, the first data refresh frequency F21 is less than the second data refresh frequency F22. When the pixel circuit 10 operates at a relatively low data refresh frequency, i.e., the first data refresh frequency F21, the data refresh cycle S2 span is relatively larger. Therefore, in order to save the time of the data adjustment stage 30, the pixel circuit 10 can keep the span between frames 12 set to be larger in each data adjustment stage at the first data refresh frequency F21.

[0119] Please continue reading. Figure 1 , Figures 6 to 9 ,in Figure 1 and Figure 8 and Figure 9 The pixel circuit 10 described above can operate at the first data refresh frequency F21, and the data adjustment stage 30 includes N1 stages sequentially set from the first data adjustment stage 31 to the N1th data adjustment stage 30, where N1 ≥ 1. In this example, N1 = 3.

[0120] in Figure 1 , Figure 6 and Figure 7 The diagram illustrates that when the pixel circuit 10 operates at the second data refresh frequency F22, the data adjustment stage 30 includes N2 stages sequentially arranged from the first data adjustment stage 31 to the N2nd data adjustment stage 30, where N2 ≥ 1; and N1 > N2. In this example, N2 = 2.

[0121] This configuration is because when the data refresh frequency is relatively low, the difference between the number of hold frames 12 in the normal data refresh cycle S2 and the number of hold frames 12 in the first data adjustment stage 31 is larger. Therefore, more subsequent data adjustment stages 30 are needed for a smooth transition. When the data refresh frequency is relatively high, only a few subsequent data refresh stages other than the first data adjustment stage 31 are needed for a smooth transition.

[0122] The above text combines Figures 1 to 12 The present invention describes in detail the display panel of an embodiment of the present invention. Based on this, the present application also protects a display device, see reference... Figure 13 , Figure 13 This is a schematic diagram of a display device provided in this application. The display device includes the display panel 200 provided in any of the foregoing embodiments. The display device can be at least one of wearable devices, cameras, mobile phones, tablet computers, displays, televisions, and vehicle-mounted display terminals. Since the display device includes the display panel provided in the above embodiments, it possesses all the beneficial effects of the aforementioned display panel.

[0123] Furthermore, the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0124] It should be understood that, in the embodiments of the present invention, "B corresponding to A" means that B is associated with A, and B can be determined based on A. However, it should also be understood that determining B based on A does not mean that B is determined solely based on A; B can also be determined based on A and / or other information.

[0125] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A display panel, characterized in that, include: Pixel circuit; The operation of the pixel circuit includes a first data refresh cycle, a data adjustment stage, and a second data refresh cycle set sequentially. The data adjustment stage includes a first data adjustment stage, a second data adjustment stage, and a third data adjustment stage set sequentially. The first data adjustment stage includes T1 first sub-data adjustment stages set sequentially. Each first sub-data adjustment stage includes m1 data write frames and n1 hold frames, where T1≥1, m1≥0, n1≥0, and m1+n1≥1. The second data adjustment phase includes T2 second sub-data adjustment phases set sequentially. Each second sub-data adjustment phase includes m2 data write frames and n2 hold frames, where T2≥1, m2≥0, n2≥0, and m2+n2≥1. The third data adjustment stage includes T3 sequentially set third sub-data adjustment stages, each sub-data adjustment stage comprising m3 data write frames and n3 hold frames, where T3 ≥ 1, m3 ≥ 0, n3 ≥ 0, and m3 + n3 ≥ 1; wherein... n1 < n2 < n3, m1 ≥ m2 ≥ m3 > 0; and T1>T2≥T3, T1-T2>T2-T3; (m3+n3)-( m2+n2)>( m2+n2)-( m1+n1); (m3+n3) / ( m2+n2)= ( m2+n2) / ( m1+n1)≥1.

2. The display panel according to claim 1, characterized in that, The display panel also includes light-emitting elements; The brightness of the light-emitting element during the first data refresh cycle is less than the brightness of the light-emitting element during the second data refresh cycle.

3. The display panel according to claim 1, characterized in that, T1 / T2 = T2 / T3.

4. A display panel, characterized in that, include: Pixel circuit; The operation of the pixel circuit includes a first data refresh cycle, a data adjustment stage, and a second data refresh cycle set sequentially. The data adjustment stage includes a first data adjustment stage, a second data adjustment stage, and a third data adjustment stage set sequentially. The first data adjustment stage includes T1 first sub-data adjustment stages set sequentially. Each first sub-data adjustment stage includes m1 data write frames and n1 hold frames, where T1≥1, m1≥0, n1≥0, and m1+n1≥1. The second data adjustment phase includes T2 second sub-data adjustment phases set sequentially. Each second sub-data adjustment phase includes m2 data write frames and n2 hold frames, where T2≥1, m2≥0, n2≥0, and m2+n2≥1. The third data adjustment stage includes T3 sequentially set third sub-data adjustment stages, each sub-data adjustment stage comprising m3 data write frames and n3 hold frames, where T3 ≥ 1, m3 ≥ 0, n3 ≥ 0, and m3 + n3 ≥ 1; wherein... n1 < n2 < n3, m1 ≥ m2 ≥ m3 > 0; and T1>T2≥T3, T1-T2>T2-T3, and (m3+n3)-(m2+n2)>(m2+n2)-(m1+n1); or, (m3+n3)-(m2+n2)>(m2+n2)-(m1+n1), and (m3+n3) / (m2+n2)= (m2+n2) / (m1+n1)≥1; or, T1>T2≥T3, T1-T2>T2-T3, and (m3+n3) / (m2+n2)= (m2+n2) / (m1+n1)≥1.

5. The display panel according to claim 4, characterized in that, The display panel also includes light-emitting elements; The brightness of the light-emitting element during the first data refresh cycle is less than the brightness of the light-emitting element during the second data refresh cycle.

6. The display panel according to claim 4, characterized in that, T1 / T2 = T2 / T3.

7. A display panel, characterized in that, include: Pixel circuit; The operation of the pixel circuit includes a first data refresh cycle, a data adjustment stage, and a second data refresh cycle set sequentially. The data adjustment stage includes a first data adjustment stage, a second data adjustment stage, and a third data adjustment stage set sequentially. The first data adjustment stage includes T1 first sub-data adjustment stages set sequentially. Each first sub-data adjustment stage includes m1 data write frames and n1 hold frames, where T1≥1, m1≥0, n1≥0, and m1+n1≥1. The second data adjustment phase includes T2 second sub-data adjustment phases set sequentially. Each second sub-data adjustment phase includes m2 data write frames and n2 hold frames, where T2≥1, m2≥0, n2≥0, and m2+n2≥1. The third data adjustment stage includes T3 sequentially set third sub-data adjustment stages, each sub-data adjustment stage comprising m3 data write frames and n3 hold frames, where T3 ≥ 1, m3 ≥ 0, n3 ≥ 0, and m3 + n3 ≥ 1; wherein... n1 < n2 < n3, m1 ≥ m2 ≥ m3 > 0; and T1>T2≥T3, T1-T2>T2-T3; or, (m3+n3)-(m2+n2)>(m2+n2)-(m1+n1); or, (m3+n3) / ( m2+n2)= ( m2+n2) / ( m1+n1)≥1.

8. The display panel according to claim 7, characterized in that, The display panel also includes light-emitting elements; The brightness of the light-emitting element during the first data refresh cycle is less than the brightness of the light-emitting element during the second data refresh cycle.

9. The display panel according to claim 7, characterized in that, T1 / T2 = T2 / T3.

10. A display device, characterized in that, Includes the display panel as described in any one of claims 1-9.

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