Pixel circuit, driving method thereof, and display device

Abstract

The application discloses a pixel circuit and a driving method thereof, and a display device. The pixel circuit comprises a data writing unit, a storage unit, a storage control unit, a driving unit and a compensation unit. The data writing unit is configured to write a data signal into a first end of the driving unit according to a first scanning signal. The storage unit stores a voltage of a second end of the driving unit. The storage control unit is configured to turn on or off a connection between the second end of the driving unit and the storage unit according to a second scanning signal. The driving unit is configured to generate a driving signal according to the data signal. The driving signal is used for driving a light-emitting unit to emit light. The compensation unit is configured to perform threshold compensation on the driving unit according to a third scanning signal. When the storage unit completes voltage storage and the third scanning signal changes in level, the storage control unit turns off the connection between the driving unit and the storage unit, thereby reducing the influence on the potential of the storage unit and solving the ghosting problem.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a pixel circuit and its driving method, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, and extremely fast response speed. They are widely used in display products such as mobile phones, tablets, and digital cameras. OLED displays are current-driven, requiring current to be output to the OLED through pixel circuits to drive it to emit light. Summary of the Invention

[0003] Based on this, a pixel circuit and its driving method, as well as a display device, are provided to improve the display effect.

[0004] A pixel circuit includes a data writing unit, a storage unit, a storage control unit, a driving unit, a compensation unit, and a light-emitting unit.

[0005] A data writing unit is connected to the first end of the driving unit, and the data writing unit is configured to write a data signal to the first end of the driving unit according to a first scan signal; a compensation unit is connected between the second end and the third end of the driving unit, and the compensation unit is configured to perform threshold compensation on the driving unit according to a third scan signal; a storage control unit is connected between the second end of the driving unit and a storage unit, and the storage control unit is configured to turn on or off the connection between the second end of the driving unit and the storage unit according to a second scan signal; the storage unit is used to store the voltage at the second end of the driving unit; the third end of the driving unit is connected to the light-emitting unit, and the driving unit is configured to generate a driving signal according to the voltage at the second end of the driving unit to drive the light-emitting unit to emit light.

[0006] In one embodiment, the driving unit includes a first transistor, the first electrode of the first transistor serving as the first terminal of the driving unit, the second electrode of the first transistor serving as the second terminal of the driving unit, and the third electrode of the first transistor serving as the third terminal of the driving unit.

[0007] Optionally, the data writing unit includes a second transistor, the first terminal of the second transistor is connected to the first terminal of the driving unit, the second terminal of the second transistor is connected to the first scan line, and the third terminal of the second transistor is connected to the data line;

[0008] Optionally, the compensation unit includes a third transistor, the first terminal of the third transistor is connected to the second terminal of the driving unit, the third terminal of the third transistor is connected to the third terminal of the driving unit, and the second terminal of the third transistor is connected to the third scan line.

[0009] Optionally, the storage unit includes a storage capacitor, a first end of which is connected to a first power line, and a second end of which is connected to a storage control unit.

[0010] Optionally, the storage control unit includes a fourth transistor, the first terminal of the fourth transistor is connected to the second terminal of the driving unit, the second terminal of the fourth transistor is connected to the second scan line, and the third terminal of the fourth transistor is connected to the storage unit.

[0011] Optionally, the third transistor is an N-type transistor.

[0012] In one embodiment, the pixel circuit further includes a first light-emitting control unit and / or a second light-emitting control unit. The first light-emitting control unit is connected between a first power line and a first end of a driving unit, and is configured to turn on or off the connection between the first power line and the first end of the driving unit according to a light-emitting control signal. The second light-emitting control unit is connected between a third end of the driving unit and the light-emitting unit, and is configured to turn on or off the connection between the third end of the driving unit and the light-emitting unit according to a light-emitting control signal.

[0013] Optionally, the first light-emitting control unit includes a fifth transistor, the first terminal of which is connected to the first terminal of the driving unit, the second terminal of which is connected to the control signal line, and the third terminal of which is connected to the first power supply line; and / or, the second light-emitting control unit includes a sixth transistor, the first terminal of which is connected to the third terminal of the driving unit, the second terminal of which is connected to the control signal line, and the third terminal of which is connected to the light-emitting unit.

[0014] In one embodiment, the pixel circuit further includes an initialization unit and / or a reset unit. The initialization unit is connected to the second terminal of the driving unit and is configured to transmit a first voltage signal to the second terminal of the driving unit according to a fourth scan signal to initialize the driving unit. The reset unit is connected to the light-emitting unit and is configured to transmit a second voltage signal to the light-emitting unit according to a fifth scan signal to reset the light-emitting unit.

[0015] Optionally, the initialization unit includes a seventh transistor, the first terminal of which is connected to the second terminal of the driving unit, the second terminal of which is connected to the fourth scan line, and the third terminal of which is connected to the initialization signal line; and / or, the reset unit includes an eighth transistor, the first terminal of which is connected to the light-emitting unit, the second terminal of which is connected to the fifth scan line, and the third terminal of which is connected to the reset signal line.

[0016] Optionally, the seventh transistor is an N-type transistor.

[0017] In one embodiment, the pixel circuit further includes a voltage regulator unit, with the storage control unit connected to the second terminal of the driving unit via the voltage regulator unit, and the compensation unit connected to the second terminal of the driving unit via the voltage regulator unit; or, the voltage regulator unit is connected between the second terminal of the driving unit and the storage control unit, and the voltage regulator unit is connected between the storage control unit and the compensation unit; or, the pixel circuit further includes an initialization unit, with the voltage regulator unit connected between the second terminal of the driving unit and the initialization unit, the voltage regulator unit connected between the storage control unit and the initialization unit, and the voltage regulator unit connected between the compensation unit and the initialization unit; the voltage regulator unit is used to stabilize the voltage at the second terminal of the driving unit.

[0018] In one embodiment, the voltage regulating unit includes a voltage regulating capacitor.

[0019] Optionally, the storage unit includes a storage capacitor, with a first end connected to a first power supply line and a second end connected to a storage control unit; the voltage regulator capacitor and the storage capacitor have the same capacitance value.

[0020] A display device includes pixel circuitry as described in any of the above embodiments.

[0021] A driving method for a pixel circuit is provided for driving a pixel circuit as described in any of the above embodiments. The pixel circuit includes a charging phase during the operation of a display frame. The driving method includes controlling the level of a first scan signal to be on, controlling the level of a second scan signal to be on, and controlling the level of a third scan signal to be on during the charging phase; at the end of the charging phase, controlling the level of the first scan signal to be off, controlling the level of the second scan signal to be off, and controlling the level of the third scan signal to be off; wherein the on level of the third scan signal is greater than the off level of the third scan signal.

[0022] In one embodiment, the pixel circuit further includes an initialization phase before the charging phase. The driving method includes, during the initialization phase, controlling a second scan signal to be on and controlling a fourth scan signal to be on.

[0023] Optionally, during the initialization phase, the fifth scan signal is controlled to be at the on level.

[0024] In one embodiment, the pixel circuit further includes a light-emitting stage after the charging stage ends, and the driving method includes controlling the light-emitting control signal to be at the on level and controlling the second scanning signal to be a pulse signal of a preset frequency during the light-emitting stage.

[0025] In the aforementioned pixel circuit, the data writing unit can transmit a data signal to the first terminal of the driving unit based on the first scan signal. The compensation unit can perform threshold compensation on the driving unit, and the threshold-compensated data signal is transmitted to the second terminal of the driving unit, allowing the storage unit to store the voltage at the second terminal of the driving unit. The driving unit can generate a driving signal based on the voltage at the second terminal of the driving unit to drive the light-emitting unit to emit light. This configuration achieves at least one of the following effects: during a portion of the light-emitting phase, turning off the storage control unit reduces the impact of leakage current from the compensation unit on the potential at the second terminal of the driving unit; the storage control unit can resolve the issue of the coupling capacitor affecting the storage unit's potential by disconnecting the coupling capacitor between the storage unit and the scan line transmitting the third scan signal when the storage unit completes storing the voltage at the second terminal of the driving unit and when the level of the third scan signal changes. Simultaneously, by reducing the impact of the scan line transmitting the third scan signal on the storage unit's potential, the problem of ghosting can be improved or resolved. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of this specification or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this specification. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0027] Figure 1 This is a schematic diagram of a pixel driving circuit in related technologies;

[0028] Figure 2 This is a schematic diagram of the pixel circuit structure in one embodiment of this application;

[0029] Figure 3 This is a schematic diagram of a structure where there is a coupling capacitor between the memory cell and the third scan line.

[0030] Figure 4 This is a schematic diagram of the pixel circuit structure in another embodiment of this application;

[0031] Figure 5 This is a schematic diagram of the pixel circuit structure in one embodiment of this application;

[0032] Figure 6 This is a schematic diagram of the pixel circuit in another embodiment of this application;

[0033] Figure 7 This is a schematic diagram of the pixel circuit in another embodiment of this application;

[0034] Figure 8 This is a schematic diagram of the pixel circuit in another embodiment of this application;

[0035] Figure 9 This is a schematic diagram of the circuit structure of the voltage regulator capacitor in the pixel circuit in one embodiment of this application;

[0036] Figure 10 This is a schematic diagram of the circuit structure of the voltage regulator capacitor in the pixel circuit in another embodiment of this application;

[0037] Figure 11 This is a schematic diagram of the circuit structure of the voltage regulator capacitor in the pixel circuit in another embodiment of this application;

[0038] Figure 12 This is a flowchart illustrating the driving method of the pixel circuit in one embodiment of this application;

[0039] Figure 13 This is a flowchart illustrating a pixel circuit driving method in another embodiment of this application;

[0040] Figure 14 This is a timing diagram of the pixel circuit in one embodiment of this application. Detailed Implementation

[0041] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. The drawings illustrate optional embodiments of the invention. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0043] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0044] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this application, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0045] In this application, unless otherwise expressly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a direct connection or an indirect connection through an intermediate medium, or they can refer to the internal connection of two elements or the interaction between two elements. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0046] In the display panel industry, LTPO (Low-Temperature Polycrystalline Oxid) products use indium gallium zinc oxide thin-film transistors (IGZO TFTs) connected to the driving transistors to improve the problem of unstable gate voltage under low-frequency driving by utilizing the low leakage current of IGZO TFTs themselves.

[0047] However, due to the high PPI (pixel density unit) requirement, the internal wiring space of the product is limited, so coupling capacitance between components is unavoidable. This coupling capacitance may affect the potential of some components. Furthermore, LTPO products typically have higher VGMP (Voltage Gain Maximum) requirements than LTPS (Low Temperature Poly-Silicon) products to avoid issues such as L0 image brightness manipulation. Therefore, LTPO products may exhibit ghosting problems.

[0048] In the pixel driving circuit of relevant LTPO products, the following is used: Figure 1 The 7T1C circuit shown. Figure 1This is a schematic diagram of a pixel driving circuit in related technologies. The 7T1C circuit includes 7 transistors and 1 storage capacitor. In the LTPO product, the TFT M3 is an IGZO. Since the IGZO TFT is N-type and LTPO products require high PPI (pixel density unit), coupling capacitance between devices is unavoidable given limited layout space. For example, when M2 completes the Vdata signal writing and the gate voltage of the IGZO TFT (i.e., scan signal S3) changes from high to low, the coupling capacitance C0 between the storage capacitor and the scan line transmitting the scan signal S3 will affect the potential of the storage capacitor. Simultaneously, to avoid issues such as L0 stealth, LTPO products often have higher VGMP (black state voltage) requirements than LTPS products. Therefore, using the same vapor deposition material system, LTPO products may exhibit ghosting issues.

[0049] Figure 2 This is a schematic diagram of the pixel circuit in one embodiment of the present application. In one embodiment, the pixel circuit may include a data writing unit 100, a storage unit 200, a storage control unit 300, a driving unit 400, a compensation unit 500, and a light-emitting unit 10.

[0050] The data writing unit 100 can be connected to the first terminal of the driving unit 400. The data writing unit 100 can be configured to write the data signal Vdata to the first terminal of the driving unit 400 according to the first scan signal S1. The data writing unit 100 can also be connected to the first scan line and the data line respectively. The data writing unit 100 obtains the first scan signal S1 through the first scan line and obtains the data signal Vdata through the data line, thereby transmitting the data signal Vdata to the first terminal of the driving unit 400 according to the first scan signal S1.

[0051] The compensation unit 500 can be connected between the second end and the third end of the drive unit 400. The compensation unit 500 can be configured to perform threshold compensation on the drive unit 400 according to the third scan signal S3. The compensation unit 500 can also be connected to the third scan line to obtain the third scan signal S3, so that the compensation unit 500 can perform threshold compensation on the drive unit 400 according to the third scan signal S3.

[0052] A storage control unit 300 can be connected between the second terminal of the drive unit 400 and the storage unit 200. The storage control unit 300 can be configured to turn the connection between the second terminal of the drive unit 400 and the storage unit 200 on or off according to a second scan signal S2. The storage control unit 300 can also be connected to a second scan line to acquire the second scan signal S2. The storage control unit 300 may include a switching transistor, which is controlled to turn on or off according to the second scan signal S2, thereby enabling the storage control unit 300 to turn the connection between the second terminal of the drive unit 400 and the storage unit 200 on or off according to the second scan signal S2. The storage unit 200 can be used to store the voltage at the second terminal of the drive unit 400.

[0053] The third terminal of the driving unit 400 can be connected to the light-emitting unit 10. The driving unit 400 can be configured to generate a driving signal based on the voltage at the second terminal of the driving unit 400. This driving signal can be used to drive the light-emitting unit 10 to emit light. That is, when the threshold-compensated data signal is transmitted to the second terminal of the driving unit 400, the driving unit 400 can generate a driving current based on the voltage received at the second terminal of the driving unit 400 and transmit it to the light-emitting unit 10 to drive the light-emitting unit 10 to emit light.

[0054] The pixel circuit provided in this embodiment allows the data writing unit 100 to write a data signal to the first terminal of the driving unit 400 based on a first scan signal. The compensation unit 500 performs threshold compensation on the driving unit 400 and transmits the threshold-compensated data signal to the second terminal of the driving unit 400. The storage unit 200 stores the voltage at the second terminal of the driving unit 400. During the light-emitting phase, the driving unit 400 generates a driving signal based on the voltage at its second terminal to drive the light-emitting unit 10 to emit light.

[0055] Considering that after the data writing unit 100 completes writing the data signal Vdata to the first terminal of the driving unit 400, the compensation unit 500 completes threshold compensation for the driving unit 400, and the storage unit 200 completes storing the voltage at the second terminal of the driving unit 400, the third scan signal S3 received by the compensation unit 500 will undergo a level change. The coupling capacitance C0 between the storage unit 200 and the third scan line will be affected by the level change of the third scan signal S3, thus influencing the potential of the storage unit 200.

[0056] Figure 3This is a schematic diagram showing the structure when there is a coupling capacitor between the storage unit and the third scan line. In the pixel circuit provided in this embodiment, by setting a storage control unit 300, the connection between the storage unit 200 and the coupling capacitor C0 can be disconnected when the charging of the storage unit 200 ends and when the voltage of the third scan signal S3 changes. This solves the problem that the coupling capacitor C0 between the storage unit 200 and the third scan line affects the potential of the storage unit 200 due to the voltage change of the third scan signal S3. By reducing the influence of the third scan line on the potential of the storage unit 200, it can be ensured that the storage unit 200 can normally control the output of the driving unit 400 during the light emission stage of the pixel circuit, thereby improving or solving the problem of ghosting.

[0057] During certain periods of the light-emitting phase, turning off the storage control unit 300 can reduce the impact of leakage current from the compensation unit 500 on the potential of the second terminal of the drive unit 400, thereby improving the stability of the voltage at the second terminal of the drive unit 400 and thus enhancing the display effect.

[0058] Figure 4 This is a schematic diagram of the pixel circuit in another embodiment of the present application. In one embodiment, the pixel circuit may further include an initialization unit 800 and / or a reset unit 900.

[0059] The initialization unit 800 can be connected to the second terminal of the driving unit 400, and can also be connected to the fourth scan line to acquire the fourth scan signal S4. The initialization unit 800 can be configured to transmit the first voltage signal Vref1 to the second terminal of the driving unit 400 according to the fourth scan signal S4 to initialize the driving unit 400. During a portion of the light-emitting phase, turning off the storage control unit 300 can reduce the impact of leakage current from the compensation unit 500 and the initialization unit 800 on the potential of the second terminal of the driving unit 400, thereby improving the voltage stability of the second terminal of the driving unit 400 and enhancing the display effect.

[0060] The reset unit 900 can be connected to the light-emitting unit 10, and can also be connected to the fifth scan line to obtain the fifth scan signal S5. The reset unit 900 can be configured to transmit the second voltage signal Vref2 to the light-emitting unit 10 according to the fifth scan signal S5 to reset the light-emitting unit 10.

[0061] Figure 5This is a schematic diagram of the circuit structure of the pixel circuit in one embodiment of this application. In one embodiment, the driving unit 400 may include a first transistor M1. The first electrode of the first transistor M1 may serve as the first terminal of the driving unit 400, the second electrode of the first transistor M1 may serve as the second terminal of the driving unit 400, and the third electrode of the first transistor M1 may serve as the third terminal of the driving unit 400.

[0062] In embodiments of this disclosure, a transistor refers to a device that includes at least a gate, a drain, and a source. In this disclosure, the first terminal of a transistor can be the drain and the third terminal can be the source, or vice versa. When using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. In embodiments of this disclosure, the second terminal of all or part of the transistor can be the gate, serving as the control electrode, while the first and third terminals can be interchanged as needed.

[0063] In one embodiment, the data writing unit 100 may include a second transistor M2. The first terminal of the second transistor M2 may be connected to the first terminal of the driving unit 400, the second terminal of the second transistor M2 may be connected to a first scan line, and the third terminal of the second transistor M2 may be connected to a data line. The second transistor M2 can obtain a first scan signal S1 transmitted by the first scan line through its second terminal, and obtain a data signal Vdata transmitted by the data line through its third terminal. The first scan signal S1 can be used to control the second transistor M2 to enter an on or off state, so that when the second transistor M2 enters the on state according to the first scan signal S1, it can write the data signal Vdata to the first terminal of the driving unit 400.

[0064] In one embodiment, the compensation unit 500 may include a third transistor M3. The first terminal of the third transistor M3 is connected to the second terminal of the driving unit 400, the third terminal of the third transistor M3 is connected to the third terminal of the driving unit 400, and the second terminal of the third transistor M3 is connected to a third scan line. The third transistor M3 can obtain the third scan signal S3 transmitted by the third scan line through its second terminal. The third scan signal S3 can be used to control the third transistor M3 to enter an on or off state, so that the third transistor M3 can perform threshold compensation on the driving unit 400 when it enters the on state according to the third scan signal S3.

[0065] In one embodiment, the storage unit 200 may include a storage capacitor Cst, the first end of which may be connected to a first power supply line. The first power supply line may continuously provide a first voltage VDD, for example, a high level. The second end of the storage capacitor Cst may be connected to a storage control unit 300. The storage capacitor Cst may be used to store the voltage at the second terminal of the first transistor M1, that is, the voltage stored in the storage capacitor Cst is a threshold-compensated data signal.

[0066] In one embodiment, the storage control unit 300 may include a fourth transistor M4. The first terminal of the fourth transistor M4 may be connected to the second terminal of the driving unit 400, the second terminal of the fourth transistor M4 may be connected to the second scan line, and the third terminal of the fourth transistor M4 may be connected to the storage unit 200. The fourth transistor M4 can obtain the second scan signal S2 transmitted by the second scan line through its second terminal. The second scan signal S2 can be used to control the fourth transistor M4 to enter an on or off state, thereby enabling the fourth transistor M4 to turn on or off the connection between the second terminal of the driving unit 400 and the storage unit 200 according to the second scan signal S2.

[0067] In one embodiment, the light-emitting unit 10 may include a light-emitting diode (LED) D1. When a drive signal generated by the first transistor M1 is transmitted to the LED D1, the LED D1 can emit light with a brightness corresponding to the drive signal. The LED D1 may include an anode and a cathode. The cathode of the LED D1 is connected to a second power supply line. One of the voltages on the first power supply line and the second power supply line is at a high level, and the other is at a low level. The second power supply line can continuously provide a second voltage VSS, for example, it can be at a low level.

[0068] In one embodiment, the third transistor M3 can be an N-type transistor. Optionally, the third transistor M3 can be an indium gallium zinc oxide thin-film transistor (IGZO TFT). That is, the above pixel circuit is applied to LTPO products. By replacing the switching transistor connected to the driving transistor with an IGZO TFT, the leakage current of the pixel circuit can be reduced due to the lower leakage current of the IGZO TFT, thereby ensuring the display effect under low-frequency driving. That is, the low leakage current of the IGZO TFT itself is used to improve the problem of unstable gate voltage under low-frequency driving. Optionally, the third transistor M3 can also be a P-type transistor.

[0069] However, as Figure 1 As shown, after the storage capacitor Cst finishes charging and the data signal Vdata is written, the gate voltage of the third transistor M3 will change from high level to low level according to the third scan signal S3, thereby the coupling capacitor C0 will pull down the potential of the second terminal of the storage capacitor Cst.

[0070] This embodiment of the invention provides a fourth transistor M4. When the storage capacitor Cst finishes charging and the third scan signal S3 changes level (e.g., from high to low), the fourth transistor M4 can enter a cutoff state according to the second scan signal S2, thus disconnecting the connection between the storage capacitor Cst and the coupling capacitor C0. This solves the problem of the coupling capacitor C0 affecting the potential of the storage capacitor Cst due to the voltage jump of the third scan signal S3. By reducing the impact on the potential of the storage capacitor Cst, it is ensured that the storage capacitor Cst can normally transmit a stable electrical signal to the second electrode of the first transistor M1 during the light-emitting stage, thereby improving or solving the ghosting problem of the product. Simultaneously, when the fourth transistor M4 is turned off, the connection between the storage capacitor Cst and the third transistor M3 is also broken, thus also solving the problem of the leakage current of the third transistor M3 affecting the potential of the storage capacitor Cst.

[0071] like Figure 4 As shown, in one embodiment, the pixel circuit may further include a first light-emitting control unit 600 and / or a second light-emitting control unit 700.

[0072] A first light-emitting control unit 600 can be connected between a first power supply line and a first terminal of a driving unit 400. The first light-emitting control unit 600 can be configured to turn the connection between the first power supply line and the first terminal of the driving unit 400 on or off according to a light-emitting control signal EM. The first light-emitting control unit 600 may include a switching transistor, which is turned on or off according to the light-emitting control signal EM, thereby enabling the first light-emitting control unit 600 to turn the connection between the first power supply line and the first terminal of the driving unit 400 on or off according to the light-emitting control signal EM.

[0073] The second light-emitting control unit 700 can be connected between the third terminal of the driving unit 400 and the light-emitting unit 10. The second light-emitting control unit 700 can be configured to turn the connection between the third terminal of the driving unit 400 and the light-emitting unit 10 on or off according to the light-emitting control signal EM. Similarly, the second light-emitting control unit 700 may also include a switching transistor, which is turned on or off according to the light-emitting control signal EM, so that the second light-emitting control unit 700 can turn the connection between the third terminal of the driving unit 400 and the light-emitting unit 10 on or off according to the light-emitting control signal EM.

[0074] In one embodiment, such as Figure 5As shown, the first light-emitting control unit 600 may include a fifth transistor M5. The first terminal of the fifth transistor M5 may be connected to the first terminal of the driving unit 400, the second terminal of the fifth transistor M5 may be connected to a control signal line, and the third terminal of the fifth transistor M5 may be connected to a first power supply line. The fifth transistor M5 can receive a light-emitting control signal EM transmitted through the control signal line through its second terminal. The light-emitting control signal EM can be used to control the conduction or de-conduction of the fifth transistor M5, thereby enabling the first light-emitting control unit 600 to turn on or off the connection between the first power supply line and the first terminal of the driving unit 400 according to the light-emitting control signal EM.

[0075] In one embodiment, such as Figure 5 As shown, the second light-emitting control unit 700 may include a sixth transistor M6. The first terminal of the sixth transistor M6 can be connected to the third terminal of the driving unit 400, the second terminal of the sixth transistor M6 can be connected to a control signal line, and the third terminal of the sixth transistor M6 can be connected to the light-emitting unit 10. The third terminal of the sixth transistor M6 can be connected to the anode of the light-emitting diode D1. The sixth transistor M6 can receive a light-emitting control signal EM transmitted through the control signal line via its second terminal. The light-emitting control signal EM can also be used to control the conduction or de-conduction of the sixth transistor M6, thereby enabling the second light-emitting control unit 700 to turn on or off the connection between the third terminal of the driving unit 400 and the light-emitting unit 10 according to the light-emitting control signal EM.

[0076] In one embodiment, such as Figure 5 As shown, the initialization unit 800 may include a seventh transistor M7. The first terminal of the seventh transistor M7 can be connected to the second terminal of the driving unit 400, the second terminal of the seventh transistor M7 is connected to the fourth scan line, and the third terminal of the seventh transistor M7 is connected to the initialization signal line. The seventh transistor M7 can receive the fourth scan signal S4 transmitted from the fourth scan line through its second terminal. The fourth scan signal S4 can be used to control the turning on or off of the seventh transistor M7. Therefore, when the fourth scan signal S4 is turned on, the initialization unit 800 can transmit the first voltage signal Vref1 to the second terminal of the driving unit 400 to initialize the driving unit 400. When the fourth transistor M4 is turned off, the connection between the storage capacitor Cst and the seventh transistor M7 is also broken, and the connection between the storage capacitor Cst and the third transistor M3 is also broken. Therefore, the influence of leakage current in the third transistor M3 and the seventh transistor M7 on the potential of the storage capacitor Cst can be resolved.

[0077] In one embodiment, such as Figure 5As shown, the reset unit 900 may include an eighth transistor M8. The first terminal of the eighth transistor M8 can be connected to the light-emitting unit 10, the second terminal of the eighth transistor M8 is connected to the fifth scan line, and the third terminal of the eighth transistor M8 is connected to the reset signal line. The eighth transistor M8 can receive the fifth scan signal S5 transmitted from the fifth scan line through its second terminal. The fifth scan signal S5 can be used to control the conduction or de-conduction of the eighth transistor M8. Therefore, when the eighth transistor M8 is turned on according to the fifth scan signal S5, the reset unit 900 can transmit the second voltage signal Vref2 to the light-emitting unit 10 to reset the light-emitting unit 10. The first terminal of the eighth transistor M8 can be connected to the anode of the light-emitting diode D1 to reset the anode of the light-emitting diode D1.

[0078] The second terminal of the second transistor M2 is connected to the first scan line. The first scan line can transmit the first scan signal S1 to the second terminal of the second transistor M2, so as to control the conduction or deactivation of the second transistor M2 using the first scan signal S1. The third terminal of the second transistor M2 is connected to the data line, so that the data signal Vdata can be transmitted to the third terminal of the second transistor M2. When the second transistor M2 is turned on according to the first scan signal, the second transistor M2 can transmit the data signal Vdata to the first terminal of the first transistor M1 through the first terminal of the second transistor M2.

[0079] The second terminal of the third transistor M3 is connected to the third scan line. The third scan line transmits the third scan signal S3 to the second terminal of the third transistor M3, so as to control the conduction or deactivation of the third transistor M3 using the third scan signal S3. The third transistor M3 is connected between the second and third terminals of the first transistor M1. When the pixel circuit is operating in the charging phase and the third transistor M3 is turned on according to the third scan signal S3, the third transistor M3 can perform threshold compensation on the first transistor M1.

[0080] The second terminal of the fourth transistor M4 is connected to the second scan line, which transmits the second scan signal S2 to the second terminal of the fourth transistor M4, thereby controlling the fourth transistor M4 to turn on or off. The third terminal of the fourth transistor M4 is connected to the second terminal of the storage capacitor Cst.

[0081] The first terminal of the fifth transistor M5 can be connected to the first terminal of the first transistor M1 and the first terminal of the second transistor M2, respectively. The second terminal of the fifth transistor M5 can be connected to a control signal line, which transmits a light emission control signal EM to the second terminal of the fifth transistor M5, thereby controlling the conduction or disconnection of the fifth transistor M5 using the light emission control signal EM. The third terminal of the fifth transistor M5 can be connected to the first terminal of the storage capacitor Cst and the first power supply line, respectively.

[0082] The first terminal of the sixth transistor M6 can be connected to the third terminals of both the first transistor M1 and the third transistor M3. The second terminal of the sixth transistor M6 can be connected to a control signal line, which transmits the light-emitting control signal EM to the second terminal of the sixth transistor M6, thereby controlling the conduction or disconnection of the sixth transistor M6. The third terminal of the sixth transistor M6 can be connected to the anode of the light-emitting diode D1.

[0083] When the pixel circuit is operating in the charging phase, the second transistor M2 can transmit the data signal Vdata to the first terminal of the first transistor M1 according to the first scan signal S1. At this time, the first transistor M1, the third transistor M3, and the fourth transistor M4 can all be in the conducting state, thereby transmitting the data signal Vdata to the second terminal of the first transistor M1. Consequently, the storage capacitor Cst can store the voltage at the second terminal of the first transistor M1. That is, the voltage stored in the storage capacitor Cst is the data signal after threshold compensation, for example, it can be Vdata + Vth, where Vth is the threshold voltage of the first transistor M1.

[0084] In practical layout design, due to the size compression of individual pixel units in small-sized, high-PPI products, the distance between the scan line and the storage capacitor Cst may be compressed, resulting in an increase in coupling capacitance. Please refer to [link to relevant documentation]. Figure 5 In this embodiment, the distance between the third scan line connected to the third transistor M3 and the storage capacitor Cst is compressed, thereby increasing the coupling capacitance C0 between points A and B (i.e., the coupling capacitance C0 between the third scan line and the storage capacitor Cst).

[0085] In addition, after the storage capacitor Cst finishes charging and the data signal Vdata is written, the gate voltage of the third transistor M3 will change from high level to low level according to the third scan signal S3, thereby the coupling capacitor C0 will pull down the potential of the second terminal of the storage capacitor Cst.

[0086] This embodiment of the invention provides a fourth transistor M4. When the storage capacitor Cst finishes charging and the third scan signal S3 changes level, the fourth transistor M4 can enter a cutoff state according to the second scan signal S2, thus disconnecting the connection between the storage capacitor Cst and the coupling capacitor C0. This solves the problem of the coupling capacitor C0 affecting the potential of the storage capacitor Cst due to the voltage jump of the third scan signal S3. By reducing the impact on the potential of the storage capacitor Cst, it is ensured that the storage capacitor Cst can normally transmit a stable electrical signal to the second electrode of the first transistor M1 during the light-emitting stage, thereby improving or solving the ghosting problem of the product. At the same time, when the fourth transistor M4 is turned off, the connection between the storage capacitor Cst and the third transistor M3 is also broken. Therefore, the impact of leakage current of the third transistor M3 on the potential of the storage capacitor Cst can also be solved.

[0087] When the pixel circuit operates in the light-emitting phase, both the fifth transistor M5 and the sixth transistor M6 are turned on according to the light-emitting control signal EM. At this time, the connections between the first power line and the first terminal of the first transistor M1, as well as between the third terminal of the first transistor M1 and the anode of the light-emitting diode D1, are all made conductive. The first voltage VDD provided by the first power line can be transmitted to the first terminal of the first transistor M1 through the fifth transistor M5, and the storage capacitor Cst can transmit the stored threshold-compensated data signal to the second terminal of the first transistor M1. The first transistor M1 can generate a corresponding driving signal according to the voltage at the first and second terminals, and output it to the light-emitting diode D1 through the sixth transistor M6 to drive the light-emitting diode D1 to emit light.

[0088] like Figure 5 As shown, the first terminal of the seventh transistor M7 can be connected to the first terminal of the third transistor M3. The second terminal of the seventh transistor M7 can be connected to the fourth scan line, which transmits the fourth scan signal S4 to the second terminal of the seventh transistor M7, thereby controlling the switching on or off of the seventh transistor M7. The third terminal of the seventh transistor M7 can be connected to the initialization signal line, which transmits the first voltage signal Vref1 to the third terminal of the seventh transistor M7.

[0089] When the pixel circuit is in the initialization phase, the seventh transistor M7 can be turned on according to the fourth scan signal S4, and the fourth transistor M4 can be turned on according to the second scan signal S2. Thus, the initialization signal line can transmit the first voltage signal Vref1 sequentially through the seventh transistor M7 and the fourth transistor M4 to the storage capacitor Cst. The first voltage signal Vref1, which charges the storage capacitor Cst, provides a negative initial voltage to the second terminal of the first transistor M1, initializing the first transistor M1 and facilitating the subsequent data signal Vdata to charge the storage capacitor Cst through the first transistor M1.

[0090] like Figure 5 As shown, the first terminal of the eighth transistor M8 can be connected to the third terminal of the sixth transistor M6 and the anode of the light-emitting diode D1, respectively. The second terminal of the eighth transistor M8 can be connected to the fifth scan line, which transmits the fifth scan signal S5 to the second terminal of the eighth transistor M8, thereby controlling the conduction or disconnection of the eighth transistor M8. The third terminal of the eighth transistor M8 can be connected to the reset signal line, which transmits the second voltage signal Vref2 to the third terminal of the eighth transistor M8.

[0091] When the pixel circuit is in the initialization phase, the eighth transistor M8 can be turned on according to the fifth scan signal S5 to transmit the second voltage signal Vref2 to the anode of the light-emitting diode D1. The second voltage signal Vref2 is used to give a negative voltage to the anode of the light-emitting diode D1 to realize the reset of the light-emitting diode D1.

[0092] During the operation of a display frame in the pixel circuit, the first transistor M1 can be initialized using the first voltage signal Vref1 by turning on the seventh transistor M7 and the eighth transistor M8, and the light-emitting diode D1 can be reset using the second voltage signal Vref2. This prevents residual electrical signals from the previous display frame's light-emitting stage from affecting the current light-emitting stage.

[0093] In one embodiment, the first transistor M1, the second transistor M2, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the eighth transistor M8 can be P-type transistors, such as polycrystalline silicon thin-film transistors.

[0094] Optionally, the seventh transistor M7 can be a P-type transistor. Alternatively, the seventh transistor M7 can be an N-type transistor, such as an oxide thin-film transistor, for example, an indium gallium zinc oxide thin-film transistor.

[0095] In the pixel circuit provided in this disclosure, the switching transistors M3 and M7, which are connected to the driving transistor, are indium gallium zinc oxide (IGZO) thin-film transistors (TFTs), while the other transistors are polysilicon thin-film transistors (PSTs). This utilizes the low leakage current of the IGZO TFT itself to improve the problem of unstable gate voltage under low-frequency driving. Considering that P-type TFTs have more significant advantages than N-type TFTs in the display technology field, and that P-type TFTs do not affect the drain current when providing hole current to the OLED anode, higher quality display applications can be achieved. Therefore, the first transistor M1, the second transistor M2, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the eighth transistor M8 are selected as P-type transistors, such as polysilicon thin-film transistors. In some other embodiments, the device selection for each unit in the pixel circuit can also be other suitable functional components according to actual application requirements.

[0096] Figure 6 This is a schematic diagram of the pixel circuit in another embodiment of the present application. In one embodiment, the pixel circuit may further include a voltage regulator unit 201. Figure 6 This illustrates one possible connection method of the voltage regulator unit 201 in the pixel circuit. In this embodiment, the storage control unit 300 is connected to the second terminal of the driving unit 400 via the voltage regulator unit 201, and the compensation unit 500 is also connected to the second terminal of the driving unit 400 via the voltage regulator unit 201. The voltage regulator unit 201 can be used to stabilize the voltage at the second terminal of the driving unit 400.

[0097] In some other embodiments, the voltage regulator unit 201 may also have other connection methods. Figure 7 This is a schematic diagram of the pixel circuit in another embodiment of this application. Optionally, the voltage regulator unit 201 can be connected between the second terminal of the driving unit 400 and the storage control unit 300.

[0098] In some other embodiments, Figure 8 This is a schematic diagram of the pixel circuit in another embodiment of this application. Optionally, the voltage regulator unit 201 can be connected between the second terminal of the driving unit 400 and the initialization unit 800. The voltage regulator unit 201 can be connected between the storage control unit 300 and the initialization unit 800, and the voltage regulator unit 201 can also be connected between the compensation unit 500 and the initialization unit 800.

[0099] In one embodiment, the voltage regulator unit 201 may include a voltage regulator capacitor C1. Optionally, when selecting circuit components, a capacitor with the same specifications as the storage capacitor Cst can be selected as the voltage regulator capacitor C1, and the capacitance value of the voltage regulator capacitor C1 is the same as the capacitance value of the storage capacitor Cs.

[0100] In one circuit connection configuration, the storage control unit 300 is connected to the second terminal of the drive unit 400 via a voltage-stabilizing capacitor C1, and the compensation unit 500 is also connected to the second terminal of the drive unit 400 via a voltage-stabilizing capacitor C1. The first terminal of the voltage-stabilizing capacitor C1 can be connected to the second terminal of the drive unit 400. The storage control unit 300 can be connected between the second terminal of the voltage-stabilizing capacitor C1 and the storage unit 200. The compensation unit 500 can be connected between the second terminal of the voltage-stabilizing capacitor C1 and the third terminal of the drive unit 400. The initialization unit 800 is connected to the second terminal of the voltage-stabilizing capacitor C1.

[0101] In another circuit connection method, the voltage regulator capacitor C1 can be connected between the second terminal of the driving unit 400 and the storage control unit 300. The first terminal of the voltage regulator capacitor C1 can be connected to the second terminal of the driving unit 400, the compensation unit 500, and the initialization unit 800 respectively, and the storage control unit 300 can be connected between the second terminal of the voltage regulator capacitor C1 and the storage unit 200.

[0102] In another circuit connection method, the voltage regulator capacitor C1 can be connected between the second terminal of the driving unit 400 and the initialization unit 800. The first terminal of the voltage regulator capacitor C1 can be connected to the second terminal of the driving unit 400, the compensation unit 500, and the storage control unit 300, respectively, and the second terminal of the voltage regulator capacitor C1 can be connected to the initialization unit 800.

[0103] Figures 9 to 11 The diagram illustrates three different circuit connection methods for the voltage regulator capacitor C1 in the pixel circuit, taking into account factors such as... Figure 5 In the pixel circuit shown, the potential at point H is maintained by parasitic capacitance, which may lead to leakage current, causing the potential at the second electrode of the first transistor M1 to become uncontrolled. Therefore, in this embodiment, by placing a voltage-stabilizing capacitor C1 near point H, the potential at point H can be stabilized using the voltage-stabilizing capacitor C1, preventing leakage current from affecting the potential at the second electrode of the first transistor M1, thereby further solving the ghosting problem of the product and optimizing the display effect.

[0104] exist Figure 9 In one of the circuit connection methods of the voltage regulator capacitor C1 shown, the first terminal of the voltage regulator capacitor C1 can be connected to the second terminal of the first transistor M1, and the second terminal of the voltage regulator capacitor C1 can be connected to the first terminal of the third transistor M3, the first terminal of the fourth transistor M4 and the first terminal of the seventh transistor M7 respectively.

[0105] exist Figure 10In another circuit connection method of the voltage regulator capacitor C1 shown, the first terminal of the voltage regulator capacitor C1 can be connected to the second terminal of the first transistor M1, the first terminal of the third transistor M3 and the first terminal of the seventh transistor M7 respectively, and the second terminal of the voltage regulator capacitor C1 can be connected to the first terminal of the fourth transistor M4.

[0106] exist Figure 11 In another circuit connection method of the voltage regulator capacitor C1 shown, the first terminal of the voltage regulator capacitor C1 can be connected to the second terminal of the first transistor M1, the first terminal of the third transistor M3 and the first terminal of the fourth transistor M4 respectively, and the second terminal of the voltage regulator capacitor C1 can be connected to the first terminal of the seventh transistor M7.

[0107] This invention also provides a display device, which includes the pixel circuit described in any of the above embodiments. The display device may include one or more sets of pixel circuits. The display device may include mobile phones, laptops, tablet computers, wearable devices, etc.

[0108] The present invention also provides a driving method for driving a pixel circuit as described in any of the above embodiments, wherein the pixel circuit may include a charging phase T2 during the operation of a display frame. Figure 12 This is a flowchart illustrating a pixel circuit driving method in one embodiment of the present application. In one embodiment, the driving method may include the following steps S100 to S200.

[0109] Step S100: During the charging phase, the level of the first scan signal is controlled to be on, the level of the second scan signal is controlled to be on, and the level of the third scan signal is controlled to be on.

[0110] During the charging phase, the levels of the first scan signal, the second scan signal, and the third scan signal can be controlled to be on, thereby turning on the second transistor M2, the third transistor M3, and the fourth transistor M4. After the second transistor M2 is turned on according to the first scan signal S1, it can transmit the data signal Vdata to the first terminal of the first transistor M1. After the third transistor M3 is turned on according to the second scan signal S2, it can perform threshold compensation on the first transistor M1, so that the data signal Vdata can be transmitted sequentially through the first transistor M1 and the third transistor M3 to the second terminal of the first transistor M1, resulting in a threshold-compensated data signal. Simultaneously, after the fourth transistor M4 is turned on according to the third scan signal S3, the connection between the storage capacitor Cst and the first transistor M1 is also turned on, thus the storage capacitor Cst can store the threshold-compensated data signal applied at the second terminal of the first transistor M1.

[0111] In practical applications, appropriate voltage levels can be selected as the conduction levels for each transistor based on its type in the pixel circuit. In this embodiment, using... Figure 5 Taking the pixel circuit shown as an example, the driving method of the pixel circuit will be explained. Figure 5 In the circuit, the third transistor M3 is an N-type transistor, so its on-level is high, meaning the on-level of the third scan signal S3 is greater than its off-level. The second transistor M2 and the fourth transistor M4 are P-type transistors, so their on-levels are low. Therefore, during the charging phase T2, the level of the first scan signal S1 can be controlled to be low, the level of the second scan signal S2 can be controlled to be low, and the level of the third scan signal S3 can be controlled to be high.

[0112] Step S200: At the end of the charging phase, control the level of the first scan signal to the cutoff level, control the level of the second scan signal to the cutoff level, and control the level of the third scan signal to the cutoff level; wherein, the on level of the third scan signal is greater than the off level of the third scan signal.

[0113] At the end of charging phase T2, the level of the first scan signal S1 can be controlled to change from an on level to an off level, the level of the second scan signal S2 can be controlled to change from an on level to an off level, and the level of the third scan signal S3 can be controlled to change from an on level to an off level. That is, after the storage capacitor Cst has finished charging, the second transistor M2, the third transistor M3, and the fourth transistor M4 are turned off. In practical applications, appropriate levels can also be selected as the cutoff levels of each transistor according to the type of each transistor in the pixel circuit.

[0114] like Figure 1 As shown, since the on level of the third transistor M3 is greater than the off level, when the third transistor M3 is off, the voltage level applied to the second terminal of the third transistor M3 changes from high level to low level. The coupling capacitance between the third scan line and the storage capacitor Cst will affect the potential of the storage capacitor Cst, thereby affecting the normal operation of the pixel circuit.

[0115] In the pixel circuit provided in this disclosure, by controlling the fourth transistor M4 to turn off when the storage capacitor Cst finishes charging, the connection point between the storage capacitor Cst and the coupling capacitor C0 is disconnected, thus preventing the coupling capacitor from affecting the potential of the storage capacitor Cst when the third scan signal S3 changes from high to low. Simultaneously, when the fourth transistor M4 is turned off, the connection between the storage capacitor Cst and the third transistor M3 is also broken, thereby reducing the impact of leakage current in the third transistor M3 on the potential of the storage capacitor Cst.

[0116] Figure 13 This is a flowchart illustrating a driving method for a pixel circuit in another embodiment of this application. In one embodiment, during the operation of a display frame, the pixel circuit may further include an initialization phase T1 before the charging phase T2. Optionally, during the initialization phase, the second scan signal S2 and the fourth scan signal S4 are controlled to be on. Optionally, during the initialization phase, the fifth scan signal S5 is controlled to be on. The driving method may further include step S10.

[0117] Step S10: During the initialization phase, control the second scan signal to be on and control the fourth scan signal to be on.

[0118] In an optional embodiment, the driving method may further include step S11: during the initialization phase, controlling the fifth scan signal to be at the on level.

[0119] In one embodiment, such as Figure 10 As shown, during the operation of a display frame, the pixel circuit may include a light-emitting phase T3 after the charging phase T2 ends. The driving method may also include step S20.

[0120] Step S20: During the light emission stage, the light emission control signal is controlled to be at the on level, and the second scanning signal is controlled to be a pulse signal of a preset frequency.

[0121] Figure 14 This is a timing diagram of the pixel circuit in one embodiment of this application. Figure 14 In this diagram, S1 represents the first scan signal, S2 represents the second scan signal, S3 represents the third scan signal, S4 represents the fourth scan signal, S5 represents the fifth scan signal, EM represents the light emission control signal, and Vdata represents the data signal. In this embodiment, [the diagram is used]. Figure 5 Taking the pixel circuit shown as an example, combined with Figure 14 The timing diagram shown provides a detailed description of the operation of the pixel circuit within a display frame.

[0122] Figure 5 In this configuration, the third transistor M3 and the seventh transistor M7 are N-type transistors. Therefore, the on-level of the third transistor M3 and the seventh transistor M7 is high, and the off-level of the third transistor M3 and the seventh transistor M7 is low. The remaining transistors are all P-type transistors, and their on-level is low, while their off-level is high.

[0123] During the initialization phase T1, the second scan signal S2 can be controlled to be at an on level (e.g., low level), the fourth scan signal S4 can be controlled to be at an on level (e.g., high level), and the fifth scan signal S5 can be controlled to be at an on level (e.g., low level). The first scan signal S1 can also be controlled to be at an off level (e.g., high level), the third scan signal S3 can be controlled to be at an off level (e.g., low level), and the light emission control signal EM can be controlled to be at an off level (e.g., high level). That is, during the initialization phase T1, the fourth transistor M4, the seventh transistor M7, and the eighth transistor M8 are turned on, while the remaining transistors are turned off.

[0124] Therefore, during the initialization phase T1, the pixel circuit can charge the storage capacitor Cst with the first voltage signal Vref1 sequentially through the seventh transistor M7 and the fourth transistor M4. Simultaneously, since the fourth transistor M4 is turned on, the storage capacitor Cst is connected to the second terminal of the first transistor M1. This allows the first voltage signal Vref1, which charges the storage capacitor Cst, to provide a negative initial voltage to the second terminal of the first transistor M1, thus initializing the first transistor M1 and facilitating the subsequent charging of the storage capacitor Cst with the data signal Vdata through the first transistor M1.

[0125] Simultaneously, the eighth transistor M8 can transmit the second voltage signal Vref2 to the anode of LED D1, applying a negative voltage to the anode of LED D1 using the second voltage signal Vref2 to reset the anode of LED D1. During the initialization phase T1, by turning on the fourth transistor M4, the seventh transistor M7, and the eighth transistor M8, the first transistor M1 is initialized using the first voltage signal Vref1, and LED D1 is reset using the second voltage signal Vref2. This prevents residual electrical signals from the previous display frame's illumination phase from affecting the current illumination phase.

[0126] At the end of the initialization phase T1, the second scan signal S2 can be controlled to change from the on level to the off level (e.g., from low level to high level), the fourth scan signal S4 can be controlled to change from the on level to the off level (e.g., from high level to low level), and the fifth scan signal S5 can be controlled to change from the on level to the off level (e.g., from low level to high level) so that the fourth transistor M4, the seventh transistor M7, and the eighth transistor M8 are turned off.

[0127] During the charging phase T2, the levels of the first scan signal S1, the second scan signal S2, the third scan signal S3, the fourth scan signal S4, and the fifth scan signal S5 can be controlled to be on (e.g., low), and the light emission control signal EM can be controlled to be off (e.g., high). At this time, the second transistor M2, the fourth transistor M4, and the third transistor M3 are on, while the remaining transistors are off. Thus, during the charging phase T2, the third transistor M3 performs threshold compensation on the first transistor M1, and the second transistor M2 can transmit the data signal Vdata sequentially through the first transistor M1 and the third transistor M3 to the second terminal of the first transistor M1. Simultaneously, since the fourth transistor M4 is on, the connection between the storage capacitor Cst and the second terminal of the first transistor M1 is established, allowing the storage capacitor Cst to store the threshold-compensated data signal Vdata+Vth applied at the second terminal of the first transistor M1.

[0128] At the end of charging phase T2, the level of the first scan signal S1 can be controlled to change from an on level to an off level (e.g., from low level to high level), the level of the second scan signal S2 can be controlled to change from an on level to an off level (e.g., from low level to high level), and the level of the third scan signal S3 can be controlled to change from an on level to an off level (e.g., from high level to low level). That is, after the storage capacitor Cst has finished charging, the second transistor M2, the third transistor M3, and the fourth transistor M4 are turned off. By turning off the fourth transistor M4 when the storage capacitor Cst finishes charging, the connection point between the storage capacitor Cst and the coupling capacitor C0 is disconnected, solving the problem of the coupling capacitor C0 between the storage capacitor Cst and the third signal line lowering the potential of the storage capacitor Cst.

[0129] During the light-emitting phase T3, the level of the first scan signal S1 can be controlled to remain at the cutoff level (e.g., high level), the level of the third scan signal S3 can be controlled to remain at the cutoff level (e.g., low level), the level of the fourth scan signal S4 can be controlled to remain at the cutoff level (e.g., low level), and the level of the fifth scan signal S5 can be controlled to remain at the cutoff level (e.g., high level). That is, during the light-emitting phase T3, the second transistor M2, the third transistor M3, the seventh transistor M7, and the eighth transistor M8 are all kept off. The second scan signal S2 is controlled to be on during a portion of the light-emitting phase, so that the fourth transistor M4 is on during a portion of the light-emitting phase. At the same time, the level of the light-emitting control signal EM can be controlled to be on (e.g., low level), so that the fifth transistor M5 and the sixth transistor M6 are on. At this time, the connection between the first power line and the first terminal of the first transistor M1, as well as the connection between the third terminal of the first transistor M1 and the anode of the light-emitting diode D1, are all on. The first voltage VDD provided by the first power line can be transmitted to the first terminal of the first transistor M1 through the fifth transistor M5.

[0130] If the fourth transistor M4 remains on during the light-emitting phase T3, the potential at the second terminal of the storage capacitor Cst may leak from the third transistor M3 and / or the fourth transistor M4, thus affecting the stable control of the first transistor M1 by the storage capacitor Cst. In other words, the potential at point H is maintained by parasitic capacitance, which may lead to leakage, causing the potential at the second terminal of the first transistor M1 to become uncontrolled.

[0131] In this embodiment, the stabilization of the potential at point H can be achieved by controlling the second scan signal S2 to be a pulse signal with a preset frequency (i.e., alternating between on and off levels, with multiple pulses). The voltage at the second terminal of the fourth transistor M4 will periodically change synchronously according to the pulse signal of the second scan signal S2, thereby extending the leakage path at point H and maintaining the potential at point H at a high level. This enables stable control of the first transistor M1 by the storage capacitor Cst, further resolving the ghosting problem and improving the display effect.

[0132] Optional, please see Figures 9 to 11 If the pixel circuit can also include a voltage regulator unit 201, then during the light-emitting stage T3, the second scanning signal is controlled to be a long-term continuous on-level (which can reduce leakage current compared to the scheme without a voltage regulator unit 201), or a pulse signal of a preset frequency (which can reduce the frequency of the pulse signal and achieve the same display effect compared to the scheme without a voltage regulator unit 201).

[0133] like Figure 14 As shown, during the light-emitting stage, T3 can set a pulse signal of a corresponding frequency as the second scanning signal S2 according to the different actual application requirements of the pixel circuit. Figure 12 This illustrates one timing configuration of the second scan signal S2. In some embodiments, the pulse frequency of the second scan signal S2 can be determined based on parameters such as the display panel resolution, response speed, effective display lines, and transistor response speed. When the pixel circuit uses the voltage regulator capacitor C1 to stabilize the voltage at point H, the pulse frequency of the second scan signal S2 can be appropriately reduced to decrease power consumption.

[0134] The pixel circuit provided in this embodiment utilizes the aforementioned driving method to provide a driving signal for driving the light-emitting unit 10 to emit light, effectively improving the ghosting phenomenon when the pixel circuit is applied to a display device. By providing a fourth transistor M4, the fourth transistor M4 can be turned off by the second scan signal S2 when the storage capacitor Cst finishes charging and when the level of the third scan signal S3 changes, thereby disconnecting the connection point between the storage capacitor Cst and the coupling capacitor C0. This solves the problem that the coupling capacitor C0 between the storage capacitor Cst and the third scan line is affected by the voltage change of the third scan signal S3, thus affecting the potential of the storage capacitor Cst. At the same time, when the fourth transistor M4 is turned off, the connection between the storage capacitor Cst and the third transistor M3 is also broken. Therefore, the influence of leakage current of the third transistor M3 on the potential of the storage capacitor Cst can also be solved, thereby optimizing the ghosting effect when the pixel circuit is applied to a display device.

[0135] It should be understood that although the steps in the flowcharts of the accompanying drawings are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some of the steps in the flowcharts of the accompanying drawings may include multiple steps or stages, which are not necessarily completed at the same time, but may be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0136] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0137] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification. The above embodiments only illustrate several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A pixel circuit, characterized in that, It includes a data writing unit, a storage unit, a storage control unit, a driving unit, a compensation unit, and a light-emitting unit. The data writing unit is connected to the first end of the driving unit, and the data writing unit is configured to write a data signal to the first end of the driving unit according to the first scan signal; The compensation unit is connected between the second end and the third end of the driving unit, and the compensation unit is configured to perform threshold compensation on the driving unit according to the third scan signal; The storage control unit is connected between the second end of the drive unit and the storage unit, and the storage control unit is configured to turn on or off the connection between the second end of the drive unit and the storage unit according to the second scan signal. The storage unit is used to store the voltage at the second terminal of the driving unit; The third terminal of the driving unit is connected to the light-emitting unit, and the driving unit is configured to generate a driving signal based on the voltage of the second terminal of the driving unit to drive the light-emitting unit to emit light. The pixel circuit further includes a voltage regulator unit, the storage control unit is connected to the second terminal of the driving unit via the voltage regulator unit, and the compensation unit is connected to the second terminal of the driving unit via the voltage regulator unit; Alternatively, the voltage regulator unit is connected between the second end of the drive unit and the storage control unit; The voltage regulator unit is used to stabilize the voltage at the second terminal of the drive unit, and the voltage regulator unit includes a voltage regulator capacitor.

2. The pixel circuit according to claim 1, characterized in that, The driving unit includes a first transistor, the first electrode of the first transistor serving as the first terminal of the driving unit, the second electrode of the first transistor serving as the second terminal of the driving unit, and the third electrode of the first transistor serving as the third terminal of the driving unit.

3. The pixel circuit according to claim 1, characterized in that, The data writing unit includes a second transistor, the first terminal of the second transistor is connected to the first terminal of the driving unit, the second terminal of the second transistor is connected to the first scan line, and the third terminal of the second transistor is connected to the data line.

4. The pixel circuit according to claim 1, characterized in that, The compensation unit includes a third transistor, the first terminal of which is connected to the second terminal of the driving unit, the third terminal of which is connected to the third terminal of the driving unit, and the second terminal of which is connected to the third scan line.

5. The pixel circuit according to claim 1, characterized in that, The storage unit includes a storage capacitor, a first end of which is connected to a first power line, and a second end of which is connected to the storage control unit.

6. The pixel circuit according to claim 1, characterized in that, The storage control unit includes a fourth transistor, the first terminal of which is connected to the second terminal of the driving unit, the second terminal of which is connected to the second scan line, and the third terminal of which is connected to the storage unit.

7. The pixel circuit according to claim 4, characterized in that, The third transistor is an N-type transistor.

8. The pixel circuit according to claim 1, characterized in that, The pixel circuit further includes a first light-emitting control unit and / or a second light-emitting control unit. The first light-emitting control unit is connected between the first power line and the first end of the driving unit. The first light-emitting control unit is configured to turn on or off the connection between the first power line and the first end of the driving unit according to the light-emitting control signal. The second light-emitting control unit is connected between the third terminal of the driving unit and the light-emitting unit. The second light-emitting control unit is configured to turn on or off the connection between the third terminal of the driving unit and the light-emitting unit according to the light-emitting control signal.

9. The pixel circuit according to claim 8, characterized in that, The first light-emitting control unit includes a fifth transistor, the first terminal of which is connected to the first terminal of the driving unit, the second terminal of which is connected to a control signal line, and the third terminal of which is connected to the first power supply line. And / or, the second light-emitting control unit includes a sixth transistor, the first terminal of the sixth transistor being connected to the third terminal of the driving unit, the second terminal of the sixth transistor being connected to the control signal line, and the third terminal of the sixth transistor being connected to the light-emitting unit.

10. The pixel circuit according to claim 1, characterized in that, The pixel circuit also includes an initialization unit and / or a reset unit. The initialization unit is connected to the second terminal of the driving unit, and the initialization unit is configured to transmit a first voltage signal to the second terminal of the driving unit according to the fourth scan signal in order to initialize the driving unit; The reset unit is connected to the light-emitting unit, and the reset unit is configured to transmit a second voltage signal to the light-emitting unit according to the fifth scan signal in order to reset the light-emitting unit.

11. The pixel circuit according to claim 10, characterized in that, The initialization unit includes a seventh transistor. The first terminal of the seventh transistor is connected to the second terminal of the driving unit, the second terminal of the seventh transistor is connected to the fourth scan line, and the third terminal of the seventh transistor is connected to the initialization signal line. And / or, the reset unit includes an eighth transistor, the first terminal of which is connected to the light-emitting unit, the second terminal of which is connected to the fifth scan line, and the third terminal of which is connected to the reset signal line.

12. The pixel circuit according to claim 11, characterized in that, The seventh transistor is an N-type transistor.

13. The pixel circuit according to claim 1, characterized in that, The storage unit includes a storage capacitor, the first end of which is connected to a first power line, and the second end of which is connected to the storage control unit; the voltage regulator capacitor and the storage capacitor have the same capacitance value.

14. A display device, characterized in that, Includes the pixel circuit as described in any one of claims 1 to 13.

15. A method for driving a pixel circuit, used to drive the pixel circuit as described in any one of claims 1 to 13, wherein the pixel circuit includes a charging phase during operation of a display frame, characterized in that... The driving method includes: During the charging phase, the level of the first scan signal is controlled to be on, the level of the second scan signal is controlled to be on, and the level of the third scan signal is controlled to be on. At the end of the charging phase, the level of the first scan signal is controlled to be at the cutoff level, the level of the second scan signal is controlled to be at the cutoff level, and the level of the third scan signal is controlled to be at the cutoff level; wherein, the on level of the third scan signal is greater than the off level of the third scan signal.

16. The driving method according to claim 15, characterized in that, The pixel circuit further includes an initialization phase before the charging phase, and the driving method includes: During the initialization phase, the second scan signal is controlled to be at the on level, and the fourth scan signal is controlled to be at the on level.

17. The driving method according to claim 16, characterized in that, During the initialization phase, the fifth scan signal is controlled to be at the on level.

18. The driving method according to claim 15, characterized in that, The pixel circuit further includes a light-emitting phase after the charging phase ends, and the driving method includes: During the light-emitting stage, the light-emitting control signal is controlled to be at the on level, and the second scanning signal is controlled to be a pulse signal of a preset frequency.

19. A pixel circuit, characterized in that, It includes a data writing unit, a storage unit, a storage control unit, a driving unit, a compensation unit, and a light-emitting unit. The data writing unit is connected to the first end of the driving unit, and the data writing unit is configured to write a data signal to the first end of the driving unit according to the first scan signal; The compensation unit is connected between the second end and the third end of the driving unit, and the compensation unit is configured to perform threshold compensation on the driving unit according to the third scan signal; The storage control unit is connected between the second end of the drive unit and the storage unit, and the storage control unit is configured to turn on or off the connection between the second end of the drive unit and the storage unit according to the second scan signal. The storage unit is used to store the voltage at the second terminal of the driving unit; The third terminal of the driving unit is connected to the light-emitting unit, and the driving unit is configured to generate a driving signal based on the voltage of the second terminal of the driving unit to drive the light-emitting unit to emit light. The pixel circuit includes a charging phase during the operation of a display frame. During the charging phase, the level of the first scan signal is controlled to be on, the level of the second scan signal is controlled to be on, and the level of the third scan signal is controlled to be on. At the end of the charging phase, the level of the first scan signal is controlled to be at the cutoff level, the level of the second scan signal is controlled to be at the cutoff level, and the level of the third scan signal is controlled to be at the cutoff level; wherein, the on level of the third scan signal is greater than the off level of the third scan signal.

20. The pixel circuit according to claim 19, characterized in that, The driving unit includes a first transistor, the first electrode of the first transistor serving as the first terminal of the driving unit, the second electrode of the first transistor serving as the second terminal of the driving unit, and the third electrode of the first transistor serving as the third terminal of the driving unit.

21. The pixel circuit according to claim 19, characterized in that, The data writing unit includes a second transistor, the first terminal of the second transistor is connected to the first terminal of the driving unit, the second terminal of the second transistor is connected to the first scan line, and the third terminal of the second transistor is connected to the data line.

22. The pixel circuit according to claim 19, characterized in that, The compensation unit includes a third transistor, the first terminal of which is connected to the second terminal of the driving unit, the third terminal of which is connected to the third terminal of the driving unit, and the second terminal of which is connected to the third scan line.

23. The pixel circuit according to claim 19, characterized in that, The storage unit includes a storage capacitor, a first end of which is connected to a first power line, and a second end of which is connected to the storage control unit.

24. The pixel circuit according to claim 19, characterized in that, The storage control unit includes a fourth transistor, the first terminal of which is connected to the second terminal of the driving unit, the second terminal of which is connected to the second scan line, and the third terminal of which is connected to the storage unit.

25. The pixel circuit according to claim 22, characterized in that, The third transistor is an N-type transistor.

26. The pixel circuit according to claim 19, characterized in that, The pixel circuit further includes a first light-emitting control unit and / or a second light-emitting control unit. The first light-emitting control unit is connected between the first power line and the first end of the driving unit. The first light-emitting control unit is configured to turn on or off the connection between the first power line and the first end of the driving unit according to the light-emitting control signal. The second light-emitting control unit is connected between the third terminal of the driving unit and the light-emitting unit. The second light-emitting control unit is configured to turn on or off the connection between the third terminal of the driving unit and the light-emitting unit according to the light-emitting control signal.

27. The pixel circuit according to claim 26, characterized in that, The first light-emitting control unit includes a fifth transistor, the first terminal of which is connected to the first terminal of the driving unit, the second terminal of which is connected to a control signal line, and the third terminal of which is connected to the first power supply line. And / or, the second light-emitting control unit includes a sixth transistor, the first terminal of the sixth transistor being connected to the third terminal of the driving unit, the second terminal of the sixth transistor being connected to the control signal line, and the third terminal of the sixth transistor being connected to the light-emitting unit.

28. The pixel circuit according to claim 19, characterized in that, The pixel circuit also includes an initialization unit and / or a reset unit. The initialization unit is connected to the second terminal of the driving unit, and the initialization unit is configured to transmit a first voltage signal to the second terminal of the driving unit according to the fourth scan signal in order to initialize the driving unit; The reset unit is connected to the light-emitting unit, and the reset unit is configured to transmit a second voltage signal to the light-emitting unit according to the fifth scan signal in order to reset the light-emitting unit.

29. The pixel circuit according to claim 28, characterized in that, The initialization unit includes a seventh transistor. The first terminal of the seventh transistor is connected to the second terminal of the driving unit, the second terminal of the seventh transistor is connected to the fourth scan line, and the third terminal of the seventh transistor is connected to the initialization signal line. And / or, the reset unit includes an eighth transistor, the first terminal of which is connected to the light-emitting unit, the second terminal of which is connected to the fifth scan line, and the third terminal of which is connected to the reset signal line.

30. The pixel circuit according to claim 29, characterized in that, The seventh transistor is an N-type transistor.

31. The pixel circuit according to claim 19, characterized in that, The pixel circuit further includes a voltage regulator unit and an initialization unit. The voltage regulator unit is connected between the second terminal of the driving unit and the initialization unit. The initialization unit is configured to transmit a first voltage signal to the second terminal of the driving unit according to the fourth scan signal to initialize the driving unit. The voltage regulator unit is used to stabilize the voltage at the second terminal of the drive unit.

32. The pixel circuit according to claim 31, characterized in that, The voltage regulator unit includes a voltage regulator capacitor.

33. The pixel circuit according to claim 32, characterized in that, The storage unit includes a storage capacitor, the first end of which is connected to a first power line, and the second end of which is connected to the storage control unit; the voltage regulator capacitor and the storage capacitor have the same capacitance value.

34. The pixel circuit according to claim 28 or 31, characterized in that, The pixel circuit also includes an initialization phase before the charging phase. During the initialization phase, the second scan signal is controlled to be at the on level, and the fourth scan signal is controlled to be at the on level.

35. The pixel circuit according to claim 28, characterized in that, The pixel circuit also includes an initialization phase before the charging phase. During the initialization phase, the fifth scan signal is controlled to be at the on level.

36. The pixel circuit according to claim 26, characterized in that, The pixel circuit also includes a light-emitting phase after the charging phase is completed. During the light emission stage, the light emission control signal is controlled to be at the on level, and the second scanning signal is controlled to be a pulse signal of a preset frequency.

37. The pixel circuit according to claim 19, characterized in that, The pixel circuit further includes a voltage regulator unit, the storage control unit is connected to the second terminal of the driving unit via the voltage regulator unit, and the compensation unit is connected to the second terminal of the driving unit via the voltage regulator unit; Alternatively, the voltage regulator unit is connected between the second end of the drive unit and the storage control unit; The voltage regulator unit is used to stabilize the voltage at the second terminal of the drive unit.

38. A display device, characterized in that, Includes the pixel circuitry as described in any one of claims 19 to 37.

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