A quantum bit electrode and a method of designing the same, a quantum bit device
By optimizing the epitaxial structure and electrode design of silicon-based qubits, the stress fluctuation problem caused by thermal shrinkage effect of silicon-based qubits was solved, thereby improving the stability and scalability of qubit devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HEFEI NATIONAL LABORATORY
- Filing Date
- 2023-08-02
- Publication Date
- 2026-06-26
AI Technical Summary
Stress fluctuations caused by the thermal shrinkage effect of materials during electrode fabrication of silicon-based qubits at low temperatures affect the stability and scalability of the qubits.
By epitaxially growing silicon-based qubit epitaxial structures, determining the strain distribution, designing the maximum electrode length to be lower than the stress accumulation wavelength, optimizing the electrode shape and growth region, avoiding stress accumulation locations, and using AFM technology for characterization and etching, stable qubit electrodes are fabricated.
It improves the stress conditions of qubit devices, reduces temperature-induced strain fluctuations, and provides a more stable qubit device unit array, laying the foundation for large-scale qubit expansion.
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Figure CN116936614B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor device technology, and more specifically, to a quantum bit electrode and its design method, and a quantum bit device. Background Technology
[0002] Silicon-based qubits, due to their compatibility with CMOS technology and their scalability, have become a major research direction for qubits today.
[0003] The fabrication of electrodes for silicon-based qubits has a significant impact on their transmission performance. Due to the low-temperature operation required for qubits, different electrode materials exhibit thermal contraction with temperature, resulting in temperature-dependent material stress fluctuations. Furthermore, the direct contact between the qubit manipulation electrodes and the underlying silicon material inevitably generates stress, which can have a severe negative impact on the qubit.
[0004] As the qubit array is gradually expanded, the cumulative effect of strain will seriously affect the stability of the qubit expansion. Summary of the Invention
[0005] In view of this, to solve the above problems, the present invention provides a quantum bit electrode and its design method, and a quantum bit device, the technical solution of which is as follows:
[0006] A method for designing qubit electrodes, the method comprising:
[0007] Epitaxial growth of silicon-based quantum bit epitaxial structures, wherein the silicon-based quantum bit epitaxial structures have quantum well structures;
[0008] Determine the strain distribution state of each region on the surface of the silicon-based quantum bit epitaxial structure;
[0009] Select a silicon-based quantum bit epitaxial structure sample, wherein the silicon-based quantum bit epitaxial structure sample is identical to the silicon-based quantum bit epitaxial structure;
[0010] The silicon-based quantum bit epitaxial structure sample is processed to determine the maximum length of the quantum bit electrode in the working region. The maximum length of the electrode is lower than the stress accumulation wavelength of the silicon-based quantum bit epitaxial structure sample.
[0011] Based on the processing results of the silicon-based quantum bit epitaxial structure sample and the strain type of the quantum well structure, the target electrode growth region is determined in each region on the surface of the silicon-based quantum bit epitaxial structure.
[0012] The electrode shape of the qubit electrode is designed based on the target electrode growth region and the maximum length of the electrode.
[0013] Preferably, in the above-described design method for quantum bit electrodes, the epitaxial growth of the silicon-based quantum bit epitaxial structure includes:
[0014] Epitaxial growth of silicon-based quantum bit epitaxial structures with single quantum well structures;
[0015] or,
[0016] Epitaxial growth of silicon-based quantum bit epitaxial structures with double quantum wells;
[0017] or,
[0018] Epitaxial growth of silicon-based quantum bit epitaxial structures with multiple quantum wells.
[0019] Preferably, in the above-described design method for qubit electrodes, determining the strain distribution state of each region on the surface of the silicon-based qubit epitaxial structure includes:
[0020] The surface of the silicon-based quantum bit epitaxial structure is processed by electron beam lithography and dry etching to divide it into multiple regions, and each region is marked with a location.
[0021] The strain distribution state of each region on the surface of the silicon-based quantum bit epitaxial structure was determined based on AFM technology.
[0022] Preferably, in the above-described design method for qubit electrodes, determining the strain distribution state of each region on the surface of the silicon-based qubit epitaxial structure further includes:
[0023] Each region is magnified and scanned to determine the distribution of grooves and ridges on the surface of the silicon-based quantum bit epitaxial structure.
[0024] Preferably, in the above-described design method for qubit electrodes, the step of processing the silicon-based qubit epitaxial structure sample to determine the maximum electrode length of the qubit electrode in the working region, wherein the maximum electrode length is lower than the stress accumulation wavelength of the silicon-based qubit epitaxial structure sample, includes:
[0025] The surface of the silicon-based quantum bit epitaxial structure sample is etched down to the location of the quantum well structure.
[0026] The fluctuation frequency of stress accumulation in the silicon-based quantum bit epitaxial structure sample is determined based on AFM technology, and the maximum electrode length of the quantum bit electrode in the working region is determined based on the fluctuation frequency. The maximum electrode length is lower than the stress accumulation wavelength of the silicon-based quantum bit epitaxial structure sample.
[0027] Preferably, in the above-mentioned design method for qubit electrodes, the step of determining the stress accumulation fluctuation frequency of the silicon-based qubit epitaxial structure sample based on AFM technology, and determining the maximum electrode length of the qubit electrode in the working region based on the fluctuation frequency, wherein the maximum electrode length is lower than the stress accumulation wavelength of the silicon-based qubit epitaxial structure sample, includes:
[0028] The overall RMS roughness of silicon-based quantum bit epitaxial structure samples after etching was obtained by AFM characterization based on AFM technology.
[0029] Multiple one-dimensional morphological features were extracted from the surface of the silicon-based quantum bit epitaxial structure sample using AFM analysis software.
[0030] Peak counting is performed on the one-dimensional morphology, wherein the minimum peak fluctuation is not lower than the overall RMS roughness;
[0031] Calculate the average peak spacing, which is the stress accumulation wavelength of the silicon-based quantum bit epitaxial structure sample;
[0032] Based on the stress accumulation wavelength of the silicon-based quantum bit epitaxial structure sample, the maximum electrode length of the quantum bit electrode in the working region is determined.
[0033] Preferably, in the above-described method for designing qubit electrodes, determining the target electrode growth region in each region on the surface of the silicon-based qubit epitaxial structure based on the processing results of the silicon-based qubit epitaxial structure sample and the strain type of the quantum well structure includes:
[0034] Exclude regions with a roughness higher than the overall RMS roughness;
[0035] Determine the strain type of the quantum well structure;
[0036] When the strain type is compressive strain, the target ridge position is determined as the target electrode growth region in other regions on the surface of the silicon-based quantum bit epitaxial structure.
[0037] When the strain type is tensile strain, the target groove location is determined as the target electrode growth region in other regions on the surface of the silicon-based quantum bit epitaxial structure.
[0038] Preferably, in the above-described design method for qubit electrodes, after the step of determining the strain distribution state of each region on the surface of the silicon-based qubit epitaxial structure, the design method further includes:
[0039] Epitaxial growth of the corresponding working steps and gate oxide structure.
[0040] This application also provides a qubit electrode, which is designed based on the design method described in any of the preceding claims.
[0041] This application also provides a quantum bit device, which includes the quantum bit electrodes described above.
[0042] Compared with the prior art, the beneficial effects achieved by the present invention are as follows:
[0043] The present invention provides a method for designing a qubit electrode, comprising: epitaxially growing a silicon-based qubit epitaxial structure, wherein the silicon-based qubit epitaxial structure has a quantum well structure; determining the strain distribution state of each region on the surface of the silicon-based qubit epitaxial structure; selecting a silicon-based qubit epitaxial structure sample, wherein the silicon-based qubit epitaxial structure sample is identical to the silicon-based qubit epitaxial structure; processing the silicon-based qubit epitaxial structure sample to determine the maximum electrode length of the qubit electrode in the working region, wherein the maximum electrode length is lower than the stress accumulation wavelength of the silicon-based qubit epitaxial structure sample; based on the processing result of the silicon-based qubit epitaxial structure sample and the strain type of the quantum well structure, determining the target electrode growth region in each region on the surface of the silicon-based qubit epitaxial structure; and designing the electrode shape of the qubit electrode based on the target electrode growth region and the maximum electrode length. This method for designing qubit electrodes involves growing silicon-based qubit epitaxial structures using epitaxial technology and performing comprehensive morphological characterization of the surface. It designs a qubit electrode structure and shape optimized for different materials, and further improves the overall stress condition of the qubit device by adjusting the shape and distribution of the qubit electrodes. This improves the temperature-dependent strain fluctuations of the qubit device, ultimately resulting in a novel qubit electrode structure. The optimized qubit electrode structure is then used to fabricate silicon-based qubit devices, providing a more stable qubit device unit array for large-scale qubit expansion. This microscopic improvement in stress fluctuations of qubit devices has significant implications for qubit manipulation. Attached Figure Description
[0044] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0045] Figure 1 A flowchart illustrating a design method for a quantum bit electrode provided in an embodiment of the present invention;
[0046] Figure 2A flowchart illustrating another design method for a quantum bit electrode provided in an embodiment of the present invention;
[0047] Figure 3 This is a schematic diagram illustrating the surface positioning marking of a silicon-based quantum bit epitaxial structure, provided as an embodiment of the present invention.
[0048] Figure 4 A flowchart illustrating another design method for a quantum bit electrode provided in an embodiment of the present invention;
[0049] Figure 5 A flowchart illustrating another design method for a quantum bit electrode provided in an embodiment of the present invention;
[0050] Figure 6 A schematic diagram illustrating the determination of stress accumulation wavelength provided in an embodiment of the present invention;
[0051] Figure 7 A schematic diagram of a process for determining the wavelength of stress accumulation is provided in an embodiment of the present invention;
[0052] Figure 8 This is a schematic diagram of the growth position of a quantum bit electrode provided in an embodiment of the present invention. Detailed Implementation
[0053] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0054] Based on the background art, silicon-based materials, due to the stress introduced during their growth, will form uniformly distributed cross-hatch patterns, also known as cross shadows, on their surface. Further accumulation of these cross-hatch patterns will produce deeper grooves and ridges. These deeper grooves and ridges have greater stress fluctuations, which will have a severe negative impact on qubits. As the qubit array gradually expands, the cumulative effect of strain will seriously affect the stability of the qubit expansion.
[0055] Based on this, embodiments of this application provide a qubit electrode and its design method, as well as a qubit device. Silicon-based single / double / multiple quantum well qubit epitaxial structures are grown using epitaxial technology, and the surface morphology is comprehensively characterized. A qubit electrode structure and shape optimized for different materials are designed, and the overall stress condition of the qubit device is further improved by adjusting the shape and distribution of the qubit electrode, thus mitigating temperature-induced strain fluctuations. Ultimately, a novel qubit electrode structure is obtained, and silicon-based qubit devices are fabricated using this optimized qubit electrode structure. This provides a more stable qubit device unit array for large-scale qubit expansion, i.e., improving the stress fluctuations of the qubit device at the microscopic level, which has significant implications for qubit manipulation.
[0056] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0057] refer to Figure 1 , Figure 1 This is a flowchart illustrating a design method for a quantum bit electrode according to an embodiment of the present invention. The design method for a quantum bit electrode according to an embodiment of the present invention includes:
[0058] S101: Epitaxial growth of silicon-based quantum bit epitaxial structure, wherein the silicon-based quantum bit epitaxial structure has a quantum well structure.
[0059] Specifically, the epitaxial growth of silicon-based quantum bit epitaxial structures in this step includes: epitaxial growth of silicon-based quantum bit epitaxial structures with single quantum wells; or, epitaxial growth of silicon-based quantum bit epitaxial structures with double quantum wells; or, epitaxial growth of silicon-based quantum bit epitaxial structures with multiple quantum wells.
[0060] In other words, the quantum well structure of the silicon-based quantum bit epitaxial structure in this embodiment of the invention can be a single quantum well structure, a double quantum well structure, or a multi-quantum well structure.
[0061] Optionally, silicon-based single / double / multiple quantum well structures, including Si MOS (Si Metal Oxide Semiconductor), bulk two-dimensional electron gas, and bulk two-dimensional hole gas, can be epitaxially grown on a CMOS (Complementary Metal Oxide Semiconductor) production line using techniques such as RPCVD (Reduced Pressure Chemical Vapor Deposition).
[0062] S102: Determine the strain distribution state of each region on the surface of the silicon-based quantum bit epitaxial structure.
[0063] Specifically, in this step, refer to Figure 2 , Figure 2 This is a flowchart illustrating another design method for a quantum bit electrode provided by an embodiment of the present invention. One possible implementation of step S102, "determining the strain distribution state of each region on the surface of the silicon-based quantum bit epitaxial structure," is as follows:
[0064] S1021: The surface of the silicon-based quantum bit epitaxial structure is processed by electron beam lithography and dry etching to divide it into multiple regions, and each region is marked with a location.
[0065] S1022: Determine the strain distribution state of each region on the surface of the silicon-based quantum bit epitaxial structure based on AFM (Atomic Force Microscope) technology.
[0066] S1023: Perform a magnified scan of each region to determine the distribution of grooves and ridges on the surface of the silicon-based quantum bit epitaxial structure.
[0067] In other words, reference Figure 3 , Figure 3 This is a schematic diagram of a silicon-based quantum bit epitaxial structure surface positioning marking provided by an embodiment of the present invention. The surface of the silicon-based quantum bit epitaxial structure is positioned and marked by electron beam lithography and dry etching, and the strain distribution state of the structure surface within a preset scale range is confirmed by AFM scanning, for example, by scanning the structure surface in a large scale range of 50μm-100μm.
[0068] Optionally, in actual operation, different colored positioning marks can represent positioning marks of different shapes for rapid array positioning.
[0069] Furthermore, after the positioning and marking are completed, each region can be magnified and scanned, for example, a 10μm×10μm magnified scan can be performed on each region to determine the distribution of grooves and ridges on the surface of the silicon-based quantum bit epitaxial structure, that is, to accurately determine its cross-hatch surface distribution.
[0070] It should be noted that the reference Figure 4 , Figure 4 This is a flowchart illustrating another design method for a quantum bit electrode provided by an embodiment of the present invention. After step S102, which determines the strain distribution state of each region on the surface of the silicon-based quantum bit epitaxial structure, the design method further includes:
[0071] S107: Epitaxial growth of the corresponding working steps and gate oxide structure.
[0072] S103: Select a silicon-based quantum bit epitaxial structure sample, wherein the silicon-based quantum bit epitaxial structure sample is the same as the silicon-based quantum bit epitaxial structure.
[0073] Specifically, among the silicon-based quantum bit epitaxial structures grown in the same batch, one silicon-based quantum bit epitaxial structure is selected as a silicon-based quantum bit epitaxial structure sample to determine the corresponding stress accumulation wavelength, thereby determining the maximum electrode length of the quantum bit electrode in the working region.
[0074] S104: Process the silicon-based quantum bit epitaxial structure sample to determine the maximum length of the quantum bit electrode in the working region. The maximum length of the electrode is lower than the stress accumulation wavelength of the silicon-based quantum bit epitaxial structure sample.
[0075] In this step, refer to Figure 5 , Figure 5 This is a flowchart illustrating another design method for a quantum bit electrode provided by an embodiment of the present invention. One possible implementation of step S104, "processing the silicon-based quantum bit epitaxial structure sample to determine the maximum electrode length of the quantum bit electrode in the working region, wherein the maximum electrode length is lower than the stress accumulation wavelength of the silicon-based quantum bit epitaxial structure sample," is as follows:
[0076] S1041: The surface of the silicon-based quantum bit epitaxial structure sample is etched down to the location of the quantum well structure.
[0077] S1042: Determine the fluctuation frequency of stress accumulation in the silicon-based quantum bit epitaxial structure sample based on AFM technology, and determine the maximum electrode length of the quantum bit electrode in the working region based on the fluctuation frequency. The maximum electrode length is lower than the stress accumulation wavelength of the silicon-based quantum bit epitaxial structure sample.
[0078] In this embodiment of the invention, a silicon-based quantum bit epitaxial structure sample is selected, and the surface of the silicon-based quantum bit epitaxial structure sample is etched using an etching solution. The etching rate is controlled to the position of the quantum well structure. Then, the etched silicon-based quantum bit epitaxial structure sample is characterized by AFM to confirm the fluctuation frequency of stress accumulation in the silicon-based quantum bit epitaxial structure sample. This ensures that the maximum length of a single quantum bit electrode in the working area is lower than the stress accumulation wavelength.
[0079] For details, please refer to Figure 6 , Figure 6 This is a schematic diagram illustrating the determination of stress accumulation wavelength according to an embodiment of the present invention, with reference to... Figure 7 , Figure 7This is a schematic diagram of a process for determining the wavelength of stress accumulation, provided as an embodiment of the present invention.
[0080] S201: The silicon-based quantum bit epitaxial structure sample after etching was characterized by AFM technology to obtain the overall RMS roughness.
[0081] S202: Based on AFM analysis software, multiple one-dimensional morphological features are extracted from the surface of the silicon-based quantum bit epitaxial structure sample.
[0082] S203: Perform peak counting on the one-dimensional morphology, wherein the minimum peak fluctuation is not lower than the overall RMS roughness.
[0083] S204: Calculate the average peak spacing, which is the stress accumulation wavelength of the silicon-based quantum bit epitaxial structure sample.
[0084] S205: Based on the stress accumulation wavelength of the silicon-based quantum bit epitaxial structure sample, determine the maximum electrode length of the quantum bit electrode in the working region.
[0085] S105: Based on the processing results of the silicon-based quantum bit epitaxial structure sample and the strain type of the quantum well structure, determine the target electrode growth region in each region on the surface of the silicon-based quantum bit epitaxial structure.
[0086] S106: Based on the target electrode growth region and the maximum length of the electrode, design the electrode shape of the qubit electrode.
[0087] Specifically, after determining the maximum length of the electrode, the shape of the surface qubit electrode is designed rationally, and the qubit electrode structure is optimized by using positioning marker overlay / atomic probe growth, so that the qubit is grown on the ridge or groove of the cross-hatch in a flat position, in order to obtain a qubit electrode that can offset the strain fluctuation effect at low temperature.
[0088] First, regions with a roughness higher than the overall RMS roughness are excluded; then, based on the divided regions, the shape of the qubit electrode is designed so that the working area is no larger than the maximum length of the electrode.
[0089] Determine the strain type of the quantum well structure; when the strain type is compressive strain, determine the target ridge position as the target electrode growth region in other regions on the surface of the silicon-based quantum bit epitaxial structure; that is, take the relatively flat ridge position as the target ridge position, and grow the designed quantum bit electrode on the relatively flat ridge position.
[0090] When the strain type is tensile strain, the target trench position is determined as the target electrode growth region in other regions on the surface of the silicon-based quantum bit epitaxial structure; that is, the relatively flat trench position is taken as the target trench position, and the designed quantum bit electrode is grown on the relatively flat trench position.
[0091] refer to Figure 8 , Figure 8 This is a schematic diagram of the growth position of a quantum bit electrode provided in an embodiment of the present invention. The control electrodes of the key working area AA and the quantum dot formation area BB of the quantum bit device are grown in a non-stress-accumulated area, and the width of the quantum dot and bit coupling working area should be less than the maximum length of the electrode.
[0092] It should be noted that, Figure 8 The image shows a compressive strain surface, with the qubit electrodes positioned at relatively flat ridge locations.
[0093] like Figure 8 As shown, taking the surface of a compressive strain sample as an example: the growth material can be Al or other electrode materials. Since its thermal shrinkage coefficient is greater than that of silicon-based quantum well materials, when the temperature drops to the working temperature (about 70mK), the mismatched dislocations on the surface of the compressive strain sample are squeezed at the groove due to thermal changes (arrow 1), while the larger relative shrinkage of the quantum bit electrode is opposite to the strain fluctuation of the surface mismatched dislocations (arrow 2).
[0094] It should be noted that, Figure 8 In the figure, Lm represents the maximum length of the electrode.
[0095] It should be noted that, in the top view of the optimized qubit electrode in the embodiments of the present invention, it can be a rectangle, square, rhombus, circle, etc., and is not limited to one type. In the overall view, it can be a cuboid, cylinder, frustum, cone, etc., and is not limited to one type. The oxide layer structure can be any gate oxide material such as aluminum oxide and hafnium oxide. The material of the qubit electrode can be Al, Ti / Au, or any metal conductor with thermal shrinkage effect, and is not limited to one type of material.
[0096] It should be further noted that the surface strain method on which the quantum bit electrode material is based in the embodiments of the present invention can be the compressive strain or tensile strain of the bulk material as proposed in the above embodiments, or it can be the surface strain fluctuation caused by any kind of strain.
[0097] It should be further noted that the implementation method and fabrication process of the surface strain-optimized qubit electrode in the embodiments of the present invention extend the protection to the fabrication process of various strained qubit electrodes such as strained germanium / silicon / silicon-germanium / gallium arsenide using this substrate structure (including but not limited to silicon, germanium-silicon, germanium-silicon stacked structures, etc.).
[0098] In summary, the design method for qubit electrodes provided in this invention effectively avoids stress accumulation locations caused by surface mismatch dislocation grids, reduces long-range impurity scattering in the quantum well due to surface roughness within the working region (S-QD-D) (i.e., source-quantum dot-drain), and cleverly suppresses strain fluctuations caused by surface mismatch dislocations and the electrode itself by utilizing the temperature-varying thermal contraction effect of the strain-optimized distributed electrode, ensuring the stability of strain band splitting of the qubit and laying the foundation for qubit expansion.
[0099] Optionally, based on the above embodiments of the present invention, another embodiment of the present invention also provides a quantum bit electrode, which is designed based on the design method described in the above embodiments.
[0100] Optionally, based on the above embodiments of the present invention, another embodiment of the present invention also provides a quantum bit device, the quantum bit device including the quantum bit electrodes described in the above embodiments.
[0101] The present invention provides a detailed description of a quantum bit electrode and its design method, as well as a quantum bit device. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.
[0102] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to the method section.
[0103] It should also be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that elements inherent to a process, method, article, or apparatus that comprises a list of elements, or elements inherent to such processes, methods, articles, or apparatus, are also included. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0104] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A method for designing a quantum bit electrode, characterized in that, The design method includes: Epitaxial growth of silicon-based quantum bit epitaxial structures, wherein the silicon-based quantum bit epitaxial structures have quantum well structures; Determine the strain distribution state of each region on the surface of the silicon-based quantum bit epitaxial structure; Select a silicon-based quantum bit epitaxial structure sample, wherein the silicon-based quantum bit epitaxial structure sample is identical to the silicon-based quantum bit epitaxial structure; The silicon-based quantum bit epitaxial structure sample is processed to determine the maximum length of the quantum bit electrode in the working region. The maximum length of the electrode is lower than the stress accumulation wavelength of the silicon-based quantum bit epitaxial structure sample. Based on the processing results of the silicon-based quantum bit epitaxial structure sample and the strain type of the quantum well structure, the target electrode growth region is determined in each region on the surface of the silicon-based quantum bit epitaxial structure. The electrode shape of the qubit electrode is designed based on the target electrode growth region and the maximum length of the electrode.
2. The design method of quantum bit electrodes according to claim 1, characterized in that, The epitaxially grown silicon-based quantum bit epitaxial structure includes: Epitaxial growth of silicon-based quantum bit epitaxial structures with single quantum well structures; or, Epitaxial growth of silicon-based quantum bit epitaxial structures with double quantum wells; or, Epitaxial growth of silicon-based quantum bit epitaxial structures with multiple quantum wells.
3. The design method for quantum bit electrodes according to claim 1, characterized in that, Determining the strain distribution state of each region on the surface of the silicon-based quantum bit epitaxial structure includes: The surface of the silicon-based quantum bit epitaxial structure is processed by electron beam lithography and dry etching to divide it into multiple regions, and each region is marked with a location. The strain distribution state of each region on the surface of the silicon-based quantum bit epitaxial structure was determined based on AFM technology.
4. The design method for quantum bit electrodes according to claim 3, characterized in that, The determination of the strain distribution state in each region on the surface of the silicon-based quantum bit epitaxial structure further includes: Each region is magnified and scanned to determine the distribution of grooves and ridges on the surface of the silicon-based quantum bit epitaxial structure.
5. The design method for a quantum bit electrode according to claim 1, characterized in that, The process of processing the silicon-based quantum bit epitaxial structure sample to determine the maximum electrode length of the quantum bit electrode in the working region, wherein the maximum electrode length is lower than the stress accumulation wavelength of the silicon-based quantum bit epitaxial structure sample, includes: The surface of the silicon-based quantum bit epitaxial structure sample is etched down to the location of the quantum well structure. The fluctuation frequency of stress accumulation in the silicon-based quantum bit epitaxial structure sample is determined based on AFM technology, and the maximum electrode length of the quantum bit electrode in the working region is determined based on the fluctuation frequency. The maximum electrode length is lower than the stress accumulation wavelength of the silicon-based quantum bit epitaxial structure sample.
6. The design method for a quantum bit electrode according to claim 5, characterized in that, The step of determining the stress accumulation fluctuation frequency of the silicon-based quantum bit epitaxial structure sample based on AFM technology, and determining the maximum electrode length of the quantum bit electrode in the working region based on the fluctuation frequency, wherein the maximum electrode length is lower than the stress accumulation wavelength of the silicon-based quantum bit epitaxial structure sample, includes: The overall RMS roughness of silicon-based quantum bit epitaxial structure samples after etching was obtained by AFM characterization based on AFM technology. Multiple one-dimensional morphological features were extracted from the surface of the silicon-based quantum bit epitaxial structure sample using AFM analysis software. Peak counting is performed on the one-dimensional morphology, wherein the minimum peak fluctuation is not lower than the overall RMS roughness; Calculate the average peak spacing, which is the stress accumulation wavelength of the silicon-based quantum bit epitaxial structure sample; Based on the stress accumulation wavelength of the silicon-based quantum bit epitaxial structure sample, the maximum electrode length of the quantum bit electrode in the working region is determined.
7. The design method for a quantum bit electrode according to claim 6, characterized in that, Based on the processing results of the silicon-based quantum bit epitaxial structure sample and the strain type of the quantum well structure, the target electrode growth region is determined in each region on the surface of the silicon-based quantum bit epitaxial structure, including: Exclude regions with a roughness higher than the overall RMS roughness; Determine the strain type of the quantum well structure; When the strain type is compressive strain, the target ridge position is determined as the target electrode growth region in other regions on the surface of the silicon-based quantum bit epitaxial structure. When the strain type is tensile strain, the target groove location is determined as the target electrode growth region in other regions on the surface of the silicon-based quantum bit epitaxial structure.
8. The design method of a quantum bit electrode according to claim 1, characterized in that, Following the step of determining the strain distribution in various regions on the surface of the silicon-based quantum bit epitaxial structure, the design method further includes: Epitaxial growth of the corresponding working steps and gate oxide structure.
9. A quantum bit electrode, characterized in that, The quantum bit electrode is designed based on the design method described in any one of claims 1-8.
10. A quantum bit device, characterized in that, The quantum bit device includes the quantum bit electrode as described in claim 9.