Clock correction method and device of power terminal, power terminal and storage medium

Abstract

The application relates to the technical field of power systems, and provides a clock correction method and device of a power terminal, the power terminal, and a storage medium. The power terminal updates a hard clock in a running process in a time manner and records a current time into a file according to a preset period; when the power terminal is powered on normally after power failure, a current clock of a metering core and a current time of a management core are acquired, and a last start time and a last power-off time are read from the file; in the case that the last power-off time is greater than the last start time, the current clock, the current time and the last power-off time are compared in terms of credibility; in the case that the last power-off time is less than or equal to the last start time, the current clock and the current time are compared in terms of credibility, and the one with the maximum credibility is taken as a system time for time correction. Therefore, the clock correction of the power terminal can be realized without using external equipment, and the consistency, synchronism and accuracy of the clock in the power terminal are realized.

Description

Technical Field

[0001] This invention relates to the field of power system technology, and more specifically, to a clock correction method, apparatus, power terminal, and storage medium for a power terminal. Background Technology

[0002] With the gradual development of the power industry, power terminal products have entered the era of the Internet of Things (IoT). Power terminal products are becoming increasingly multi-chip (metering chip, management chip) and multi-APP (data center APP, meter reading APP, transaction processing APP). Ensuring that a product operates on a single timeline is a prerequisite for guaranteeing reliable and stable product data. In extreme environments or due to improper operation, battery damage, chip clock discrepancies, or time anomalies in the power terminal may occur. Currently, common methods for synchronizing power terminal products include GPS or BeiDou positioning systems, and remote master stations are also used. However, these methods only work under normal network and positioning system conditions; under abnormal conditions, time synchronization is impossible. Summary of the Invention

[0003] In view of this, the object of the present invention is to provide a clock correction method, apparatus, power terminal and storage medium for a power terminal.

[0004] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0005] In a first aspect, the present invention provides a clock correction method for a power terminal, applied to a power terminal including a metering chip and a management chip, the method comprising:

[0006] During the operation of the power terminal, the hard clock is updated periodically and the current time is recorded to a file according to a preset cycle;

[0007] When the power terminal is powered on normally after a power outage, the current clock of the metering core and the current time of the management core are obtained, and the last start time and the last power outage time are read from the file.

[0008] If the last power outage time is greater than the last startup time, the credibility of the current clock, the current time, and the last power outage time is compared, and the one with the highest credibility is taken as the system time and the time is synchronized based on the system time.

[0009] If the last power outage time is less than or equal to the last startup time, the current clock and the current time are compared for reliability, and the one with the highest reliability is taken as the system time and the time is synchronized based on the system time.

[0010] In an optional implementation, the step of comparing the reliability of the current clock, the current time, and the last power outage time includes:

[0011] Compare the current clock with the last power outage time, and compare the current time with the last power outage time;

[0012] If the current clock is greater than the last power outage time, then the current clock is taken as the one with the highest confidence.

[0013] If the current clock is less than or equal to the last power outage time and the current time is greater than the last power outage time, then the current time is taken as the one with the highest confidence.

[0014] If both the current clock and the current time are less than or equal to the last power outage time, then the last power outage time is taken as the one with the highest reliability.

[0015] In an optional implementation, the step of comparing the credibility of the current clock and the current time includes:

[0016] Determine whether the current clock and the current time belong to a preset time range;

[0017] If the current clock falls within a preset time range, then the current clock will be considered the one with the highest reliability.

[0018] If the current clock does not belong to the preset time range but the current moment belongs to the preset time range, then the current moment is taken as the one with the highest credibility.

[0019] If neither the current clock nor the current time falls within a preset time range, then the current clock will be considered the one with the highest reliability.

[0020] In an optional implementation, the method further includes:

[0021] Delete the last power outage time from the file, and if the current clock is the most reliable one, record the current clock as the current startup time in the file, or if the current time is the most reliable one, record the current time as the current startup time in the file.

[0022] In an optional implementation, the method further includes:

[0023] When the power terminal is powered off and the battery is powered on, the current time of the management chip is obtained, and the last start time and the last power failure time are read from the file.

[0024] If the last power outage time is greater than the last startup time, the current time and the last power outage time are compared in terms of reliability, and the one with the highest reliability is taken as the system time.

[0025] If the last power outage time is less than or equal to the last startup time, the current time shall be used as the system time.

[0026] The hard clock is updated based on the system time and the last power outage time is retained.

[0027] In an optional implementation, the step of comparing the reliability of the current time and the last power outage time includes:

[0028] Compare the current time with the last power outage time;

[0029] If the current time is greater than the last power outage time, then the current time is taken as the one with the highest credibility.

[0030] If the current time is less than or equal to the last power outage time, then the last power outage time is taken as the one with the highest credibility.

[0031] In an optional implementation, the method further includes:

[0032] During the operation of the power terminal, when a time synchronization command is received, the time carried in the time synchronization command is used as the system time and time synchronization is performed.

[0033] Secondly, the present invention provides a clock correction device for a power terminal, applied to a power terminal including a metering core and a management core, the device comprising:

[0034] The recording module is used to update the hard clock periodically and record the current time to a file according to a preset cycle during the operation of the power terminal.

[0035] The correction module is used to obtain the current clock of the metering core and the current time of the management core when the power terminal is powered on normally after a power outage, and to read the last start time and the last power outage time from the file.

[0036] If the last power outage time is greater than the last startup time, the credibility of the current clock, the current time, and the last power outage time is compared, and the one with the highest credibility is taken as the system time and the time is synchronized based on the system time.

[0037] If the last power outage time is less than or equal to the last startup time, the current clock and the current time are compared for reliability, and the one with the highest reliability is taken as the system time and the time is synchronized based on the system time.

[0038] Thirdly, the present invention provides a power terminal, including a processor and a memory, wherein the memory stores a computer program, and when the processor executes the computer program, it implements the method described in any one of the foregoing embodiments.

[0039] Fourthly, the present invention provides a storage medium storing a computer program, which, when executed by a processor, implements the method described in any one of the foregoing embodiments.

[0040] This invention provides a clock correction method, apparatus, power terminal, and storage medium for a power terminal. During operation, the power terminal periodically updates its hard clock and records the current time to a file according to a preset cycle. When the power terminal is powered on again after a power outage, it acquires the current clock of the metering chip and the current time of the management chip, and reads the last startup time and the last power outage time from the file. If the last power outage time is greater than the last startup time, the reliability of the current clock, the current time, and the last power outage time is compared. If the last power outage time is less than or equal to the last startup time, the reliability of the current clock and the current time is compared, and the one with the highest reliability is used for system time synchronization. By updating the hard clock and recording the current time during operation, the power terminal can acquire the last startup time and the last power outage time upon power-on after a power outage, compare their reliability with the current time of the metering chip and the management chip, and use the one with the highest reliability as the system time for time synchronization. This eliminates the need for external devices to correct the power terminal's clock, ensuring reliable and continuous operation and achieving consistency, synchronization, and accuracy of the clock within the power terminal.

[0041] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0042] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 A block diagram of a power terminal provided in an embodiment of the present invention is shown;

[0044] Figure 2 This invention illustrates a flowchart of a clock correction method for a power terminal provided in an embodiment of the present invention.

[0045] Figure 3 This illustration shows another flowchart of the clock correction method for a power terminal provided in an embodiment of the present invention;

[0046] Figure 4 A functional block diagram of a clock correction device for a power terminal provided in an embodiment of the present invention is shown.

[0047] Icons: 110-Processor; 120-Memory; 130-Communication module; 150-Metering chip; 170-Management chip; 300-Clock correction device for power terminal; 310-Recording module; 330-Correction module. Detailed Implementation

[0048] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0049] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0050] It should be noted that relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0051] Please refer to Figure 1This is a block diagram of a power terminal provided in an embodiment of the present invention. The power terminal includes a processor 110, a memory 120, a communication module 130, a metering core 150, and a management core 170. The components are directly or indirectly electrically connected to each other to realize data transmission or interaction. For example, these components can be electrically connected to each other through one or more communication buses or signal lines.

[0052] The processor 110 is used to read / write data or programs stored in the memory 120 and perform corresponding functions. It can be a general-purpose processor, including CPU (Central Processing Unit), NP (Network Processor), etc.; it can also be a DSP digital signal processor, ASIC application-specific integrated circuit, FPGA off-the-shelf programmable gate array or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0053] The memory 120 is used to store programs or data. The memory 120 can be RAM (Random Access Memory), ROM (Read Only Memory), PROM (Programmable Read-Only Memory), EPROM (Erasable Programmable Read-Only Memory), EEPROM (Electric Erasable Programmable Read-Only Memory), etc.

[0054] Communication module 130 is used for signaling or data communication with other devices. Metering chip 150 is an integrated circuit chip specifically designed for electricity metering and measurement. Management chip 170 is an integrated power chip for control and management, capable of managing the time of all chips in the power terminal.

[0055] Understandable, Figure 1 The structure shown is only a schematic diagram of a power terminal; the power terminal may also include components that are larger than those shown. Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown. Figure 1 The components shown can be implemented using hardware, software, or a combination thereof.

[0056] It should be noted that the power terminal may also include multiple other chips, and the power terminal is equipped with an application with clock correction function. The power terminal executes the method provided in the embodiments of the present invention through the application.

[0057] The following will use the aforementioned power terminal as the execution subject to execute the various steps in the methods provided in the embodiments of the present invention and achieve the corresponding technical effects.

[0058] Please see Figure 2 , Figure 2 This is a flowchart illustrating a clock correction method for a power terminal provided in an embodiment of the present invention.

[0059] Step S202: During the operation of the power terminal, the hard clock is updated periodically and the current time is recorded to a file according to a preset cycle;

[0060] In this embodiment, during normal operation, the power terminal can periodically update the hard clock via the management chip. The hard clock can be understood as a high-precision time reference source; periodically updating the hard clock can reduce data deviation after a power outage and restart.

[0061] The power terminal will also write the current time to a file at a preset period, such as every minute, to record the time of power failure in case of abnormal power outage, so that the power terminal can correct its clock based on the time of power failure after power is restored.

[0062] Step S204: When the power terminal is powered on normally after a power outage, obtain the current clock of the metering core and the current time of the management core, and read the last start time and the last power outage time from the file.

[0063] In this embodiment, the power terminal has two power-on modes after a complete power outage. The first mode is when the power supply voltage reaches the rated voltage of the power terminal, such as 220V, which is normal power-on. The second mode is when the power terminal is powered by its battery, which is battery-powered power-on.

[0064] When the power terminal is powered on normally after a power outage, all devices in the power terminal will start running. In this case, the current clock of the metering core, such as A, and the current time of the management core, such as B, can be obtained. Then, the power-on time and the power-off time of the last power terminal are read from the file to obtain the last start time, such as C, and the last power-off time, such as D.

[0065] Step S206a: If the last power failure time is greater than the last startup time, compare the reliability of the current clock, the current time and the last power failure time, and take the one with the highest reliability as the system time and synchronize the time based on the system time.

[0066] Step S206b: If the last power failure time is less than or equal to the last startup time, compare the current clock and the current time with their reliability, and use the one with the highest reliability as the system time and synchronize the time based on the system time.

[0067] In this embodiment, after obtaining the last startup time and the last power failure time, the validity of the last power failure time can be judged, that is, whether the last power failure time is greater than the last startup time.

[0068] If the last power outage time D is greater than the last startup time C, it means that the last power outage time D is later than the last startup time C. Therefore, the last power outage time D is deemed valid. Then, the credibility of the current clock A, the current time B, and the last power outage time D is compared, and the one with the highest credibility is taken as the system time. Time synchronization is then performed based on this system time, that is, the system time is synchronized to other chips through the management chip.

[0069] If the last power outage time D is less than or equal to the last startup time C, it means that the last power outage time D is earlier than or equal to the last startup time C. Therefore, the last power outage time D is deemed invalid. Then, the credibility of the current clock A and the current time B is compared, and the one with the highest credibility is taken as the system time. Time synchronization is then performed based on this system time, that is, the system time is synchronized to other chips through the management chip.

[0070] As can be seen from the above steps, the power terminal updates its hard clock periodically during operation and records the current time to a file according to a preset cycle. When the power terminal is powered on again after a power outage, it obtains the current clock of the metering chip and the current time of the management chip, and reads the last startup time and the last power outage time from the file. If the last power outage time is greater than the last startup time, the reliability of the current clock, the current time, and the last power outage time is compared. If the last power outage time is less than or equal to the last startup time, the reliability of the current clock and the current time is compared, and the one with the highest reliability is used for system time synchronization. By updating the hard clock and recording the current time during operation, the power terminal can obtain the last startup time and the last power outage time when it is powered on again after a power outage, compare their reliability with the current time of the metering chip and the management chip, and use the one with the highest reliability as the system time for time synchronization. Therefore, clock correction of the power terminal can be achieved without the use of external devices, ensuring that the power terminal can operate in a reliable and continuous time environment, and realizing the consistency, synchronization, and accuracy of the clock in the power terminal.

[0071] Optionally, for the process of comparing the reliability of the current clock, the current time and the last power failure time in step S206a above, the present invention provides a possible implementation method.

[0072] Step S206a-1: Compare the current clock with the last power failure time, and compare the current time with the last power failure time;

[0073] Step S206a-3: If the current clock is greater than the last power outage time, then the current clock is taken as the one with the highest confidence.

[0074] Step S206a-5: If the current clock is less than or equal to the last power outage time and the current time is greater than the last power outage time, then the current time is taken as the one with the highest confidence.

[0075] Step S206a-7: If both the current clock and the current time are less than or equal to the last power outage time, then the last power outage time is taken as the one with the highest credibility.

[0076] In this embodiment, if the last power outage time is determined to be valid, then the credibility of the current clock, the current time, and the last power outage time is compared to obtain the one with the highest credibility, so that the one with the highest credibility can be used as the system time for subsequent time synchronization.

[0077] Continuing with the example above, compare the current clock A with the last power outage time D, and compare the current time B with the last power outage time D.

[0078] If the current clock A is greater than the last power outage time D, it means that the current clock A is later than the last power outage time D, and the reliability of the current clock A is greater than that of the last power outage time D. If the current time B is less than or equal to the last power outage time D, it means that the current time B is earlier than or equal to the last power outage time D, and the reliability of the current time B is less than that of the last power outage time D. In this case, the current clock A is taken as the one with the highest reliability.

[0079] If the current clock A is greater than the last power outage time D, it means that the current clock A is later than the last power outage time D, and the reliability of the current clock A is greater than that of the last power outage time D; if the current time B is greater than the last power outage time D, it means that the current time B is later than the last power outage time D, and the reliability of the current time B is greater than that of the last power outage time D.

[0080] Understandably, since the timekeeping chip is based on a hard clock, which is more accurate, if the current clock and the current moment are both compared to the last power outage moment, and both have a higher reliability than the last power outage moment, then the current clock is considered the most reliable. In other words, as long as the current clock A is greater than the last power outage moment D, the current clock A is considered the most reliable.

[0081] If the current clock A is less than or equal to the last power outage time D, it means that the current clock A is earlier than or equal to the last power outage time D, and the reliability of the current clock A is less than that of the last power outage time D; if the current time B is greater than the last power outage time D, it means that the current time B is later than the last power outage time D, and the reliability of the current time B is greater than that of the last power outage time D. Therefore, the current time B is taken as the one with the highest reliability.

[0082] If the current clock A is less than or equal to the last power outage time D, it means that the current clock A is earlier than or equal to the last power outage time D, and the reliability of the current clock A is less than that of the last power outage time D. If the current time B is less than or equal to the last power outage time D, it means that the current time B is earlier than or equal to the last power outage time D, and the reliability of the current clock A is less than that of the last power outage time D. In this case, the last power outage time D is taken as the one with the highest reliability.

[0083] Optionally, for the process of comparing the credibility of the current clock and the current time in step S206b above, the present invention provides a possible implementation method.

[0084] Step S206b-1: Determine whether the current clock and the current time belong to the preset time range;

[0085] Step S206b-3: If the current clock falls within a preset time range, then the current clock is taken as the one with the highest reliability.

[0086] Step S206b-5: If the current clock does not belong to the preset time range but the current moment belongs to the preset time range, then the current moment is taken as the one with the highest confidence.

[0087] Step S206b-7: If neither the current clock nor the current time falls within the preset time range, then the current clock is taken as the one with the highest reliability.

[0088] In this embodiment, if the last power outage time is determined to be invalid, the current clock and the current time are compared in terms of reliability to obtain the one with the highest reliability, so that the one with the highest reliability can be used as the system time for subsequent time synchronization.

[0089] It is understandable that since the last power outage time was invalid, the credibility comparison between the current clock and the current time cannot be made based on the last power outage time. Therefore, in this embodiment of the invention, a reasonable time range is preset according to the production time of the power terminal, so as to make a credibility comparison between the current clock and the current time based on this time.

[0090] Continuing with the example above, we compare the current clock A and the current time B with the preset time range, that is, we determine whether the current clock A and the current time B belong to the preset time range.

[0091] If the current clock A is within the preset time range, it means that the current clock A is reliable; if the current time B is not within the preset time range, it means that the current time B is not reliable, then the current clock A is taken as the most reliable one.

[0092] If the current clock A is within the preset time range, it means that the current clock A is reliable; if the current time B is within the preset time range, it means that the current time B is reliable.

[0093] Understandably, since the timekeeping chip is based on a hard clock, which is more accurate, if the current clock and the current time are compared with a preset time range and both are deemed reliable, the current clock will be considered the most reliable. In other words, as long as the current clock A falls within the preset time range, the current clock A will be considered the most reliable.

[0094] If the current clock A is not within the preset time range, it means that the current clock A is unreliable; if the current time B is within the preset time range, it means that the current time B is reliable, so the current time B is taken as the most reliable.

[0095] If the current clock A is not within the preset time range, it means that the current clock A is unreliable; if the current time B is not within the preset time range, it means that the current time B is unreliable. Based on the foregoing, the current clock A is more accurate than the current time B, so even if both the current clock A and the current time B are unreliable, the current clock A will be considered the most reliable.

[0096] Optionally, after step S206a or step S206b above, the present invention also provides a possible implementation method, namely: delete the last power failure time in the file, and if the current clock is the most reliable one, record the current clock as the current startup time in the file, or if the current time is the most reliable one, record the current time as the current startup time in the file.

[0097] In this embodiment, after synchronizing the system time, the last power outage time can be deleted from the file to continue writing time to the file. Furthermore, if the current clock has the highest reliability, then the current clock is used as the current startup time and written to the file; if the current time has the highest reliability, then the current time is used as the current startup time and written to the file.

[0098] It can be understood that, in the embodiments of the present invention, when powering on, multiple times are compared for reliability to determine the system time before synchronization is performed, and the power-on time is immediately recorded in a file after synchronization, so as to avoid the power terminal being powered off or restarted again without recording the time, thus ensuring the continuity of time.

[0099] Optionally, after step S202 above, this embodiment of the invention also provides a possible implementation, please refer to [link to relevant documentation]. Figure 3 .

[0100] Step S208: When the power terminal is powered off and the battery is powered on, obtain the current time of the management chip and read the last start time and the last power failure time from the file.

[0101] In this embodiment, when the power terminal is powered off and the battery is powered on, since the voltage provided by the battery does not reach the rated voltage, only some devices in the power terminal start to operate, such as the management chip starting while the metering chip does not start. In this case, only the current time of the management chip can be obtained, such as B. Then, the last power-on time and the last power-off time of the power terminal are read from the file to obtain the last start time, such as C and the last power-off time, such as D.

[0102] Step S210a: If the last power failure time is greater than the last startup time, compare the current time with the last power failure time and take the one with the highest confidence as the system time.

[0103] Step S210b: If the last power failure time is less than or equal to the last startup time, the current time is used as the system time.

[0104] In this embodiment, after obtaining the last startup time and the last power failure time, the validity of the last power failure time can be judged, that is, whether the last power failure time is greater than the last startup time.

[0105] If the last power outage time D is greater than the last startup time C, it means that the last power outage time D is later than the last startup time C. Therefore, the last power outage time D is deemed valid. Then, the credibility of the current time B and the last power outage time D is compared, and the one with the highest credibility is taken as the system time.

[0106] If the last power outage time D is less than or equal to the last startup time C, it means that the last power outage time D is earlier than or equal to the last startup time C. Therefore, the last power outage time D is deemed invalid, and the current time B is used as the system time.

[0107] Step S212: Update the hard clock based on the system time and retain the last power outage time;

[0108] It is understandable that since the power terminal is powered by a battery, it is in a low-power state, meaning the chips cannot synchronize time. Therefore, this embodiment of the invention updates the hard clock based on the system time to record the time when the power terminal is powered on by the battery. Furthermore, after the power terminal is powered by the battery, it will not perform the operation of recording the current time to a file to avoid writing the time and causing file corruption, thus ensuring the integrity and accuracy of the data in the file.

[0109] Optionally, for the process of comparing the credibility of the current time and the last power outage time in step S210a above, the present invention provides a possible implementation method.

[0110] Step S210a-1: Compare the current time with the last power outage time;

[0111] Step S210a-3: If the current time is greater than the last power outage time, then the current time is taken as the one with the highest confidence.

[0112] Step S210a-5: If the current time is less than or equal to the last power outage time, then the last power outage time is taken as the one with the highest confidence.

[0113] In this embodiment, if the last power outage time is determined to be valid, then the credibility of the current time and the last power outage time is compared to obtain the one with the highest credibility, so that the one with the highest credibility can be used as the system time for subsequent time synchronization.

[0114] Continuing with the example above, compare the current time B with the last power outage time D. If the current time B is greater than the last power outage time D, it means that the current time B is later than the last power outage time D. Therefore, the credibility of the current time B is greater than that of the last power outage time D, and the current time B is taken as the one with the highest credibility.

[0115] If the current time B is less than or equal to the last power outage time D, it means that the current time B is earlier than or equal to the last power outage time D. Therefore, the credibility of the current time B is less than that of the last power outage time D, and the last power outage time D is taken as the one with the highest credibility.

[0116] Optionally, during the operation of the power terminal, this embodiment of the invention also provides a possible implementation method, namely: during the operation of the power terminal, when a time synchronization command is received, the time carried in the time synchronization command is used as the system time and time synchronization is performed.

[0117] In this embodiment, if the power terminal receives a time synchronization command from an external device during operation, it obtains the time carried in the time synchronization command and uses it as the system time. Then, it performs time synchronization based on the system time, that is, it synchronizes the system time to other chips through the management chip.

[0118] To perform the corresponding steps in the above embodiments and various possible methods, an implementation of a clock correction device for a power terminal is given below. Please refer to... Figure 4 , Figure 4This is a functional block diagram of a clock correction device 300 for a power terminal provided in an embodiment of the present invention. It should be noted that the basic principle and technical effects of the clock correction device 300 for a power terminal provided in this embodiment are the same as those in the above embodiments. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the above embodiments. The clock correction device 300 for the power terminal includes:

[0119] The recording module 310 is used to update the hard clock periodically and record the current time to a file according to a preset cycle during the operation of the power terminal;

[0120] The correction module 330 is used to obtain the current clock of the metering core and the current time of the management core when the power terminal is powered on normally after a power outage, and to read the last start time and the last power outage time from the file.

[0121] If the last power outage time is greater than the last startup time, compare the reliability of the current clock, the current time and the last power outage time, and take the one with the highest reliability as the system time and perform time synchronization based on the system time.

[0122] If the last power outage time is less than or equal to the last startup time, compare the current clock and the current time in terms of reliability, and use the one with the highest reliability as the system time and synchronize the time based on the system time.

[0123] Optionally, the correction module 330 is further configured to: compare the current clock with the last power outage time, and compare the current time with the last power outage time; if the current clock is greater than the last power outage time, then the current clock is taken as the one with the highest confidence; if the current clock is less than or equal to the last power outage time and the current time is greater than the last power outage time, then the current time is taken as the one with the highest confidence; if both the current clock and the current time are less than or equal to the last power outage time, then the last power outage time is taken as the one with the highest confidence.

[0124] Optionally, the correction module 330 is further configured to: determine whether the current clock and the current time belong to a preset time range; if the current clock belongs to the preset time range, then the current clock is selected as the one with the highest confidence; if the current clock does not belong to the preset time range but the current time belongs to the preset time range, then the current time is selected as the one with the highest confidence; if neither the current clock nor the current time belongs to the preset time range, then the current clock is selected as the one with the highest confidence.

[0125] Optionally, the recording module 310 is also used to: delete the last power failure time from the file, and record the current clock as the start time of this operation in the file if the current clock is the most reliable one, or record the current time as the start time of this operation in the file if the current time is the most reliable one.

[0126] Optionally, the correction module 330 is further configured to: when the power terminal is powered off and the battery is powered on, obtain the current time of the management chip and read the last startup time and the last power failure time from the file; if the last power failure time is greater than the last startup time, compare the reliability of the current time and the last power failure time and take the one with the highest reliability as the system time; if the last power failure time is less than or equal to the last startup time, take the current time as the system time; update the hard clock based on the system time and retain the last power failure time.

[0127] Optionally, the correction module 330 is also used to: compare the current time with the last power outage time; if the current time is greater than the last power outage time, then the current time is taken as the one with the highest confidence; if the current time is less than or equal to the last power outage time, then the last power outage time is taken as the one with the highest confidence.

[0128] Optionally, the correction module 330 is also used to: when a time synchronization command is received during the operation of the power terminal, use the time carried in the time synchronization command as the system time and perform time synchronization.

[0129] This invention also provides a power terminal, including a processor and a memory. The memory stores a computer program, and when the processor executes the computer program, it implements the clock correction method for the power terminal disclosed in this invention.

[0130] This invention also provides a storage medium storing a computer program, which, when executed by a processor, implements the clock correction method for a power terminal disclosed in this invention.

[0131] In the several embodiments provided by this invention, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative; for example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of the invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0132] In addition, the functional modules in the various embodiments of the present invention can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0133] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0134] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A clock correction method for a power terminal, characterized by, Applied to an electricity terminal, the electricity terminal including a metering chip and a management chip, the method includes: During the operation of the power terminal, the hard clock is updated periodically and the current time is recorded to a file according to a preset cycle; When the power terminal is powered on normally after a power outage, the current clock of the metering core and the current time of the management core are obtained, and the last start time and the last power outage time are read from the file. If the last power outage time is greater than the last startup time, the credibility of the current clock, the current time, and the last power outage time is compared, and the one with the highest credibility is taken as the system time and the time is synchronized based on the system time. If the last power outage time is less than or equal to the last startup time, the current clock and the current time are compared for reliability, and the one with the highest reliability is taken as the system time and the time is synchronized based on the system time. The step of comparing the credibility of the current clock, the current time, and the last power outage time includes: comparing the current clock with the last power outage time, and comparing the current time with the last power outage time; if the current clock is greater than the last power outage time, then the current clock is taken as the one with the highest credibility; if the current clock is less than or equal to the last power outage time and the current time is greater than the last power outage time, then the current time is taken as the one with the highest credibility; if both the current clock and the current time are less than or equal to the last power outage time, then the last power outage time is taken as the one with the highest credibility. The step of comparing the credibility of the current clock and the current time includes: determining whether the current clock and the current time belong to a preset time range; if the current clock belongs to the preset time range, then the current clock is taken as the one with the highest credibility; if the current clock does not belong to the preset time range but the current time belongs to the preset time range, then the current time is taken as the one with the highest credibility; if neither the current clock nor the current time belongs to the preset time range, then the current clock is taken as the one with the highest credibility.

2. The method of claim 1, wherein, The method further includes: Delete the last power outage time from the file, and if the current clock is the most reliable one, record the current clock as the current startup time in the file, or if the current time is the most reliable one, record the current time as the current startup time in the file.

3. The method of claim 1, wherein, The method further includes: When the power terminal is powered off and the battery is powered on, the current time of the management chip is obtained, and the last start time and the last power failure time are read from the file. If the last power outage time is greater than the last startup time, the current time and the last power outage time are compared in terms of reliability, and the one with the highest reliability is taken as the system time. If the last power outage time is less than or equal to the last startup time, the current time shall be used as the system time. The hard clock is updated based on the system time and the last power outage time is retained.

4. The method of claim 3, wherein, The step of comparing the reliability of the current time and the last power outage time includes: Compare the current time with the last power outage time; If the current time is greater than the last power outage time, then the current time is taken as the one with the highest credibility. If the current time is less than or equal to the last power outage time, then the last power outage time is taken as the one with the highest credibility.

5. The method of claim 1, wherein, The method further includes: During the operation of the power terminal, when a time synchronization command is received, the time carried in the time synchronization command is used as the system time and time synchronization is performed.

6. A clock correction device for a power terminal, characterized in that, Applied to a power terminal, the power terminal including a metering core and a management core, the device includes: The recording module is used to update the hard clock periodically and record the current time to a file according to a preset cycle during the operation of the power terminal. The correction module is used to obtain the current clock of the metering core and the current time of the management core when the power terminal is powered on normally after a power outage, and to read the last start time and the last power outage time from the file. If the last power outage time is greater than the last startup time, a confidence comparison is performed on the current clock, the current time, and the last power outage time, and the system time with the highest confidence level is used as the system time and time synchronization is performed based on the system time. The step of comparing the confidence level of the current clock, the current time, and the last power outage time includes: comparing the current clock with the last power outage time, and comparing the current time with the last power outage time; if the current clock is greater than the last power outage time, then the current clock is used as the one with the highest confidence level; if the current clock is less than or equal to the last power outage time and the current time is greater than the last power outage time, then the current time is used as the one with the highest confidence level; if both the current clock and the current time are less than or equal to the last power outage time, then the last power outage time is used as the one with the highest confidence level. If the last power outage time is less than or equal to the last startup time, the current clock and the current time are compared for reliability, and the one with the highest reliability is taken as the system time and time synchronization is performed based on the system time. The step of comparing the reliability of the current clock and the current time includes: determining whether the current clock and the current time belong to a preset time range; if the current clock belongs to the preset time range, then the current clock is taken as the one with the highest reliability; if the current clock does not belong to the preset time range but the current time does belong to the preset time range, then the current time is taken as the one with the highest reliability; if neither the current clock nor the current time belongs to the preset time range, then the current clock is taken as the one with the highest reliability.

7. A power terminal, characterized in that, It includes a processor and a memory, the memory storing a computer program, and the processor, when executing the computer program, implements the method of any one of claims 1 to 5.

8. A storage medium, characterized in that, The storage medium stores a computer program, which, when executed by a processor, implements the method of any one of claims 1 to 5.

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