Ion trap chip, ion movement method, and electronic device

Abstract

This application discloses an ion trap chip, an ion movement method, and an electronic device, relating to the technical field of quantum computing. The ion trap chip includes a chip body and a multiplexed data circuit. The chip body contains multiple electrodes, at least some of which have different voltages. The multiplexed data circuit includes an input terminal, multiple output terminals, and a control terminal. The input terminal receives input signals, the control terminal receives control signals, and one output terminal of the multiplexed data circuit is connected to one of the electrodes in a one-to-one correspondence. Different output terminals of the multiplexed data circuit are connected to different electrodes. The multiplexed data circuit outputs the input signal from the output interface corresponding to the received control signal according to the received control signal. This ion trap chip only requires pins in the multiplexed data circuit for receiving input and control signals, thereby significantly reducing the number of pins required for the ion trap chip.

Description

Technical Field

[0001] This application relates to the field of quantum computing technology, and more specifically, to an ion trap chip, an ion movement method, and an electronic device. Background Technology

[0002] Ion trap chips utilize surface electrodes on multiple chips to achieve one-dimensional chain trapping and two-dimensional array trapping of ions, enabling linear ion movement and thus increasing the number of ion qubits. However, a single region on an ion trap chip that enables trapping often requires a large number of surface electrodes. Currently, each electrode on the chip corresponds to a packaged chip pin, leading to a significant increase in the number of chip pins and making it difficult for existing packaging technologies to meet higher precision packaging requirements. Summary of the Invention

[0003] This application provides an ion trap chip, an ion movement method, and an electronic device to solve the problem that existing technologies cannot achieve higher precision packaging requirements for ion trap chips.

[0004] In a first aspect, this application provides an ion trap chip, including a chip body and a multi-channel data circuit. The chip body includes multiple electrodes, at least some of which have different voltages. The multi-channel data circuit includes an input terminal, multiple output terminals, and a control terminal. The input terminal receives an input signal, the control terminal receives a control signal, one output terminal of the multi-channel data circuit is connected to one of the electrodes, and different output terminals are connected to different electrodes. The multi-channel data circuit outputs the input signal from an output interface corresponding to the received control signal.

[0005] In this embodiment, the multi-channel data circuit inputs the input signal to the output interface corresponding to the control signal, so that the electrode on the chip body connected to the output interface changes its voltage according to the input signal. Therefore, the ion trap chip only needs to set the pins in the multi-channel data circuit for receiving input signals and control signals, instead of setting a separate pin for each electrode, thereby significantly reducing the number of pins required for the ion trap chip and reducing the requirements for packaging precision.

[0006] In conjunction with the technical solution provided in the first aspect above, in some possible implementations, the ion trap chip further includes: a plurality of signal holding circuits, wherein each output terminal of the multi-channel data circuit is connected to a corresponding electrode through one of the signal holding circuits, and the signal holding circuits are used to hold the received input signals.

[0007] In this embodiment of the application, by setting a signal holding circuit, the signal holding circuit can maintain the voltage of the last received input signal when the output interface stops outputting the input signal, thereby keeping the voltage of the electrode connected to the signal holding circuit unchanged.

[0008] In conjunction with the technical solution provided in the first aspect above, in some possible implementations, when the input signal is an analog signal, the signal holding circuit includes a sample-and-hold circuit, the sample-and-hold circuit includes a holding capacitor and a sampling switch, the first end of the sampling switch is connected to an output terminal of the multiplexed data circuit, the second end of the sampling switch is connected to an electrode corresponding to the chip body, and the second end of the sampling switch is also grounded through the holding capacitor.

[0009] In this embodiment, when the input signal is an analog signal, the input signal is held by a sample-and-hold circuit including a holding capacitor and a sampling switch. After the holding capacitor holds the input signal, the sampling switch is turned off, so that the voltage held by the holding capacitor no longer changes with the signal output by the multi-channel data circuit, thus isolating voltage source noise.

[0010] In conjunction with the technical solution provided in the first aspect above, in some possible implementations, the sample-and-hold circuit further includes an amplifier, the first terminal of the sampling switch is connected to the multiplex data circuit through the amplifier, and / or the second terminal of the sampling switch is connected to the corresponding electrode of the chip body through the amplifier.

[0011] In this embodiment, by setting an amplifier between the first terminal of the sampling switch and the multiplexed data circuit, the charging time for the holding capacitor is reduced, and the voltage signal held by the holding capacitor is made consistent with the input voltage signal. And / or, by setting an amplifier between the second terminal of the sampling switch and the chip body, the voltage discharge problem of the holding capacitor can be effectively reduced, and the holding time of the voltage signal held by the holding capacitor can be increased.

[0012] In conjunction with the technical solution provided in the first aspect above, in some possible implementations, if the first terminal of the sampling switch is connected to the multiplex data circuit through the amplifier, the non-inverting input terminal of the amplifier is connected to the multiplex data circuit, the output terminal of the amplifier is connected to the first terminal of the sampling switch, and the inverting input terminal of the amplifier is connected to the output terminal of the amplifier.

[0013] In this embodiment, by setting an amplifier between the first terminal of the sampling switch and the multiplex data circuit, the charging time for the holding capacitor is reduced, and the voltage signal held by the holding capacitor is made consistent with the input voltage signal.

[0014] In conjunction with the technical solution provided in the first aspect above, in some possible implementations, if the second terminal of the sampling switch is connected to the electrode corresponding to the chip body through the amplifier, the non-inverting input terminal of the amplifier is connected to the second terminal of the sampling switch, the output terminal of the amplifier is connected to the electrode corresponding to the chip body, and the inverting input terminal of the amplifier is connected to the electrode corresponding to the chip body.

[0015] In this embodiment, by setting an amplifier between the second end of the sampling switch and the chip body, the voltage leakage problem of the holding capacitor can be effectively reduced, thereby increasing the voltage signal time held by the holding capacitor.

[0016] In conjunction with the technical solution provided in the first aspect above, in some possible implementations, when the input signal is a digital signal, the signal holding circuit includes a digital-to-analog converter circuit, which is used to store the digital signal and convert the digital signal into an analog signal for output.

[0017] In this embodiment of the application, when the input signal is a digital signal, the signal holding circuit includes a digital-to-analog converter circuit. The digital-to-analog converter circuit can convert the digital signal into an analog signal and store the input digital signal. Furthermore, the digital signal stored by the digital-to-analog converter circuit will not change over time, making the data more stable.

[0018] In conjunction with the technical solution provided in the first aspect above, in some possible implementations, the ion trap chip further includes a controller for generating the control signal.

[0019] In this embodiment, by setting a controller for generating control signals within the ion trap chip, the ion trap chip does not require an additional external electronic device for generating control signals during actual use, thus expanding the application range of the ion trap chip.

[0020] In conjunction with the technical solution provided in the first aspect above, in some possible implementations, the multi-channel data circuit periodically inputs the input signal to the signal holding circuit corresponding to the selection signal to the signal holding circuit according to the selection signal, so that the voltage of the electrodes corresponding to different signal holding circuits changes periodically.

[0021] In this embodiment, the multi-channel data circuit inputs the input signal to the signal holding circuit corresponding to the selection signal according to the selection signal, thereby causing the voltage of the electrode corresponding to the signal holding circuit to change periodically, realizing the periodic update of the electrode voltage, so that the ion trap chip can better meet the actual use requirements.

[0022] Secondly, this application provides an ion movement method applied to an ion trap chip described in the first aspect and / or any possible embodiment of the first aspect. The method includes: based on the multiplexing data circuit, outputting an input signal from an output interface corresponding to the control signal according to a received control signal; changing the voltage of an electrode connected to the output interface corresponding to the control signal to a voltage corresponding to the input signal, thereby changing the movement trajectory of ions in the ion trap chip.

[0023] Thirdly, this application provides an electronic device, including an electronic device body and an ion trap chip as described in the first aspect embodiment and / or in combination with the first aspect embodiment, wherein the ion trap chip is electrically connected to the electronic device body. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a schematic diagram of the surface electrodes of an ion trap chip in the prior art;

[0026] Figure 2 This is a block diagram illustrating the circuit principle of a first type of ion trap chip according to an embodiment of this application;

[0027] Figure 3 This is a schematic diagram of a multi-channel data circuit shown in an embodiment of this application;

[0028] Figure 4 This is a block diagram illustrating the circuit principle of a second type of ion trap chip according to an embodiment of this application;

[0029] Figure 5 This is a circuit diagram of a first sample-and-hold circuit shown in an embodiment of this application;

[0030] Figure 6 This is a circuit diagram of a second sample-and-hold circuit shown in an embodiment of this application;

[0031] Figure 7 This is a schematic flowchart illustrating the particle motion method in an embodiment of this application;

[0032] Figure 8 This is a structural block diagram of an electronic device shown in an embodiment of this application. Detailed Implementation

[0033] The terms “first,” “second,” “third,” etc., are used only for distinguishing descriptions and do not indicate a sequence number, nor should they be interpreted as indicating or implying relative importance.

[0034] In the description of this application, unless otherwise expressly specified and limited, the terms “set up,” “connected,” and “linked” should be interpreted broadly, for example, as a fixed connection, a detachable connection, or an integral connection; as a mechanical connection or an electrical connection; as a direct connection or an indirect connection through an intermediate medium; or as a connection within two components.

[0035] The technical solution of this application will now be clearly and completely described with reference to the accompanying drawings.

[0036] Existing ion trap chips have a large number of electrodes, such as Figure 1 The ion trap chip shown includes an "X"-shaped junction and two "Y"-shaped junctions on its surface electrodes. However, a typical ion trap chip with a multi-functional area may require more than one junction structure for a single area, leading to a dramatic increase in the number of electrodes on the chip, ranging from hundreds to thousands. Currently, each electrode pin corresponds to one I / O (Input / Output) pin on the packaged chip, and the electrode voltage is directly introduced to the chip electrode through the I / O pin. As chip designs become more complex, the number of I / O pins increases dramatically. Under normal circumstances, a package with around 1000 pins is already the upper limit of current packaging technology. With the ever-increasing number of pins required for ion trap chips, existing packaging technologies struggle to meet the requirements for packaging ion trap chips. This solution provides an ion trap chip that reduces the number of pins, addressing the problem of achieving high-precision packaging of ion trap chips using existing packaging technologies.

[0037] Please see Figure 2 , Figure 2 An ion trap chip is provided in an embodiment of this application. The ion trap chip includes a chip body and multiple data circuits.

[0038] The chip body contains multiple electrodes, at least some of which have different voltages.

[0039] A multi-channel data circuit includes one input terminal, multiple output terminals, and a control terminal. The input terminal is used to receive input signals, and the control terminal is used to receive control signals. One output terminal of the multi-channel data circuit is connected to one electrode in a one-to-one correspondence, and different output terminals of the multi-channel data circuit are connected to different electrodes.

[0040] The multiplexed data circuit is used to output the input signal from the output interface corresponding to the received control signal.

[0041] The multiplexing circuit can be any circuit with a single input and multiple outputs, where the output connected to the input is determined by the control signal. For example, the multiplexing circuit can be a multiplexer circuit, a demultiplexer circuit, etc., and the specific structure of the multiplexing circuit is not limited here.

[0042] To facilitate understanding, let's take a multi-channel data circuit with eight output interfaces as an example. Figure 3 As shown, the multi-channel data circuit has 8 output interfaces (D0, D1, D2, D3, D4, D5, D6, D7).

[0043] exist Figure 3 In the multi-channel data circuit shown, since the multi-channel data circuit contains 8 output interfaces, if binary encoding is used to control which output interface the input signal is connected to, then the multi-channel data circuit must contain at least 3 control terminals (S0, S1, S2).

[0044] Before actual use, the output interfaces need to be encoded. Taking binary encoding as an example, the binary encoding for interface D0 can be 000; for interface D1, it can be 001; for interface D2, it can be 010; for interface D3, it can be 011; for interface D4, it can be 100; for interface D5, it can be 101; for interface D6, it can be 110; and for interface D7, it can be 111. When the control signal received by the three control terminals is 000, the input interface of the multiplexer circuit is connected to interface D0. That is, when the control signal is 000, the input signal of the multiplexer circuit will be output from interface D0. When the control signal received by the three control terminals is 001, the input interface of the multiplexer circuit is connected to interface D1. That is, when the control signal is 001, the input signal of the multiplexer circuit will be output from interface D1, and so on.

[0045] It should be made clear that, Figure 3 The multiplexed data circuit shown is merely an example for ease of understanding; the number of output interfaces of the multiplexed data circuit can be any integer greater than or equal to 2.

[0046] In one embodiment, the ion trap chip further includes: multiple signal holding circuits. Each output terminal of the multi-channel data circuit is connected to a corresponding electrode via a signal holding circuit, which is used to hold the received input signal. For easier understanding, please refer to [link to relevant documentation]. Figure 4 .

[0047] The input signal can be a digital signal or an analog signal.

[0048] In one implementation, the input signal is an analog signal. In this case, the signal holding circuit includes a sample-and-hold circuit. For easier understanding, please refer to [link to relevant documentation]. Figure 5 When the input signal is an analog signal, a signal holding circuit is connected to one output interface of a multiplexer circuit, and different output interfaces of the multiplexer circuit are connected to different signal holding circuits.

[0049] like Figure 5 As shown, the sample-and-hold circuit includes a holding capacitor and a sampling switch. The first terminal of the sampling switch is connected to an output terminal of the multiplexer circuit, and the second terminal of the sampling switch is connected to an electrode corresponding to the chip body. The second terminal of the sampling switch is also grounded via the holding capacitor. When the multiplexer circuit inputs a signal to the sample-and-hold circuit, the sampling switch closes, and the voltage signal is held up to the holding capacitor. When the sampling switch of the sample-and-hold circuit opens, and the output voltage signal of the multiplexer circuit connected to this sample-and-hold circuit changes, the voltage value on the holding capacitor does not change with the change in the output voltage signal, maintaining the value before the sampling switch opened. Therefore, the output voltage of the sample-and-hold circuit remains at the value before the sampling switch opened, isolating voltage source noise.

[0050] Optionally, the sample-and-hold circuit also includes an amplifier. In one embodiment, the first terminal of the sampling switch is connected to a multiplexing circuit via an amplifier. Specifically, the non-inverting input of the amplifier is connected to the multiplexing circuit, the output of the amplifier is connected to the first terminal of the sampling switch, and the inverting input of the amplifier is connected to the output of the amplifier.

[0051] In another implementation, the second terminal of the sampling switch is connected to the corresponding electrode of the chip body via an amplifier. Specifically, the non-inverting input of the amplifier is connected to the second terminal of the sampling switch, the output of the amplifier is connected to the corresponding electrode of the chip body, and the inverting input of the amplifier is connected to the corresponding electrode of the chip body.

[0052] In another implementation, the first terminal of the sampling switch is connected to a multiplexed data circuit via a first amplifier, and the second terminal of the sampling switch is connected to the corresponding electrode on the chip body via a second amplifier. Specifically, the non-inverting input of the first amplifier is connected to the multiplexed data circuit, the output of the first amplifier is connected to the first terminal of the sampling switch, and the inverting input of the first amplifier is connected to the output of the amplifier. Similarly, the non-inverting input of the second amplifier is connected to the second terminal of the sampling switch, the output of the second amplifier is connected to the corresponding electrode on the chip body, and the inverting input of the second amplifier is connected to the corresponding electrode on the chip body.

[0053] For easier understanding, please refer to Figure 6 , Figure 6This refers to a sample-and-hold circuit that includes two amplifiers. It should be clarified that the three sample-and-hold circuits with amplifiers described above are for ease of understanding only. The specific number of amplifiers can be set according to actual usage requirements. For example, the number of amplifiers can be any number, such as 2, 3, 4, 5, 6, 7, or 8, placed between the first terminal of the sampling switch and the multiplexed data circuit, or between the second terminal of the sampling switch and the chip body.

[0054] In one implementation, the input signal is a digital signal, and the signal holding circuit includes a digital-to-analog converter (DAC). The DAC stores the input digital signal and converts it into an analog signal for output. This DAC includes a digital latch circuit or a demultiplexing circuit to latch the input digital signal. Because the latched digital signal does not change over time, the held data is more stable. DAC circuits are well known to those skilled in the art and will not be described in detail here.

[0055] When the input signal is a digital signal, a signal holding circuit (digital-to-analog converter) is connected to one output interface of the multiplexer circuit, and different output interfaces of the multiplexer circuit are connected to different signal holding circuits.

[0056] In one implementation, the multi-channel data circuit periodically inputs the input signal to the signal holding circuit corresponding to the control signal, causing the voltage of the electrodes corresponding to different signal holding circuits to change periodically. Figure 3 For example, if the control signal changes periodically between 000 and 111, the input terminal interface will periodically connect with interfaces D0-D7, thereby periodically changing the signals held by the signal holding circuits connected to interfaces D0-D7, and thus causing the voltages of the electrodes corresponding to the different signal holding circuits to change periodically.

[0057] In one embodiment, the ion trap chip further includes a controller for generating control signals. Since the ion trap chip itself can generate control signals, no external electronic device for generating control signals is required during use.

[0058] In one embodiment, the ion trap chip further includes program storage firmware for storing a voltage update plan for the ion trap chip electrodes. This voltage update plan may include the electrode number to be updated, the update time, and the update voltage. By incorporating the program storage firmware, automated and programmed loading of ion transport sequence voltages can be achieved, integrating ion transport functionality and voltage calculation, thus reducing the computational and timing accuracy requirements on the control system.

[0059] Based on the same technical concept, this application provides a method for ion movement, which will be described below in conjunction with... Figure 7 The steps involved are explained.

[0060] S100: Based on the multi-channel data circuit, the input signal is output from the output interface corresponding to the control signal according to the received control signal.

[0061] In the case where the ion trap chip includes a controller, before S100, a control signal is generated based on the controller and sent to a multiplex data circuit.

[0062] The specific implementation method of the control signal has been clearly described above, and will not be repeated here for the sake of brevity.

[0063] S200: The voltage of the electrode connected to the output interface corresponding to the control signal is changed to the voltage corresponding to the input signal, so as to change the movement trajectory of ions in the ion trap chip.

[0064] When the ion trap chip includes a signal holding circuit, the specific implementation of S200 is as follows: the signal holding circuit receives the input signal output from the output terminal of the multi-channel data circuit connected to itself, and transmits the input signal to the electrode connected to itself, so as to change the voltage of the electrode connected to itself.

[0065] When the connection between the output terminal of the multiplexed data circuit connected to the signal holding circuit and the output terminal is disconnected, the signal holding circuit holds the voltage value of the last received input signal so that the voltage of the electrode connected to the signal holding circuit remains stable.

[0066] Optionally, the above-mentioned ion movement method can be executed multiple times in succession to update multiple electrodes sequentially, thereby achieving continuous control of the ion movement trajectory.

[0067] Please see Figure 8 This application provides an electronic device 10, which includes an electronic device body 100 and the aforementioned ion trap chip 200, the ion trap chip 200 being electrically connected to the electronic device body 100. The ion trap chip 200 has been clearly described above and will not be repeated here.

[0068] Among them, electronic device 10 can be a quantum computer or a mass spectrometer.

[0069] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. An ion trap chip, characterized in that, include: A chip body, wherein the chip body includes a plurality of electrodes, at least some of which have different voltages; Multiple signal holding circuits are provided, wherein the signal holding circuits are used to hold the received input signals; A multi-channel data circuit includes an input terminal, multiple output terminals, and a control terminal. The input terminal receives input signals, and the control terminal receives control signals. Each output terminal of the multi-channel data circuit is connected to a corresponding electrode through a signal holding circuit. Each output terminal of the multi-channel data circuit is connected to one electrode in a one-to-one correspondence, and different output terminals of the multi-channel data circuit are connected to different electrodes. The multiplexed data circuit is used to output the input signal from the output interface corresponding to the received control signal, according to the received control signal. When the input signal is a digital signal, the signal holding circuit includes a digital-to-analog converter circuit, which is used to store the digital signal and convert the digital signal into an analog signal for output. When the input signal is an analog signal, the signal holding circuit includes a sample-and-hold circuit, which includes a holding capacitor, a sampling switch, and an amplifier. The first terminal of the sampling switch is connected to an output terminal of the multiplexed data circuit, and the second terminal of the sampling switch is connected to an electrode corresponding to the chip body. The second terminal of the sampling switch is also grounded through the holding capacitor. The first terminal of the sampling switch is connected to the multiplexed data circuit through the amplifier, and / or the second terminal of the sampling switch is connected to an electrode corresponding to the chip body through the amplifier.

2. The ion trap chip according to claim 1, characterized in that, When the first terminal of the sampling switch is connected to the multiplex data circuit through the amplifier, the non-inverting input terminal of the amplifier is connected to the multiplex data circuit, the output terminal of the amplifier is connected to the first terminal of the sampling switch, and the inverting input terminal of the amplifier is connected to the output terminal of the amplifier.

3. The ion trap chip according to claim 1, characterized in that, When the second terminal of the sampling switch is connected to the electrode corresponding to the chip body through the amplifier, the non-inverting input terminal of the amplifier is connected to the second terminal of the sampling switch, the output terminal of the amplifier is connected to the electrode corresponding to the chip body, and the inverting input terminal of the amplifier is connected to the electrode corresponding to the chip body.

4. The ion trap chip according to claim 1, characterized in that, The ion trap chip also includes: A controller, which generates the control signal.

5. A method for ion movement, characterized in that, Applied to the ion trap chip as described in any one of claims 1-4, the method comprises: Based on the received control signal, the multi-channel data circuit outputs the input signal from the output interface corresponding to the control signal. The voltage of the electrode connected to the output interface corresponding to the control signal is changed to the voltage corresponding to the input signal, so as to change the movement trajectory of ions in the ion trap chip.

6. An electronic device, characterized in that, include: The main body of the electronic device; The ion trap chip as described in any one of claims 1-4, wherein the ion trap chip is electrically connected to the main body of the electronic device.

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