Multi-connected air conditioner communication system

Abstract

The application discloses a multi-connected air conditioner communication system, which comprises a signaling communication node, and the signaling communication node comprises a main controller, a Homebus communication module and an impedance matching circuit. The main controller is provided with a signaling port, a receiving port and a control port. The Homebus communication module is provided with a data output end, a data receiving end, a receiving end and a signaling end. The receiving end and the signaling end are connected to the Homebus bus respectively. The impedance matching circuit is controlled by the signaling state of the main controller. When the main controller signals, the impedance matching circuit is controlled to be connected between the first differential end and the second differential end of the signaling end. When the main controller does not signal, the impedance matching circuit is controlled to be disconnected between the first differential end and the second differential end. At the same time when the main controller signals, the main controller judges whether the sending and the receiving are consistent. The application can realize impedance matching in the communication signal transmission process by introducing the impedance matching circuit, and improve the long-distance transmission and high-quality communication.

Description

Technical Field

[0001] This invention relates to the field of communication technology for multi-split air conditioners, and more particularly to a communication system for multi-split air conditioners. Background Technology

[0002] Multi-split air conditioning systems consist of numerous indoor and outdoor units and wired controllers. Communication between the indoor and outdoor units typically uses the HomeBus (i.e., home bus system) communication protocol. Currently, most multi-split air conditioning systems use the Sanmei Electric MM1192 communication chip as the core, with various communication circuits, drive circuits, and protection circuits integrated in the periphery to form a HomeBus communication system.

[0003] Existing Homebus communication systems that rely on the MM1192 communication chip typically use a communication rate of 9600 baud. Due to design limitations of the communication hardware circuit, they often cannot support higher communication rates and more communication node devices. With the integration of Bluetooth MESH (i.e., wireless mesh networking), NFC, and WIFI functions with multi-split air conditioners, the low communication baud rate of the Homebus communication system leads to low information transmission efficiency, which can no longer meet the functional interaction requirements of multi-split air conditioners with emerging communication technologies, thus restricting the development of multi-split air conditioners.

[0004] When the existing Homebus communication system increases the communication baud rate (higher than the commonly used 9600 baud rate), the differential signal output by the MM1192 communication chip exhibits ringing, resulting in poor communication quality and affecting the normal communication of the air conditioner. Furthermore, the increase in communication nodes further exacerbates the impact on communication quality.

[0005] The information disclosed in this background section is only intended to enhance the understanding of the background technology of this application, and therefore may include prior art that is not known to those skilled in the art. Summary of the Invention

[0006] To address the problems mentioned in the background art, this application provides a multi-split air conditioning communication system. An impedance matching circuit is set at the transmitting communication node. During transmission, it is ensured that only one transmitting communication node's impedance matching circuit is connected to the Homebus at any given time, thereby ensuring impedance matching between the transmitting and receiving communication nodes and improving communication quality and distance.

[0007] To achieve the above-mentioned objectives, the present invention employs the following technical solution:

[0008] This application relates to a multi-split air conditioning communication system, including multiple indoor units and multiple outdoor units connected to a Homebus bus. One of the indoor and outdoor units with a communication relationship is a receiving communication node, and the other is a transmitting communication node. The transmitting communication node includes:

[0009] The main controller has a transmitting port and a receiving port;

[0010] The Homebus communication module has a data output terminal, a data receiving terminal, a receiving terminal, and a transmitting terminal. The data output terminal is connected to the receiving port, the data receiving terminal is connected to the transmitting port, the receiving terminal is connected to the Homebus bus and is used to receive communication data sent by the receiving communication node to the master controller, and the transmitting terminal is connected to the Homebus bus and is used by the master controller to send communication data to the receiving communication node.

[0011] An impedance matching circuit is controlled by the transmitting state of the master controller. When the master controller transmits, the impedance matching circuit is connected between the first differential terminal and the second differential terminal of the transmitting end to match the impedance during the transmission of the communication signal. When the master controller does not transmit, the impedance matching circuit is disconnected between the first differential terminal and the second differential terminal.

[0012] During the sending of a message by the master controller, the master controller itself determines whether the sending and receiving are consistent. If not, it waits for a preset time before sending the message again, until the master controller determines that the sending and receiving are consistent.

[0013] The multi-split air conditioning communication system disclosed in this application incorporates an impedance matching circuit at the transmitting communication node. During high-speed / low-speed transmission, the impedance matching circuit is connected between the first and second differential terminals to match the impedance between the transmitting and receiving communication nodes, reducing signal reflection and improving communication quality. Furthermore, the impedance matching circuit enables communication with receiving communication nodes over long distances, increasing the communication distance. This increased communication distance allows for an increase in the number of communication nodes on the Homebus, facilitating stable communication among multiple nodes.

[0014] Furthermore, the main controller itself determines whether the sending and receiving are consistent, ensuring that only one transmitting communication node's impedance matching circuit is connected to the Homebus at any given time. This prevents multiple impedance matching circuits from being connected to the Homebus simultaneously, which could lead to impedance mismatch between the transmitting and receiving sides and result in poor communication quality.

[0015] In some embodiments of this application, the impedance matching circuit includes:

[0016] The first impedance matching circuit is controlled by the transmitting state of the main controller and its control terminal is connected to the transmitting terminal. One end is connected to the first differential terminal and the other end is connected to the second differential terminal.

[0017] The second impedance matching circuit is controlled by the transmitting state of the main controller and its control terminal is connected to the transmitting terminal. One end is connected to the first differential terminal and the other end is connected to the second differential terminal.

[0018] When the master controller transmits a signal, at least one of the first impedance matching circuit and the second impedance matching circuit is connected between the first differential terminal and the second differential terminal of the transmitting end.

[0019] In some embodiments of this application, the first impedance matching circuit and the second impedance matching circuit have the same structure and both include:

[0020] A switch control circuit includes a switch control element that is turned on at a high level. The control terminal of the switch control element is connected to the transmitting terminal through a coupling capacitor, and one end is connected to the first differential terminal.

[0021] An impedance matching unit, one end of which is connected to the other end of the switch control circuit, and the other end of the impedance matching unit is connected to the second differential terminal.

[0022] When there is a high or low level change in the transmitted signal at the transmitting end, the master controller controls the switching control element of the switching control circuit in the first impedance matching circuit to turn on and / or the switching control element of the switching control circuit in the second impedance matching circuit to turn on, so that the impedance matching unit in the first impedance matching circuit is connected and / or the impedance matching unit in the second impedance matching circuit is connected between the first differential terminal and the second differential terminal.

[0023] When there are high and low level changes in the transmitted signal at the transmitting end, the high and low levels of the first differential terminal / second differential terminal will appear randomly. Therefore, at least one impedance matching circuit must be connected between the first differential terminal and the second differential terminal.

[0024] In some embodiments of this application, the master controller further includes a clock port, the Homebus communication module has a clock signal port connected to the clock port, and the transmitting communication node further includes:

[0025] A bus waveform adjustment circuit receives the clock signal at the clock port and is connected between the first differential terminal and the second differential terminal of the transmitting end. When the clock signal is high, the bus waveform adjustment circuit adjusts and restores the bus differential signal between the first differential terminal and the second differential terminal to an intermediate level.

[0026] The bus differential signal between the first differential terminal and the second differential terminal is an AMI signal that includes high level, middle level and low level.

[0027] Under high-speed communication at the communication node, the bus differential signal between the first differential terminal and the second differential terminal exhibits waveform oscillation when returning to the intermediate level, which reduces the decoding accuracy of the communication module. Therefore, a bus waveform adjustment circuit is set up to accelerate the rate of returning to the intermediate level, reduce signal oscillation, effectively improve the communication decoding accuracy, improve the differential waveform quality, and enhance the anti-interference capability of the communication system.

[0028] In some embodiments of this application, the bus waveform adjustment circuit includes:

[0029] A coupling capacitor, one end of which receives the clock signal;

[0030] Two identical switch control circuits, including a first switch control circuit and a second switch control circuit, wherein the control terminals of the first switch control circuit and the second switch control circuit are respectively connected to the other end of the coupling capacitor, one end of the first switch control circuit is connected to the first differential terminal, and one end of the second switch control circuit is connected to the second differential terminal.

[0031] The voltage output unit outputs the intermediate level at its output terminal, and the other end of the first switch control circuit and the other end of the second switch control circuit are respectively connected to the output terminal.

[0032] In some embodiments of this application, a first coupling capacitor is connected between the first differential terminal of the transmitting end and the bus A of the Homebus bus;

[0033] A second coupling capacitor is connected between the second differential terminal of the transmitting end and the bus B of the Homebus bus;

[0034] One end of the first switch control circuit is connected to the connection point between the first differential terminal and the first coupling capacitor;

[0035] One end of the second switch control circuit is connected to the connection point between the second differential terminal and the second coupling capacitor.

[0036] In some embodiments of this application, the master controller further includes a clock port, and the transmitting communication node further includes:

[0037] The transmission duty cycle adjustment circuit receives the transmission signal sent by the transmission port and the clock signal output by the clock port, and outputs a signal to the data receiving end of the Homebus communication module to convert the duty cycle of the low-level signal in the transmission signal to 50% while maintaining the duty cycle of the high-level signal.

[0038] In some embodiments of this application, the transmission duty cycle adjustment circuit includes:

[0039] Two switch control units, including a first switch control unit and a second switch control unit, the control terminal of the first switch control unit is connected to the transmitting port, the first terminal of the first switch control unit is grounded, the control terminal of the second switch control unit is connected to the clock port, one terminal of the second switch control unit is grounded, and the other terminals of the first switch control circuit and the other terminals of the second switch control circuit are connected at the connection position;

[0040] A filter unit, which includes a grounded capacitor and is connected at the connection location;

[0041] The third switch control unit has its control terminal connected to the connection position, its first terminal connected to the data receiving terminal, and its second terminal grounded.

[0042] The clock signal and the transmission signal are performed by two switch control units to perform a "NOT OR" operation, which changes the duty cycle of the low level in the transmission signal from 100% to 50%. In addition, a filter capacitor is added to filter the signal after the "NOT OR" processing, filter out interference spike signals, and improve the anti-interference capability of the communication system during transmission.

[0043] In some embodiments of this application, the master controller further includes:

[0044] An interrupt port is connected to the transmitting end and the data output end respectively, and is used to enter the interrupt routine of the main controller. In the interrupt routine, it is used to determine whether the sending and receiving of the main controller are consistent.

[0045] A communication conflict detection mechanism is implemented through the interrupt port. When the transmitting communication node finds that its own transmission and reception are inconsistent, it waits for a period of time before trying to send again. This ensures that only one transmitting and receiving communication node is connected to the bus at the same time, preventing multiple impedance matching circuits from being connected to the Homebus at the same time, which would cause impedance mismatch between the transmitting and receiving sides again.

[0046] In some embodiments of this application, a first resistor and a first capacitor are connected in series on the input side of the first receiving terminal from the Homebus bus to the receiving terminal;

[0047] A second resistor and a second capacitor are connected in series on the input side of the second receiving terminal from the Homebus bus to the receiving terminal.

[0048] The transmitting communication node receives signals through a first resistor, a first capacitor, a second resistor, and a second capacitor, and can filter the received signals.

[0049] Other features and advantages of the present invention will become clearer after reading the detailed embodiments of the invention in conjunction with the accompanying drawings. Attached Figure Description

[0050] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0051] Figure 1 Here is a structural block diagram of an existing multi-unit communication system;

[0052] Figure 2 The waveforms of the transmitting signal, clock signal, and bus differential signal in an ideal state are shown in an example of an existing multi-unit communication system.

[0053] Figure 3 The waveforms of the transmitting signal, clock signal, and bus differential signal of an existing multi-unit communication system under high-speed transmission conditions are shown.

[0054] Figure 4 This is a structural block diagram of an embodiment of the multi-unit communication system proposed in this application;

[0055] Figure 5 The circuit diagram is shown for the impedance matching circuit in the multi-unit communication system embodiment proposed in this application;

[0056] Figure 6 The following are waveforms of the transmitting signal, clock signal, and bus differential signal of the transmitting communication node under high-speed communication conditions according to the embodiment of the multi-unit communication system proposed in this application.

[0057] Figure 7 This is a structural block diagram of another embodiment of the multi-unit communication system proposed in this application;

[0058] Figure 8 The circuit diagram of the bus waveform adjustment circuit in another embodiment of the multi-unit communication system proposed in this application is shown.

[0059] Figure 9 This is a structural block diagram of yet another embodiment of the multi-unit communication system proposed in this application;

[0060] Figure 10 This is a circuit diagram of the transmission duty cycle adjustment circuit in another embodiment of the multi-unit communication system proposed in this application;

[0061] Figure 11The following is a waveform diagram of the transmitting signal, clock signal, NOT OR operation output signal, Homebus communication module received signal and bus differential signal in another embodiment of the multi-unit communication system proposed in this application;

[0062] Figure 12 This is a schematic block diagram of the peripheral circuitry that works with the Homebus communication module in an embodiment of the multi-unit communication system proposed in this application.

[0063] Figure label:

[0064] 100 Indoor unit; 110 Main controller; 120 Homebus communication module; 130 Impedance matching circuit; 131 First impedance matching circuit; 132 Second impedance matching circuit; 140 Bus waveform adjustment circuit; 141 Voltage output unit; 150 Transmitter duty cycle adjustment circuit; 160 Voltage protection circuit; 170 Bus drive circuit; 180 Receiver side AC coupling circuit; 190 Transmitter side AC coupling circuit; 200 Outdoor unit; 210 Main controller; 220 Homebus communication module. Detailed Implementation

[0065] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0066] In the description of this application, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0067] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0068] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0069] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0070] The following disclosure provides many different embodiments or examples for implementing various structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the invention. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, examples of various specific processes and materials are provided in this invention, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0071] <Basic Working Principle of Air Conditioners>

[0072] Air conditioners execute a refrigeration cycle using a compressor, condenser, expansion valve, and evaporator. The refrigeration cycle involves a series of processes, including compression, condensation, expansion, and evaporation, to cool or heat an indoor space.

[0073] Low-temperature, low-pressure refrigerant enters the compressor, which compresses it into a high-temperature, high-pressure refrigerant gas and discharges the compressed refrigerant gas. The discharged refrigerant gas flows into the condenser. The condenser condenses the compressed refrigerant into a liquid phase, and the heat is released to the surrounding environment through the condensation process.

[0074] The expansion valve expands the high-temperature, high-pressure liquid refrigerant that condenses in the condenser into a low-pressure liquid refrigerant. The evaporator evaporates the expanded refrigerant in the expansion valve and returns the low-temperature, low-pressure refrigerant gas to the compressor. The evaporator achieves its cooling effect by utilizing the latent heat of refrigerant evaporation to exchange heat with the material being cooled. Throughout the cycle, the air conditioner regulates the temperature of the indoor space.

[0075] The outdoor unit of an air conditioner refers to the part of the refrigeration cycle that includes the compressor and the outdoor heat exchanger. The indoor unit of an air conditioner includes the indoor heat exchanger, and an expansion valve can be provided in either the indoor or outdoor unit.

[0076] The indoor and outdoor heat exchangers function as either condensers or evaporators. When the indoor heat exchanger is used as a condenser, the air conditioner functions as a heater in heating mode; when the indoor heat exchanger is used as an evaporator, the air conditioner functions as a cooler in cooling mode.

[0077] This application relates to a multi-split air conditioning communication system, including a multi-split air conditioner. The basic working principle of the multi-split air conditioner is described above.

[0078] In some embodiments of this application, the multi-split air conditioner includes multiple indoor units and multiple outdoor units that are communicatively connected to a Homebus bus. The indoor units and outdoor units communicate using differential signals on the Homebus bus.

[0079] See Figure 1 It shows four indoor units and two outdoor units connected to the Homebus bus, and the number of indoor and outdoor units is not limited here.

[0080] Both indoor and outdoor units can serve as transmitting communication nodes, and both can also serve as receiving communication nodes that communicate with the transmitting communication node. That is, when the indoor unit serves as the transmitting communication node, the opposite communication node is the outdoor unit, which is also the receiving communication node. When the outdoor unit serves as the transmitting communication node, the opposite communication node is the indoor unit, which is also the receiving communication node.

[0081] In some embodiments of this application, see Figure 1 To enable communication between the indoor and outdoor units, the indoor unit includes a main controller and a Homebus communication module, while the outdoor unit also includes a main controller and a Homebus communication module.

[0082] In some embodiments of this application, the Homebus communication module typically uses the MM1192 communication chip, which receives signals that have undergone Alternate Mark Inversion (AMI) (referred to as AMI signals). When the AMI signal is used and output in a home bus system or the like, it is composed of three values: high level, intermediate level, and low level, and passes through the positive signal line and the negative signal line (i.e., bipolar signal line).

[0083] In communication methods that use this signal, a logic "1" is assigned to the middle level (e.g., +2.5V), and a logic "0" is alternately assigned to the high level (e.g., +5V) and the low level (e.g., 0V).

[0084] All Homebus communication modules have a Homebus bus interface for connecting to the Homebus bus. That is, the Homebus bus interface of the Homebus communication module in the indoor unit and the Homebus bus interface of the Homebus communication module in the outdoor unit are both connected to the Homebus bus.

[0085] The Homebus includes Bus A and Bus B (i.e., bipolar signal lines), and transmits differential bus signals (i.e., AMI signals) on the Homebus.

[0086] Taking indoor unit 100 as an example, the connection between main controller 110 and Homebus communication module 120 is explained.

[0087] The main controller 110 in the indoor unit 100 has a transmitting port IO-TXD, a receiving port IO-RXD, a control port IO-CT, a clock port IO-CLK, and an interrupt port IO-INT.

[0088] The Homebus communication module 120 in the indoor unit 100 has a data output terminal Data Out, a data receiving terminal DataIn, a receiving terminal IN1 / IN2, and a transmitting terminal OUT(A) (denoted as the first differential terminal) / OUT(B) (denoted as the second differential terminal).

[0089] The receiving terminals IN1 / IN2 are connected to the Homebus bus. The first receiving terminal IN1 of the receiving terminals IN1 / IN2 receives the communication signals sent by the peer transmitting communication node to the Homebus communication module 120 through capacitor C1 and resistor Ra, and the second receiving terminal IN2 receives the communication signals sent by the peer transmitting communication node through capacitor C2 and resistor Rb. The data output terminal Data Out is connected to the receiving port IO-RXD and is used to send the communication signals output by the Homebus communication module 120 to the master controller 210, where they are received.

[0090] The transmitting port IO-TXD and the data receiving port Data In are used by the master controller 110 to send transmitting signals to the Homebus communication module 120. The transmitting ports OUT(A) / OUT(B) are connected to the Homebus bus and are used by the Homebus communication module 120 to transmit transmitting signals to the opposite receiving communication node so that they can be received by the Homebus communication module 220 in the opposite receiving communication node.

[0091] Similarly, the main controller 210 and Homebus communication module 220 in outdoor unit 200 have the same connection relationship as the main controller 110 and Homebus communication module 120 in indoor unit 100.

[0092] When using the above communication system for communication, please refer to... Figure 2 It provides waveforms of the transmit signal, clock signal CLOCK, and bus differential signal under ideal conditions.

[0093] Taking the period of transmitting 1 bit as T1, the main controller 110 transmits binary data 1011001, and the clock signal CLOCK of the main controller 110 also has a period of T1 and a duty cycle of 50%.

[0094] After being processed by the Homebus communication module 120, the bus differential signal transmitted on the Homebus bus is the AMI signal, which corresponds to the binary output signal 1011001. That is, the middle level in the AMI signal corresponds to logic "1", and the high level or low level corresponds to logic "0". The duty cycle of the AMI signal corresponding to logic "0" is 50%.

[0095] Depend on Figure 2 As can be seen, under ideal conditions, the communication waveform does not exhibit ringing, indicating good communication quality.

[0096] With the increase in communication speed and the demand for long-distance transmission, communication waveforms appear as follows during high-speed communication: Figure 3 The ringing phenomenon shown in multiple locations affects the communication quality, resulting in a situation where the indoor unit 100 and the outdoor unit 200 cannot communicate normally.

[0097] Therefore, some embodiments of this application mainly relate to the structure of the transmitting communication node. By setting an impedance matching circuit at the transmitting communication node, the impedance matching circuit is controlled to be connected between the first differential terminal and the second differential terminal during high-speed / low-speed transmission, in order to match the impedance between the transmitting and receiving communication nodes.

[0098] That is, when transmitting a signal, the impedance matched by the impedance matching circuit is matched with the impedance of the receiving communication node through the long-distance communication line, which reduces signal reflection during communication, improves communication quality and increases communication distance.

[0099] The increased communication distance allows for an increase in the number of communication nodes on the Homebus, enabling stable communication between multiple nodes over long distances.

[0100] In some embodiments of this application, as described above, the indoor unit 100 and the outdoor unit 200 communicate with each other. Therefore, either one can be used as a transmitting communication node. Thus, an impedance matching circuit 130 is arranged in both the indoor unit 100 and the outdoor unit 200. However, when the indoor unit 100 is used as a transmitting communication node, the impedance matching circuit 130 in the outdoor unit 200 that communicates with it does not work, and when the outdoor unit 200 is used as a transmitting communication node, the impedance matching circuit 130 in the indoor unit 100 that communicates with it does not work.

[0101] See below. Figure 4 The structure of the multi-split air conditioning communication system will be explained using indoor unit 100 as an example of a communication node. Similarly, the outdoor unit 200 will also be arranged accordingly, which will not be elaborated here.

[0102] In some embodiments of this application, the indoor unit 100 includes an impedance matching circuit 130, which is connected between the first differential terminal OUT(A) and the second differential terminal OUT(B) when transmitting signals, and disconnected when not transmitting signals, that is, the impedance matching circuit 130 is not connected between the first differential terminal OUT(A) and the second differential terminal OUT(B).

[0103] Whether the impedance matching circuit 130 is connected between the first differential terminal OUT(A) and the second differential terminal OUT(B) is controlled by whether the master controller 110 sends a signal.

[0104] In some embodiments of this application, the controlled terminal of the impedance matching circuit 130 is connected to the transmitting terminal IO-RXD. When the master controller 110 transmits a signal, the transmitting terminal IO-RXD connects the impedance matching circuit 130 between the first differential terminal OUT(A) and the second differential terminal OUT(B). When the master controller 110 does not transmit a signal, the transmitting terminal IO-RXD does not connect the impedance matching circuit 130 between the first differential terminal OUT(A) and the second differential terminal OUT(B).

[0105] In some embodiments of this application, the impedance matching circuit is connected or disconnected in real time by changing the high or low level of the transmitting signal at the transmitting end IO-RXD.

[0106] Because the AMI signal is transmitted on the Homebus bus, see Figure 2Since the high and low levels of the output signals of the first differential terminal OUT(A) and the second differential terminal OUT(B) are random, in this application, the impedance matching circuit 130 is designed to include a first impedance matching circuit 131 and a second impedance matching circuit 132.

[0107] The first impedance matching circuit 131 has the same structure as the second impedance matching circuit 132, such that when the transmission signal changes between high and low levels, at least the first impedance matching circuit 131 and the second impedance matching circuit 132 are connected between the first differential terminal OUT(A) and the second differential terminal OUT(B).

[0108] To filter the signal, a coupling capacitor C0 is connected between the transmitting end IO-TXD and the controlled end of the impedance matching circuit.

[0109] The transmitted signal is connected to the controlled terminal of the first impedance matching circuit 131 and the controlled terminal of the second impedance matching circuit 132 after passing through the coupling capacitor C0.

[0110] The structure of the first impedance matching circuit 131 will be used as an example for explanation.

[0111] The first impedance matching circuit 131 includes a high-level conducting switch control element and an impedance matching unit.

[0112] The switch control element is controlled by the transmitted signal, with one end connected to the first differential terminal OUT(A) and the other end connected to the impedance matching unit.

[0113] When the switch control element is turned on, the impedance matching unit is connected between the first differential terminal OUT(A) and the second differential terminal OUT(B); when the switch control element is turned off, the impedance matching unit is not connected between the first differential terminal OUT(A) and the second differential terminal OUT(B).

[0114] In some embodiments of this application, see Figure 5 The switch control element is selected as NPN transistor Q1.

[0115] The base of the NPN transistor Q1 can be connected to the coupling capacitor C0 through the base current limiting resistor Rg. A current limiting resistor Rh is also provided between the base and the emitter. The collector is connected to the first differential terminal OUT(A), the emitter is connected to one end of the impedance matching unit, and the other end of the impedance matching unit is connected to the second differential terminal OUT(B).

[0116] The base current limiting resistor Rg is used to limit the current flowing into the base of NPN transistor Q1, preventing Q1 from burning out when the level at the control port IO-CT is unstable or high, thus protecting NPN transistor Q1.

[0117] In some embodiments of this application, see also Figure 5 The impedance matching unit includes a current-limiting resistor Re, and may also include a current-limiting resistor and a matching capacitor connected in parallel.

[0118] Similarly, the impedance matching unit in the second impedance matching circuit includes a current-limiting resistor Rd.

[0119] The high and low levels of the output signals from the first differential terminal OUT (A) and the second differential terminal OUT (B) are random. Therefore, the first impedance matching circuit 131 and the second impedance matching circuit 132 are set up in parallel as described above to ensure that when the high-level pulse signal of the coupling capacitor C0 arrives, the AC pulse signal transmitted through the coupling capacitor C0 automatically controls at least one NPN transistor Q1 and NPN transistor Q2 to be turned on. This ensures that the impedance matching resistors Rc and Rd are connected to the Homebus during the transmission period to achieve impedance matching with the bus on the receiving side.

[0120] When the main controller is not transmitting, the output of the IO-TXD pin of the transmitting end can be automatically set to a high level. The coupling capacitor C0 receives the DC high-level signal of IO-TXD, and both NPN transistors Q1 and Q2 are not turned on. The impedance matching circuit does not work, which prevents interference with the outdoor transmitting signal when the outdoor side is transmitting, and avoids communication power consumption caused by long-term connection to the bus.

[0121] Thus, by using impedance matching circuit 130 for impedance matching during transmission, the impedance can be improved. Figure 3 For the waveform oscillation phenomenon at positions ① and ②, see [link to documentation]. Figure 6 .

[0122] When multiple indoor units in the communication system are transmitting signals simultaneously, a conflict detection mechanism is implemented through the IO-INT pin of the interrupt port.

[0123] While the indoor unit, acting as the communication node, transmits signals, it also receives signals through capacitors C1 and C2, resistors Ra and Rb, and simultaneously enters the interrupt routine through the interrupt port IO-INT.

[0124] In the interrupt routine, the master controller performs a self-transmission and self-reception judgment to determine whether the self-transmitted data and the self-received data are consistent. If they are consistent, it means that the transmission was successful. If they are inconsistent, it means that there is a Homebus bus conflict and other communication nodes are sending signals at the same time. At this time, it waits for a certain period of time and then tries to send again until the self-transmission and self-received data are consistent.

[0125] like Figure 3As shown, in high-speed communication, waveform oscillation will also occur when the clock signal CLOCK returns to the middle level of the corresponding bus differential signal during the high level period, i.e., at positions ③ and ④. Therefore, in order to improve the waveform in this case, the indoor unit 100 also includes a bus waveform adjustment circuit 140.

[0126] See Figure 7 The bus waveform adjustment circuit 140 receives the clock signal CLOCK at the clock port IO-CLK and connects it between the first differential terminal OUT(A) and the second differential terminal OUT(B) of the transmitting end. When the clock signal CLOCK is high, the bus waveform adjustment circuit 140 adjusts the bus differential signal between the first differential terminal OUT(A) and the second differential terminal OUT(B) to the intermediate level.

[0127] When the clock signal CLOCK is high, the bus waveform adjustment circuit 140 quickly pulls the bus differential signal back to the intermediate level. When the clock signal CLOCK is low, the bus waveform adjustment circuit 140 does not function.

[0128] In some embodiments of this application, see Figure 8 The bus waveform adjustment circuit 140 includes a coupling capacitor C4, a first switch control circuit, a second switch control circuit, and a voltage output unit 141.

[0129] The first switch control circuit and the second switch control circuit have the same structure, so they can both receive the control of the clock signal CLOCK.

[0130] One end of the coupling capacitor C4 receives the clock signal CLOCK, and the other end is connected to the control terminal of the first switch control circuit and the control terminal of the second switch control circuit.

[0131] One end of the first switch control circuit is connected to the first differential terminal OUT(A), one end of the second switch control circuit is connected to the second differential terminal OUT(B), and the other ends of the first switch control circuit and the other ends of the second switch control circuit are connected together to form the connection position ST1.

[0132] The voltage output unit 141 is used to output an intermediate level at its output terminal, and the connection position ST1 is connected to the output terminal.

[0133] In some embodiments of this application, see Figure 7 A transmitting bus coupling capacitor Cx is provided on the line connecting the first differential terminal OUT(A) to bus A, and a transmitting bus coupling capacitor Cy is provided on the line connecting the second differential terminal OUT(B) to bus B.

[0134] One end of the first switch control circuit is connected between the first differential terminal OUT(A) and the transmitter bus coupling capacitor Cx, that is, connected to the input side of the transmitter bus coupling capacitor Cx; one end of the second switch control circuit is connected between the second differential terminal OUT(B) and the transmitter bus coupling capacitor Cy, that is, connected to the input side of the transmitter bus coupling capacitor Cy.

[0135] In some embodiments of this application, the first switch control circuit and the second switch control circuit select a switch control element that is turned on by a high level.

[0136] The switching element that conducts at a high level is an NPN transistor.

[0137] The voltage output unit 141 is selected as a voltage divider circuit capable of outputting an intermediate level, including voltage balancing resistors Rd and Re connected in series between Vcc and ground, voltage balancing capacitor Cd connected in parallel with voltage balancing resistor Rd, and voltage balancing capacitor Ce connected in parallel with voltage balancing resistor Re.

[0138] The coupling capacitor C4 is connected to the clock signal CLOCK output by the main controller 110.

[0139] When the clock signal CLOCK is high, the coupling capacitor C4 couples the clock signal CLOCK to the input terminals of NPN transistor Q2 and NPN transistor Q3 respectively. NPN transistors Q2 and Q3 are turned on. Therefore, the intermediate level of Vcc / 2 output by voltage output unit 141 is placed between the first differential terminal OUT (A) and the second differential terminal OUT (B). At this time, the communication waveform of the bus differential signal output returns to the intermediate level.

[0140] Thus, by adding the bus waveform adjustment circuit 140, when the clock signal CLOCK input is high, the communication waveforms output from the first differential terminal OUT (A) and the second differential terminal OUT (B) can be quickly pulled to the intermediate level (positions ③ and ④) through the voltage balancing function of the voltage balancing resistors Rd and Re and the voltage balancing capacitors Cd and Ce, thereby accelerating the rate of return to the intermediate level.

[0141] Furthermore, the charging and discharging balancing voltage of the voltage balancing resistors Rd and Re and the voltage balancing capacitors Cd and Ce further reduces the impact of ringing on the bus differential signal, weakens signal oscillation, effectively improves communication quality, prevents the oscillation signal from exceeding the decoding threshold of the Homebus communication module 120, and reduces interference.

[0142] After adopting the bus waveform adjustment circuit 140, see [link to relevant documentation]. Figure 6 Improved in Figure 3The waveform oscillations at positions ③ and ④ accelerate the rate at which the bus differential signal returns to the intermediate level, thus improving the communication waveform quality.

[0143] To improve the anti-interference capability of signals input to the Homebus communication module 120, in some embodiments of this application, see [reference needed]. Figure 9 It also includes a transmission duty cycle adjustment circuit 150, which receives the transmission signal sent by the transmission port IO-TXD and the clock signal CLOCK output by the clock port IO-CLK, and outputs a signal to the data receiving terminal Data In of the Homebus communication module 120 to convert the duty cycle of the low-level signal in the transmission signal to 50% while maintaining the duty cycle of the high-level signal.

[0144] In some embodiments of this application, the transmission duty cycle adjustment circuit 150 includes a first switch control unit, a second switch control unit, a filter unit, and a third switch control unit.

[0145] The first switch control unit and the second switch control unit have the same structure.

[0146] The control terminal of the first switch control unit is connected to the transmitter port IO-TXD, and the control terminal of the second switch control unit is connected to the clock port IO-CLK. One end of the first switch control unit and one end of the second switch control unit are both grounded, and the other ends of the first switch control unit and the other ends of the second switch control unit are connected together (i.e., connected at the connection position).

[0147] The filtering unit includes a grounding capacitor C4 and is connected between the connection position ST2 and the control terminal of the third switch control unit. It is used to filter the signal output at the connection position to improve the anti-interference capability of the communication system during transmission.

[0148] One end of the third switch control unit is grounded, and the other end is connected to the data receiving terminal Data In; the grounding capacitor C4 is connected between the connection position and the third switch control unit.

[0149] In some embodiments of this application, both the first switch control unit and the second switch control unit are selected as switch units that are turned on by high-level control.

[0150] The switching unit that is turned on at a high level is an NPN transistor.

[0151] See Figure 10 The first switch control unit is an NPN transistor Q3, and the second switch control unit is an NPN transistor Q4.

[0152] To facilitate the operation of NPN transistors Q3 and Q4, a pull-up resistor Re is used to pull them up when the collectors of NPN transistors Q3 and Q4 are connected together at connection point ST2.

[0153] In some embodiments of this application, the third switch control unit selects a switch unit that is turned on by high-level control, and NPN transistor Q5 can be selected.

[0154] The base of NPN transistor Q5 is connected to the connection point ST2 and the non-grounded terminal of grounding capacitor C4, the emitter is grounded, the collector is connected to pull-up resistor Rf, and the data receiving terminal Data In is connected between pull-up resistor Rf and collector of NPN transistor Q5.

[0155] NPN transistors Q3 and Q4 perform the "NOT OR" operation on the transmitter signal and the clock signal.

[0156] The NPN transistor Q5 performs the inverse operation after the "NOT OR" operation.

[0157] That is, when the transmitter port IO-TXD outputs a high level and the clock port IO-CLK outputs a high level, the connection point ST2 (i.e., the NOT OR operation output) outputs a low level; when the transmitter port IO-TXD outputs a high (or low) level and the clock port IO-CLK outputs a low (or high) level, the connection point ST2 outputs a low level; when the transmitter port IO-TXD outputs a low level and the clock port IO-CLK outputs a low level, the connection point ST2 outputs a high level.

[0158] like Figure 11 As shown, when the transmitting signal is on the rising edge and the clock signal is on the falling edge (see...) Figure 11 When the signal is within the dashed box, the transmitting signal and the clock signal change simultaneously. Therefore, NPN transistors Q3 and Q4 may be turned off simultaneously, resulting in an incorrect high-level output after the NOR operation (see [link]). Figure 11 The spike in the middle of the spike caused an error signal to be sent to the Homebus communication module 120.

[0159] As described above, the filtering unit is set after the "NOT OR" operation to filter out high-level spike signals and improve the anti-interference capability of the communication system during transmission.

[0160] In some embodiments of this application, when using the Homebus communication module 120 to form a communication system for a multi-split air conditioner, an external circuit that cooperates with the Homebus communication module 120 is also required. The external circuit is set up to meet the communication needs of the Homebus communication module 120.

[0161] The following description focuses only on the peripheral circuit of the Homebus communication module 120 on the indoor unit 100 side. The corresponding peripheral circuit on the outdoor unit 200 side can be configured accordingly.

[0162] See Figure 12 The peripheral circuits mentioned above include: voltage protection circuit 160, bus drive circuit 170, signal coupling circuit, etc.

[0163] A voltage protection circuit 160 is connected between bus A and bus B of the Homebus bus for overvoltage, overcurrent and other protection to protect the subsequent circuits. It can be implemented using overcurrent and overvoltage protection circuits known in the prior art.

[0164] When the Homebus communication module 120 uses the MM1192 communication chip, due to the technical requirements of the MM1192 communication chip, a bus drive circuit 170 is also connected between bus A and bus B to drive and amplify the signal output from the transmitting side.

[0165] The signal coupling circuit includes a receiving-side AC coupling circuit 180 and a transmitting-side AC coupling circuit 190.

[0166] Signals from the Homebus are transmitted to the receiving-side AC coupling circuit 180 after passing through the voltage protection circuit 160. This circuit is used to receive communication signals from the Homebus. The receiving-side AC coupling circuit 180 is implemented by selecting appropriate resistors and capacitors to ensure that the signals received from the Homebus are filtered out from noise such as DC signals.

[0167] The signal output from the Homebus communication module 120 is transmitted to the Homebus bus through the transmitting-side AC coupling circuit 190 and the voltage protection circuit 160. The transmitting-side AC coupling circuit 190 is used to send communication signals to the Homebus bus. The appropriate coupling capacitor is selected according to the communication signal frequency of the Homebus communication module 120 to ensure that the signal sent to the Homebus bus is filtered out of noise such as DC signals.

[0168] In this embodiment, both the transmitting-side AC coupling circuit 190 and the receiving-side AC coupling circuit 180 can be implemented using coupling circuits known in the prior art.

[0169] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0170] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A multi-split air conditioning communication system, characterized in that, include: Multiple indoor units and multiple outdoor units are connected to the Homebus bus. One of the indoor and outdoor units with communication relationships is a receiving communication node, and the other of the indoor and outdoor units is a transmitting communication node. The transmitting communication node includes: The main controller has a transmitting port and a receiving port; The Homebus communication module has a data output terminal, a data receiving terminal, a receiving terminal, and a transmitting terminal. The data output terminal is connected to the receiving port, the data receiving terminal is connected to the transmitting port, the receiving terminal is connected to the Homebus bus and is used to receive communication data sent by the transmitting communication node to the master controller, and the transmitting terminal is connected to the Homebus bus and is used by the master controller to send communication data to the receiving communication node. An impedance matching circuit is controlled by the transmitting state of the master controller. When the master controller is transmitting, the impedance matching circuit is connected between the first differential terminal and the second differential terminal of the transmitting end to match the impedance during the transmission of the communication signal. When the master controller is not transmitting, the impedance matching circuit is disconnected between the first differential terminal and the second differential terminal. During the sending of a message by the master controller, the master controller itself determines whether the sending and receiving are consistent. If not, it waits for a preset time before sending the message again, until the master controller determines that the sending and receiving are consistent.

2. The multi-split air conditioning communication system according to claim 1, characterized in that, The impedance matching circuit includes: The first impedance matching circuit is controlled by the transmitting state of the main controller and its control terminal is connected to the transmitting terminal. One end is connected to the first differential terminal and the other end is connected to the second differential terminal. The second impedance matching circuit is controlled by the transmitting state of the main controller and its control terminal is connected to the transmitting terminal. One end is connected to the first differential terminal and the other end is connected to the second differential terminal. When the master controller transmits a signal, at least one of the first impedance matching circuit and the second impedance matching circuit is connected between the first differential terminal and the second differential terminal of the transmitting end.

3. The multi-split air conditioning communication system according to claim 2, characterized in that, The first impedance matching circuit and the second impedance matching circuit have the same structure and both include: A switch control circuit includes a switch control element that is turned on at a high level. The control terminal of the switch control element is connected to the transmitting terminal through a coupling capacitor, and one end is connected to the first differential terminal. An impedance matching unit, one end of which is connected to the other end of the switch control circuit, and the other end of the impedance matching unit is connected to the second differential terminal. When there is a high or low level change in the transmitted signal at the transmitting end, the master controller controls the switching control element of the switching control circuit in the first impedance matching circuit to turn on and / or the switching control element of the switching control circuit in the second impedance matching circuit to turn on, so that the impedance matching unit in the first impedance matching circuit is connected and / or the impedance matching unit in the second impedance matching circuit is connected between the first differential terminal and the second differential terminal.

4. The multi-split air conditioning communication system according to claim 1, characterized in that, The master controller also includes a clock port, and the Homebus communication module has a clock signal port connected to the clock port. The transmitting communication node also includes: A bus waveform adjustment circuit receives the clock signal at the clock port and is connected between the first differential terminal and the second differential terminal of the transmitting end. When the clock signal is high, the bus waveform adjustment circuit adjusts and restores the bus differential signal between the first differential terminal and the second differential terminal to an intermediate level. The bus differential signal between the first differential terminal and the second differential terminal is an AMI signal that includes high level, middle level and low level.

5. The multi-split air conditioning communication system according to claim 4, characterized in that, The bus waveform adjustment circuit includes: A coupling capacitor, one end of which receives the clock signal; Two identical switch control circuits, including a first switch control circuit and a second switch control circuit, wherein the control terminals of the first switch control circuit and the second switch control circuit are respectively connected to the other end of the coupling capacitor, one end of the first switch control circuit is connected to the first differential terminal, and one end of the second switch control circuit is connected to the second differential terminal. The voltage output unit outputs the intermediate level at its output terminal, and the other end of the first switch control circuit and the other end of the second switch control circuit are respectively connected to the output terminal.

6. The multi-split air conditioning communication system according to claim 5, characterized in that, A first coupling capacitor is connected between the first differential terminal of the transmitting end and the bus A of the Homebus bus; A second coupling capacitor is connected between the second differential terminal of the transmitting end and the bus B of the Homebus bus; One end of the first switch control circuit is connected to the connection point between the first differential terminal and the first coupling capacitor; One end of the second switch control circuit is connected to the connection point between the second differential terminal and the second coupling capacitor.

7. The multi-split air conditioning communication system according to claim 1, characterized in that, The master controller also includes a clock port, and the transmitting communication node also includes: The transmission duty cycle adjustment circuit receives the transmission signal sent by the transmission port and the clock signal output by the clock port, and outputs a signal to the data receiving end of the Homebus communication module to convert the duty cycle of the low-level signal in the transmission signal to 50% while maintaining the duty cycle of the high-level signal.

8. The multi-split air conditioning communication system according to claim 7, characterized in that, The transmission duty cycle adjustment circuit includes: Two switch control units, including a first switch control unit and a second switch control unit, the control terminal of the first switch control unit is connected to the transmitting port, and the first terminal of the first switch control unit is grounded; the control terminal of the second switch control unit is connected to the clock port, one terminal of the second switch control unit is grounded, and the other terminals of the first switch control unit and the other terminals of the second switch control unit are connected at the connection position. A filter unit, which includes a grounded capacitor and is connected at the connection location; The third switch control unit has its control terminal connected to the connection position, its first terminal connected to the data receiving terminal, and its second terminal grounded.

9. The multi-split air conditioning communication system according to claim 1, characterized in that, The main controller also includes: An interrupt port is connected to the transmitting end and the data output end respectively, and is used to enter the interrupt routine of the main controller. In the interrupt routine, it is used to determine whether the sending and receiving of the main controller are consistent.

10. The multi-split air conditioning communication system according to claim 9, characterized in that, A first resistor and a first capacitor are connected in series on the input side of the first receiving terminal from the Homebus bus to the receiving terminal; A second resistor and a second capacitor are connected in series on the input side of the second receiving terminal from the Homebus bus to the receiving terminal.

Images