Superconducting quantum ring isolator and method of making same

Abstract

The application discloses a superconducting ring spacer and a preparation method thereof, which greatly simplifies a superconducting quantum test system, is beneficial to the large-scale development of a superconducting quantum computing circuit, and realizes compatibility with a superconducting integrated circuit in a preparation process, so that the superconducting quantum test system is greatly simplified, and the large-scale development of the superconducting quantum computing circuit is facilitated.

Description

Technical Field

[0001] This application relates to, but is not limited to, the field of quantum computing technology, and in particular to a superconducting quantum ring spacer and its preparation method. Background Technology

[0002] In current superconducting quantum testing systems, quantum information is read out through a readout cavity on a quantum chip, and then output after passing through a series of independent devices such as filters, isolators, circulators, and reflective quantum amplifiers. However, traditional isolators and circulators are bulky and suffer from significant heat loss, which is detrimental to the large-scale development of superconducting quantum computing circuits. Summary of the Invention

[0003] This application provides a superconducting quantum ring spacer and its fabrication method, which can be used to construct large-scale superconducting quantum computers, greatly simplifying the superconducting quantum testing system and facilitating the large-scale development of superconducting quantum computing circuits.

[0004] This invention provides a superconducting quantum ring isolator, comprising: a circulator integrated on a single chip, two or more isolators, three or more capacitors, and three bias line circuits; wherein,

[0005] The circulator is a four-port on-chip superconducting circulator, with one port impedance-matched to a load, two ports used for cascaded isolators, and one port used as an input / output port for a superconducting quantum circulator isolator; the input / output ports of the circulator are connected to baluns.

[0006] The isolator is a two-port device. It uses two ports of a four-port on-chip superconducting circulator to impedance match the load. One of the other two ports is used for cascading circulators or isolators, and the other port is used as an input / output port of a superconducting quantum ring isolator or for cascading isolators. The isolator is used to convert the input signal to the output. The input port and output port of the isolator are respectively connected to baluns.

[0007] Capacitors are placed in the isolator and circulator, and the center operating frequency of the superconducting quantum ring isolator is adjusted by adjusting the capacitance value of the capacitors.

[0008] The bias line circuit is used to adjust the bias magnetic field of the superconducting quantum ring spacer. Each bias line of the bias line circuit is connected to a filter.

[0009] In one exemplary instance, the filter is a low-pass filter (LPF).

[0010] In one exemplary instance, the three bias line circuits extend through the isolator and the circulator, and include: a bias line circuit for a cosine signal, a bias line circuit for a sine signal, and a global magnetic field bias line circuit.

[0011] In one exemplary instance, one port of the circulator is impedance-matched to a load and the two ports of the isolator are impedance-matched to loads respectively, including: respectively connecting resistors with a pre-resistance of 50 ohms;

[0012] Alternatively, the impedance matching load at one port of the circulator and the impedance matching loads at the two ports of the isolator respectively include: coplanar waveguides CPW connected to λ / 4 wavelengths respectively.

[0013] In one exemplary instance, the superconducting quantum ring isolator is a three-port device, wherein the input terminal of the superconducting quantum ring isolator port 1 of the first stage isolator, and the output terminal of the superconducting quantum ring isolator port 2 and the last stage isolator port 3;

[0014] The isolator includes two units; the circulator includes one unit; and the capacitors include eight units, with two capacitors respectively provided in each isolator and each circulator.

[0015] The three bias line circuits include a bias line circuit for a Cosine signal, a bias line circuit for a Sine signal, and a global magnetic field bias line circuit.

[0016] The balun comprises three units, and the filter comprises eight units, all of which are LPFs.

[0017] The impedance matching load consists of five 50Ω gold ingot resistors or five λ / 4 wavelength CPWs.

[0018] In one exemplary instance, it also includes: a superconducting quantum interference device (SQUID) array disposed in the isolator and the circulator;

[0019] The SQUID array comprises 576 SQUIDs, with 192 SQUIDs configured in each of the isolators and the circulator;

[0020] The superconducting quantum ring isolator is based on an adjustable Wheatstone inductor bridge, the inductor being composed of the SQUID string.

[0021] This application also provides a method for fabricating a superconducting quantum ring spacer, characterized in that the method for fabricating the superconducting quantum ring spacer described in any of the above claims includes:

[0022] The first sample was obtained by growing silicon dioxide (SiO2) thin films on both sides of a silicon wafer using a thermal oxidation method.

[0023] Multiple patterns of the superconducting quantum ring spacer are formed by sequentially performing photolithography on the front side of the first sample.

[0024] The superconducting quantum ring spacer is formed by processing the reverse side of the sample after multiple patterns are formed.

[0025] In one exemplary instance, the multiple photolithography steps include ten steps;

[0026] The process of sequentially performing multiple photolithography steps on the front side of the first sample to form multiple patterns of the superconducting quantum ring spacer includes:

[0027] The first photolithography is performed on the front side of the first sample to prepare three thin A layers, and the first pattern is peeled off to obtain the second sample;

[0028] A superconducting Nb thin film B was prepared on the front side of the second sample. A second photolithography was performed to etch the Nb thin film. A first SiO2 thin film was then grown as the first protective layer of the superconducting Nb thin film B. The second pattern was then peeled off to obtain the third sample.

[0029] Thin film C is prepared on the front side of the third sample, a third photolithography is performed, and the third pattern is etched to obtain the fourth sample;

[0030] A fourth photolithography was performed on the front side of the fourth sample, and SiO2 and Al-AlOx were etched to obtain a through-hole pattern, thus obtaining the fifth sample.

[0031] A fifth photolithography was performed on the front side of the fifth sample to prepare an Au thin film E, and the fifth pattern was obtained by peeling it off to obtain the sixth sample.

[0032] On the front side of the sixth sample, a SiO2 thin film was prepared as a dielectric layer for capacitors and cross-line by plasma-enhanced chemical vapor deposition (PECVD). Then, a sixth photolithography was performed and etched to obtain the sixth pattern, namely the SiO2 dielectric layer pattern, to obtain the seventh sample.

[0033] A superconducting Nb thin film G is prepared on the front side of the seventh sample, and then a seventh photolithography is performed and etched to obtain the seventh pattern, so as to obtain the eighth sample. The seventh pattern includes: a cross-line pattern, a capacitor upper electrode pattern, a Balun pattern, and an LPF pattern.

[0034] A second SiO2 thin film was grown on the front side of the eighth sample as a second protective layer for the Nb thin film G. Then, the eighth photolithography was performed and etched to obtain the through-hole pattern to obtain the ninth sample.

[0035] A Nb thin film I was prepared on the front side of the ninth sample, and then a ninth photolithography was performed and etched to obtain the ninth pattern, namely the bias line pattern, to obtain the tenth sample.

[0036] The tenth photolithography is performed on the front side of the tenth sample to etch SiO2 in the blank areas of the device, thus obtaining the tenth pattern and the eleventh sample.

[0037] In one exemplary instance, processing the reverse side of the sample after forming multiple patterns to form the superconducting quantum ring spacer includes:

[0038] An Al thin film was prepared on the reverse side of the eleventh sample to obtain the superconducting quantum ring spacer.

[0039] In one exemplary instance, the multiple photolithography steps include four steps;

[0040] The process of sequentially performing multiple photolithography steps on the front side of the first sample to form multiple patterns of the superconducting quantum ring spacer includes:

[0041] The first photolithography is performed on the front side of the first sample to prepare a three-layer thin film A, and the first pattern is obtained by peeling it off to obtain the second sample;

[0042] A Nb thin film B is prepared on the front side of the second sample. A second photolithography is performed to etch the Nb thin film. A first SiO2 thin film is then grown as a protective layer for the Nb thin film B. The second pattern is then peeled off to obtain the third sample.

[0043] A superconducting metal film C is prepared on the front side of the third sample, a third photolithography is performed, and the third pattern is etched to obtain the fourth sample;

[0044] The fourth photolithography was performed on the front side of the fourth sample to prepare an Au thin film D, and the eleventh pattern was obtained by peeling it off to obtain the twelfth sample.

[0045] In one exemplary instance, processing the reverse side of the sample after forming multiple patterns to form the superconducting quantum ring spacer includes:

[0046] A superconducting Al thin film was prepared on the reverse side of the twelfth sample to obtain the superconducting quantum ring spacer.

[0047] In one exemplary instance, the thickness of the thin film A is 300–330 nm;

[0048] The material of the thin film A includes three layers: Nb, Al-AlOx, and Nb.

[0049] In one exemplary instance, the thickness of the thin film A is 330 nm.

[0050] In one exemplary instance, the thickness of the Nb thin film B is 160 nm; the thickness of the first protective layer is 100–250 nm.

[0051] In one exemplary instance, the thickness of the first protective layer is 250 nm.

[0052] In one exemplary instance, the thickness of the thin film C is 150–300 nm; the material of the thin film C is Nb.

[0053] In one exemplary instance, the thickness of the thin film C is 160 nm.

[0054] In one exemplary instance, the thickness of the Au thin film E is 135–225 nm.

[0055] In one exemplary instance, the thickness of the Au thin film E is 225 nm.

[0056] In one exemplary instance, the thickness of the SiO2 dielectric layer is 300–500 nm.

[0057] In one exemplary instance, the thickness of the SiO2 dielectric layer is 250 nm.

[0058] In one exemplary instance, the thickness of the Nb thin film G is 300–600 nm.

[0059] In one exemplary instance, the thickness of the Nb thin film G is 160 nm.

[0060] In one exemplary instance, the thickness of the second protective layer is 300–500 nm.

[0061] In one exemplary instance, the thickness of the second protective layer is 250 nm.

[0062] In one exemplary instance, the thickness of the Nb thin film I is 300–600 nm.

[0063] In one exemplary instance, the thickness of the Nb thin film I can be 160 nm.

[0064] In one exemplary instance, the thickness of the Au thin film E is 135–225 nm.

[0065] In one exemplary instance, the thickness of the Au thin film E is 225 nm.

[0066] In one exemplary instance, the thickness of the Al film is 300–600 nm.

[0067] In one exemplary instance, the Al film has a thickness of 600 nm.

[0068] The superconducting quantum ring spacer provided in this application embodiment is suitable for building large-scale superconducting quantum computers, greatly simplifies the superconducting quantum testing system, and is conducive to the large-scale development of superconducting quantum computing circuits.

[0069] The fabrication method of the superconducting quantum ring spacer provided in this application is compatible with superconducting integrated circuits in terms of process, which greatly simplifies the superconducting quantum testing system and is conducive to the large-scale development of superconducting quantum computing circuits.

[0070] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the description, claims, and drawings. Attached Figure Description

[0071] The accompanying drawings are used to provide a further understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0072] Figure 1 This is a schematic diagram of the composition and structure of the superconducting quantum ring spacer in the embodiments of this application;

[0073] Figure 2 This is a schematic flowchart of one embodiment of the method for fabricating a superconducting quantum ring spacer in this application.

[0074] Figure 3(a) shows the embodiment of this application. Figure 2 A schematic diagram of the layout of an on-chip superconducting quantum ring spacer ICI-1 in one of the fabrication methods shown;

[0075] Figure 3(b) shows the implementation of this application. Figure 2 A schematic diagram of the layout of another on-chip superconducting quantum ring spacer ICI-2 in one of the fabrication methods shown;

[0076] Figure 3(c) shows the implementation of this application. Figure 2 A schematic diagram of the core region layout of an on-chip superconducting control multiplexer in one of the fabrication methods shown in the figure;

[0077] Figure 3(d) shows the implementation of this application. Figure 2 A schematic diagram of the design of the alignment mark in one of the preparation methods shown;

[0078] Figure 3(e) shows the implementation of this application. Figure 2 A schematic cross-sectional view of one of the preparation methods shown;

[0079] Figure 4(a) shows the embodiment of this application. Figure 2 A schematic diagram of the layout of an on-chip superconducting quantum ring spacer ICI-2 in another fabrication method shown;

[0080] Figure 4(b) shows the implementation method used in this application. Figure 2 A schematic diagram of the layout of another on-chip superconducting quantum ring spacer ICI-2 in another fabrication method shown;

[0081] Figure 4(c) shows the implementation of this application. Figure 2 A schematic diagram of the core region layout of the on-chip superconducting control multiplexer in another fabrication method shown;

[0082] Figure 4(d) shows the implementation method used in this application. Figure 2 A schematic diagram of the alignment mark design in another preparation method shown;

[0083] Figure 4(e) shows the implementation of this application. Figure 2 A cross-sectional view of another preparation method shown. Detailed Implementation

[0084] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be arbitrarily combined with each other.

[0085] Figure 1 This is a schematic diagram of the composition and structure of the superconducting quantum ring spacer in the embodiments of this application, as shown below. Figure 1 As shown, it includes: a circulator 11 integrated on a single chip, two or more isolators 10, three or more capacitors 12, and three bias line circuits 13; wherein,

[0086] Circulator 11 is a four-port on-chip superconducting circulator, one port of which is impedance-matched to load 9, two ports of which are used for cascading isolators 10, and one port of which is used as an input / output port of a superconducting quantum circulator isolator; the input / output ports of circulator 11 are connected to balun 8.

[0087] Isolator 10 is a two-port device. It can be impedance matched to load 9 through two ports of a four-port on-chip superconducting circulator. One of the other two ports is used to cascade circulator 11 or isolator 10, and the other port is used as an input / output port of a superconducting quantum ring isolator or to cascade isolator 10. Isolator 10 is used to convert the input signal to the output. The input port of isolator 10 and the output port of isolator 4 are respectively connected to balun 8.

[0088] Capacitor 12 is installed in isolator 10 and circulator 11. The center operating frequency of the superconducting quantum ring isolator is adjusted by adjusting the capacitance value of the capacitor.

[0089] The bias line circuit 13 is used to adjust the bias magnetic field of the superconducting quantum ring spacer. Each bias line of the bias line circuit is connected to a filter 7.

[0090] In one embodiment, the four ports of the circulator 11, arranged in a clockwise direction, respectively include as follows: Figure 1 Port b1 in the middle, such as Figure 1 Port b2 in, such as Figure 1 Port b3 in, such as Figure 1 Port b4 in the middle, one of the ports is as follows Figure 1 Port b1 in the diagram is an impedance-matched load, where two ports are as follows: Figure 1 Ports b2 and b4 are used for cascading isolators, one of which is as follows: Figure 1 Port b3 in the circuit is used as an input / output port of the superconducting quantum ring isolator.

[0091] In one embodiment, the isolator 10 is also a four-port on-chip superconducting circulator, with the four ports respectively including, in a clockwise direction, the following... Figure 1 Port a1 in the example Figure 1 Port a2 in the example Figure 1 Port a3 in the example Figure 1 Port a4 in the middle, two of which are like Figure 1 Ports a3 and a4 in the diagram are impedance-matched loads, with one port as shown in the diagram. Figure 1 Port a2 in the diagram is used for cascading circulators, one of which is as follows: Figure 1 Port a1 in the diagram is used as an input / output port of the superconducting quantum ring isolator; in one embodiment, isolator 4 is also a four-port on-chip superconducting ring, and the four ports of the isolator, in a clockwise direction, respectively include the following... Figure 1 Port c1 in, such as Figure 1 Port c2 in, such as Figure 1 Port c3 in, such as Figure 1 Port c4 in the middle, two of which are as follows Figure 1 Ports C3 and C4 in the circuit are impedance-matched loads and connected to resistors with preset resistance values. One of the ports is as follows: Figure 1 Port c1 in the configuration is used for cascading circulators, one of which is as follows: Figure 1 Port c2 in the chip is used as an input / output port of the on-chip superconducting ring isolator.

[0092] In one exemplary instance, filter 7 is used to isolate the microwave field from the bias line, preventing the radio frequency bias signal from interfering with the operation of the microwave circuit, while reducing additional losses from coupling with the bias line. In one embodiment, filter 7 may include, but is not limited to, a low-pass filter (LPF).

[0093] In one exemplary instance, three bias line circuits 13 run through the isolator 10 and circulator 11 in all superconducting quantum ring isolators (e.g., Figure 1 The two isolators 10 and one circulator 11 shown in the diagram, and the three bias line circuits 13 may include: a bias line circuit for a Cosine signal, a bias line circuit for a Sine signal and a global magnetic field bias line circuit.

[0094] In one exemplary instance, Baron 8 (such as...) Figure 1 Balun18, Balun28, and Balun38 are used to realize the conversion structure between balanced and unbalanced transmission lines, that is, the conversion between coplanar waveguides (CPWs) and microstrip lines.

[0095] In one exemplary instance, two of the ports of isolator 10 used for impedance matching are respectively connected to resistors 9 with pre-valued resistances. In one embodiment, resistor 9 is a 50Ω gold ingot resistor; or, two of the ports of isolator 10 used for impedance matching are respectively connected to a λ / 4 wavelength CPW 9.

[0096] In one exemplary instance, one of the ports of circulator 11 used for impedance matching is connected to a pre-resistance resistor 9. In one embodiment, resistor 9 is a 50Ω gold ingot resistor; or, one of the ports of circulator 11 used for impedance matching is connected to a λ / 4 wavelength CPW 9.

[0097] In one exemplary instance, the center frequency of the superconducting quantum ring spacer can be changed by adjusting the area of ​​capacitor 12.

[0098] In one exemplary instance, the superconducting quantum ring isolator (ICI) is a three-port device. The input terminal of the superconducting quantum ring isolator is port 1 of the isolator 10 (i.e., the first stage) located on the left. The output terminal of the superconducting quantum ring isolator includes port 2 of the circulator and port 3 of the isolator 10 (i.e., the last stage) located on the right. There are two isolators 10. There is one circulator 11. There are eight capacitors 12. Two capacitors 12 are provided in each of the isolators 10 and the ring isolator 11. The three bias line circuits 13 include a bias line circuit for the Cosine signal, a bias line circuit for the Sine signal, and a global magnetic field bias line circuit. There are three baluns 8. There are eight filters 7, which are LPFs. The impedance matching load 9 includes five 50Ω gold block resistors or five λ / 4 wavelength CPWs. In one embodiment, the superconducting quantum ring isolator may further include a superconducting quantum interference device (SQUID) array disposed in the isolator 4 and the circulator 5; wherein the SQUID array may include 576 SQUIDs, with 192 SQUIDs disposed in each isolator 4 and circulator 5. In one embodiment, the superconducting quantum ring isolator is based on an adjustable Wheatstone inductor bridge, wherein the inductor is composed of strings of SQUIDs.

[0099] In one exemplary instance, bias line circuit 13 is used to adjust the magnetic flux in the SQUID, thereby regulating the superconducting quantum circulator. In one embodiment, bias line circuit 13 may include a first bias line circuit, a second bias line circuit, and a third bias line circuit, wherein the first bias line circuit runs through each isolator 10 and circulator 11, for example, it can be disposed on a set of SQUIDs running through each isolator and circulator, and is a cosine bias line circuit; the second bias line circuit runs through each isolator 10 and circulator 11, for example, it can be disposed on another set of SQUIDs running through each isolator and circulator, and is a sine bias line circuit; the third bias line circuit runs through each isolator 10 and circulator 11, that is, through the core region of the entire device, and is an on-chipcoil circuit, which is a global magnetic field bias line circuit.

[0100] In one embodiment, the superconducting quantum ring isolator provided in this application is a three-port device based on an adjustable Wheatstone inductor bridge, wherein the inductors are composed of SQUID strings. It operates at a temperature of 20 mK and a frequency range of 4-8 GHz, covering the entire operating frequency range of the quantum bit. It has an isolation of >40 dB and an insertion loss of <3 dB. This embodiment integrates the isolator and circulator onto the same chip, exhibiting non-reciprocity, small size, and integration with superconducting circuits. It provides both isolation and circulator functions, and enables direct connection to the quantum chip and reflective quantum amplifier. It is suitable for reading out superconducting quantum bit information, protects the quantum chip from interference, greatly simplifies the superconducting quantum testing system, and is beneficial for the large-scale development of superconducting quantum computing circuits.

[0101] The superconducting quantum ring spacer provided in this application embodiment is suitable for building large-scale superconducting quantum computers, greatly simplifies the superconducting quantum testing system, and is conducive to the large-scale development of superconducting quantum computing circuits.

[0102] Figure 2 This is a schematic flowchart of one embodiment of the method for fabricating a superconducting quantum ring spacer in this application, as shown below. Figure 2 As shown, it includes:

[0103] Step 100: Silicon dioxide (SiO2) films are grown on both sides of the silicon wafer using thermal oxidation to obtain the first sample.

[0104] In one embodiment, the silicon wafer can be 4 inches. <100> N-type single-sided polished silicon wafer. In one embodiment, the thickness of the SiO2 thin film can be, for example, 400 nanometers (nm).

[0105] Step 101: Perform multiple photolithography steps sequentially on the front side of the first sample to form multiple patterns of the superconducting quantum ring spacer.

[0106] In one embodiment of the fabrication method, step 101 may include: sequentially performing ten photolithography operations on the front side of the first sample to form ten patterns of a superconducting quantum ring spacer, specifically including:

[0107] Step 1011a: Perform photolithography on the front side of the first sample to form a first pattern, and obtain the second sample.

[0108] In one embodiment, a first photolithography is performed on the front side of the sample obtained after step 100 to prepare a three-layer thin film A, and then the first pattern is obtained by peeling off. In one embodiment, thin film A can be a superconducting metal film A, with a thickness of, for example, 300-330 nm. The material of the superconducting metal film A can be, but is not limited to, Nb, Al-AlOx, and Nb three layers. In one embodiment, the thickness of the superconducting metal film A can be 330 nm. In one embodiment, the three-layer thin film A can be prepared by methods such as DC magnetron sputtering, radio frequency magnetron sputtering, or evaporation.

[0109] Step 1012a: Perform photolithography on the front side of the second sample to form a second pattern, thus obtaining the third sample.

[0110] In one embodiment, an Nb thin film B is prepared on the front side of the sample obtained after step 1011a. A second photolithography is performed to etch the Nb thin film, and a first SiO2 thin film is regrown as the first protective layer (SiO2 protective layer) of the Nb thin film B. The second pattern is then obtained by peeling off the film. Step 102 defines the Josephson junction (JJ junction) using a self-aligned process. In one embodiment, the Nb thin film B can be prepared using methods such as DC magnetron sputtering, RF magnetron sputtering, or evaporation. In one embodiment, the first SiO2 thin film can be grown using methods such as DC magnetron sputtering, RF magnetron sputtering, or evaporation. In one embodiment, the Nb thin film B can be prepared using DC magnetron sputtering, and the first SiO2 thin film can be grown using RF magnetron sputtering.

[0111] In one embodiment, the thickness of the Nb thin film B can be, for example, 160 nm; the thickness of the SiO2 protective layer can be, for example, 100–250 nm. In one embodiment, the thickness of the SiO2 protective layer can be 250 nm.

[0112] Step 1013a: Perform photolithography on the front side of the third sample to form the third pattern, thus obtaining the fourth sample.

[0113] In one embodiment, a thin film C is prepared on the front side of the sample obtained after step 1012a, a third photolithography is performed, and a third pattern is obtained by etching.

[0114] In one embodiment, the thin film C can be a superconducting metal film C with a thickness of, for example, 150–300 nm. The material of the superconducting metal film C can be, but is not limited to, Nb. In one embodiment, the thickness of the superconducting metal film C can be 160 nm. In one embodiment, the thin film C can be prepared by methods such as DC magnetron sputtering, radio frequency magnetron sputtering, or evaporation.

[0115] Step 1014a: Perform photolithography on the front side of the fourth sample to form the fourth pattern, thus obtaining the fifth sample.

[0116] In one embodiment, after obtaining the front side of the sample through step 1013a, a fourth photolithography is performed, and SiO2 and Al-AlOx are etched to obtain the fourth pattern, namely the through-hole pattern.

[0117] Step 1015a: Perform photolithography on the front side of the fifth sample to form the fifth pattern, thus obtaining the sixth sample.

[0118] In one embodiment, a fifth photolithography is performed on the front side of the sample obtained after step 1014a to prepare an Au thin film E, and then the fifth pattern is obtained by peeling off.

[0119] In one embodiment, the thickness of the Au thin film E can be, for example, 135–225 nm. In another embodiment, the thickness of the Au thin film E can be 225 nm. In one embodiment, the Au thin film E can be prepared by methods such as DC magnetron sputtering, radio frequency magnetron sputtering, or evaporation.

[0120] Step 1016a: Perform photolithography on the front side of the sixth sample to form the sixth pattern, thus obtaining the seventh sample.

[0121] In one embodiment, on the front side of the sample obtained after step 1015a, a SiO2 thin film is prepared as a dielectric layer for capacitors and cross-line using plasma-enhanced chemical vapor deposition (PECVD), and then a sixth photolithography is performed to etch the sixth pattern, namely the SiO2 dielectric layer pattern.

[0122] In one embodiment, the thickness of the SiO2 dielectric layer can be, for example, 300–500 nm. In another embodiment, the thickness of the SiO2 dielectric layer can be 250 nm.

[0123] Step 1017a: Perform photolithography on the front side of the seventh sample to form the seventh pattern, thus obtaining the eighth sample.

[0124] In one embodiment, an Nb thin film G is prepared on the front side of the sample obtained after step 1016a, and then a seventh photolithography is performed to etch a seventh pattern, which includes: a cross-line pattern, a capacitor upper electrode pattern, a Balun pattern, and an LPF pattern.

[0125] In one embodiment, the thickness of the Nb thin film G can be, for example, 300–600 nm. In another embodiment, the thickness of the Nb thin film G can be 160 nm. In one embodiment, the Nb thin film G can be prepared by methods such as DC magnetron sputtering, radio frequency magnetron sputtering, or evaporation.

[0126] Step 1018a: Perform photolithography on the front side of the eighth sample to form the eighth pattern, thus obtaining the ninth sample.

[0127] In one embodiment, a second SiO2 film is grown on the front side of the sample obtained after step 1017a as a second protective layer for the Nb film G. Then, an eighth photolithography step is performed, and the eighth pattern, i.e., the through-hole pattern, is obtained by etching. In one embodiment, the second SiO2 film can be grown by methods such as DC magnetron sputtering, radio frequency magnetron sputtering, or evaporation.

[0128] In one embodiment, the thickness of the second protective layer can be, for example, 300-500 nm. In another embodiment, the thickness of the second protective layer can be 250 nm.

[0129] Step 1019a: Perform photolithography on the front side of the ninth sample to form the ninth pattern, thus obtaining the tenth sample.

[0130] In one embodiment, an Nb thin film I is prepared on the front side of the sample obtained after step 1018a, and then a ninth photolithography is performed to etch the ninth pattern, namely the bias line pattern.

[0131] In one embodiment, the thickness of the Nb thin film I can be, for example, 300–600 nm. In another embodiment, the thickness of the Nb thin film I can be 160 nm. In one embodiment, the Nb thin film I can be prepared by methods such as DC magnetron sputtering, radio frequency magnetron sputtering, or evaporation.

[0132] Step 1020a: Perform photolithography on the front side of the tenth sample to form the tenth pattern, thus obtaining the eleventh sample.

[0133] In one embodiment, a tenth photolithography step is performed on the front side of the sample obtained after step 1019a to etch SiO2 in the blank areas of the device, thereby reducing device loss and obtaining the tenth pattern.

[0134] Step 111: Process the reverse side of the sample after forming multiple patterns to form an on-chip superconducting quantum ring spacer.

[0135] In one embodiment, step 111 may include: preparing an Al thin film on the reverse side of the sample obtained after step 1020a, i.e., the reverse side of the eleventh sample, to obtain an on-chip superconducting control multiplexed device. In one embodiment, the thickness of the Al thin film may be, for example, 300–600 nm. In one embodiment, the thickness of the Al thin film may be 600 nm. In one embodiment, the Al thin film may be prepared by methods such as DC magnetron sputtering, radio frequency magnetron sputtering, or evaporation.

[0136] The fabrication method of the superconducting quantum ring spacer provided in this application is compatible with superconducting integrated circuits in terms of process, which greatly simplifies the superconducting quantum testing system and is conducive to the large-scale development of superconducting quantum computing circuits.

[0137] In another embodiment of the preparation method, Figure 2 Step 101 may include: performing four photolithography processes sequentially on the front side of the first sample to form four patterns of the superconducting quantum ring spacer, specifically including:

[0138] Step 1011b: Perform photolithography on the front side of the first sample to form the first pattern, and obtain the second sample.

[0139] In one embodiment, a first photolithography is performed on the front side of the sample obtained after step 100 to prepare a three-layer thin film A, and then the first pattern is obtained by peeling off.

[0140] In one embodiment, thin film A can be a superconducting metal film A, with a thickness of, for example, 300-330 nm. The material of the superconducting metal thin film A can be, but is not limited to, Nb, Al-AlOx, and three layers of Nb. In one embodiment, the thickness of the superconducting metal film A can be 330 nm.

[0141] Step 1012b: Perform photolithography on the front side of the second sample to form a second pattern, thus obtaining the third sample.

[0142] In one embodiment, an Nb thin film B is prepared on the front side of the sample obtained after step 1011b. A second photolithography is performed to etch the Nb thin film, and a first SiO2 thin film is regrown as the first protective layer of the Nb thin film B, i.e., the SiO2 protective layer. The second pattern is then obtained by peeling off the film. Step 202 defines the Josephson junction (JJ junction) by using a self-aligned process.

[0143] In one embodiment, the thickness of the Nb thin film B can be, for example, 160 nm; the thickness of the SiO2 first protective layer can be, for example, 100–250 nm. In one embodiment, the thickness of the SiO2 first protective layer can be 250 nm. In one embodiment, the Nb thin film B can be prepared by methods such as DC magnetron sputtering, radio frequency magnetron sputtering, or evaporation. In one embodiment, the first SiO2 thin film can be grown by methods such as DC magnetron sputtering, radio frequency magnetron sputtering, or evaporation. In one embodiment, the Nb thin film B can be prepared by DC magnetron sputtering, and the first SiO2 thin film can be grown by radio frequency magnetron sputtering.

[0144] Step 1013b: Perform photolithography on the front side of the third sample to form the third pattern, thus obtaining the fourth sample.

[0145] In one embodiment, a thin film C is prepared on the front side of the sample obtained after step 1012b, a third photolithography is performed, and a third pattern is obtained by etching. In another embodiment, the thin film C can be prepared by methods such as DC magnetron sputtering, radio frequency magnetron sputtering, or evaporation.

[0146] In one embodiment, the thin film C can be a superconducting metal film C with a thickness of, for example, 150–300 nm. The material of the superconducting metal film C can be, but is not limited to, Nb. In one embodiment, the thickness of the superconducting metal film C can be 160 nm.

[0147] Step 1014b: Perform photolithography on the front side of the fourth sample to form the eleventh pattern, thus obtaining the twelfth sample.

[0148] In one embodiment, after obtaining the front side of the sample through step 1013b, a fourth photolithography is performed to prepare an Au thin film D, which is then peeled off to obtain an eleventh pattern. In another embodiment, the Au thin film D can be prepared using methods such as DC magnetron sputtering, radio frequency magnetron sputtering, or evaporation.

[0149] In one embodiment, the thickness of the Au thin film E can be, for example, 135–225 nm. In another embodiment, the thickness of the Au thin film E can be 225 nm.

[0150] In another embodiment, step 111 may include: preparing an Al thin film on the reverse side of the sample obtained after step 1014b, i.e., the twelfth sample reverse side, to obtain an on-chip superconducting ring spacer. In one embodiment, the thickness of the Al thin film may be, for example, 300–600 nm. In one embodiment, the thickness of the Al thin film may be 600 nm. In one embodiment, the Al thin film may be prepared by methods such as DC magnetron sputtering, radio frequency magnetron sputtering, or evaporation.

[0151] The fabrication method of the superconducting quantum ring spacer provided in this application is compatible with superconducting integrated circuits in terms of process, which greatly simplifies the superconducting quantum testing system and is conducive to the large-scale development of superconducting quantum computing circuits.

[0152] Figure 3(a) shows the embodiment of this application. Figure 2The diagram shows a layout of an on-chip superconducting ring spacer ICI-1 in one fabrication method. In this embodiment, Figure 3(a) shows a ten-layer pattern, with each layer corresponding to a photolithography mask pattern, requiring ten photolithography steps. In Figure 3(a): 1 represents the pad of port 1, 2 represents the pad of port 2, 3 represents the pad of port 3, 4 represents the pad of the cosine bias line, 5 represents the pad of the sine bias line, 6 represents the pad of the global magnetic field bias line, 7 represents the LPF, 8 represents the balun, and 91 represents a 50Ω gold ingot resistor. As shown in Figure 3(a), the on-chip superconducting ring spacer ICI-1 in this embodiment includes 3 ports, 3 baluns, 8 LPFs, 576 SQUIDs, 1152 JJ junctions, 6 capacitors, 1 cosine bias line, 1 sine bias line, 1 global magnetic field bias line, 11 pads, and 5 50Ω gold ingot resistors. In one embodiment, the JJ junction can be a circle with a diameter of 3.5 μm, based on a self-aligned superconducting niobium junction process. Referring to Figure 3(c), the on-chip superconducting ring spacer ICI-1 in this embodiment also includes a crossover line 13 for connecting different layers of metal thin films.

[0153] Figure 3(b) shows the implementation of this application. Figure 2 The diagram shows a layout of another on-chip superconducting ring spacer ICI-2 in one fabrication method. In one fabrication method of this embodiment, Figure 3(b) shows a ten-layer pattern, with each layer corresponding to a photolithography mask pattern, requiring ten photolithography steps. In Figure 3(b), 1 represents the pad for port 1, 2 represents the pad for port 2, 3 represents the pad for port 3, 4 represents the pad for the cosine bias line, 5 represents the pad for the sine bias line, 6 represents the pad for the global magnetic field bias line, 7 represents the LPF, 8 represents the balun, and 92 represents the λ / 4 wavelength CPW. As shown in Figure 3(b), the on-chip superconducting ring spacer ICI-2 in this embodiment includes 3 ports, 3 baluns, 8 LPFs, 576 SQUIDs, 1152 JJ junctions, 6 capacitors, 1 cosine bias line, 1 sine bias line, 1 global magnetic field bias line, 11 pads, and 5 λ / 4 wavelength CPWs. In one embodiment, the JJ junction can be a circle with a diameter of 3.5 μm, based on a self-aligned superconducting niobium junction process. Referring to Figure 3(c), the on-chip superconducting ring spacer ICI-2 in this embodiment also includes a crossover line 13 for connecting different layers of metal thin films.

[0154] As shown in Figure 3(c), the following is adopted: Figure 2The diagram shows a schematic layout of the on-chip superconducting ring spacer ICI-1 (i.e., isolator 10 and circulator 11) in one fabrication method shown in Figure 3(c). In one fabrication method of this embodiment, Figure 3(c) shows a ten-layer pattern, with each layer corresponding to a photolithography mask pattern, requiring ten photolithography steps. As shown in Figure 3(c), 4 represents a cosine bias line, 5 represents a sine bias line, 6 represents a global magnetic field bias line, 10 represents a SQUID array, 11 represents a capacitor, and 12 represents a cross-line.

[0155] Common alignment marks, with the first and second layers being cross-shaped, only allow for the use of smaller cross-shaped marks over larger ones. It's crucial to carefully consider whether each layer should be designed with a large or small cross-shaped mark, and whether the mask should be a bright or dark plate. To simplify the overlay process and improve accuracy, this application's embodiment uses a new alignment mark diagram, as shown in Figure 3(d). Figure 2 The alignment mark design shown in the preparation method illustrates a method where the first layer of alignment marks is polygonal, while the second and subsequent layers are cross-shaped. The cross-shaped marks are overlaid on the polygonal marks of the first layer. This eliminates the need to consider whether the alignment marks of subsequent layers are large or small cross-shaped, or whether the mask is bright or dark, ensuring accurate overlay and providing a clearer visual representation of the alignment effect. This novel alignment mark design simplifies the overlay process and improves overlay accuracy.

[0156] Figure 3(e) shows the implementation of this application. Figure 2 A cross-sectional view of one of the preparation methods shown in Figure 3(e) is illustrated, where different grayscale blocks represent... Figure 2 The substance produced in one of the different process steps shown is as follows: Figure 2 One of the preparation methods shown here will not be described in detail here.

[0157] The embodiments of this application adopt Figure 2 Another fabrication method shown in the figure has a schematic diagram of the layout of an on-chip superconducting ring spacer ICI-1. The difference between Figure 4(a) and Figure 3(a) is that Figure 4(a) is a four-layer pattern, each layer corresponds to a photolithography mask pattern, and requires four photolithography steps, while Figure 3(a) is a ten-layer pattern, each layer corresponds to a photolithography mask pattern, and requires ten photolithography steps.

[0158] The embodiments of this application adopt Figure 2 Figure 4(b) shows a schematic diagram of another on-chip superconducting ring spacer ICI-2 fabrication method. The difference between Figure 4(b) and Figure 3(b) is that Figure 4(b) has a four-layer pattern, with each layer corresponding to a photolithography mask pattern, requiring four photolithography steps. Figure 3(b) has a ten-layer pattern, with each layer corresponding to a photolithography mask pattern, requiring ten photolithography steps.

[0159] use Figure 2 Figure 4(c) shows a schematic diagram of the core region (i.e., isolator 16) of the on-chip superconducting ring isolator ICI-2 in another fabrication method shown. The difference between Figure 4(c) and Figure 3(c) is that Figure 4(c) has a four-layer pattern, with each layer corresponding to a photolithography mask pattern, requiring four photolithography steps. Figure 3(c) has a ten-layer pattern, with each layer corresponding to a photolithography mask pattern, requiring ten photolithography steps. As shown in Figure 4(c), 4 represents a cosine bias line, 5 represents a sine bias line, 6 represents a global magnetic field bias line, 10 represents a SQUID array, 11 represents a capacitor, and 12 represents a cross-line.

[0160] Figure 2 The design of the alignment marks in another preparation method shown in Figure 4(d) is illustrated. The alignment marks in the first layer are polygonal, while those in the second and subsequent layers are cross-shaped. The cross-shaped marks are used to overlay the polygonal marks in the first layer. This eliminates the need to consider whether the alignment marks in later layers are large or small cross-shaped, or whether the mask is bright or dark, ensuring accurate overlay and providing a clearer visual representation of the alignment effect. This novel alignment mark design simplifies the overlay process and improves overlay accuracy.

[0161] Figure 4(e) shows the implementation of this application. Figure 2 A cross-sectional view of another preparation method shown in Figure 4(e) illustrates the method, where different grayscale blocks represent... Figure 2 The substance produced in another different process step shown is as follows: Figure 2 Another preparation method shown will not be described in detail here.

[0162] Although the embodiments disclosed in this application are as described above, the content described is merely for the purpose of understanding this application and is not intended to limit this application. Any person skilled in the art to which this application pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this application; however, the scope of patent protection of this application shall still be determined by the scope defined in the appended claims.

Claims

1. A superconducting quantum ring spacer, characterized in that, include: A circulator, two or more isolators, three or more capacitors, and three bias line circuits are integrated on a single chip; among them, The circulator is a four-port on-chip superconducting circulator, with one port serving as an impedance-matching load, two ports used for cascaded isolators, and one port used as an input / output port for a superconducting quantum circulator isolator; the circulator's input / output ports are connected to baluns. The isolator is a two-port device. It uses two ports of a four-port on-chip superconducting circulator to impedance match the load. One of the other two ports is used for cascading circulators or isolators, and the other port is used as an input / output port of a superconducting quantum ring isolator or for cascading isolators. The isolator is used to convert the input signal to the output. The input port and output port of the isolator are respectively connected to baluns. The impedance matching load for one port of the circulator and the impedance matching loads for the two ports of the isolator each include: a 50Ω gold block resistor or a coplanar waveguide CPW with a wavelength of λ / 4, respectively connected to the circulator. Capacitors are placed in the isolator and circulator, and the center operating frequency of the superconducting quantum ring isolator is adjusted by adjusting the capacitance value of the capacitors. Three bias line circuits run through the isolator and the circulator, including: a bias line circuit for the Cosine signal, a bias line circuit for the Sine signal, and a global magnetic field bias line circuit. The global magnetic field bias line circuit runs through the core area of ​​the entire device and is an on-chip coil circuit. The bias line circuits are used to adjust the bias magnetic field of the superconducting quantum ring isolator. Each bias line of the bias line circuit is connected to a filter.

2. The superconducting quantum ring spacer according to claim 1, wherein, The filter is a low-pass filter (LPF).

3. The superconducting quantum ring spacer according to claim 1, wherein, The superconducting quantum ring isolator is a three-port device. The input terminal of the superconducting quantum ring isolator is port 1 of the first-stage isolator, and the output terminal of the superconducting quantum ring isolator includes port 2 of the ringer and port 3 of the last-stage isolator. The isolator includes two units; the circulator includes one unit; and the capacitors include eight units, with two capacitors respectively provided in each isolator and each circulator. The balun comprises three units, and the filter comprises eight units, all of which are LPFs. The impedance matching loads include 5.

4. The superconducting quantum ring spacer according to claim 3 further comprises: A superconducting quantum interference device (SQUID) array is disposed in the isolator and the circulator; The SQUID array comprises 576 SQUIDs, with 192 SQUIDs configured in each of the isolators and the circulator; The superconducting quantum ring isolator is based on an adjustable Wheatstone inductor bridge, the inductor being composed of the SQUID string.

5. A method for fabricating a superconducting quantum ring-spacing device, characterized in that, The method for preparing the superconducting quantum ring spacer according to any one of claims 1 to 4 includes: Silicon dioxide was grown on both sides of the silicon wafer using a thermal oxidation method. Thin film, to obtain the first sample; Ten photolithography steps were performed sequentially on the front side of the first sample to form multiple patterns of the superconducting quantum ring spacer. The superconducting quantum ring spacer is formed by processing the reverse side of the sample after multiple patterns are formed. The process of sequentially performing ten photolithography steps on the front side of the first sample to form multiple patterns of the superconducting quantum ring spacer includes: The first photolithography is performed on the front side of the first sample to prepare three thin A layers, and the first pattern is peeled off to obtain the second sample; A superconducting Nb thin film B was prepared on the front side of the second sample, followed by a second photolithography process to etch the Nb film and then re-grow the first layer. The thin film serves as the first protective layer for the superconducting Nb thin film B, and is peeled off to obtain the second pattern, thus obtaining the third sample; Thin film C is prepared on the front side of the third sample, a third photolithography is performed, and the third pattern is etched to obtain the fourth sample; A fourth photolithography and etching process was performed on the front side of the fourth sample. Al-AlOx was used to obtain a through-hole pattern, thus obtaining the fifth sample; A fifth photolithography was performed on the front side of the fifth sample to prepare an Au thin film E, and the fifth pattern was obtained by peeling it off to obtain the sixth sample. On the front side of the sixth sample, plasma-enhanced chemical vapor deposition (PECVD) was used to prepare the sample. The thin film serves as the dielectric layer for capacitors and cross-lines, and then a sixth photolithography step is performed, followed by etching to obtain the sixth pattern. Dielectric layer patterning to obtain the seventh sample; A superconducting Nb thin film G is prepared on the front side of the seventh sample, and then a seventh photolithography is performed and etched to obtain the seventh pattern, so as to obtain the eighth sample. The seventh pattern includes: a cross-line pattern, a capacitor upper electrode pattern, a Balun pattern, and an LPF pattern. A second layer was grown on the front side of the eighth sample. The thin film serves as the second protective layer for the Nb thin film G. Then, the eighth photolithography is performed, and the through-hole pattern is etched to obtain the ninth sample. A Nb thin film I was prepared on the front side of the ninth sample, and then a ninth photolithography was performed and etched to obtain the ninth pattern, namely the bias line pattern, to obtain the tenth sample. The tenth photolithography step was performed on the front side of the tenth sample to etch the blank areas of the device. The tenth pattern is obtained, which leads to the eleventh sample.

6. The preparation method according to claim 5, wherein, The process of processing the reverse side of the sample after forming multiple patterns to form the superconducting quantum ring spacer includes: An Al thin film was prepared on the reverse side of the eleventh sample to obtain the superconducting quantum ring spacer.

7. The preparation method according to claim 6, wherein, The thickness of the thin film A is 300~330 nm; The material of the thin film A includes three layers: Nb, Al-AlOx, and Nb.

8. The preparation method according to claim 7, wherein, The thickness of the thin film A is 330 nm.

9. The preparation method according to claim 5, wherein, The thickness of the Nb thin film B is 160 nm; the thickness of the first protective layer is 100~250 nm.

10. The preparation method according to claim 9, wherein, The thickness of the first protective layer is 250 nm.

11. The preparation method according to claim 5, wherein, The thickness of the thin film C is 150~300 nm; the material of the thin film C is Nb.

12. The preparation method according to claim 11, wherein, The thickness of the thin film C is 160 nm.

13. The preparation method according to claim 5, wherein, The thickness of the Au thin film E is 135~225 nm.

14. The preparation method according to claim 13, wherein, The thickness of the Au thin film E is 225 nm.

15. The preparation method according to claim 5, wherein, The The thickness of the dielectric layer is 300~500 nm.

16. The preparation method according to claim 15, wherein, The The thickness of the dielectric layer is 250 nm.

17. The preparation method according to claim 5, wherein, The thickness of the Nb thin film G is 300~600 nm.

18. The preparation method according to claim 17, wherein, The thickness of the Nb thin film G is 160 nm.

19. The preparation method according to claim 5, wherein, The thickness of the second protective layer is 300~500 nm.

20. The preparation method according to claim 19, wherein, The thickness of the second protective layer is 250 nm.

21. The preparation method according to claim 5, wherein, The thickness of the Nb thin film I is 300~600 nm.

22. The preparation method according to claim 21, wherein, The thickness of the Nb thin film I is 160 nm.

23. The preparation method according to claim 6, wherein, The thickness of the Al film is 300~600 nm.

24. The preparation method according to claim 23, wherein, The thickness of the Al film is 600 nm.

25. A method for fabricating a superconducting quantum ring-spacing device, characterized in that, The method for preparing the superconducting quantum ring spacer according to any one of claims 1 to 4 includes: Silicon dioxide was grown on both sides of the silicon wafer using a thermal oxidation method. Thin film, to obtain the first sample; The superconducting quantum ring spacer is formed by performing four photolithography processes sequentially on the front side of the first sample. The superconducting quantum ring spacer is formed by processing the reverse side of the sample after multiple patterns are formed. The process of sequentially performing four photolithography steps on the front side of the first sample to form multiple patterns of the superconducting quantum ring spacer includes: The first photolithography is performed on the front side of the first sample to prepare a three-layer thin film A, and the first pattern is obtained by peeling it off to obtain the second sample; A Nb thin film B is prepared on the front side of the second sample, followed by a second photolithography process to etch the Nb thin film and then regenerate the first layer. The thin film serves as a protective layer for the Nb thin film B, and is peeled off to obtain a second pattern, thus obtaining a third sample; A superconducting metal film C is prepared on the front side of the third sample, a third photolithography is performed, and the third pattern is etched to obtain the fourth sample; The fourth photolithography was performed on the front side of the fourth sample to prepare an Au thin film D, and the eleventh pattern was obtained by peeling it off to obtain the twelfth sample.

26. The preparation method according to claim 25, wherein, The process of processing the reverse side of the sample after forming multiple patterns to form the superconducting quantum ring spacer includes: A superconducting Al thin film was prepared on the reverse side of the twelfth sample to obtain the superconducting quantum ring spacer.

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