Chip on orbit reconfiguration method, device, equipment and storage medium

Abstract

The present disclosure provides a chip on-orbit reconfiguration method, device, equipment and storage medium, which can be applied to the field of FPGA on-orbit reconfiguration technology. The method comprises: in response to receiving a reconfiguration instruction sent by a management end, running the reconfiguration instruction to erase data in a target address region of a first storage chip indicated by the reconfiguration instruction; returning feedback information indicating that the data erasure has been completed to the management end; writing a configuration data packet into the target address region of the first storage chip; running a restart instruction to control a service chip to enter a restart state, wherein the service chip is configured to send a resource loading instruction to a master control chip in response to being in the restart state; and in response to the resource loading instruction based on the interface timing of a second storage chip connected to the service chip, the configuration data packet is sent to the service chip, wherein the service chip is configured to perform on-orbit reconfiguration based on the configuration data packet.

Description

Technical Field

[0001] This disclosure relates to the field of FPGA on-orbit reconfiguration technology, and in particular to a chip on-orbit reconfiguration method, apparatus, device and storage medium. Background Technology

[0002] With the advancement of technology, aerospace systems are becoming increasingly complex, and Field Programmable Gate Arrays (FPGAs) are being used more and more widely in the aerospace field. This places higher demands on on-orbit reconfiguration. On-orbit reconfiguration refers to the process by which ground control stations, through uplink control, update the hardware configuration and parameters of the satellite payload and modify the program during the satellite's on-orbit operation. This enables onboard software system upgrades, error correction, and on-orbit maintenance.

[0003] With the continuous deepening and upgrading of on-orbit applications of aerospace systems, there is an urgent need for a technology that can systematically and comprehensively upgrade software and reconstruct FPGAs in order to achieve iterative upgrades of applications.

[0004] In the process of implementing this disclosure, it was discovered that the relevant technology usually completely burns the FPGA configuration into the flash memory, resulting in the FPGA configuration being completely solidified. When the FPGA program needs to be updated, the new version of the FPGA configuration file needs to be re-burned into the programmable memory flash memory through the FPGA development software. Summary of the Invention

[0005] In view of the above problems, this disclosure provides a method, apparatus, device and storage medium for on-orbit reconfiguration of chips.

[0006] According to a first aspect of this disclosure, a chip on-orbit reconfiguration method is provided, comprising: responding to receiving a reconfiguration instruction sent by a management terminal; executing the reconfiguration instruction to erase data in a target address region of a first storage chip indicated by the reconfiguration instruction; returning feedback information to the management terminal indicating that the data erasure has been completed, wherein the management terminal is configured to send a configuration data packet to a master control chip in response to the feedback information; writing the configuration data packet into the target address region of the first storage chip; executing a restart instruction to control a service chip to enter a restart state, wherein the service chip is configured to send a resource loading instruction to the master control chip in response to being in the restart state; and responding to the resource loading instruction based on the interface timing of a second storage chip connected to the service chip to send a configuration data packet to the service chip, wherein the service chip is configured to perform on-orbit reconfiguration based on the configuration data packet.

[0007] According to embodiments of this disclosure, the on-orbit reconfiguration method further includes: performing a correctness check on a configuration data packet to obtain a check result; and writing the configuration data packet into a first storage chip if the check result indicates that the correctness check has passed.

[0008] According to embodiments of this disclosure, the configuration data packet includes multiple configuration data frames; wherein, performing a correctness check on the configuration data packet to obtain a check result includes: performing a correctness check on each configuration data frame to obtain multiple first check results; performing an overall correctness check on the configuration data packet to obtain a second check result; and determining a check result based on the second check result and the multiple first check results.

[0009] According to embodiments of this disclosure, a configuration data frame includes a frame header, a frame sequence number, configuration data, an intra-frame correctness check value, and a frame trailer; wherein, a correctness check is performed on each configuration data frame, including: obtaining a third check result based on the frame header, frame trailer, and frame sequence number; obtaining a fourth check result based on the configuration data and the intra-frame correctness check value; and determining a first check result based on the third check result and the fourth check result.

[0010] According to embodiments of this disclosure, performing an overall correctness check on a configuration data packet includes: obtaining a first correctness check value based on the intra-frame correctness check values ​​of each of the multiple configuration data frames other than the last configuration data frame in the configuration data packet; obtaining a second correctness check value of the configuration data packet based on the configuration data of the last configuration data frame in the configuration data packet; and comparing the first correctness check value with the second correctness check value to obtain a second check result.

[0011] According to embodiments of this disclosure, the chip on-orbit reconfiguration method further includes: in response to receiving fault identification information from a service chip, if the fault identification information indicates a functional error after reconfiguration, sending a rollback instruction to the service chip, wherein the service chip is configured to execute the rollback instruction, load the configuration data packet before reconfiguration from a second storage chip, and perform reconfiguration rollback based on the configuration data packet before reconfiguration.

[0012] According to embodiments of this disclosure, a resource loading instruction is responded to based on the interface timing of a second storage chip connected to a service chip to send a configuration data packet to the service chip. This includes: simulating the interface timing of the second storage chip connected to the service chip to receive the resource loading instruction; parsing the resource loading instruction to obtain the type of the resource loading instruction and its corresponding parameters; reading the configuration data packet from the first storage chip according to the type of the resource loading instruction and its corresponding parameters; and sending the configuration data packet to the service chip.

[0013] A second aspect of this disclosure provides an on-orbit chip reconfiguration apparatus, comprising:

[0014] The reconstruction instruction execution module is used to respond to the reconstruction instruction sent by the receiving management terminal, execute the reconstruction instruction, and erase the data in the target address region of the first memory chip indicated by the reconstruction instruction;

[0015] The information feedback module is used to return feedback information to the management terminal indicating that the data erasure has been completed. The management terminal is configured to send a configuration data packet to the main control chip in response to the feedback information.

[0016] The data writing module is used to write configuration data packets into the target address region of the first storage chip;

[0017] The restart instruction execution module is used to run restart instructions to control the service chip to enter the restart state. The service chip is configured to send a resource loading instruction to the main control chip in response to being in the restart state.

[0018] The instruction response module is used to respond to resource loading instructions based on the interface timing of the second storage chip connected to the service chip, in order to send a configuration data packet to the service chip, wherein the service chip is configured to perform on-orbit reconstruction based on the configuration data packet.

[0019] A third aspect of this disclosure provides an electronic device comprising: one or more processors; and a memory for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors perform the methods described above.

[0020] A fourth aspect of this disclosure also provides a computer-readable storage medium having executable instructions stored thereon, which, when executed by a processor, cause the processor to perform the methods described above.

[0021] The fifth aspect of this disclosure also provides a computer program product, including a computer program that, when executed by a processor, implements the above-described method.

[0022] According to the chip on-orbit reconfiguration method, apparatus, device, and storage medium provided in this disclosure, the main control chip writes a configuration data packet to a first storage chip and simulates the interface timing of a second storage chip to simulate the function of the second storage chip, thereby responding to a resource loading command and sending the configuration data packet corresponding to the resource loading command to the service chip, enabling the service chip to complete on-orbit reconfiguration. Since the main control chip can simulate the interface timing of the second storage chip to simulate its function, upon receiving a resource loading command from the service chip, it reads the configuration data packet from the first storage chip. This allows the service chip to read the configuration data packet from the main control chip in the same way it reads configuration data from the second storage chip, thus completing the on-orbit reconfiguration of the service chip. Therefore, the on-orbit reconfiguration process of the service chip does not require the participation of an additional controller chip, at least partially solving the problem of on-orbit reconfiguration relying on a controller chip in related technologies, without increasing additional hardware costs. Attached Figure Description

[0023] The foregoing contents, as well as other objects, features, and advantages of this disclosure, will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0024] Figure 1 The illustration schematically depicts application scenarios of the chip on-orbit reconfiguration method, apparatus, device, medium, and program product according to embodiments of the present disclosure;

[0025] Figure 2 A flowchart illustrating an on-orbit reconfiguration method for a chip according to an embodiment of the present disclosure is shown schematically.

[0026] Figure 3 A flowchart illustrating a method for parsing resource loading instructions according to an embodiment of the present disclosure is shown schematically;

[0027] Figure 4 A schematic block diagram of a chip-on-orbit reconfiguration apparatus according to an embodiment of the present disclosure is shown; and

[0028] Figure 5 A block diagram schematically illustrates an electronic device suitable for implementing an on-orbit chip reconfiguration method according to an embodiment of the present disclosure. Detailed Implementation

[0029] The embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the present disclosure for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0030] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0031] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0032] When using expressions such as "at least one of A, B, and C", they should generally be interpreted in accordance with the meaning that is commonly understood by a person skilled in the art (e.g., "a system having at least one of A, B, and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B, and C, etc.).

[0033] In the technical solution of this invention, the user information (including but not limited to user personal information, user image information, user device information, such as location information) and data (including but not limited to data used for analysis, stored data, and displayed data) involved are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, storage, use, processing, transmission, provision, disclosure, and application of related data all comply with the relevant laws, regulations, and standards of the relevant countries and regions, take necessary confidentiality measures, do not violate public order and good morals, and provide corresponding operation entry points for users to choose to authorize or refuse.

[0034] During the implementation of this disclosure, it was discovered that once a satellite is launched, the FPGA configuration file in the satellite payload equipment is fixed and its state cannot be changed. This makes it unable to adapt to the development of new technologies or the updating and optimization of the FPGA program. If the onboard payload program malfunctions after launch, the payload's functionality will be lost, causing incalculable losses. Therefore, satellite payload equipment requires FPGA code upgrades. FPGA code is typically several megabytes in size, and conventional reconfiguration schemes require the use of a controller chip to complete on-orbit reconfiguration, increasing additional hardware costs.

[0035] Embodiments of this disclosure provide a chip on-orbit reconfiguration method, comprising: responding to a reconfiguration instruction sent by a management terminal; executing the reconfiguration instruction to erase data in a target address region of a first storage chip indicated by the reconfiguration instruction; returning feedback information to the management terminal indicating that the data erasure has been completed, wherein the management terminal is configured to send a configuration data packet to a master control chip in response to the feedback information; writing the configuration data packet into the target address region of the first storage chip; executing a restart instruction to control a service chip to enter a restart state, wherein the service chip is configured to send a resource loading instruction to the master control chip in response to being in the restart state; and responding to the resource loading instruction based on the interface timing of a second storage chip connected to the service chip to send a configuration data packet to the service chip, wherein the service chip is configured to perform on-orbit reconfiguration based on the configuration data packet.

[0036] Figure 1 The diagram illustrates an application scenario of on-orbit reconfiguration of a chip according to an embodiment of the present disclosure.

[0037] like Figure 1 As shown, application scenario 100 according to this embodiment may include a ground control station 110 and a satellite 120. The satellite 120 may include a management terminal 121, a main control chip 122, a first storage chip 123, a service chip 124, and a second storage chip 125. The main control chip 122 can be a flash memory type FPGA chip, the first storage chip 123 can be a chip using non-volatile flash memory (NOR Flash) technology, the service chip 124 can be a fully programmable system-on-a-chip (FPGA) chip, and the second storage chip 125 can be a Queued Serial Peripheral Interface (QSPI) flash memory chip.

[0038] Ground control station 110 is used to send configuration data frames to satellite 120, and management terminal 121 is used to provide command relay services between ground control station 110 and main control chip 122.

[0039] The main control chip 122 is connected to the first storage chip 123, and can read and write data from the first storage chip 123 according to instructions. The service chip 124 is connected to the second storage chip 125, and can read and write data from the second storage chip according to instructions. The main control chip 122 is also connected to the service chip 124, and can control the service chip 124 to power on and restart according to instructions for on-orbit reconfiguration.

[0040] It should be noted that the chip-on-orbit reconfiguration method provided in this embodiment can generally be executed by the main control chip 122. Correspondingly, the chip-on-orbit reconfiguration device provided in this embodiment can generally be located within the main control chip 122. The chip-on-orbit reconfiguration method provided in this embodiment can also be executed by a chip or chip cluster that is different from the server 125 and capable of communicating with the management terminal 121, the first storage chip 123, the service chip 124, the second storage chip 125, and / or the main control chip 122. Correspondingly, the chip-on-orbit reconfiguration device provided in this embodiment can also be located within a chip or chip cluster that is different from the main control chip 122 and capable of communicating with the management terminal 121, the first storage chip 123, the service chip 124, the second storage chip 125, and / or the main control chip 122.

[0041] It should be understood that Figure 1 The number of ground control stations, satellites, main control chips, first memory chips, service chips, and second memory chips shown in the diagram is merely illustrative. Depending on implementation needs, any number of ground control stations, satellites, main control chips, first memory chips, service chips, and second memory chips can be included.

[0042] The following will be based on Figure 1 The described scene, through Figures 2-3 The on-orbit reconfiguration method for chips according to the disclosed embodiments is described in detail.

[0043] Figure 2 A flowchart illustrating an on-orbit reconfiguration method for a chip according to an embodiment of the present disclosure is shown schematically.

[0044] like Figure 2 As shown, the on-orbit reconfiguration of the chip in this embodiment includes operations S210 to S250.

[0045] In operation S210, in response to the reconfiguration instruction sent by the receiving management terminal, the reconfiguration instruction is executed to erase the data in the target address region of the first memory chip indicated by the reconfiguration instruction.

[0046] According to embodiments of this disclosure, the management terminal can be an on-board management terminal connected to a ground tracking and control station. The ground tracking and control station sends a reconfiguration command to the on-board management terminal via uplink control, and the on-board management terminal then forwards the reconfiguration command to the main control chip. The reconfiguration command may include address parameters, and the target address region is the address region indicated by the address parameters in the reconfiguration command. Based on the reconfiguration command, the main control chip erases the data stored at the corresponding address in the first memory chip.

[0047] According to embodiments of this disclosure, the main control chip primarily implements instruction and data communication with the on-board management terminal, receives instructions sent by the on-board management terminal, parses and executes the instructions, and controls the first storage chip to perform read, write, and erase operations to complete the storage and retrieval of configuration data.

[0048] During operation S220, feedback information indicating that data erasure has been completed is returned to the management terminal. The management terminal is configured to send a configuration data packet to the main control chip in response to the feedback information.

[0049] According to embodiments of this disclosure, after erasing the data in the target address region of the first memory chip, a feedback message indicating successful flash memory erasure is returned to the onboard management terminal. The onboard management terminal then forwards the flag information to the ground telemetry and control station. Upon receiving the feedback message, the ground telemetry and control station splits and frames the configuration file corresponding to the service chip to be reconstructed, generating a configuration data packet. This configuration data packet is then uploaded to the onboard management terminal via an uploading method. The onboard management terminal receives and caches the configuration data packet and sends it to the main control chip via the Low Voltage Differential Signaling (LVDS) bus interface in the form of configuration data frames.

[0050] According to embodiments of this disclosure, a configuration data frame may include a frame header, a frame sequence number, configuration data, an intra-frame correctness check value, and a frame tail.

[0051] In operation S230, the configuration data packet is written to the target address area of ​​the first memory chip.

[0052] According to an embodiment of this disclosure, after receiving a configuration data frame, the main control chip saves the configuration data in the configuration data frame to the address area of ​​the first storage chip connected to the main control chip where the data has been erased.

[0053] In operation S240, a restart command is executed to control the service chip to enter a restart state. The service chip is configured to send a resource loading command to the main control chip in response to being in a restart state.

[0054] According to an embodiment of this disclosure, the main control chip controls the power-on of the service chip via a restart command, thereby restarting the service chip, and the service chip sends a resource loading command to the main control chip.

[0055] During operation S250, based on the interface timing of the second storage chip connected to the service chip, a resource loading command is responded to in order to send a configuration data packet to the service chip, wherein the service chip is configured to perform on-orbit reconstruction based on the configuration data packet.

[0056] According to embodiments of this disclosure, the main control chip simulates the interface timing of the second storage chip to implement the functions of the second storage chip, identifies and responds to the resource loading instruction sent by the service chip, sends the configuration data packet requested in the resource loading instruction to the service chip, and the service chip completes on-orbit reconstruction according to the received configuration data packet.

[0057] According to embodiments of this disclosure, the main control chip simulates the function of the second storage chip by writing configuration data packets into the first storage chip and simulating the interface timing of the second storage chip to respond to resource loading instructions. It then sends the configuration data packets corresponding to the resource loading instructions to the service chip, enabling the service chip to complete on-orbit reconfiguration. Since the main control chip can simulate the interface timing of the second storage chip to simulate its function, upon receiving a resource loading instruction from the service chip, it reads configuration data packets from the first storage chip. This allows the service chip to read configuration data packets from the main control chip in the same way it reads configuration data from the second storage chip, thus completing the on-orbit reconfiguration of the service chip. Therefore, the on-orbit reconfiguration process of the service chip does not require the participation of an additional controller chip, at least partially solving the problem of on-orbit reconfiguration relying on a controller chip in related technologies, without increasing additional hardware costs.

[0058] According to embodiments of this disclosure, the on-orbit reconfiguration method further includes: performing a correctness check on a configuration data packet to obtain a check result; and writing the configuration data packet into a first storage chip if the check result indicates that the correctness check has been passed.

[0059] According to embodiments of this disclosure, correctness verification can be performed based on the intra-frame correctness check value in the configuration data frame. The configuration data packet is written to the first storage chip only after passing the correctness verification, thus ensuring the correctness of the written data and thereby ensuring the correctness of the reconstruction of the service chip.

[0060] According to embodiments of this disclosure, the configuration data packet includes multiple configuration data frames; wherein, performing a correctness check on the configuration data packet to obtain a check result includes: performing a correctness check on each configuration data frame to obtain multiple first check results; performing an overall correctness check on the configuration data packet to obtain a second check result; and determining a check result based on the second check result and the multiple first check results.

[0061] According to embodiments of this disclosure, the verification of the configuration data packet includes verification of each configuration data frame and overall correctness verification of the configuration data packet. A first verification result is obtained after the correctness verification of each configuration data frame, and a second verification result is obtained after the overall correctness verification of the configuration data packet. The verification result indicates that the configuration data packet has passed the correctness verification when both the second verification result and all first verification results indicate that the correctness verification has been passed.

[0062] According to embodiments of this disclosure, by setting correctness checks for each data frame and correctness checks for the configuration data packet, the correctness and integrity of the configuration data packet written to the first storage chip are ensured.

[0063] According to embodiments of this disclosure, a configuration data frame includes a frame header, a frame sequence number, configuration data, an intra-frame correctness check value, and a frame trailer; wherein, a correctness check is performed on each configuration data frame, including: obtaining a third check result based on the frame header, frame trailer, and frame sequence number; obtaining a fourth check result based on the configuration data and the intra-frame correctness check value; and determining a first check result based on the third check result and the fourth check result.

[0064] According to embodiments of this disclosure, intra-frame correctness verification can be cyclic redundancy check (CRC), and the intra-frame correctness verification value can be a CRC check value.

[0065] According to embodiments of this disclosure, when the frame header and trailer are complete and correct, and the frame sequence numbers are consecutive, the third verification result indicates that the correctness check has passed; otherwise, the third verification result indicates that the correctness check has failed. A modulo-2 division is performed on the configuration data, divided by the CRC check value. If the calculation result has no remainder, then the fourth verification result indicates that the correctness check has passed, and the quotient obtained from the modulo-2 division is the actual data; otherwise, the fourth verification result indicates that the correctness check has failed. When both the third and fourth verification results indicate that the correctness check has passed, the first verification result indicates that the correctness check has passed, and the correctness check of the next configuration data frame can proceed; otherwise, the first verification result indicates that the correctness check has failed, and the error information is sent to the on-board management terminal via the main control chip, waiting for the configuration data frame to be retransmitted.

[0066] According to embodiments of this disclosure, when a configuration data frame encounters an error, the configuration data frame is retransmitted through the buffer of the onboard management terminal, eliminating the need for retransmission from the ground telemetry and control station and reducing the time cost associated with data retransmission. Intra-frame correctness verification ensures the correctness of each configuration data frame written to the first storage chip, improving the reliability of on-orbit reconfiguration.

[0067] According to embodiments of this disclosure, performing an overall correctness check on a configuration data packet includes: obtaining a first correctness check value based on the intra-frame correctness check values ​​of each of the multiple configuration data frames other than the last configuration data frame in the configuration data packet; obtaining a second correctness check value of the configuration data packet based on the configuration data of the last configuration data frame in the configuration data packet; and comparing the first correctness check value with the second correctness check value to obtain a second check result.

[0068] According to embodiments of this disclosure, after the last configuration data frame passes the correctness check using its intra-frame correctness check value, the sum of the intra-frame correctness check values ​​of all other data frames in the configuration data packet is compared with the configuration data of the last configuration data frame. If the second check result indicates that the first correctness check value is consistent with the second correctness check value, it means that all data in the configuration data packet has been correctly received, and a correct overall correctness check flag can be sent to the on-board management terminal, and the configuration data packet can be written into the address area of ​​the erased data in the first storage chip; if the second check result indicates that the first correctness check value is inconsistent with the second correctness check value, the current reconstruction can be terminated, a correct overall correctness check error flag can be sent to the on-board management terminal, and the system can wait for the next reconstruction instruction sent by the on-board management terminal.

[0069] According to embodiments of this disclosure, by setting the last configuration data frame, the intra-frame correctness check value of all configuration data frames in the configuration data packet is checked for correctness, ensuring the integrity of the configuration data packet written to the first storage chip and further improving the reliability of on-orbit reconfiguration.

[0070] According to embodiments of this disclosure, the chip on-orbit reconfiguration method further includes: in response to receiving fault identification information from a service chip, if the fault identification information indicates a functional error after reconfiguration, sending a rollback instruction to the service chip, wherein the service chip is configured to execute the rollback instruction, load the configuration data packet before reconfiguration from a second storage chip, and perform reconfiguration rollback based on the configuration data packet before reconfiguration.

[0071] According to embodiments of this disclosure, the second storage chip can store the configuration data package of the service chip before its on-orbit reconfiguration. Reconfiguration rollback can be the process of restoring the service chip to its functionality before on-orbit reconfiguration. Through reconfiguration rollback, it is ensured that if the service chip malfunctions or cannot function properly after on-orbit reconfiguration, its functionality will be rolled back to the state before on-orbit reconfiguration, thus guaranteeing the normal operation of the service chip.

[0072] According to embodiments of this disclosure, a resource loading instruction is responded to based on the interface timing of a second storage chip connected to a service chip to send a configuration data packet to the service chip. This includes: simulating the interface timing of the second storage chip connected to the service chip to receive the resource loading instruction; parsing the resource loading instruction to obtain the type of the resource loading instruction and its corresponding parameters; reading the configuration data packet from the first storage chip according to the type of the resource loading instruction and its corresponding parameters; and sending the configuration data packet to the service chip.

[0073] Figure 3 A flowchart illustrating a method for parsing resource loading instructions according to an embodiment of the present disclosure is shown.

[0074] like Figure 3As shown, the parsing resource loading instructions in this embodiment include operations S301 to S310.

[0075] In operation S301, determine the type of resource loading instruction. If it is a register configuration command, execute operation S302; if it is a read ID command, execute operation S304; if it is a read data command, execute operation S306.

[0076] In operation S302, configuration parameters are transmitted.

[0077] In operation S303, it is determined whether the register parameters have been transferred successfully. If the transfer is not successful, operation S302 is executed; if the transfer is successful, operation S301 is executed to read the next resource load instruction.

[0078] When operating S304, ID data is transmitted.

[0079] In operation S305, determine whether the ID data transmission is complete. If the transmission is not complete, execute operation S304; if the transmission is complete, execute operation S301 to read the next resource loading instruction.

[0080] When operating S306, receive address data.

[0081] When operating S307, a command to read the first memory chip is sent.

[0082] The S308 is used to read data from the first memory chip.

[0083] Data is transmitted while operating S309.

[0084] In operation S310, it is determined whether the data transmission is complete. If the transmission is not complete, operation S309 is executed; if the transmission is complete, operation S301 is executed to read the next resource loading instruction.

[0085] According to embodiments of this disclosure, the resource loading instruction may include a register configuration command, a read ID command, and a read data command. The register configuration command can configure register parameters. The read ID command can read the ID of a first storage chip to determine the first storage chip that the resource loading instruction corresponds to. The read data command can read data after determining the first storage chip that needs to be read. The main control chip receives and parses the resource loading instruction, first determining the type of the resource loading instruction. If it is a register configuration command, it transmits configuration parameters until the register parameters are transmitted; if it is a read ID command, it transmits ID data until the ID data transmission is complete; if it is a read data command, it first receives the address data in the read data command, sends a read command to the first storage chip, reads the data at the corresponding address, and transmits it to the service chip until the data transmission is complete.

[0086] According to embodiments of this disclosure, the main control chip simulates the interface timing of the second storage chip to implement the functions of the second storage chip, so as to receive and respond to the resource loading instructions of the service chip, thereby sending the configuration data packet stored in the first storage chip to the service chip to complete the on-orbit reconfiguration of the service chip.

[0087] Based on the above-described on-orbit chip reconfiguration method, this disclosure also provides an on-orbit chip reconfiguration apparatus. The following will be combined with... Figure 4 The device is described in detail.

[0088] Figure 4 A schematic block diagram of a chip-on-orbit reconfiguration apparatus according to an embodiment of the present disclosure is shown.

[0089] like Figure 4 As shown, the chip on-orbit reconfiguration device 400 of this embodiment includes a reconfiguration instruction execution module 410, an information feedback module 420, a data writing module 430, a restart instruction execution module 440, and an instruction response module 450.

[0090] The reconstruction instruction execution module 410 is used to respond to a reconstruction instruction sent by the receiving management terminal, and to execute the reconstruction instruction to erase the data in the target address region of the first memory chip indicated by the reconstruction instruction. In one embodiment, the reconstruction instruction execution module 410 can be used to perform the operation S210 described above, which will not be repeated here.

[0091] The information feedback module 420 is used to return feedback information to the management terminal indicating that data erasure has been completed. The management terminal is configured to send a configuration data packet to the main control chip in response to the feedback information. In one embodiment, the information feedback module 420 can be used to perform the operation S220 described above, which will not be repeated here.

[0092] The data writing module 430 is used to write the configuration data packet into the target address region of the first memory chip. In one embodiment, the data writing module 430 can be used to perform the operation S230 described above, which will not be repeated here.

[0093] The restart instruction execution module 440 is used to execute restart instructions to control the service chip to enter a restart state. The service chip is configured to send a resource loading instruction to the main control chip in response to being in a restart state. In one embodiment, the restart instruction execution module 440 can be used to execute the operation S240 described above, which will not be repeated here.

[0094] The instruction response module 450 is used to respond to resource loading instructions based on the interface timing of the second storage chip connected to the service chip, in order to send a configuration data packet to the service chip, wherein the service chip is configured to perform on-orbit reconstruction based on the configuration data packet. In one embodiment, the instruction response module 450 can be used to execute the operation S250 described above, which will not be repeated here.

[0095] According to embodiments of this disclosure, the chip on-orbit reconfiguration device 400 further includes a correctness verification module and a data writing module.

[0096] The correctness verification module is used to verify the correctness of the configuration data packet and obtain the verification result.

[0097] The data writing module is used to configure the data packet to be written to the first storage chip when the verification result indicates that the correctness verification has been passed.

[0098] According to embodiments of this disclosure, the correctness verification module includes a first verification submodule, a second verification submodule, and a result determination submodule.

[0099] The first verification submodule is used to verify the correctness of each configuration data frame and obtain multiple first verification results.

[0100] The second verification submodule is used to perform overall correctness verification on the configuration data packet and obtain the second verification result.

[0101] The result determination submodule is used to determine the verification result based on the second verification result and multiple first verification results.

[0102] According to embodiments of this disclosure, the first verification submodule includes a third verification unit, a fourth verification unit, and a first result determination unit.

[0103] The third verification unit is used to obtain the third verification result based on the frame header, frame tail, and frame sequence number.

[0104] The fourth verification unit is used to obtain the fourth verification result based on the configuration data and the intra-frame correctness verification value.

[0105] The first result determination unit is used to determine the first verification result based on the third verification result and the fourth verification result.

[0106] According to embodiments of this disclosure, the second verification submodule includes a first verification value determination unit, a second verification value determination unit, and a second result determination unit.

[0107] The first verification value determination unit is used to obtain a first correctness verification value based on the intra-frame correctness verification values ​​of the other configuration data frames in the configuration data packet, excluding the last configuration data frame.

[0108] The second verification value determination unit is used to obtain a second correctness verification value of the configuration data packet based on the configuration data of the last configuration data frame in the configuration data packet.

[0109] The second result determination unit is used to compare the first correctness check value with the second correctness check value to obtain the second check result.

[0110] According to embodiments of this disclosure, the chip on-orbit reconfiguration apparatus 400 further includes a reconfiguration rollback module.

[0111] The reconstruction rollback module is used to respond to receiving fault identification information from the service chip. If the fault identification information indicates that there is a functional error after reconstruction, the module sends a rollback instruction to the service chip. The service chip is configured to execute the rollback instruction, load the configuration data packet before reconstruction from the second storage chip, and perform reconstruction rollback based on the configuration data packet before reconstruction.

[0112] According to embodiments of this disclosure, the instruction response module 450 includes a timing simulation submodule, an instruction parsing submodule, a data reading submodule, and a data sending submodule.

[0113] The timing simulation submodule is used to simulate the interface timing of the second storage chip connected to the service chip in order to receive resource loading instructions.

[0114] The instruction parsing submodule is used to parse resource loading instructions to obtain the type of the resource loading instruction and its corresponding parameters.

[0115] The data reading submodule is used to read configuration data packets from the first storage chip according to the type of resource loading instruction and the corresponding parameters.

[0116] The data transmission submodule is used to send configuration data packets to the service chip.

[0117] According to embodiments of this disclosure, any multiple modules among the reconfiguration instruction execution module 410, information feedback module 420, data writing module 430, restart instruction execution module 440, and instruction response module 450 can be combined into one module, or any one of these modules can be split into multiple modules. Alternatively, at least some of the functions of one or more of these modules can be combined with at least some of the functions of other modules and implemented in one module. According to embodiments of this disclosure, at least one of the reconfiguration instruction execution module 410, information feedback module 420, data writing module 430, restart instruction execution module 440, and instruction response module 450 can be at least partially implemented as hardware circuitry, such as a field-programmable gate array (FPGA), a programmable logic array (PLA), a system-on-a-chip, a system-on-a-substrate, a system-on-package, an application-specific integrated circuit (ASIC), or implemented in hardware or firmware by any other reasonable means of integrating or packaging the circuitry, or implemented in any one of the three implementation methods of software, hardware, and firmware, or in a suitable combination of any of these. Alternatively, at least one of the reconfiguration instruction execution module 410, information feedback module 420, data writing module 430, restart instruction execution module 440, and instruction response module 450 can be at least partially implemented as a computer program module, which can perform corresponding functions when the computer program module is run.

[0118] Figure 5 A block diagram schematically illustrates an electronic device suitable for implementing an on-orbit chip reconfiguration method according to an embodiment of the present disclosure.

[0119] like Figure 5 As shown, an electronic device 500 according to an embodiment of the present disclosure includes a processor 501, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 502 or a program loaded from a storage portion 508 into a random access memory (RAM) 503. The processor 501 may include, for example, a general-purpose microprocessor (e.g., a CPU), an instruction set processor and / or an associated chipset and / or a special-purpose microprocessor (e.g., an application-specific integrated circuit (ASIC)), etc. The processor 501 may also include onboard memory for caching purposes. The processor 501 may include a single processing unit or multiple processing units for performing different actions of the method flow according to an embodiment of the present disclosure.

[0120] RAM 503 stores various programs and data required for the operation of electronic device 500. Processor 501, ROM 502, and RAM 503 are interconnected via bus 504. Processor 501 performs various operations of the method flow according to embodiments of the present disclosure by executing programs in ROM 502 and / or RAM 503. It should be noted that the programs may also be stored in one or more memories other than ROM 502 and RAM 503. Processor 501 may also perform various operations of the method flow according to embodiments of the present disclosure by executing programs stored in said one or more memories.

[0121] According to embodiments of this disclosure, the electronic device 500 may further include an input / output (I / O) interface 505, which is also connected to a bus 504. The electronic device 500 may also include one or more of the following components connected to the input / output (I / O) interface 505: an input section 506 including a keyboard, mouse, etc.; an output section 507 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 508 including a hard disk, etc.; and a communication section 509 including a network interface card such as a LAN card, modem, etc. The communication section 509 performs communication processing via a network such as the Internet. A drive 510 is also connected to the input / output (I / O) interface 505 as needed. A removable medium 511, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on the drive 510 as needed so that computer programs read from it can be installed into the storage section 508 as needed.

[0122] This disclosure also provides a computer-readable storage medium, which may be included in the device / apparatus / system described in the above embodiments; or it may exist independently and not assembled into the device / apparatus / system. The computer-readable storage medium carries one or more programs that, when executed, implement the method according to the embodiments of this disclosure.

[0123] According to embodiments of this disclosure, the computer-readable storage medium may be a non-volatile computer-readable storage medium, such as including, but not limited to: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this disclosure, the computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. For example, according to embodiments of this disclosure, the computer-readable storage medium may include ROM 502 and / or RAM 503 and / or one or more memories other than ROM 502 and RAM 503 described above.

[0124] Embodiments of this disclosure also include a computer program product comprising a computer program containing program code for performing the methods shown in the flowchart. When the computer program product is run on a computer system, the program code is used to enable the computer system to implement the on-orbit chip reconfiguration method provided in embodiments of this disclosure.

[0125] When the computer program is executed by the processor 501, it performs the functions defined in the system / apparatus of this disclosure embodiments. According to embodiments of this disclosure, the systems, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0126] In one embodiment, the computer program may rely on a tangible storage medium such as an optical storage device or a magnetic storage device. In another embodiment, the computer program may also be transmitted and distributed in the form of signals over a network medium, and may be downloaded and installed via the communication section 509, and / or installed from a removable medium 511. The program code contained in the computer program can be transmitted using any suitable network medium, including but not limited to: wireless, wired, etc., or any suitable combination thereof.

[0127] In such an embodiment, the computer program can be downloaded and installed from a network via communication section 509, and / or installed from removable medium 511. When the computer program is executed by processor 501, it performs the functions defined in the system of this disclosure embodiment. According to embodiments of this disclosure, the systems, devices, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0128] According to embodiments of this disclosure, program code for executing the computer programs provided in embodiments of this disclosure can be written in any combination of one or more programming languages. Specifically, these computational programs can be implemented using high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. Programming languages ​​include, but are not limited to, languages ​​such as Java, C++, Python, "C", or similar programming languages. The program code can execute entirely on the user's computing device, partially on the user's device, partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0129] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0130] Those skilled in the art will understand that the features described in the various embodiments and / or claims of this disclosure can be combined or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments and / or claims of this disclosure can be combined or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0131] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A chip on-orbit reconfiguration method, comprising: The main control chip responds to the reconstruction instruction sent by the receiving management terminal and executes the reconstruction instruction to erase the data in the target address region of the first memory chip indicated by the reconstruction instruction; The main control chip returns feedback information to the management terminal indicating that the data erasure has been completed. The management terminal is configured to send a configuration data packet to the main control chip in response to the feedback information. The main control chip writes the configuration data packet into the target address region of the first storage chip; The main control chip executes a restart command to control the service chip to enter a restart state, wherein the service chip is configured to send a resource loading command to the main control chip in response to being in the restart state; and The main control chip simulates the interface timing of the second storage chip connected to the service chip in order to receive the resource loading instruction; The main control chip parses the resource loading instruction to obtain the type of the resource loading instruction and its corresponding parameters; The main control chip reads the configuration data packet from the first storage chip according to the type and corresponding parameters of the resource loading instruction; The main control chip sends the configuration data packet to the service chip.

2. The method according to claim 1, further comprising: The correctness of the configuration data packet is verified, and the verification result is obtained; as well as If the verification result indicates that the correctness verification has been passed, the configuration data packet is written to the first storage chip.

3. The method according to claim 2, wherein, The configuration data packet includes multiple configuration data frames; The step of verifying the correctness of the configuration data packet and obtaining the verification result includes: Each configuration data frame is checked for correctness to obtain multiple first verification results. Perform an overall correctness check on the configuration data packet to obtain a second check result; and Based on the second verification result and multiple first verification results, a verification result is determined.

4. The method according to claim 3, wherein the configuration data frame includes a frame header, a frame sequence number, configuration data, an intra-frame correctness check value, and a frame trailer; in, The step of performing correctness checks on each configuration data frame includes: Based on the frame header, the frame tail, and the frame sequence number, a third verification result is obtained; Based on the configuration data and the intra-frame correctness check value, a fourth check result is obtained; and Based on the third and fourth verification results, the first verification result is determined.

5. The method according to claim 4, wherein, The overall correctness check of the configuration data packet includes: Based on the intra-frame correctness check values ​​of each of the multiple configuration data frames in the configuration data packet except for the last configuration data frame, a first correctness check value is obtained; Based on the configuration data of the last configuration data frame in the configuration data packet, a second correctness check value of the configuration data packet is obtained; The first correctness check value is compared with the second correctness check value to obtain the second check result.

6. The method according to claim 1, further comprising: In response to receiving fault identification information from the service chip, if the fault identification information indicates a functional error after reconstruction, a rollback instruction is sent to the service chip, wherein the service chip is configured to execute the rollback instruction, load the configuration data packet before reconstruction from the second storage chip, and perform reconstruction rollback based on the configuration data packet before reconstruction.

7. A chip on-orbit reconfiguration device, comprising: The reconfiguration instruction execution module is used by the main control chip to respond to the reconfiguration instruction sent by the receiving management terminal, and to execute the reconfiguration instruction to erase the data in the target address region of the first memory chip indicated by the reconfiguration instruction; The information feedback module is used for the main control chip to return feedback information indicating that the data erasure has been completed to the management terminal, wherein the management terminal is configured to send a configuration data packet to the main control chip in response to the feedback information; A data writing module is used by the main control chip to write the configuration data packet into the target address region of the first storage chip; A restart instruction execution module is used for the main control chip to execute a restart instruction to control the service chip to enter a restart state, wherein the service chip is configured to send a resource loading instruction to the main control chip in response to being in the restart state; The instruction response module is used by the main control chip to simulate the interface timing of the second storage chip connected to the service chip to receive the resource loading instruction; the main control chip parses the resource loading instruction to obtain the type of the resource loading instruction and the corresponding parameters; the main control chip reads the configuration data packet from the first storage chip according to the type of the resource loading instruction and the corresponding parameters; and the main control chip sends the configuration data packet to the service chip.

8. An electronic device, comprising: One or more processors; Storage device for storing one or more programs. Wherein, when the one or more programs are executed by the one or more processors, the one or more processors perform the method according to any one of claims 1 to 6.

9. A computer-readable storage medium having stored thereon executable instructions that, when executed by a processor, cause the processor to perform the method according to any one of claims 1 to 6.

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