Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure includes: removing an initial dielectric layer in a second region, forming a first opening in the initial dielectric layer; filling a limiting dielectric layer in the first opening, the limiting dielectric layer having an etching selectivity ratio between a material of the limiting dielectric layer and a material of the initial dielectric layer; removing a remaining initial dielectric layer in a first region by using an isotropic etching process, forming a second opening, the second opening including an interconnection groove in the limiting dielectric layer and exposing a source / drain doped region, and a conductive via in an isolation layer and exposing a power supply rail, the conductive via being located at a bottom of the interconnection groove and communicating with the interconnection groove; and filling the conductive via and the interconnection groove, forming a conductive plug in the conductive via and a source / drain interconnection layer in the interconnection groove, the conductive plug being in contact with the power supply rail and the source / drain interconnection layer, respectively. The embodiment of the present application reduces a contact resistance between the conductive plug and the power supply rail and a resistance of the conductive plug.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a method for forming a semiconductor structure. Background Technology

[0002] To meet the ever-growing needs of logic chip miniaturization, and to optimize power supply capabilities when metal spacing is very tight, one approach is to move the power rails down into the substrate to form buried power rails (BPR).

[0003] In buried power rail structures, the power rails are embedded in the substrate, extending deep into the shallow trench isolation (STI) module, thereby freeing up interconnect wiring resources. Furthermore, buried power rails provide lower resistive local current distribution for techniques that increase BEOL resistance through pitch miniaturization. Additionally, buried power rails help reduce the effects of wiring congestion and resistance degradation on the grid-like distribution of VDD, VSS, word lines, and bit lines, improving write margin and read speed. To enable buried power rails to power the various components of the device, conductive plugs that contact the buried power rails are typically required.

[0004] However, forming conductive plugs for power rails still presents significant challenges. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure, thereby reducing the contact resistance between the conductive plug and the power rail, as well as the resistance of the conductive plug.

[0006] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, including a substrate, protrusions discretely disposed on the substrate, and a channel structure located on the protrusions; power rails arranged parallel to and spaced apart from the protrusions are further formed in the substrate; an isolation layer surrounding the protrusions is further formed on the substrate; a gate structure spanning the channel structure is formed on the isolation layer; source / drain doped regions are formed in the channel structures on both sides of the gate structure; an initial dielectric layer is further formed on the isolation layer and the source / drain doped regions on the side of the gate structure; the initial dielectric layer further covers the power rails; the substrate includes a first region and a second region, the first region being used to form a source / drain interconnect layer; wherein, along a projection plane parallel to the substrate, a portion of the first region has a distance from the power rails. Overlapping region; removing the initial dielectric layer located in the second region to form a first opening in the initial dielectric layer; filling the first opening with a limiting dielectric layer, wherein the material of the limiting dielectric layer has an etching selectivity ratio with the material of the initial dielectric layer; using an isotropic etching process to remove the remaining initial dielectric layer located in the first region to form a second opening, the second opening including an interconnect trench located in the limiting dielectric layer and exposing the source / drain doped regions, and a conductive via located in the isolation layer and exposing the power rail, the conductive via being located at the bottom of the interconnect trench and communicating with the interconnect trench; filling the conductive via and the interconnect trench to form a conductive plug located in the conductive via and a source / drain interconnect layer located in the interconnect trench, the conductive plug being in contact with the power rail and the source / drain interconnect layer respectively.

[0007] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0008] In the semiconductor structure formation method provided by this invention, an initial dielectric layer located in a second region is removed to form a first opening. Subsequently, a limiting dielectric layer is filled into the first opening. The material of the limiting dielectric layer has an etching selectivity ratio with the material of the initial dielectric layer. Therefore, in the step of forming the second opening (including interconnect trenches and conductive vias), the position and pattern of the second opening are defined by the limiting dielectric layer. Furthermore, an isotropic etching process can be used to remove the remaining initial dielectric layer located in the first region. The isotropic etching process has the characteristics of isotropic etching, which is beneficial for reducing the tapered profile of conductive vias. The probability of surface roughness is increased, thereby improving the sidewall steepness and cross-sectional morphology quality of the conductive via and increasing the bottom width of the conductive via. This, in turn, helps to increase the bottom size of the conductive plug and improve the cross-sectional morphology quality and dimensional accuracy of the conductive plug. Consequently, it increases the contact area between the conductive plug and the power rail and the volume of the conductive plug, and correspondingly reduces the contact resistance between the conductive plug and the power rail and the resistance of the conductive plug. In addition, the position and pattern of the conductive plug are defined by the overlapping area of ​​the first region and the power rail, so the process of forming the conductive plug does not require the use of an additional photomask, which helps to reduce the process cost. Attached Figure Description

[0009] Figures 1 to 3 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0010] Figures 4 to 23 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0011] As the background technology shows, forming power rail conductive plugs still presents significant challenges. This paper analyzes the reasons why forming power rail conductive plugs remains a challenging process, using a semiconductor structure formation method as an example.

[0012] Figures 1 to 3 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0013] refer to Figure 1 A substrate 10 is provided, including multiple device cell regions 10a and a power supply region 10b located between the device cell regions 10a. Discrete fins 11 are formed on the substrate 10 of the device cell regions 10a. Power rails 12 are formed in the substrate 10 of the power supply region 10b. An isolation layer 13 is also formed on the substrate 10 surrounding the fins 11. The top surface of the isolation layer 13 is lower than the top surface of the fins 11. A cover layer 14 covering the power rails 12 is formed in the isolation layer 13. A gate structure (not shown) spanning the fins 11 is also formed on the isolation layer 13 and the cover layer 14. Source and drain doped regions 15 are formed in the fins 11 on both sides of the gate structure. A contact etch barrier layer (not shown) is formed on the source and drain doped regions 15. An interlayer dielectric layer 16 is formed on the isolation layer 13 and the cover layer 14 on the side of the gate structure. The interlayer dielectric layer 16 covers the contact etch barrier layer.

[0014] refer to Figure 2 The interlayer dielectric layer 16 located on top of the source / drain doped region 15 and a portion of the thickness of the interlayer dielectric layer 16 in the power supply region 10b are removed to form a source / drain interconnect trench 5, which exposes the contact etch barrier layer on the source / drain doped region 15. A conductive via 6 is formed at the bottom of the source / drain interconnect trench 5, penetrating the interlayer dielectric layer 16 and the capping layer 14 in the power supply region 10b, and the conductive via 6 exposes the power rail 12. After forming the conductive via 6, the contact etch barrier layer exposed by the source / drain interconnect trench 5 is removed.

[0015] refer to Figure 3 After removing the contact etching barrier layer exposed in the source-drain interconnect trench 5, the conductive via 6 and the source-drain interconnect trench 5 are filled to form the power rail conductive plug 17 located in the conductive via 6 and the source-drain interconnect layer 18 located in the source-drain interconnect trench 5.

[0016] In the above method for forming a semiconductor structure, the contact etch barrier layer located on the source / drain doped region 15 can protect the source / drain doped region 15 during the step of forming the conductive via 6. Therefore, in order to prevent damage to the contact etch barrier layer during the step of forming the conductive via 6, over-etching is usually not performed or the amount of over-etching is small.

[0017] Correspondingly, the cross-section of the conductive via 6 is typically tapered, meaning that along the direction perpendicular to the substrate 10, the opening width of the conductive via 6 decreases as it approaches the power rail 12. The cross-section of the power rail conductive plug 17 is also tapered, resulting in a smaller bottom dimension of the power rail conductive plug 17. This further reduces the contact area between the power rail conductive plug 17 and the power rail 12, increasing the contact resistance between them and potentially leading to a higher resistance in the power rail conductive plug 17. Furthermore, the formation method described above requires a separate photomask for the conductive via 6, which can easily result in excessively high process costs.

[0018] To address the technical problem, embodiments of the present invention provide a method for forming a semiconductor structure. The method involves removing an initial dielectric layer located in a second region to form a first opening, followed by filling the first opening with a limiting dielectric layer. The material of the limiting dielectric layer has an etching selectivity ratio with the material of the initial dielectric layer. Thus, in the step of forming the second opening (including interconnect trenches and conductive vias), the position and pattern of the second opening are defined by the limiting dielectric layer. Furthermore, an isotropic etching process can be used to remove the remaining initial dielectric layer located in the first region. The isotropic etching process has the characteristics of isotropic etching, which is beneficial for reducing the number of conductive vias. The probability of having a tapered profile increases the steepness of the sidewalls and the quality of the cross-sectional morphology of the conductive via, as well as the width of the bottom of the conductive via. This, in turn, helps to increase the bottom size of the conductive plug and improve the cross-sectional morphology and dimensional accuracy of the conductive plug. Consequently, it increases the contact area between the conductive plug and the power rail, as well as the volume of the conductive plug, and reduces the contact resistance between the conductive plug and the power rail, as well as the resistance of the conductive plug. Furthermore, the position and shape of the conductive plug are defined by the overlapping area of ​​the first region and the power rail, so the process of forming the conductive plug does not require an additional photomask, which helps to reduce the process cost.

[0019] To make the above-mentioned objects, features, and advantages of the embodiments of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. (Reference) Figures 4 to 23 The diagram shows a schematic diagram of each step in an embodiment of the method for forming a semiconductor structure according to the present invention.

[0020] refer to Figures 4 to 11A substrate 200 is provided, including a substrate 100, a protrusion 110 discrete on the substrate 100, and a channel structure 120 located on the protrusion 110. Power rails 130 are also formed in the substrate 100, arranged parallel to and spaced apart from the protrusion 110. An isolation layer 140 is also formed on the substrate 100 surrounding the protrusion 110. A gate structure 150 is formed on the isolation layer 140, spanning the channel structure 120. Source / drain doped regions 160 are formed in the channel structures 120 on both sides of the gate structure 150. An initial dielectric layer 170 is also formed on the isolation layer 140 and the source / drain doped regions 160 on the side of the gate structure 150, and the initial dielectric layer 170 also covers the power rails 130. The substrate 200 includes a first region I and a second region II. The first region I is used to form a source / drain interconnect layer. Along a projection plane parallel to the substrate 100, a portion of the first region I overlaps with the power rails 130.

[0021] The substrate 200 is used to provide a platform for subsequent process technology.

[0022] In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate material may also be one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride. The substrate may also be other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates.

[0023] The protrusion 110 is used to support the channel structure 120. The protrusion 110 is also used to form an isolation layer 140 to provide space so that the isolation layer 140 can surround the protrusion 110 and expose the channel structure 120, and so that the isolation layer 140 can isolate the substrate 100 and the gate structure 150.

[0024] In this embodiment, the protrusion 110 and the substrate 100 are an integral structure, and the protrusion 110 and the substrate 100 are made of the same material, silicon. In other embodiments, the material of the protrusion may be different from that of the substrate. The material of the protrusion may be other suitable materials, such as one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride.

[0025] The channel structure 120 is used to provide a conductive channel for the field-effect transistor.

[0026] In this embodiment, the material of the channel structure 120 includes one or more of the following: monocrystalline silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride. In this embodiment, the material of the channel structure 120 is monocrystalline silicon.

[0027] In this embodiment, a fin field-effect transistor (FinFET) is used as an example for explanation. In a fin field-effect transistor, the gate structure 150 spans the fin and covers part of the top and sidewalls of the fin. The gate structure can control the fin from three sides, thereby improving the control capability of the gate structure 150 over the channel, which in turn helps to suppress short-channel effects and improve device performance.

[0028] Correspondingly, the channel structure 120 is a fin, which is used to provide the conductive channel for the fin field-effect transistor. In this embodiment, the fin and the protrusion 110 are an integral structure, and the fin and the protrusion are made of the same material.

[0029] In other embodiments, when forming other types of field-effect transistors, the channel structure can also be other types of channel structures accordingly. For example, a gate-all-around (GAA) transistor, a nanosheet field-effect transistor (NSFET), or a forksheet transistor can also be formed, with the channel structure suspended at intervals on the protrusions. The channel structure includes one or more channel layers that are suspended at intervals in sequence, with the stacking direction of the channel layers perpendicular to the substrate surface. The channel layers are used to provide conductive channels for the GAA transistor or the nanosheet field-effect transistor. The gate structure correspondingly surrounds the channel layer.

[0030] Power rails 130 are used to provide power to different components of the chip. In this embodiment, the power rails 130 are located in the substrate 100 of the power supply area. The power rails 130 are buried power rails (BPR), which helps to free up wiring resources for subsequent interconnects and reduces the height of standard cells to meet the needs of continuous logic chip miniaturization. In addition, buried power rails also help to provide a lower resistive local current distribution.

[0031] In this embodiment, the power rail 130 is a long strip structure. The extension direction of the power rail 130 is parallel to that of the channel structure 120 and the protrusion 110, and there is a gap between the power rail 130, the channel structure 120 and the protrusion 110.

[0032] The power rail 130 is made of a conductive material. In this embodiment, the power rail 130 is made of a metallic material, including one or more of Co, W, Ni, and Ru. By selecting these materials, the resistivity of the power rail 130 is low, which is beneficial for improving RC delay and increasing the processing speed of the chip.

[0033] It should be noted that, in this embodiment, an insulating layer (not shown) is also formed between the power rail 130 and the substrate 100.

[0034] The insulating layer is used to achieve insulation between the power rail 130 and the substrate 100. Therefore, the material of the insulating layer 125 is an insulating material, such as silicon oxide, silicon oxynitride, or silicon nitride.

[0035] The isolation layer 140 is used to isolate adjacent protrusions 110, and the isolation layer 140 is also used to isolate the substrate 100 from the gate structure 150. The isolation layer 140 surrounds the protrusions 110 and exposes the channel structure 120.

[0036] In this embodiment, the isolation layer 140 is a shallow trench isolation structure (STI). The material of the isolation layer 140 is an insulating material, including one or more of silicon oxycarbonate, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon carbonitride, germanium silicon oxide, boron nitride, and boron carbonitride. The isolation layer 140 is selected from materials that have etching selectivity with the initial dielectric layer 170 to reduce the probability of damage to the isolation layer 140 during subsequent etching of the initial dielectric layer 170.

[0037] The gate structure 150 serves as the device gate structure, used to control the opening or closing of the conductive channel during device operation. In this embodiment, the gate structure 150 is located on the isolation layer 140.

[0038] In this embodiment, the channel structure 120 is a fin, and the gate structure 150 spans the fin and covers part of the top and part of the sidewalls of the fin. In other embodiments, when the channel structure is suspended from the protrusion and includes one or more spaced-apart channel layers, the gate structure correspondingly surrounds the channel layers.

[0039] In this embodiment, the extension direction of the gate structure 150 is perpendicular to the extension direction of the channel structure 120 and the power rail 130.

[0040] In this embodiment, the gate structure 150 is a metal gate structure. The gate structure 150 includes a gate dielectric layer (not shown), a work function layer (not shown) located on the gate dielectric layer, and a gate electrode layer (not shown) located on the work function layer.

[0041] The gate dielectric layer is used to achieve electrical insulation between the work function layer and the electrode material layer and the channel structure 120.

[0042] In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer. The material of the high-k gate dielectric layer is a high-k dielectric material; wherein, a high-k dielectric material refers to a dielectric material with a relative permittivity greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer is HfO2. In other embodiments, the material of the high-k gate dielectric layer may also be selected from ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc.

[0043] In other embodiments, the gate dielectric layer may further include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer. The gate oxide layer is made of one or both of silicon oxide and silicon oxynitride. In still other embodiments, the gate dielectric layer may consist only of a gate oxide layer.

[0044] The work function layer is used to adjust the work function of the metal gate structure, thereby regulating the threshold voltage of the transistor. When forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the work function layer includes one or more of titanium aluminide, tantalum carbide, aluminum, or titanium carbide. When forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the work function layer includes one or more of titanium nitride, tantalum nitride, titanium carbide, silicon tantalum nitride, silicon titanium nitride, and tantalum carbide.

[0045] The electrode material layer serves as an electrode to draw out the electrical properties of the metal gate structure, thereby achieving electrical connection between the metal gate structure and the external circuit.

[0046] In this embodiment, the electrode material layer is made of W. In other embodiments, the electrode material layer may also be made of Al, Cu, Ag, Au, Pt, Ni, or Ti, etc.

[0047] It should be noted that, in this embodiment, a gate cap layer 155 is also formed on the top of the gate structure 150, and the gate cap layer 155 is used to protect the top of the gate structure 150.

[0048] The gate cap layer 155 can be made of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbonate, silicon carbonitride, boron nitride, and boron carbonitride.

[0049] In this embodiment, a gate sidewall 180 is also formed on the sidewalls of the gate structure 150 and the gate cap layer 155. The gate sidewall 180 is used to protect the sidewalls of the gate structure 150 and the gate cap layer 155, and is also used to define the formation location of the source and drain doped regions 160.

[0050] The gate sidewall 180 can be made of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbonate, silicon carbonitride, boron nitride, and boron carbonitride. The gate sidewall 180 can be a single-layer structure or a multilayer structure. In this embodiment, the gate sidewall 180 is a single-layer structure, and the material of the gate sidewall 180 is silicon nitride.

[0051] When the device is operating, the source / drain doped regions 160 are used to provide carrier sources. In this embodiment, the source / drain doped regions 160 are located in the fins on both sides of the gate structure 150.

[0052] In this embodiment, the source / drain doped region 160 includes a stress layer doped with ions. The source / drain doped region 160 is also used to provide stress to the channel, thereby improving the carrier mobility of the channel.

[0053] Specifically, when forming an NMOS transistor, the source and drain doped regions 160 are made of a stress layer doped with N-type ions. The stress layer is made of Si or SiC. The stress layer provides tensile stress to the channel region of the NMOS transistor, which helps to improve the carrier mobility of the NMOS transistor. The N-type ions are P ions, As ions, or Sb ions.

[0054] When forming a PMOS transistor, the source and drain doped regions 160 are made of a stress layer doped with P-type ions. The stress layer material includes Si or SiGe. The stress layer provides compressive stress to the channel region of the PMOS transistor, which helps to improve the carrier mobility of the PMOS transistor. The P-type ions are B ions, Ga ions, or In ions.

[0055] The initial dielectric layer 170 located in the first region I is used to occupy space for the subsequent formation of the source-drain interconnect layer and conductive plug, and the initial dielectric layer 170 located in the second region II is used to occupy space for the subsequent formation of the limiting dielectric layer.

[0056] The initial dielectric layer 170 is made of an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In this embodiment, the initial dielectric layer 170 is made of silicon oxide.

[0057] It should be noted that, in this embodiment, during the step of providing the substrate 200, there is an etching selectivity ratio between the materials of the isolation layer 140 and the initial dielectric layer 170. Subsequently, the initial dielectric layer 170 located in the second region II is removed to form the first opening, and a limiting dielectric layer is filled into the first opening. The remaining initial dielectric layer 170 located in the first region I is also removed to form the second opening. During these steps, there is an etching selectivity ratio between the materials of the isolation layer 140 and the initial dielectric layer 170. This allows the isolation layer 140 to define the etching stop position, and reduces the probability of damage to the isolation layer 140, thereby improving the profile control of the first and second openings.

[0058] In this embodiment, the material of the initial dielectric layer 170 includes one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0059] The steps for providing the substrate in this embodiment will be described in detail below with reference to the accompanying drawings.

[0060] like Figure 4 As shown, a substrate 100 is provided, which includes a device cell region (not shown) and a power supply region (not shown) located between the device cell regions. Separate protrusions 110 and channel structures 120 located on the protrusions 110 are formed on the substrate 100 of the device cell region.

[0061] It should be noted that a channel mask layer 125 is also formed on the top of the channel structure 120. The channel mask layer 125 is used as an etching mask for forming the channel structure 120 and the protrusion 110, and the channel mask layer 125 can also protect the top of the channel structure 120 in subsequent process steps.

[0062] As an example, the material of the channel mask layer 125 is silicon nitride.

[0063] like Figure 5 As shown, an isolation material layer 135 covering the protrusion 110 and the channel structure 120 is formed on the substrate 100. The isolation material layer 135 is used for subsequent formation of the isolation layer, and also serves to protect the channel structure 120 and the protrusion 110 during the subsequent formation of the power rail.

[0064] Specifically, the insulating material layer 135 is located on the substrate 100 and surrounds the protrusion 110 and the channel structure 120.

[0065] In this embodiment, the insulating material layer 135 also surrounds the trench mask layer 125.

[0066] like Figure 6 As shown, a trench 105 is formed, which extends through the power supply area, forming an isolation material layer 135 and a partially thick substrate 100. The trench 105 provides space for the formation of power rails.

[0067] In this embodiment, an anisotropic etching process is used to sequentially etch the isolation material layer of the power supply area and a portion of the substrate 100 to form a trench 105.

[0068] like Figure 7 As shown, a power rail 130 is formed at the bottom of the groove 105, and the top surface of the power rail 130 is lower than the top surface of the protrusion 110.

[0069] Specifically, the steps for forming the power rail 130 include: filling the trench 105 with a power rail material layer (not shown), the power rail material layer also being formed on the insulating material layer 135; using a planarization process to remove the power rail material layer above the top surface of the insulating material layer 135; removing a portion of the thickness of the power rail material layer located in the trench 105, the remaining power rail material layer located in the trench 105 being used as the power rail 130.

[0070] like Figure 8 As shown, an initial cover layer 115 is formed on the power rail 130 to fill the groove 105.

[0071] The initial capping layer 115 is used for subsequent capping layer formation. In this embodiment, the process for forming the initial capping layer 115 includes chemical vapor deposition, flow-through chemical vapor deposition, or high aspect ratio deposition, etc.

[0072] It should be noted that, in this embodiment, after the power rail 130 is formed and before the initial cover layer 115 is formed, the forming method further includes: forming the bottom and sidewalls of the conformal cover trench 105 and the padding layer 145 on the top surface of the isolation material layer 135 and the trench mask layer 125.

[0073] The padding layer 145 is used to isolate the power rail 130 from the initial cover layer 115, preventing oxygen from diffusing into the power rail 130 caused by the thermal process of forming the initial cover layer 115, which would reduce the resistance of the power rail 130. In addition, the padding layer 145 is also used to prevent the material of the initial cover layer 115 from diffusing outward and causing contamination in the front-end process.

[0074] The pad layer 145 is selected from a material that has etching selectivity with the material of the etch barrier layer. In the subsequent step of removing the remaining initial dielectric layer 190 located in the first region I, the pad layer 145 can be removed, and the probability of damage to the etch barrier layer is reduced, thereby preventing damage to the source and drain doped regions.

[0075] In this embodiment, the material of the liner layer 145 includes a low-k dielectric material, such as SiOCN or SIBCN.

[0076] As an example, an atomic layer deposition process is used to form a backing layer 145.

[0077] Accordingly, in the step of forming the initial cover layer 115, the initial cover layer 115 covers the padding layer 145.

[0078] like Figure 9 As shown, the initial cover layer 115 and the insulating material layer 135 above the protrusion 110 are removed, and the remaining insulating material layer 135 is used as the insulating layer 140, and the remaining initial cover layer 115 on the power rail 130 is used as the cover layer 171.

[0079] The capping layer 171 is used together with the subsequently formed interlayer dielectric layer to form the initial dielectric layer.

[0080] In this embodiment, the cover layer 171 is made of a material that has etching selectivity with the material of the isolation layer 140. Therefore, in the subsequent step of removing the remaining initial dielectric layer located in the first region I, the cover layer 171 and the isolation layer 140 have an etching selectivity ratio, which helps to reduce the probability of the cover layer 171 causing damage to the isolation layer 140 when removing the cover layer 171 in the first region I, and also helps to improve the profile control of the conductive via.

[0081] As one embodiment, the material of the capping layer 171 is silicon oxide.

[0082] In this embodiment, in the step of removing the initial cover layer 115 and the isolation material layer 135 above the protrusion 110, the channel mask layer 125 and the padding layer 145 above the protrusion 110 are also removed.

[0083] like Figures 10 to 11 As shown, Figure 11 yes Figure 10 A cross-sectional view along the x1-x1 direction shows a gate structure 150 located on the isolation layer 140 and the capping layer 171 and spanning the channel structure 120, source / drain doped regions 160 located on both sides of the gate structure 150 within the channel structure 120, and an interlayer dielectric layer 172 located on the isolation layer 140, the capping layer 171, and the source / drain doped regions 160 on the side of the gate structure 150. The interlayer dielectric layer 172 and the capping layer 171 are used as the initial dielectric layer 170.

[0084] The interlayer dielectric layer 172 is made of a material that is etch-selective with the material of the isolation layer 140, thereby reducing the probability of damage to the isolation layer 140 in the subsequent steps of removing the initial dielectric layer 170 located in the second region II to form the first opening and removing the remaining initial dielectric layer 170 located in the first region I to form the second opening, thereby improving the profile control of the first opening and the second opening.

[0085] As an example, the material of the interlayer dielectric layer 172 is the same as that of the capping layer 171, thereby improving process compatibility.

[0086] As one embodiment, the steps of forming the gate structure 150, the source / drain doped regions 160, and the interlayer dielectric layer 172 include: forming a dummy gate structure (not shown) on the isolation layer 140 and the capping layer 171 and spanning the channel structure 120; forming source / drain doped regions 160 in the channel structure 120 on both sides of the dummy gate structure; forming an interlayer dielectric layer 172 on the isolation layer 140, the capping layer 171, and the source / drain doped regions 160 on the side of the dummy gate structure (not shown); after forming the interlayer dielectric layer 172, removing the dummy gate structure to form a gate opening (not shown); and forming the gate structure 150 in the gate opening.

[0087] Specifically, after the formation of the dummy gate structure and before the formation of the source / drain doped region 160, a gate sidewall 180 is formed on the sidewall of the dummy gate structure.

[0088] Furthermore, after forming the gate structure 150, a portion of the thickness of the gate structure 150 is removed, so that the top of the remaining gate structure 150 and the gate sidewall 180 form a gate groove (not shown); a gate cap layer 155 is formed in the gate groove.

[0089] It should be noted that, in this embodiment, the step of providing the substrate 200 further includes: after forming the source / drain doped region 160 and before forming the interlayer dielectric layer 172, forming a contact etch barrier layer (not shown).

[0090] The contact stop layer (CESL) is used to define the location of the etch stop in the subsequent step of forming the first opening, thereby reducing the probability of damage to the source / drain doped region 160 caused by removing the initial dielectric layer 170 of the second region II; and in the subsequent step of forming the second opening, the contact stop layer can protect the source / drain doped region 160, thereby reducing the probability of damage to the source / drain doped region 160.

[0091] The contact etch barrier layer is made of a material that has etch selectivity with the initial dielectric layer 170. As an example, the material of the contact etch barrier layer includes silicon nitride.

[0092] refer to Figures 12 to 15 Remove the initial dielectric layer 170 located in the second region II and form a first opening 210 in the initial dielectric layer 170.

[0093] The first opening 210 is used to provide space for the subsequent formation of the limiting medium layer.

[0094] In this embodiment, the step of forming the first opening 210 includes:

[0095] like Figures 12 to 13 As shown, Figure 13 yes Figure 12 A cross-sectional view along the x1-x1 direction shows a mask layer 214 formed on the initial dielectric layer 170 of the first region I.

[0096] The mask layer 214 is used as a mask for etching the initial dielectric layer 170 to form the first opening 210.

[0097] In this embodiment, the mask layer 214 can be formed by using the reversed pattern of the source-drain interconnect layer, so that the mask layer 214 can be formed without the need for an additional photomask, which helps to save costs.

[0098] Specifically, the pattern of the mask layer 214 is complementary to the pattern of the source-drain interconnect layer.

[0099] In this embodiment, the material of the mask layer 214 includes photoresist.

[0100] In this embodiment, before forming the mask layer 214 on the initial dielectric layer 170 forming the first region I, the method further includes: forming a first hard mask material layer 211 on the initial dielectric layer 170 and the gate structure 150; forming a second hard mask material layer 212 on the first hard mask material layer 211; and forming a planarization layer 213 on the second hard mask material layer 212.

[0101] In this process, after the first hard mask material layer 211 is etched using the mask layer 214 as a mask, the remaining first mask material layer 211 can continue to serve as a mask for etching the initial dielectric layer 170, which is beneficial to improving the accuracy and stability of pattern transfer.

[0102] In this embodiment, the material of the first hard mask material layer 211 includes one or more of silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon germanium oxide, boron nitride, and boron carbonitride.

[0103] The second hard mask material layer 212 is selected from materials that have etching selectivity with the material of the first hard mask material layer 211, thereby improving the accuracy of pattern transfer and process stability.

[0104] As an example, the material of the second hard mask material layer 212 includes titanium nitride.

[0105] The planarization layer 213 is used to provide a flat top surface for forming the mask layer 214.

[0106] As an example, the material of the planarization layer 213 includes spin-on carbon (SOC).

[0107] like Figures 14 to 15 As shown, using the mask layer 214 as a mask, the initial dielectric layer 170 is etched to form the first opening 210 located in the second region II.

[0108] Specifically, in this embodiment, an anisotropic etching process is used to remove the initial dielectric layer 170 located in the second region II. In this embodiment, the anisotropic etching process includes a dry etching process. The dry etching process has high etching precision and profile control, thereby improving the sidewall steepness and profile quality of the first opening 210, and further improving the profile quality and sidewall steepness of the subsequent confining dielectric layer.

[0109] It should be noted that, in this embodiment, even in the step of forming the first opening 210, the cross-sectional shape of the first opening 210 is an inverted trapezoid along the extension direction perpendicular to the channel structure 120, that is, the bottom opening width of the first opening 210 is smaller than the top opening width. Correspondingly, the bottom width of the subsequent limiting layer is smaller than the top width. Thus, after the remaining initial dielectric layer 170 of the first region I is removed to form the second opening, the bottom opening size of the second opening is larger along the extension direction perpendicular to the channel structure 120, which in turn makes the bottom opening width of the formed conductive via larger, which is also beneficial to increasing the size of the bottom of the subsequent conductive plug.

[0110] refer to Figures 16 to 17 , Figure 17 yes Figure 16 A cross-sectional view along the x1-x1 direction shows that the first opening 210 is filled with a limiting dielectric layer 230, and the material of the limiting dielectric layer 230 has an etching selectivity ratio with the material of the initial dielectric layer 170.

[0111] The limiting dielectric layer 230 is used to define the position, pattern, and cross-sectional morphology of the subsequently formed second opening. The material of the limiting dielectric layer 230 has an etching selectivity ratio with the material of the initial dielectric layer 170, so that in the step of forming the second opening (including interconnect trenches and conductive vias), the position and pattern of the second opening are defined by the limiting dielectric layer 230, and an isotropic etching process can be used to remove the remaining initial dielectric layer 170 located in the first region I. The isotropic etching process has the characteristics of isotropic etching, which helps to reduce the probability of the conductive via having a tapered cross-section, thereby improving the sidewall steepness and cross-sectional morphology quality of the conductive via, and increasing the width of the bottom of the conductive via.

[0112] In this embodiment, the material of the limiting dielectric layer 230 includes one or more of silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon germanium oxide, boron nitride, and boron carbonitride.

[0113] As an example, the material of the limiting dielectric layer 230 is the same as that of the isolation layer 140, which is beneficial for improving process compatibility. In this embodiment, the material of the limiting dielectric layer 230 is carbon-containing silicon oxide, and the etching selectivity between carbon-containing silicon oxide and silicon oxide is relatively high.

[0114] In this embodiment, the step of forming the limiting medium layer 230 includes: filling the first opening 210 with a medium material layer (not shown), the medium material layer is also formed on the initial medium layer 170; removing the medium material layer above the top surface of the initial medium layer 170, and using the remaining medium material layer as the limiting medium layer.

[0115] In this embodiment, the process for forming the dielectric material layer includes a flow-through chemical vapor deposition process. This process provides good gap-filling capability, which is beneficial for improving the filling quality of the dielectric material layer within the first opening 210 and reducing the probability of defects such as voids in the dielectric material layer.

[0116] In this embodiment, a planarization process is used to remove the dielectric material layer that is 170 mm above the top surface of the initial dielectric layer. The planarization process helps to improve the flatness of the top surface of the remaining dielectric material layer.

[0117] As an example, the planarization process is chemical mechanical planarization (CMP). CMP is a global planarization process with high planarization efficiency and is beneficial for improving the flatness of the planarized film surface. Therefore, by selecting CMP, it is beneficial to improve the flatness and height consistency of the top surface of the dielectric material layer above the initial dielectric layer 170, as well as the top surface of the limiting dielectric layer 230, the initial dielectric layer 170, and the gate cap layer 155, thereby providing a flat top surface for subsequent process fabrication.

[0118] In this embodiment, in the step of removing the dielectric material layer on the top surface of the initial dielectric layer 170, the remaining first hard mask material layer 211 is also removed.

[0119] refer to Figures 18 to 20 , Figure 19 yes Figure 18 A sectional view along the x1-x1 direction. Figure 20 yes Figure 18 A cross-sectional view along the x2-x2 direction shows that an isotropic etching process is used to remove the remaining initial dielectric layer 170 located in the first region I, forming a second opening 220. The second opening 220 includes an interconnect trench 22 located in the limiting dielectric layer 230 and exposing the source / drain doped regions 160, and a conductive via 21 located in the isolation layer 140 and exposing the power rail 130. The conductive via 21 is located at the bottom of the interconnect trench 22 and is connected to the interconnect trench 22.

[0120] Interconnect slot 22 is used to provide space for forming source-drain interconnect layers.

[0121] The conductive through-hole 21 is used to provide space for forming the conductive plug.

[0122] There is an etching selectivity between the material of the limiting dielectric layer 230 and the material of the initial dielectric layer 170. In the step of forming the second opening 220, the position and pattern of the second opening 220 are defined by the limiting dielectric layer 230, and an isotropic etching process can be used to remove the remaining initial dielectric layer 170 located in the first region I. The isotropic etching process has the characteristics of isotropic etching. Compared with the anisotropic etching process, it is beneficial to reduce the probability of the conductive via 21 having a tapered cross-section, thereby improving the sidewall steepness and cross-sectional morphology quality of the conductive via 21, and increasing the width of the bottom of the conductive via 21.

[0123] Correspondingly, after the conductive plug is formed in the conductive through hole 21, it is beneficial to increase the bottom size of the conductive plug and improve the cross-sectional morphology quality and dimensional accuracy of the conductive plug, thereby increasing the contact area between the conductive plug and the power rail 130 and the volume of the conductive plug, and correspondingly reducing the contact resistance between the conductive plug and the power rail 130 and the resistance of the conductive plug.

[0124] Moreover, the position and pattern of the conductive via 21 are defined by the overlapping area of ​​the first region I and the power rail 130, so the process of forming the conductive via 21 does not require an additional photomask, which helps to reduce process costs.

[0125] Furthermore, the conductive via 21 and the interconnect trench 22 are formed in the same step by removing the remaining initial dielectric layer 170 located in the first region I. Compared with the conductive via and the interconnect trench being formed in different steps, this embodiment also helps to simplify the process flow.

[0126] In this embodiment, during the step of forming the second opening 220, the conductive via 21 penetrates the cover layer 171 at the top of the power rail 130. More specifically, the conductive via 21 penetrates the pad layer 145 and the cover layer 171 at the top of the power rail 130.

[0127] In this embodiment, the step of forming the second opening 220 includes: removing the remaining interlayer dielectric layer 172 and cover layer 171 located in the first region I; removing the padding layer 145 located in the first region I to expose the power rail 130.

[0128] In the step of removing the cover layer 171 located in the first region I, the pad layer 145 can temporarily define the location where the etching stops, thereby reducing the probability of damage to the power rail 130.

[0129] In this embodiment, the process for removing the remaining initial dielectric layer 170 located in the first region I includes a vapor phase etching process. Vapor phase etching is easy to achieve isotropic etching and has low process cost.

[0130] As an example, etching gases in vapor phase etching processes include NH3, HF, Ar, and He.

[0131] It should be noted that in this embodiment, an isotropic etching process is used to remove the initial dielectric layer 170 located in the first region I to form the first opening 210, and the cross-sectional morphology of the first opening 210 is defined by the limiting layer 230. The isotropic etching process has a high selectivity for etching the initial dielectric layer 170 and the contact etch barrier layer, so the probability of damage to the contact etch barrier layer is low, thereby enabling the contact etch barrier layer to protect the source and drain doped regions.

[0132] refer to Figures 21 to 23 The conductive via 21 and the interconnect trench 22 are filled to form a conductive plug 250 in the conductive via 21 and a source-drain interconnect layer 260 in the interconnect trench 22. The conductive plug 250 is in contact with the power rail 130 and the source-drain interconnect layer 260, respectively.

[0133] In the step of forming the second opening 220, it is beneficial to reduce the probability that the conductive via 21 has a tapered profile, thereby improving the steepness of the sidewall and the quality of the profile of the conductive via 21, as well as increasing the opening width at the bottom of the conductive via 21.

[0134] Correspondingly, after forming the conductive plug 250 located in the conductive via 21, it is beneficial to increase the bottom size of the conductive plug 250 and improve the cross-sectional morphology quality and dimensional accuracy of the conductive plug 250, thereby increasing the contact area between the conductive plug 250 and the power rail 130 and the volume of the conductive plug 250, and correspondingly reducing the contact resistance between the conductive plug 250 and the power rail 130 and the resistance of the conductive plug 250, thereby improving the electrical performance of the semiconductor structure, such as reducing voltage drop (IRdrop).

[0135] The conductive plug 250 contacts the power rail 130, thereby establishing an electrical connection between the power rail 130 and external circuits or other interconnect structures, and thus supplying power to different components of the chip. Specifically, in this embodiment, the conductive plug 250 contacts the source-drain interconnect layer 260, thereby supplying power from the power rail 130 to the source-drain interconnect layer 260, and in turn to the source-drain doped region 160.

[0136] The source-drain interconnect layer 260 is in contact with the source-drain doped region 160, thereby enabling electrical connection between the source-drain doped region 160 and external circuits or other interconnect structures.

[0137] In this embodiment, the source-drain interconnect layer 260 extends longitudinally, and the extension direction of the source-drain interconnect layer 260 is perpendicular to the extension direction of the power rail 130.

[0138] In this embodiment, on a projection plane parallel to the substrate 100, the source-drain interconnect layer 260 spans the power rail 130, and the extension direction of the source-drain interconnect layer 260 is perpendicular to the extension direction of the power rail 130. Thus, the position of the conductive plug 250 can be accurately located by the position of the source-drain interconnect layer 260 and the power rail 130, so that the conductive plug 250 is located at the overlapping position of the source-drain interconnect layer 250 pattern and the power rail 130 pattern.

[0139] In this embodiment, a conductive plug 250 is formed in the conductive via 21 and a source-drain interconnect layer 260 is formed in the interconnect trench 22 through a filling process. The conductive plug 250 and the source-drain interconnect layer 260 are integral structures, which helps to reduce the contact resistance between the conductive plug 250 and the source-drain interconnect layer 260 and improve the performance of the semiconductor structure.

[0140] Therefore, the conductive plug 250 and the source-drain interconnect layer 260 are made of the same material. Both the conductive plug 250 and the source-drain interconnect layer 260 are made of conductive materials. In this embodiment, the conductive plug 250 and the source-drain interconnect layer 260 are made of metallic materials, such as one or more of W, Co, Cu, Ru, and Ni.

[0141] In this embodiment, the steps of forming the conductive plug 250 and the source-drain interconnect layer 260 include: filling the conductive via 21 and the interconnect trench 22 with conductive material (not shown), the conductive material is also formed on the limiting dielectric layer 230; removing the conductive material above the top surface of the limiting dielectric layer 230, the remaining conductive material in the conductive via 21 is used as the conductive plug 250, and the remaining conductive material in the interconnect trench 22 is used as the source-drain interconnect layer 260.

[0142] In this embodiment, the process for forming the conductive material may include one or more of physical vapor deposition, chemical vapor deposition, and electrochemical plating.

[0143] In this embodiment, a planarization process is used to remove the conductive material above the top surface of the limiting dielectric layer 230. Specifically, the planarization process can be a chemical mechanical planarization (CMP) process.

[0144] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, including a substrate, protrusions discrete on the substrate, and a channel structure located on the protrusions. Power rails are also formed in the substrate, spaced parallel to the protrusions. An isolation layer is also formed on the substrate surrounding the protrusions. A gate structure is formed on the isolation layer spanning the channel structure. Source / drain doped regions are formed in the channel structures on both sides of the gate structure. An initial dielectric layer is also formed on the isolation layer and the source / drain doped regions on the side of the gate structure, and the initial dielectric layer also covers the power rails. The substrate includes a first region and a second region, the first region being used to form a source / drain interconnect layer. Specifically, along a projection plane parallel to the substrate, a portion of the first region overlaps with the power rails. Remove the initial dielectric layer located in the second region and form a first opening in the initial dielectric layer; A limiting medium layer is filled into the first opening, and the material of the limiting medium layer has an etching selectivity ratio with the material of the initial medium layer; An isotropic etching process is used to remove the remaining initial dielectric layer in the first region to form a second opening. The second opening includes an interconnect trench located in the limiting dielectric layer and exposing the source and drain doped regions, and a conductive via located in the isolation layer and exposing the power rail. The conductive via is located at the bottom of the interconnect trench and is connected to the interconnect trench. The conductive vias and interconnect trenches are filled to form conductive plugs in the conductive vias and source-drain interconnect layers in the interconnect trenches. The conductive plugs are in contact with the power rails and the source-drain interconnect layers, respectively.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming the first opening includes: forming a mask layer on the initial dielectric layer in the first region; Using the mask layer as a mask, the initial dielectric layer is etched to form the first opening located in the second region.

3. The method for forming a semiconductor structure as described in claim 1 or 2, characterized in that, An anisotropic etching process is used to remove the initial dielectric layer located in the second region.

4. The method for forming a semiconductor structure as described in claim 3, characterized in that, The anisotropic etching process includes dry etching.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of providing the substrate, there is an etching selectivity ratio between the materials of the isolation layer and the initial dielectric layer.

6. The method for forming a semiconductor structure as described in claim 1 or 5, characterized in that, The material of the limiting medium layer is the same as the material of the isolation layer.

7. The method for forming a semiconductor structure as described in claim 1 or 5, characterized in that, In the step of providing the substrate, the material of the insulating layer includes one or more of silicon oxycarbonate, silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon carbonitride, silicon germanium oxide, boron nitride, and boron carbonitride; The material of the initial dielectric layer includes one or more of silicon oxide, silicon nitride, and silicon oxynitride. In the step of forming the limiting dielectric layer, the material of the limiting dielectric layer includes one or more of silicon oxycarbonate, silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon carbonitride, silicon germanium oxide, boron nitride, and boron carbonitride.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming the limiting medium layer includes: filling the first opening with a medium material layer, wherein the medium material layer is also formed on the initial medium layer; Remove the dielectric material layer above the top surface of the initial dielectric layer, and use the remaining dielectric material layer as the limiting dielectric layer.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The process for forming a dielectric material layer includes flow chemical vapor deposition.

10. The method for forming a semiconductor structure as described in claim 8, characterized in that, A planarization process is used to remove the dielectric material layer that is above the top surface of the initial dielectric layer.

11. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of providing a substrate includes: providing a substrate, the substrate including a device cell region and a power supply region located between the device cell regions, wherein discrete protrusions and channel structures located on the protrusions are formed on the substrate of the device cell region; An insulating material layer covering the protrusions and the channel structure is formed on the substrate; A trench is formed that extends through the isolation material layer and a portion of the substrate thickness of the power supply area; The power rail is formed at the bottom of the groove, and the top surface of the power rail is lower than the top surface of the protrusion. An initial cover layer is formed on the power rail to fill the trench; Remove the initial cover layer and the insulating material layer that are above the protrusion, and use the remaining insulating material layer as an insulating layer; use the remaining initial cover layer located on the power rail as a cover layer. A gate structure is formed on the isolation layer and the capping layer and spanning the channel structure, the source and drain doped regions are located in the channel structures on both sides of the gate structure, and an interlayer dielectric layer is formed on the isolation layer, the capping layer and the source and drain doped regions on the side of the gate structure, wherein the interlayer dielectric layer and the capping layer are used as the initial dielectric layer; In the step of forming the second opening, the conductive via penetrates the cover layer at the top of the power rail.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, The material of the cover layer is the same as the material of the interlayer dielectric layer.

13. The method for forming a semiconductor structure as described in claim 11, characterized in that, The steps of forming the gate structure, source / drain doped regions, and interlayer dielectric layer include: forming a pseudo-gate structure on the isolation layer and capping layer and spanning the channel structure; forming source / drain doped regions in the channel structure on both sides of the pseudo-gate structure; forming the interlayer dielectric layer on the isolation layer, capping layer, and source / drain doped regions on the side of the pseudo-gate structure; after forming the interlayer dielectric layer, removing the pseudo-gate structure to form a gate opening; and forming the gate structure in the gate opening.

14. The method for forming a semiconductor structure as described in claim 11, characterized in that, The step of providing the substrate further includes forming a contact etch barrier layer on the source / drain doped regions after forming the source / drain doped regions and before forming the interlayer dielectric layer.

15. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process for removing the remaining initial dielectric layer located in the first region includes a vapor phase etching process, and the etching gases include NH3, HF, Ar and He.

16. The method for forming a semiconductor structure as described in claim 1, characterized in that, The steps of forming the conductive plug and the source-drain interconnect layer include: filling the conductive via and the interconnect groove with conductive material, the conductive material also being formed on the limiting dielectric layer; removing the conductive material above the top surface of the limiting dielectric layer, the remaining conductive material in the conductive via being used as the conductive plug, and the remaining conductive material in the interconnect groove being used as the source-drain interconnect layer.

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