DC-DC converter

Abstract

Embodiments of this disclosure provide a DC-DC converter, comprising: upper and lower power transistors, an inductor, a bootstrap capacitor, a first transistor, a power supply control circuit, a drive control circuit, and a drive circuit. The drive circuit generates a power-on signal for the upper and lower transistors based on a drive control signal. The two ends of the bootstrap capacitor are respectively coupled to a first node and the first terminal of the first transistor. The power supply control circuit generates a power supply control voltage based on a PWM signal. When the PWM signal is at a first level, the power supply control voltage is set to the voltage at the first terminal of the first transistor; when the PWM signal is at a second level, the power supply control voltage is set to the voltage at the first node. The control terminal of the first transistor is provided with the power supply control voltage. The drive control circuit determines the switching state of the first transistor based on the power supply control voltage, and sets the drive control signal to the first level when the PWM signal is at the first level and the first transistor is completely off, otherwise sets the drive control signal to the second level.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of integrated circuit technology, and more specifically, to DC-DC converters. Background Technology

[0002] DC-DC converters are commonly used in various electronic devices to convert DC voltages. DC-DC converters include buck converters and boost converters. Buck converters convert higher DC voltages to lower DC voltages, while boost converters convert lower DC voltages to higher DC voltages. In applications with wide input / output ranges, excessively high input or output voltages can cause the upper power transistor to be mistakenly turned off. To avoid this problem, a bootstrap capacitor is typically used to keep the upper power transistor on. Summary of the Invention

[0003] The embodiments described herein provide a DC-DC converter.

[0004] According to a first aspect of this disclosure, a DC-DC converter is provided. The DC-DC converter includes: an upper power transistor, a lower power transistor, an inductor, a bootstrap capacitor, a first transistor, a power supply control circuit, a drive control circuit, and a drive circuit. The drive circuit is configured to generate an upper power transistor turn-on signal and a lower power transistor turn-on signal based on a drive control signal output by the drive control circuit. When the drive control signal is at a first level, the upper power transistor turn-on signal is at an active level and the lower power transistor turn-on signal is at an inactive level. When the drive control signal is at a second level, the upper power transistor turn-on signal is at an inactive level and the lower power transistor turn-on signal is at an active level. The control terminal of the upper power transistor is provided with the upper power transistor turn-on signal. The control terminal of the lower power transistor is provided with the lower power transistor turn-on signal. The first terminal of the upper power transistor is coupled to the second terminal of the lower power transistor and the first terminal of the inductor via a first node. The two terminals of the bootstrap capacitor are respectively coupled to the first node and the first terminal of the first transistor. The power supply control circuit is configured to generate a power supply control voltage based on a PWM signal. Specifically, when the PWM signal is at a first level, the supplementary power control voltage is set to the voltage at the first terminal of the first transistor, and when the PWM signal is at a second level, the supplementary power control voltage is set to the voltage at the first node. The control terminal of the first transistor is provided with the supplementary power control voltage. The second terminal of the first transistor is coupled to the supplementary power voltage terminal. The drive control circuit is configured to: determine the switching state of the first transistor based on the supplementary power control voltage, and, when the PWM signal is at the first level and the first transistor is completely off, set the drive control signal to the first level; otherwise, set the drive control signal to the second level.

[0005] In some embodiments of this disclosure, the drive control circuit includes a shutdown determination circuit and a control signal output circuit. The shutdown determination circuit is configured to output a shutdown indication signal at an active level when the supplementary control voltage is greater than or equal to a reference voltage, and otherwise output a shutdown indication signal at an inactive level. The active level of the shutdown indication signal indicates that the first transistor has been completely turned off, and the reference voltage is set according to the threshold voltage of the first transistor. The control signal output circuit is configured to output a drive control signal at a first level when the PWM signal is at a first level and the shutdown indication signal is at an active level, and otherwise output a drive control signal at a second level.

[0006] In some embodiments of this disclosure, the shutdown determination circuit includes a voltage comparator. A first input terminal of the voltage comparator is coupled to the control electrode of a first transistor. A second input terminal of the voltage comparator is coupled to a reference voltage terminal. A reference voltage is output from the reference voltage terminal. The output terminal of the voltage comparator is coupled to a control signal output circuit.

[0007] In some embodiments of this disclosure, the shutdown determination circuit includes a Schmitt trigger and a first level-shifting circuit. The input of the Schmitt trigger is coupled to the control electrode of a first transistor. An upper threshold of the Schmitt trigger is set to a reference voltage. The Schmitt trigger is configured to generate a trigger signal based on a supplementary control voltage. The trigger signal flips to a third level when the supplementary control voltage rises to the reference voltage, and flips to a fourth level when the supplementary control voltage falls to a lower threshold. The lower threshold is lower than the reference voltage. The first level-shifting circuit is configured to generate a shutdown indication signal based on the trigger signal. The third level of the trigger signal is converted to an active level for the shutdown indication signal, and the fourth level of the trigger signal is converted to an inactive level for the shutdown indication signal.

[0008] In some embodiments of this disclosure, the control signal output circuit includes an AND gate. A first input terminal of the AND gate is provided with a turn-off indication signal. A PWM signal is provided at the second input terminal of the AND gate. A drive control signal is output from the output terminal of the AND gate.

[0009] In some embodiments of this disclosure, the power-up control circuit includes a second level-shifting circuit and second to fifth transistors. The second level-shifting circuit is configured to convert a first level of the PWM signal to a fifth level and a second level of the PWM signal to a sixth level. The control electrode of the second transistor is coupled to the control electrode of the third transistor and the output of the second level-shifting circuit. The first electrode of the second transistor is coupled to the first electrode of the first transistor and the first electrode of the fourth transistor. The second electrode of the second transistor is coupled to the second electrode of the third transistor, the control electrode of the fourth transistor, and the control electrode of the fifth transistor. The first electrode of the third transistor is coupled to the first node and the first electrode of the fifth transistor. The second electrode of the fourth transistor is coupled to the second electrode of the fifth transistor and the control electrode of the first transistor.

[0010] In some embodiments of this disclosure, both the upper power transistor and the lower power transistor are NMOS transistors.

[0011] In some embodiments of this disclosure, the first transistor is a PMOS transistor.

[0012] In some embodiments of this disclosure, the second terminal of the power transistor is coupled to one of the input voltage terminal and the output voltage terminal. The second terminal of the inductor is coupled to the other of the input voltage terminal and the output voltage terminal.

[0013] According to a second aspect of this disclosure, a DC-DC converter is provided. The DC-DC converter includes: an upper power transistor, a lower power transistor, an inductor, a bootstrap capacitor, first to fifth transistors, a Schmitt trigger, a first level-shifting circuit, a second level-shifting circuit, an AND gate, and a drive circuit. The drive circuit is configured to generate an upper transistor turn-on signal and a lower transistor turn-on signal based on a drive control signal output from the output of the AND gate. When the drive control signal is at a first level, the upper transistor turn-on signal is at an active level and the lower transistor turn-on signal is at an inactive level. When the drive control signal is at a second level, the upper transistor turn-on signal is at an inactive level and the lower transistor turn-on signal is at an active level. The control terminal of the upper power transistor is provided with the upper transistor turn-on signal. The control terminal of the lower power transistor is provided with the lower transistor turn-on signal. The first terminal of the upper power transistor is coupled to the second terminal of the lower power transistor and the first terminal of the inductor via a first node. The two terminals of the bootstrap capacitor are respectively coupled to the first node and the first terminal of the first transistor. The second level-shifting circuit is configured to convert the first level of the PWM signal to a fifth level and to convert the second level of the PWM signal to a sixth level. The control electrode of the second transistor is coupled to the control electrode of the third transistor and the output of the second level conversion circuit. The first electrode of the second transistor is coupled to the first electrode of the first transistor and the first electrode of the fourth transistor. The second electrode of the second transistor is coupled to the second electrode of the third transistor, the control electrode of the fourth transistor, and the control electrode of the fifth transistor. The first electrode of the third transistor is coupled to the first node and the first electrode of the fifth transistor. The second electrode of the fourth transistor is coupled to the second electrode of the fifth transistor and the control electrode of the first transistor. The second electrode of the first transistor is coupled to the supplementary voltage terminal. The Schmitt trigger is configured to generate a trigger signal based on the supplementary control voltage at the control electrode of the first transistor. The trigger signal flips to a third level when the supplementary control voltage rises to an upper threshold and flips to a fourth level when the supplementary control voltage falls to a lower threshold. The lower threshold is lower than the upper threshold. The first level conversion circuit is configured to generate a shutdown indication signal based on the trigger signal. The third level of the trigger signal is converted to an active level for the shutdown indication signal, and the fourth level of the trigger signal is converted to an inactive level for the shutdown indication signal. The first input of the AND gate is provided with the shutdown indication signal. The second input of the AND gate is provided with a PWM signal.

[0014] According to a third aspect of this disclosure, a chip is provided. The chip includes a DC-DC converter as described in a first or second aspect of this disclosure.

[0015] According to a fourth aspect of this disclosure, an electronic device is provided. The electronic device includes the chip described in a third aspect of this disclosure. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein:

[0017] Figure 1 An exemplary circuit diagram of a DC-DC converter;

[0018] Figure 2 This is a schematic block diagram of a DC-DC converter according to an embodiment of the present disclosure;

[0019] Figure 3 These are exemplary circuit diagrams of DC-DC converters according to embodiments of the present disclosure; and

[0020] Figure 4 This is another exemplary circuit diagram of a DC-DC converter according to embodiments of the present disclosure; and

[0021] Figure 5 This is yet another exemplary circuit diagram of a DC-DC converter according to embodiments of the present disclosure.

[0022] In the accompanying diagram, markers with the same last two digits correspond to the same elements. It should be noted that the elements in the diagram are schematic and not drawn to scale. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0024] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0025] In all embodiments of this disclosure, since the source and drain of a metal-oxide-semiconductor (MOS) transistor are symmetrical, and the conduction current directions between the source and drain of an N-type transistor and a P-type transistor are opposite, the controlled middle terminal of the MOS transistor is referred to as the control terminal, and the remaining two terminals of the MOS transistor are referred to as the first terminal and the second terminal, respectively. Furthermore, for the sake of consistency, in this context, the base of a bipolar junction transistor (BJT) is referred to as the control terminal, the emitter of the BJT as the first terminal, and the collector of the BJT as the second terminal. Additionally, terms such as "first" and "second" are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0026] Figure 1 An exemplary circuit diagram of a DC-DC converter 100 is shown. The DC-DC converter 100 includes: an upper power transistor HS, a lower power transistor LS, an inductor L, a bootstrap capacitor Cbst, a first transistor M1, a power supply control circuit 120, and a drive circuit 110. Figure 1 The example also shows the body diode of the first transistor M1. To avoid obscuring the focus of this disclosure with unimportant details, in Figure 1 Not all components in the DC-DC converter 100 are shown. Figure 1 In the example, the upper power transistor HS and the lower power transistor LS are both NMOS transistors. The first transistor M1 is a PMOS transistor.

[0027] The drive circuit 110 is configured to generate an upper transistor turn-on signal HDR and a lower transistor turn-on signal LDR based on a PWM signal. The PWM signal can be generated by the logic control circuit in the DC-DC converter 100 based on the output voltage VO and a reference voltage. Figure 1 The logic control circuit is not shown in the example. When the PWM signal is at the first level, the upper MOSFET's on signal HDR is active and the lower MOSFET's on signal LDR is inactive. When the PWM signal is at the second level, the upper MOSFET's on signal HDR is inactive and the lower MOSFET's on signal LDR is active.

[0028] The control terminal of the upper power transistor HS is provided with the upper transistor turn-on signal HDR. The control terminal of the lower power transistor LS is provided with the lower transistor turn-on signal LDR. The first terminal of the upper power transistor HS is coupled to the second terminal of the lower power transistor LS and the first terminal of the inductor L via the first node SW. The first terminal of the lower power transistor LS is grounded. The second terminal of the upper power transistor HS is coupled to one of the input voltage terminal VIN and the output voltage terminal VO. The second terminal of the inductor L is coupled to the other of the input voltage terminal VIN and the output voltage terminal VO. In the example where the second terminal of the upper power transistor HS is coupled to the input voltage terminal VIN and the second terminal of the inductor L is coupled to the output voltage terminal VO, the DC-DC converter 100 is a buck converter (BUCK). In the example where the second terminal of the upper power transistor HS is coupled to the output voltage terminal VO and the second terminal of the inductor L is coupled to the input voltage terminal VIN, the DC-DC converter 100 is a boost converter (BOOST).

[0029] The two ends of the bootstrap capacitor Cbst are coupled to the first node SW and the first terminal (bootstrap node BTST) of the first transistor M1, respectively.

[0030] The power supply control circuit 120 is configured to generate a power supply control voltage CTL1 based on a PWM signal. Specifically, when the PWM signal is at a first level, the power supply control voltage CTL1 is set to the voltage at the first terminal of the first transistor M1, and when the PWM signal is at a second level, the power supply control voltage CTL1 is set to the voltage at the first node SW.

[0031] The control electrode of the first transistor M1 is supplied with a supplementary control voltage CTL1. The second electrode of the first transistor M1 is coupled to the supplementary voltage terminal REGN.

[0032] In one example, when the PWM signal is low, the lower power transistor LS is turned on and the upper power transistor HS is turned off, and the power supply control voltage CTL1 is set to the voltage at the first node SW. At this time, the voltage of the first node SW is pulled low to ground, thereby pulling down the voltage of the bootstrap node BTST and turning on the first transistor M1. The bootstrap capacitor Cbst is charged by the voltage from the power supply voltage terminal REGN. When the PWM signal flips to high, the upper power transistor HS is turned on and the lower power transistor LS is turned off, and the power supply control voltage CTL1 is set to the voltage at the first terminal of the first transistor M1. The voltage of the first node SW is pulled high to the input voltage VIN or the output voltage VO (depending on whether the DC-DC converter 100 is BUCK or BOOST). The voltage of the bootstrap node BTST rises accordingly. At this time, the first transistor M1 is turned off to prevent the bootstrap node BTST from discharging to the power supply voltage terminal REGN through the first transistor M1. The above description ignores the delay of each stage of the circuit. The inventors of this disclosure have discovered that, in practical applications where a delay exists, it is possible that when the PWM signal flips to a high level, the upper power transistor HS is turned on and the lower power transistor LS is turned off. However, when the voltage at the bootstrap node BTST begins to rise, the first transistor M1 may still not be turned off. This would cause the bootstrap node BTST to discharge in reverse to the compensation voltage terminal REGN. The compensation voltage terminal REGN is typically the output of the LDO inside the DC-DC converter 100 chip. If the bootstrap node BTST discharges in reverse to the compensation voltage terminal REGN, it may affect the normal operation of the chip.

[0033] To prevent the bootstrap node BTST from discharging in reverse to the supplementary voltage terminal REGN, embodiments of this disclosure propose a DC-DC converter that allows the upper power transistor HS to turn on and the lower power transistor LS to turn off only after the first transistor M1 is completely turned off.

[0034] Figure 2 A schematic block diagram of a DC-DC converter 200 according to an embodiment of the present disclosure is shown. The DC-DC converter 200 includes: an upper power transistor HS, a lower power transistor LS, an inductor L, a bootstrap capacitor Cbst, a first transistor M1, a power supply control circuit 120, a drive control circuit 230, and a drive circuit 110. Figure 2 The example also shows the body diode of the first transistor M1. To avoid obscuring the focus of this disclosure with unimportant details, in Figure 2 Not all components in the DC-DC converter 200 are shown. Figure 2 In the example, the upper power transistor HS and the lower power transistor LS are both NMOS transistors. The first transistor M1 is a PMOS transistor.

[0035] The input terminal of the drive circuit 110 is coupled to the output terminal of the drive control circuit 230. The first output terminal of the drive circuit 110 is coupled to the control electrode of the upper power transistor HS. The second output terminal of the drive circuit 110 is coupled to the control electrode of the lower power transistor LS. The drive circuit 110 is configured to generate an upper transistor turn-on signal HDR and a lower transistor turn-on signal LDR based on the drive control signal CTL2 output by the drive control circuit 230. Specifically, when the drive control signal CTL2 is at the first level, the upper transistor turn-on signal HDR is at an active level and the lower transistor turn-on signal LDR is at an inactive level. When the drive control signal CTL2 is at the second level, the upper transistor turn-on signal HDR is at an inactive level and the lower transistor turn-on signal LDR is at an active level.

[0036] The drive circuit 110 provides an upper-transistor turn-on signal HDR from its first output terminal to the control terminal of the upper-power transistor HS. The drive circuit 110 also provides a lower-transistor turn-on signal LDR from its second output terminal to the control terminal of the lower-power transistor LS. The first terminal of the upper-power transistor HS is coupled to the second terminal of the lower-power transistor LS and the first terminal of the inductor L via a first node SW. The first terminal of the lower-power transistor LS is grounded. The second terminal of the upper-power transistor HS is coupled to one of the input voltage terminal VIN and the output voltage terminal VO. The second terminal of the inductor L is coupled to the other of the input voltage terminal VIN and the output voltage terminal VO. In the example where the second terminal of the upper-power transistor HS is coupled to the input voltage terminal VIN and the second terminal of the inductor L is coupled to the output voltage terminal VO, the DC-DC converter 200 is a buck converter. In the example where the second terminal of the upper-power transistor HS is coupled to the output voltage terminal VO and the second terminal of the inductor L is coupled to the input voltage terminal VIN, the DC-DC converter 200 is a boost converter.

[0037] The two ends of the bootstrap capacitor Cbst are coupled to the first node SW and the first terminal (bootstrap node BTST) of the first transistor M1, respectively.

[0038] The power supply control circuit 120 is coupled to the first node SW, the first terminal (bootstrap node BTST) of the first transistor M1, and the control terminal of the first transistor M1. The power supply control circuit 120 is also provided with a PWM signal. The power supply control circuit 120 is configured to generate a power supply control voltage CTL1 based on the PWM signal. Specifically, when the PWM signal is at a first level, the power supply control voltage CTL1 is set to the voltage at the first terminal of the first transistor M1, and when the PWM signal is at a second level, the power supply control voltage CTL1 is set to the voltage at the first node SW.

[0039] The control electrode of the first transistor M1 is supplied with a supplementary control voltage CTL1. The second electrode of the first transistor M1 is coupled to the supplementary voltage terminal REGN. The supplementary voltage terminal REGN can be the output terminal of an LDO inside the chip of the DC-DC converter 200.

[0040] One input terminal of the drive control circuit 230 is coupled to the control electrode of the first transistor M1. The other input terminal of the drive control circuit 230 is provided with a PWM signal. The output terminal of the drive control circuit 230 is coupled to the input terminal of the drive circuit 110. The drive control circuit 230 is configured to: determine the switching state of the first transistor M1 based on the supplementary power control voltage CTL1, and to set the drive control signal CTL2 to a first level when the PWM signal is at a first level and the first transistor M1 is completely off, otherwise setting the drive control signal CTL2 to a second level. In some embodiments of this disclosure, the first level is a high level and the second level is a low level. In some embodiments of this disclosure, the drive control circuit 230 also determines the switching state of the first transistor M1 based on a threshold voltage of the first transistor M1 (i.e., based on the supplementary power control voltage CTL1 and the threshold voltage of the first transistor M1). The switching state of the first transistor M1 may include: completely off and partially off.

[0041] When the PWM signal is at the second level (low level), the power supply control circuit 120 sets the power supply control voltage CTL1 to the voltage at the first node SW, and the drive control circuit 230 sets the drive control signal CTL2 to the second level (low level). At this time, the lower power transistor LS is turned on and the upper power transistor HS is turned off. The voltage at the first node SW is pulled low to ground, thereby pulling down the voltage at the bootstrap node BTST and turning on the first transistor M1. The upper plate of the bootstrap capacitor Cbst (bootstrap node BTST) is powered by the voltage from the power supply voltage terminal REGN.

[0042] When the PWM signal flips to the first level (high level), the power supply control circuit 120 sets the power supply control voltage CTL1 to the voltage at the first terminal of the first transistor M1. Since there is an internal delay in the power supply control circuit 120, the power supply control voltage CTL1 gradually increases. After the power supply control voltage CTL1 rises to a level that causes the gate-source voltage of the first transistor M1 to be higher than its threshold voltage (the absolute value of the gate-source voltage of the first transistor M1 is lower than the absolute value of its threshold voltage), the first transistor M1 is completely turned off. At this time, the drive control circuit 230 causes the drive control signal CTL2 to flip to the first level (high level). Therefore, the upper power transistor HS is turned on and the lower power transistor LS is turned off. The voltage of the first node SW is pulled high to either the input voltage VIN or the output voltage VO (depending on whether the DC-DC converter 100 is BUCK or BOOST). The voltage of the bootstrap node BTST subsequently increases. Since the first transistor M1 is turned off before the upper power transistor HS is turned on, and the body diode of the first transistor M1 will not be turned on under these circumstances, the bootstrap node BTST can be effectively prevented from discharging to the compensation voltage terminal REGN through the first transistor M1.

[0043] According to an embodiment of the present disclosure, the DC-DC converter 200 is configured with a drive control circuit 230 to ensure that the upper power transistor HS is turned on and the lower power transistor LS is turned off only after the first transistor M1 is completely turned off, which can effectively prevent the bootstrap node BTST from discharging to the supplementary voltage terminal REGN through the first transistor M1.

[0044] Figure 3 An exemplary circuit diagram of a DC-DC converter 300 according to an embodiment of the present disclosure is shown. Figure 3 In the example, the drive control circuit 330 includes a shutdown determination circuit 331 and a control signal output circuit 332.

[0045] The input terminal of the turn-off determination circuit 331 is coupled to the control electrode of the first transistor M1. The output terminal of the turn-off determination circuit 331 is coupled to the input terminal of the control signal output circuit 332. The turn-off determination circuit 331 is configured to output a turn-off indication signal FN at an active level when the supplementary control voltage CTL1 is greater than or equal to the reference voltage, and otherwise output a turn-off indication signal FN at an inactive level. The active level of the turn-off indication signal FN indicates that the first transistor M1 has been completely turned off. The reference voltage is set according to the threshold voltage of the first transistor M1. In some embodiments of this disclosure, the difference between the reference voltage and the voltage at the supplementary voltage terminal REGN is equal to or greater than the threshold voltage of the first transistor M1.

[0046] One input terminal of the control signal output circuit 332 is coupled to the output terminal of the turn-off determination circuit 331. The other input terminal of the control signal output circuit 332 is supplied with a PWM signal. The output terminal of the control signal output circuit 332 is coupled to the input terminal of the drive circuit 110. The control signal output circuit 332 is configured to output a drive control signal CTL2 at the first level when the PWM signal is at the first level and the turn-off indication signal FN is at the active level; otherwise, it outputs a drive control signal CTL2 at the second level.

[0047] The power supply control circuit 320 may include a second level conversion circuit 321 and second transistors M2 to M5. The second level conversion circuit 321 is configured to convert a first level of the PWM signal to a fifth level and a second level of the PWM signal to a sixth level. The control electrode of the second transistor M2 is coupled to the control electrode of the third transistor M3 and the output of the second level conversion circuit 321. The first electrode of the second transistor M2 is coupled to the first electrode of the first transistor M1 and the first electrode of the fourth transistor M4. The second electrode of the second transistor M2 is coupled to the second electrode of the third transistor M3, the control electrode of the fourth transistor M4, and the control electrode of the fifth transistor M5. The first electrode of the third transistor M3 is coupled to the first node SW and the first electrode of the fifth transistor M5. The second electrode of the fourth transistor M4 is coupled to the second electrode of the fifth transistor M5 and the control electrode of the first transistor M1. In some embodiments of this disclosure, the fifth level is a level that enables the third transistor M3 to be fully turned on. The sixth level is a level that enables the second transistor M2 to be fully turned on.

[0048] exist Figure 3 In the example, the first transistor M1, the second transistor M2, and the fourth transistor M4 are PMOS transistors. The upper power transistor HS, the lower power transistor LS, the third transistor M3, and the fifth transistor M5 are NMOS transistors. Those skilled in the art will understand that, based on the above inventive concept... Figure 3 Any modifications to the circuit shown should also fall within the scope of this disclosure. In such modifications, the transistor and voltage terminals may also have the same characteristics as described above. Figure 3 The examples shown have different settings.

[0049] When the PWM signal is at the second level (low level), the second transistor M2 and the fifth transistor M5 are turned on, while the third transistor M3 and the fourth transistor M4 are turned off. The power supply control voltage CTL1 is set to the voltage at the first node SW. The turn-off determination circuit 331 outputs a turn-off indication signal FN at an invalid level. Therefore, the control signal output circuit 332 outputs a drive control signal CTL2 at the second level (low level). At this time, the lower power transistor LS is turned on and the upper power transistor HS is turned off. The voltage at the first node SW is pulled low to ground, thereby pulling down the voltage at the bootstrap node BTST and turning on the first transistor M1. The voltage from the power supply voltage terminal REGN supplies power to the upper plate of the bootstrap capacitor Cbst (bootstrap node BTST).

[0050] When the PWM signal flips to the first level (high level), the second transistor M2 and the fifth transistor M5 are turned off, while the third transistor M3 and the fourth transistor M4 are turned on. The power supply control voltage CTL1 is set to the voltage at the first terminal of the first transistor M1. The power supply control voltage CTL1 gradually increases. After the power supply control voltage CTL1 increases to the point that the gate-source voltage of the first transistor M1 is higher than its threshold voltage, the first transistor M1 is completely turned off. At this time, the turn-off determination circuit 331 outputs a turn-off indication signal FN at an effective level, and the drive control signal CTL2 output by the control signal output circuit 332 flips to the first level (high level). Therefore, the upper power transistor HS is turned on and the lower power transistor LS is turned off. The voltage of the first node SW is pulled high to the input voltage VIN or the output voltage VO (depending on whether the DC-DC converter 100 is BUCK or BOOST). The voltage of the bootstrap node BTST increases accordingly. Since the first transistor M1 is turned off before the upper power transistor HS is turned on, and the body diode of the first transistor M1 will not be turned on under these circumstances, the bootstrap node BTST can be effectively prevented from discharging to the compensation voltage terminal REGN through the first transistor M1.

[0051] Figure 4 An exemplary circuit diagram of a DC-DC converter 400 according to an embodiment of the present disclosure is shown. Figure 4 In the example, the shutdown determination circuit 431 may include a voltage comparator CMP. The first input terminal of the voltage comparator CMP is coupled to the control electrode of the first transistor M1. The second input terminal of the voltage comparator CMP is coupled to a reference voltage terminal Vref. A reference voltage Vref is output from the reference voltage terminal Vref. The output terminal of the voltage comparator CMP is coupled to a control signal output circuit 432. As described above, in some embodiments of this disclosure, the difference between the reference voltage Vref and the voltage at the compensation voltage terminal REGN is equal to or greater than the threshold voltage of the first transistor M1.

[0052] The control signal output circuit 432 includes an AND gate. The first input of the AND gate is provided with a shutdown indication signal FN (coupled to the output of the voltage comparator CMP). The second input of the AND gate is provided with a PWM signal. A drive control signal CTL2 is output from the output of the AND gate.

[0053] exist Figure 4 In the example, the first input terminal of the voltage comparator CMP is the non-inverting input terminal. The second input terminal of the voltage comparator CMP is the inverting input terminal. Those skilled in the art will understand that, based on the above inventive concept... Figure 4 Any modifications to the circuit shown should also fall within the scope of this disclosure. In such modifications, the transistor and voltage terminals may also have the same characteristics as described above. Figure 4 The examples shown have different settings.

[0054] When the PWM signal is at the second level (low level), the second transistor M2 and the fifth transistor M5 are turned on, while the third transistor M3 and the fourth transistor M4 are turned off. The power supply control voltage CTL1 is set to the voltage at the first node SW. Since the second input of the AND gate is provided with the second level (low level), the drive control signal CTL2 output by the AND gate is at the second level (low level). At this time, the lower power transistor LS is turned on and the upper power transistor HS is turned off. The voltage at the first node SW is pulled low to ground, thereby pulling down the voltage at the bootstrap node BTST and turning on the first transistor M1. The upper plate of the bootstrap capacitor Cbst (bootstrap node BTST) is powered by the voltage from the power supply voltage terminal REGN. At this time, the power supply control voltage CTL1 is at a low level (below the reference voltage Vref), so the shutdown indication signal FN output by the voltage comparator CMP is at an invalid level (low level).

[0055] When the PWM signal flips to the first level (high level), the second transistor M2 and the fifth transistor M5 are turned off, while the third transistor M3 and the fourth transistor M4 are turned on. The power supply control voltage CTL1 is set to the voltage at the first terminal of the first transistor M1. The power supply control voltage CTL1 gradually increases. After the power supply control voltage CTL1 rises to the reference voltage Vref, causing the gate-source voltage of the first transistor M1 to be higher than its threshold voltage, the first transistor M1 is completely turned off. At this time, the turn-off indication signal FN output by the voltage comparator CMP flips from an invalid level (low level) to an active level (high level). Both inputs of the AND gate are provided with the first level (high level), so the drive control signal CTL2 output by the AND gate flips to the first level (high level). The upper power transistor HS is turned on and the lower power transistor LS is turned off. The voltage of the first node SW is pulled high to the input voltage VIN or the output voltage VO (depending on whether the DC-DC converter 100 is BUCK or BOOST). The voltage of the bootstrap node BTST increases accordingly. Since the first transistor M1 is turned off before the upper power transistor HS is turned on, and the body diode of the first transistor M1 will not be turned on under these circumstances, the bootstrap node BTST can be effectively prevented from discharging to the compensation voltage terminal REGN through the first transistor M1.

[0056] Figure 5 An exemplary circuit diagram of a DC-DC converter 500 according to an embodiment of the present disclosure is shown. Figure 5In the example, the shutdown determination circuit 531 may include a Schmitt trigger (SHT) and a first level shifting circuit (LF). The input of the Schmitt trigger (SHT) is coupled to the control electrode of the first transistor M1. The output of the Schmitt trigger (SHT) is coupled to the input of the first level shifting circuit (LF). The upper threshold of the Schmitt trigger (SHT) is set to a reference voltage. As described above, in some embodiments of this disclosure, the difference between the reference voltage and the voltage at the supplementary voltage terminal REGN is equal to or greater than the threshold voltage of the first transistor M1. The Schmitt trigger (SHT) is configured to generate a trigger signal based on the supplementary control voltage CTL1. The trigger signal flips to a third level when the supplementary control voltage CTL1 rises to the reference voltage, and flips to a fourth level when the supplementary control voltage CTL1 falls to the lower threshold. The lower threshold is lower than the reference voltage. In practical applications, the third level of the trigger signal may not be correctly identified as a high level by the AND gate, or the fourth level of the trigger signal may not be correctly identified as a low level by the AND gate. Therefore, the first level shifting circuit (LF) is also provided.

[0057] The first level conversion circuit LF is configured to generate a shutdown indication signal FN based on a trigger signal. Specifically, the third level of the trigger signal is converted to an active level for the shutdown indication signal FN, and the fourth level of the trigger signal is converted to an inactive level for the shutdown indication signal FN.

[0058] Using a Schmitt trigger (SHT) in the shutdown determination circuit 531 can prevent fluctuations in the power supply control voltage CTL1 from causing the shutdown indication signal FN to flip incorrectly.

[0059] When the PWM signal is at the second level (low level), the second transistor M2 and the fifth transistor M5 are turned on, while the third transistor M3 and the fourth transistor M4 are turned off. The power supply control voltage CTL1 is set to the voltage at the first node SW. Since the second input of the AND gate is provided with the second level (low level), the drive control signal CTL2 output by the AND gate is at the second level (low level). At this time, the lower power transistor LS is turned on and the upper power transistor HS is turned off. The voltage at the first node SW is pulled low to ground, thereby pulling down the voltage at the bootstrap node BTST and turning on the first transistor M1. The upper plate of the bootstrap capacitor Cbst (bootstrap node BTST) is powered by the voltage from the power supply voltage terminal REGN. At this time, the power supply control voltage CTL1 is at a low level (lower than the reference voltage Vref), so the trigger signal output by the Schmitt trigger SHT is at the fourth level. The first level conversion circuit LF converts the fourth level of the trigger signal to the invalid level (low level) of the turn-off indicator signal FN.

[0060] When the PWM signal flips to the first level (high level), the second transistor M2 and the fifth transistor M5 are turned off, while the third transistor M3 and the fourth transistor M4 are turned on. The power supply control voltage CTL1 is set to the voltage at the first terminal of the first transistor M1. The power supply control voltage CTL1 gradually increases. After the power supply control voltage CTL1 increases to the reference voltage Vref, making the gate-source voltage of the first transistor M1 higher than its threshold voltage, the first transistor M1 is completely turned off. At this time, the trigger signal output by the Schmitt trigger SHT flips from the fourth level to the third level, and the first level conversion circuit LF converts the third level of the trigger signal to the effective level (high level) of the turn-off indication signal FN. Both inputs of the AND gate are provided with the first level (high level), so the drive control signal CTL2 output by the AND gate flips to the first level (high level). The upper power transistor HS is turned on and the lower power transistor LS is turned off. The voltage of the first node SW is pulled high to the input voltage VIN or the output voltage VO (depending on whether the DC-DC converter 100 is BUCK or BOOST). The voltage of the bootstrap node BTST increases accordingly. Since the first transistor M1 is turned off before the upper power transistor HS is turned on, and the body diode of the first transistor M1 will not be turned on under these circumstances, the bootstrap node BTST can be effectively prevented from discharging to the compensation voltage terminal REGN through the first transistor M1.

[0061] Embodiments of this disclosure also provide a chip. This chip includes a DC-DC converter according to embodiments of this disclosure. This chip is, for example, a power management chip.

[0062] Embodiments of this disclosure also provide an electronic device. This electronic device includes a chip according to embodiments of this disclosure. The electronic device is, for example, a smart terminal device, such as a tablet computer or smartphone.

[0063] In summary, the DC-DC converter according to the embodiments of this disclosure can ensure that the upper power transistor HS is allowed to turn on and the lower power transistor LS is allowed to turn off only after the first transistor M1 is completely turned off. This can effectively prevent the bootstrap node BTST from discharging to the supplementary voltage terminal REGN through the first transistor M1, thereby protecting the chip using the DC-DC converter.

[0064] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0065] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0066] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A DC-DC converter, comprising: The circuit consists of an upper power transistor, a lower power transistor, an inductor, a bootstrap capacitor, a first transistor, a power supply control circuit, a drive control circuit, and a drive circuit. The driving circuit is configured to generate an upper transistor turn-on signal and a lower transistor turn-on signal according to the driving control signal output by the driving control circuit. When the driving control signal is at a first level, the upper transistor turn-on signal is at an active level and the lower transistor turn-on signal is at an inactive level. When the driving control signal is at a second level, the upper transistor turn-on signal is at an inactive level and the lower transistor turn-on signal is at an active level. The control electrode of the upper power transistor is provided with the upper power transistor conduction signal, and the control electrode of the lower power transistor is provided with the lower power transistor conduction signal. The first electrode of the upper power transistor is coupled to the second electrode of the lower power transistor and the first terminal of the inductor via a first node. The two ends of the bootstrap capacitor are respectively coupled to the first node and the first electrode of the first transistor; The power-compensation control circuit is configured to generate a power-compensation control voltage based on a PWM signal, wherein the power-compensation control voltage is set to the voltage at the first terminal of the first transistor when the PWM signal is at the first level, and the power-compensation control voltage is set to the voltage at the first node when the PWM signal is at the second level. The control electrode of the first transistor is provided with the supplementary control voltage, and the second electrode of the first transistor is coupled to the supplementary voltage terminal; The drive control circuit is configured to: determine the switching state of the first transistor based on the supplementary power control voltage, and to make the drive control signal at the first level when the PWM signal is at the first level and the first transistor is completely turned off, otherwise make the drive control signal at the second level.

2. The DC-DC converter according to claim 1, wherein, The drive control circuit includes: a shutdown determination circuit and a control signal output circuit. The shutdown determination circuit is configured to output a shutdown indication signal at an active level when the power supply control voltage is greater than or equal to a reference voltage, and otherwise output a shutdown indication signal at an inactive level. The active level of the shutdown indication signal indicates that the first transistor has been completely turned off, and the reference voltage is set according to the threshold voltage of the first transistor. The control signal output circuit is configured to output a drive control signal at the first level when the PWM signal is at the first level and the shutdown indication signal is at the active level, and otherwise output a drive control signal at the second level.

3. The DC-DC converter according to claim 2, wherein, The shutdown determination circuit includes: a voltage comparator. The voltage comparator has a first input terminal coupled to the control electrode of the first transistor, a second input terminal coupled to a reference voltage terminal, and outputs the reference voltage from the reference voltage terminal. The voltage comparator's output terminal is coupled to the control signal output circuit.

4. The DC-DC converter according to claim 2, wherein, The shutdown determination circuit includes: a Schmitt trigger and a first level conversion circuit. The upper threshold of the Schmitt trigger is set to the reference voltage, and the Schmitt trigger is configured to generate a trigger signal based on the power supply control voltage, wherein the trigger signal flips to a third level when the power supply control voltage rises to the reference voltage, and flips to a fourth level when the power supply control voltage drops to a lower threshold, wherein the lower threshold is lower than the reference voltage; The first level conversion circuit is configured to generate the shutdown indication signal based on the trigger signal, wherein the third level of the trigger signal is converted to an active level of the shutdown indication signal, and the fourth level of the trigger signal is converted to an inactive level of the shutdown indication signal.

5. The DC-DC converter according to claim 2, wherein, The control signal output circuit includes: an AND gate, The first input terminal of the AND gate is provided with the shutdown indication signal, the second input terminal of the AND gate is provided with the PWM signal, and the drive control signal is output from the output terminal of the AND gate.

6. The DC-DC converter according to claim 1, wherein, The power supply control circuit includes: a second level conversion circuit, and second to fifth transistors. The second level conversion circuit is configured to convert the first level of the PWM signal to a fifth level and to convert the second level of the PWM signal to a sixth level. The control electrode of the second transistor is coupled to the control electrode of the third transistor and the output terminal of the second level conversion circuit; the first electrode of the second transistor is coupled to the first electrode of the first transistor and the first electrode of the fourth transistor; and the second electrode of the second transistor is coupled to the second electrode of the third transistor, the control electrode of the fourth transistor, and the control electrode of the fifth transistor. The first terminal of the third transistor is coupled to the first node and the first terminal of the fifth transistor; The second terminal of the fourth transistor is coupled to the second terminal of the fifth transistor and the control terminal of the first transistor.

7. The DC-DC converter according to any one of claims 1 to 6, wherein, Both the upper power transistor and the lower power transistor are NMOS transistors.

8. The DC-DC converter according to any one of claims 1 to 6, wherein, The first transistor is a PMOS transistor.

9. The DC-DC converter according to any one of claims 1 to 6, wherein, The second terminal of the power transistor is coupled to one of the input voltage terminal and the output voltage terminal, and the second terminal of the inductor is coupled to the other of the input voltage terminal and the output voltage terminal.

10. A DC-DC converter, comprising: The circuit consists of an upper power transistor, a lower power transistor, an inductor, a bootstrap capacitor, transistors one through five, a Schmitt trigger, a first level shifter circuit, a second level shifter circuit, an AND gate, and a driver circuit. The driving circuit is configured to generate an upper transistor turn-on signal and a lower transistor turn-on signal based on the driving control signal output from the output terminal of the AND gate. When the driving control signal is at a first level, the upper transistor turn-on signal is at an active level and the lower transistor turn-on signal is at an inactive level. When the driving control signal is at a second level, the upper transistor turn-on signal is at an inactive level and the lower transistor turn-on signal is at an active level. The control electrode of the upper power transistor is provided with the upper power transistor conduction signal, and the control electrode of the lower power transistor is provided with the lower power transistor conduction signal. The first electrode of the upper power transistor is coupled to the second electrode of the lower power transistor and the first terminal of the inductor via a first node. The two ends of the bootstrap capacitor are respectively coupled to the first node and the first electrode of the first transistor; The second level conversion circuit is configured to convert a first level of the PWM signal to a fifth level, and to convert a second level of the PWM signal to a sixth level; The control electrode of the second transistor is coupled to the control electrode of the third transistor and the output terminal of the second level conversion circuit. The first electrode of the second transistor is coupled to the first electrode of the first transistor and the first electrode of the fourth transistor. The second electrode of the second transistor is coupled to the second electrode of the third transistor, the control electrode of the fourth transistor, and the control electrode of the fifth transistor. The first terminal of the third transistor is coupled to the first node and the first terminal of the fifth transistor; The second terminal of the fourth transistor is coupled to the second terminal of the fifth transistor and the control terminal of the first transistor; The second terminal of the first transistor is coupled to the compensation voltage terminal; The Schmitt trigger is configured to generate a trigger signal based on a supplementary control voltage at the control electrode of the first transistor, wherein the trigger signal flips to a third level when the supplementary control voltage rises to an upper threshold, and flips to a fourth level when the supplementary control voltage falls to a lower threshold, the lower threshold being lower than the upper threshold. The first level conversion circuit is configured to generate a shutdown indication signal based on the trigger signal, wherein the third level of the trigger signal is converted to an active level of the shutdown indication signal, and the fourth level of the trigger signal is converted to an inactive level of the shutdown indication signal; The first input of the AND gate is provided with the shutdown indication signal, and the second input of the AND gate is provided with the PWM signal.

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