Pixel circuit, display device, and driving method of pixel circuit

Abstract

The application provides a pixel circuit, a display device and a driving method of the pixel circuit. The pixel circuit comprises a driving module connected between a first power voltage terminal and a first terminal of a light-emitting unit and configured to provide a driving current for the light-emitting unit; an initialization module connected between an initialization voltage terminal and the first terminal of the light-emitting unit and configured to be turned on in response to an initialization gate signal so as to connect the first terminal of the light-emitting unit to the initialization voltage; and an impedance control module connected to the initialization voltage, wherein the impedance of the impedance control module is adjustable. The pixel circuit can avoid local display dimming and screen splitting during display of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a pixel circuit, a display device, and a method for driving the pixel circuit. Background Technology

[0002] Organic light-emitting diode (OLED) display panels have broad application prospects in display devices due to their numerous advantages such as self-illumination and high contrast. However, these display panels still require improvement. Summary of the Invention

[0003] This application provides a pixel circuit, a display device, and a method for driving the pixel circuit. The various aspects related to the embodiments of this application are described below.

[0004] In a first aspect, a pixel circuit is provided, comprising: a driving module connected between a first power supply voltage terminal and a first terminal of a light-emitting unit, configured to provide a driving current to the light-emitting unit; an initialization module connected between an initialization voltage terminal and the first terminal of the light-emitting unit, configured to be turned on in response to an initialization gate signal, so that the first terminal of the light-emitting unit is connected to the initialization voltage; and an impedance control module connected to the initialization voltage, wherein the impedance of the impedance control module is adjustable.

[0005] In a second aspect, a display device is provided, comprising: a plurality of pixel circuits arranged in an array, each pixel circuit having an impedance control module, the impedance of which is adjustable; a scanning circuit and a plurality of preset scan lines, the scanning circuit being connected to the pixel circuits in corresponding rows via the corresponding preset scan lines; and a first voltage terminal connected to the pixel circuits and / or the impedance control module, wherein the pixel circuits are configured to transmit a voltage on the first voltage terminal to the pixel circuits in response to a pulse signal on the preset scan lines.

[0006] Thirdly, a display panel is provided, including the pixel circuitry described in the first aspect.

[0007] Fourthly, a driving method for a pixel circuit is provided, the driving method employing the pixel circuit as described in the first aspect, the driving method comprising: making the impedance of the impedance control module different during a first time period and a second time period within at least one frame refresh cycle.

[0008] The pixel circuit proposed in this application includes an impedance control module connected between the initialization voltage terminal and the first terminal of the light-emitting unit, and the impedance of the impedance control module is adjustable. This impedance control module allows adjustment of the impedance during the initialization process of the first terminal of the light-emitting unit, thereby preventing localized dimness and screen splitting issues during display. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of this application.

[0010] Figure 2 This is a schematic diagram of a pixel circuit provided in another embodiment of this application.

[0011] Figure 3a For use Figure 2 This is a schematic diagram of the display panel of the pixel circuit in the display.

[0012] Figure 3b For use Figure 2 Another schematic diagram of the display panel of the pixel circuit in the image during display.

[0013] Figure 4 This is a schematic diagram of the structure of the display device provided in the embodiments of this application.

[0014] Figure 5 This is a schematic diagram of the pixel circuit provided in another embodiment of this application.

[0015] Figure 6 Provided for the embodiments of this application Figure 5 The timing diagram of the driving signals of the pixel circuit in the image.

[0016] Figure 7 This is a schematic diagram of the pixel circuit provided in another embodiment of this application.

[0017] Figure 8 This is a schematic diagram of the pixel circuit provided in another embodiment of this application.

[0018] Figure 9 This is a schematic diagram of the pixel circuit provided in another embodiment of this application.

[0019] Figure 10 This is a schematic flowchart of a pixel circuit driving method provided in an embodiment of this application. Detailed Implementation

[0020] To facilitate understanding of this application, it will be described in more detail below based on exemplary embodiments and in conjunction with the accompanying drawings. The same or similar reference numerals are used in the drawings to denote the same or similar modules. It should be understood that the drawings are merely illustrative, and the scope of protection of this application is not limited thereto.

[0021] like Figure 1 As shown, the conventional pixel circuit 10 uses LTPS transistors. Specifically, as... Figure 1 As shown, the pixel circuit 10 includes a light-emitting unit LE, a driving transistor T1, a data writing transistor T2, a compensation transistor T3, a reset transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, and an initialization transistor T7. The light-emitting unit LE can be an OLED, and the light-emitting unit LE can include an anode and a cathode. T1, T2, T3, T4, T5, T6, and T7 are all LTPS transistors (or P-type transistors).

[0022] However, due to the relatively large leakage current of LTPS transistors, including Figure 1 The pixel circuit display device shown is prone to flickering problems in low-frequency applications, hence the development of LTPO technology.

[0023] Because LTPO transistors combine the high mobility of low-temperature polycrystalline silicon with the low leakage current of oxide transistors, they can be used in both high-frequency and low-frequency applications. Therefore, how to apply LTPO transistors in applications such as... Figure 1 The pixel circuit shown has become a problem that urgently needs to be solved.

[0024] As a feasible approach, such as Figure 2 As shown, the compensation transistor T3 and reset transistor T4 can be manufactured using an oxide process, that is, replacing these two transistors T3 and T4 with LTPO transistors (or N-type transistors). See also... Figure 2 A new bias transistor T8 can be added. The gate of T8 shares the initialization gate signal SP2 with the gate of T7; therefore, both T7 and T8 can be turned on in response to SP2. The difference lies in the connection between the source and drain of the initialization transistor T7. The source of the initialization transistor T7 receives the initialization voltage Vrefn2, and its drain is connected to the anode of the light-emitting unit LE to provide the initialization voltage. Conversely, the source of the bias transistor T8 receives the bias voltage Vrefp, and its drain is connected to either the source or drain of the driving transistor T1 to provide the bias voltage to either the source or drain of the driving transistor T1. This bias voltage can perform high-frequency reset of the source or drain of the driving transistor T1, thereby improving the low-frequency flickering phenomenon.

[0025] In the field of display panel technology, a screen refresh cycle of a display panel includes an active phase and a blanking phase. The active phase, commonly referred to as the display frame or Vactive phase, and the blanking phase as the Vblank phase, are typically located between display frames. This Vblank phase is used to prepare and transmit screen data but does not actually display the screen. More specifically, the Vblank phase can be located between the last row of pixels in the active display area of ​​the display panel writing data from the previous frame to the first row of pixels writing data for the next frame. Specifically, the display panel includes multiple rows of virtual pixels, where the pixels are not used for actual light emission. The number of virtual pixel rows is equal to the number of pixel rows that the scan signal controlling data writing can scan during the duration of the Vblank phase. For example, as shown in FIG3, the display panel 30 includes an active area (Vactive) 310 and a blanking area (Vblank) 320. The active area 310 can be equivalent to the display area AA. The blanking area 320 includes multiple rows of virtual pixels (blank).

[0026] As mentioned earlier, the initialization gate signal SP2 needs to simultaneously control the source of the driving transistor T1 and the anode of the light-emitting unit LE, and the initialization gate signal SP2 can be a multi-pulse signal with a frequency greater than or equal to 120Hz. A multi-pulse signal can be understood as a signal containing multiple pulses. Therefore, when using... Figure 2 In the LTPO pixel circuit shown, when the initialization gate signal SP2 scans the display area (AA) on the display panel, if one of the pulse signals in the multi-pulse signal scans the aforementioned virtual pixel row, the number of pulses actually driving the pixels on the display surface will decrease. This reduction in the number of pulses driving the pixels is equivalent to a decrease in the number of pixels being driven, i.e., a decrease in impedance. This leads to more thorough initialization of the anode of the light-emitting unit (LE), resulting in a problem of localized darkening and uneven display (mura), causing screen splitting.

[0027] As shown in Figure 3, the initialization gate signal SP2 uses a 3-pulse signal. When one of the pulses (the dashed pulse in Figure 3) scans into the virtual pixel row in the blanking region 320, the number of pixel rows being driven by SP2 is reduced to 1 / 3, which is equivalent to 2 effective pulses for SP2. It should be noted that when all 3 pulses are in the effective region 310, the number of effective pulses for SP2 is 3, while when the lowest pulse enters the blanking region 320, the number of effective pulses for SP2 can be reduced from 3 to 2.

[0028] When the number of effective pulses of SP2 decreases, the driving impedance of the gate signal (e.g., SP2) and the initialization voltage (e.g., Vrefn2) in the driving circuit decreases, resulting in a reduction in the delay of the SP2 signal. This leads to more thorough initialization of the anode of the light-emitting unit LE, resulting in differences in display brightness and forming a three-screen phenomenon.

[0029] In view of this, this application proposes a pixel circuit with an impedance control module connected between the initialization voltage terminal and the first terminal of the light-emitting unit. The impedance of the impedance control module is adjustable. This pixel circuit allows the impedance of the corresponding driving circuit to remain constant even when the number of effective pulses of the initialization gate signal changes, thereby preventing localized dimming of the display panel and screen splitting during display.

[0030] The following is combined Figure 4 and Figure 5 The display device 40 and pixel circuit 420 in the embodiments of this application will be described in detail.

[0031] The display device 40 described in this application embodiment can be a display panel, such as: a liquid crystal panel, an OLED panel, a mobile phone, a tablet computer, a laptop computer, a handheld computer, a mobile internet device (MID), a wearable device, a television, a monitor, a digital photo frame, or any other product or component with display function.

[0032] See Figure 4 The display device 40 includes a display panel 41 and a driving circuit 42.

[0033] The display panel 41 includes a display area AA, within which multiple light-emitting units (or light-emitting pixels) 410 are disposed. The multiple light-emitting units 410 are arranged in an array according to the row and column directions of the display panel 41. For example... Figure 5 As shown, each light-emitting unit 410 corresponds to a pixel circuit 420.

[0034] The driving circuit 42 provides a driving signal to each of the multiple pixel circuits 420 that correspond one-to-one with the multiple light-emitting units 410. Combined with... Figure 5 and Figure 6As shown, the driving signals may include, for example, a data signal data provided by the Data terminal, a first scan signal sp1 provided by the SP1 terminal, an initialization gate signal sp2 provided by the SP2 terminal, a reset signal sn1 provided by the SN1 terminal, a second scan signal sn2 provided by the SN2 terminal, a bias voltage vrefp provided by the VREFP terminal, a drive initialization voltage vrefn1 provided by the VREFN1 terminal, an initialization voltage vrefn2 provided by the VREFN2 terminal, a light emission control signal em provided by the EM terminal, a first power supply voltage elvdd provided by the ELVDD terminal, and a second power supply voltage elvss provided by the ELVSS terminal.

[0035] For example, Figure 6 A timing diagram is shown for a first scan signal sp1, an initialization gate signal sp2, a reset signal sn1, a second scan signal sn2, and a light emission control signal em provided by a driving circuit. Figure 5 The pixel circuit in can be according to Figure 6 The timing diagram shown is used for operation.

[0036] See Figure 5 Each pixel circuit 420 is used to control the corresponding light-emitting unit 410, for example, to control the initialization of the light-emitting unit 410 or to control the light-emitting unit 410 to emit light or not emit light. A pixel circuit 420 may include a driving module 421, an initialization module 422, and an impedance control module 423.

[0037] The driving module 421 is connected between the first power supply voltage terminal ELVDD and the first terminal of the light-emitting unit 410. The driving module 421 is configured to provide driving current to the light-emitting unit 410 during the light-emitting phase.

[0038] As before, the light-emitting unit 410 can be an OLED and includes an anode + and a cathode -. The first end of the light-emitting unit 410 is the anode +. The anode + is connected to the connection point S1, and the cathode - is used to receive the second power supply voltage ELVSS.

[0039] In some embodiments, such as Figure 7 As shown, the driving module 421 can be a driving transistor T1. The driving transistor T1 includes a gate, a source, and a drain. The gate of the driving transistor T1 is connected to the control terminal S2 of the driving module 421, its source is used to receive the first power supply voltage elvdd, and its drain can be connected to the first terminal of the light-emitting unit 410. The driving transistor T1 can be turned on based on the voltage at the control terminal S2 of the driving module 421 to control the driving current supplied to the light-emitting unit 410.

[0040] The initialization module 422 is connected between the initialization voltage terminal VREFN2 and the first terminal of the light-emitting unit 410. The initialization module 422 is configured to be turned on in response to the initialization gate signal SP2, so that the light-emitting unit 410 is connected to the initialization voltage input to the initialization voltage terminal VREFN2.

[0041] In some embodiments, such as Figure 7 As shown, the initialization module 422 can be an initialization transistor T7. The initialization transistor T7 includes a gate, a source, and a drain. The gate of the initialization transistor T7 receives an initialization gate signal SP2, its source receives an initialization voltage vrefn2, and its drain is connected to the first terminal of the light-emitting unit 410. Preferably, its drain is connected to the impedance control module 423. The initialization transistor T7 is configured to turn on in response to the initialization gate signal sp2, so as to provide an initialization voltage to the light-emitting unit 410 through the impedance control module 423.

[0042] Impedance control module 423 is also connected between the initialization voltage terminal VREFN2 and the first terminal of the light-emitting unit 410, and the impedance of impedance control module 423 is adjustable. It can be understood that the adjustable impedance of impedance control module 423 means that the total impedance of the light-emitting unit 410 and the pixel circuit 420 is adjustable. Specifically, impedance control module 423 is configured to keep the impedance of the driving circuit 42 corresponding to the pixel circuit 420 constant in response to a change in the number of effective pulses of the initialization gate signal sp2. In this embodiment, impedance may include capacitance and / or resistance. In other words, the adjustable impedance in this embodiment can be understood as the capacitance and / or resistance values ​​being adjustable.

[0043] In this embodiment, the impedance of the impedance control module 423 can be adjusted during the initialization of the anode + by the pixel circuit 420.

[0044] For example, the impedance of the impedance control module 423 can be adjusted according to the time period within the screen refresh cycle. Specifically, in the first time period and the second time period within at least one screen refresh cycle, the impedance of the impedance control module 423 in the first time period can be adjusted to be different from the impedance of the impedance control module 423 in the second time period.

[0045] As an example, there are multiple light-emitting units 410, and the number of light-emitting units 410 connected to the initialization voltage differs between the first time period and the second time period. Specifically, the number of light-emitting units 410 connected to the initialization voltage in the first time period is greater than the number of light-emitting units 410 connected to the initialization voltage in the second time period, and the impedance of the impedance control module 423 in the first time period is less than the impedance of the impedance control module 423 in the second time period.

[0046] As another example, the number of light-emitting units 410 is multiple, and these multiple light-emitting units 410 can form multiple rows of light-emitting units. Each row of light-emitting units includes multiple light-emitting units 410. The number of rows of light-emitting units connected to the initialization voltage is different in the first time period and the second time period. Specifically, the number of rows of light-emitting units connected to the initialization voltage in the first time period is greater than the number of rows of light-emitting units connected to the initialization voltage in the second time period, and the impedance of the impedance control module in the first time period is less than the impedance of the impedance control module in the second time period. In this embodiment, each screen refresh cycle may include the aforementioned active phase and blanking phase. The first time period in this embodiment may be located in the active phase, and the second time period may be located in the blanking phase. In each screen refresh cycle, the initialization gate signal includes multiple pulse signals. The number of active pulses of the initialization gate signal in the active phase is x, and the number of active pulses of the initialization gate signal in the blanking phase is y, where x is greater than y.

[0047] Optionally, a screen refresh cycle includes a write frame, with the active phase occurring within the write frame and at least a portion of the blanking phase occurring within the write frame. Optionally, a screen refresh cycle also includes a hold frame, which occurs within the blanking phase.

[0048] As an example, the impedance control module is configured to: control both the first impedance path and the second impedance path to be turned on when the number of rows of light-emitting units connected to the initial voltage is m; control one of the first impedance path and the second impedance path to be turned on when the number of rows of light-emitting units connected to the initial voltage is n; wherein m is greater than n.

[0049] One screen refresh cycle includes an active phase and a blanking phase. The number of light-emitting unit rows connected to the initialization voltage is m in the active phase and n in the blanking phase.

[0050] This application embodiment does not impose specific limitations on the connection method between the impedance control module 423 and the initialization module 422 at the initialization voltage terminal VREFN2 and the first terminal of the light-emitting unit 410.

[0051] As an example, such as Figure 5 As shown, the impedance control module 423 and the initialization module 422 are connected in series between the initialization voltage terminal VREFN2 and the first terminal of the light-emitting unit 410.

[0052] Optionally, such as Figure 5 As shown, the impedance control module 423 is connected between the initialization module 422 and the first end of the light-emitting unit 410. Alternatively, as... Figure 8As shown, the impedance control module 423 is connected between the initialization voltage terminal VREFN2 and the initialization module 422.

[0053] As another example, such as Figure 9 As shown, the impedance control module 423 and the initialization module 422 are connected in parallel between the initialization voltage terminal VREFN2 and the first terminal of the light-emitting unit 410.

[0054] This application does not impose specific limitations on the structure of the impedance control module 423, as long as the impedance of the impedance control module 423 is adjustable.

[0055] In one implementation, the impedance control module 423 may include a variable resistor, and the impedance control module 423 can be made adjustable by adjusting the resistance value of the variable resistor.

[0056] As another implementation, the impedance control module 423 may include multiple impedance paths connected in parallel, each of which (e.g., 4231 or 4232) is equipped with a switching element. Optionally, each of the multiple impedance paths may include a resistor element R and / or a capacitor element and a switching element D connected in series. The impedance of the impedance control module 423 can be adjusted by controlling the on / off state of the switching elements on different impedance paths.

[0057] This application embodiment does not impose a specific limitation on the number of impedance paths in the impedance control module 423. For example, such as Figure 5 , Figures 8-9 As shown, the multiple impedance paths include a first impedance path 4231 and a second impedance path 4232. The first impedance path 4231 includes a resistor R1 and a switch D1 connected in series; the second impedance path 4232 includes a resistor R2 and a switch D2 connected in series. Optionally, the resistance values ​​of resistor R1 and resistor R2 can be the same, or alternatively, the resistance values ​​of resistor R1 and resistor R2 can also be the same. Optionally, the switch D can be a transistor switch or a single-pole single-throw switch.

[0058] It should be understood that, such as Figure 5 , Figures 8-9 The example shown is only two impedance paths; multiple impedance paths can also include three impedance paths, four impedance paths, etc.

[0059] As an example, using Figure 5 , Figures 8-9The impedance control module 423 shown can adjust the impedance during the initialization of the anode + as follows: when the number of effective pulses of the initialization gate signal is x, both the first impedance path and the second impedance path are turned on; when the number of effective pulses is y, one of the first impedance path and the second impedance path is turned on. When both the first and second impedance paths are turned on, the impedance of the impedance control module 423 is the first impedance; when only one of the first and second impedance paths is turned on, the impedance of the impedance control module 423 is the second impedance. The difference between the first impedance and the second impedance is the difference in impedance of the light-emitting unit driven by the initialization gate signal SP2.

[0060] By implementing the embodiments of this application, when scanning the display surface (AA) on the display panel using the initialization gate signal SP2, the driving impedance of the driving circuit can be kept constant regardless of whether the number of effective pulses of the initialization gate signal SP2 changes. Therefore, the phenomenon of uneven local display and screen splitting that occurs when displaying a display panel using pixel circuits can be avoided.

[0061] Taking the scenario in Figure 3 as an example, when the sp2 signal within the effective area is detected as a 3-pulse scan (such as... Figure 3a At this time, multiple pulse signals equivalent to the initialization gate signal are all in the scan effective area, that is, at this time, it is in the first stage of the screen refresh cycle. For this scenario, the impedance control module 423 transmits the initialization signal by connecting R1 and R2 in parallel (both D1 and D2 switches are closed to form a smaller impedance). When the sp2 signal in the effective area is detected to be 2pulse (e.g., ... Figure 3b As shown in the diagram, at this time, some of the multiple pulse signals that initialize the gate signal are in the active scanning region, while the other part is in the blanking region. This corresponds to the second stage of the screen refresh cycle. In this scenario, the initialization signal is transmitted via either the R1 branch (D1 closed, D2 open) or the R2 branch (D2 closed, D1 open) in the impedance control module 423. Given the adjustable impedance of the impedance control module 423, a consistent impedance can be maintained even when the sp2 signal in the active region has different pulse numbers during scanning, thus resolving the three-screen issue.

[0062] When the number of effective pulses in the initialization gate signal sp2 changes, it can be understood as follows: when the timing signal (or pulse) in the initialization gate signal sp2 scans from the active region to the blanking region (at this time, the number of effective pulses in the initialization gate signal sp2 will change from x to y, where x is greater than y), or when the timing signal (or pulse) in the initialization gate signal sp2 scans back from the blanking region to the active region (at this time, the number of effective pulses in the initialization gate signal sp2 will change from y to x). Taking the initialization gate signal sp2 in Figure 3 as an example, when the timing signal scans from the active region to the blanking region, the number of effective pulses in the initialization gate signal sp2 changes from 3 to 2; while when the timing signal re-scans from the blanking region to the active region, the number of effective pulses in the initialization gate signal sp2 changes from 2 to 3.

[0063] To further control the reset, data writing, and / or voltage compensation of the pixel circuit 420, in some embodiments, such as Figure 5 , Figures 8-9 As shown, the pixel circuit 420 also includes a bias module 424, a data writing module 425, a compensation module 426, a reset module 427, a light emission control module 428, and a storage module 429.

[0064] The bias module 424 is connected between the bias voltage terminal VREFP and either the first terminal S3 or the second terminal S5 of the drive module 421. The bias module 424 is configured to be turned on in response to the initialization gate signal sp2 to provide a bias voltage to the drive module 421.

[0065] As one implementation method, such as Figure 7 As shown, the bias module 424 can be a bias transistor T8, which includes a gate, a source, and a drain. The gate of bias transistor T8 is also used to receive the initialization gate signal sp2, its source is used to receive the bias voltage output from the bias voltage terminal VREFP, and its drain is connected to the source of driving transistor T1 through the first terminal S3 of driving module 421. Bias transistor T8 is configured to turn on in response to the initialization gate signal sp2 to provide a bias voltage to driving transistor T1.

[0066] The data writing module 425 is connected between the data signal terminal DATA and the first terminal S3 of the drive module 421. The data writing module 425 is configured to be turned on in response to the first scan signal SP1 to provide a data signal to the drive module 421.

[0067] As one implementation method, such as Figure 7As shown, the data writing module 425 can be a data writing transistor T2. The data writing transistor T2 includes a gate, a source, and a drain. The gate of the writing transistor T2 receives the gate write signal sp1, its source receives the data signal data, and its drain is connected to the first terminal S3 of the driving module 421. The data writing transistor T2 can be turned on when the gate write signal SP1 is high to transmit the data signal data to the first terminal S3 of the driving module 421. The first terminal S3 of the driving module 421 is connected to the source of the driving transistor T1.

[0068] The compensation module 426 is connected between the second terminal S5 of the drive module 421 and the control terminal S2 of the drive module 421. The compensation module 426 is configured to be turned on in response to the second scan signal SN2 to compensate the threshold voltage of the drive module 421.

[0069] As one implementation method, such as Figure 7 As shown, the compensation module 426 can be a compensation transistor T3, which includes a gate, a source, and a drain. The gate of the voltage divider transistor T3 receives the second scan signal sn2, its source is connected to connection point S4, and its drain is connected to the control terminal S2 of the driving module 421. During the data writing phase, when the second scan signal sn2 is low, both the data writing transistor T2 and the compensation transistor T3 are turned on. The data voltage input at the DATA terminal is transmitted to the source of the driving transistor T1 through the data writing transistor T2, and then sequentially written to the gate of the driving transistor T1 through the driving transistor T1 and the compensation transistor T3. As the data voltage is written, the gate voltage of the driving transistor T1 gradually increases until the gate voltage of the driving transistor M1 rises to Vdata + Vth. Vdata refers to the data voltage input to DATA, and Vth refers to the threshold voltage of the driving transistor M1.

[0070] The reset module 427 is connected between the drive initialization voltage terminal VREFN1 and the control terminal S2 of the drive module 421. The reset module 427 is configured to be turned on in response to the reset signal sn1, so as to provide the drive initialization voltage input to the drive initialization voltage terminal VREFN1 to the control terminal S2 of the drive module 421.

[0071] As one implementation method, such as Figure 7As shown, the reset module 427 can be a reset transistor T4. The reset transistor T4 includes a gate, a source, and a drain. The gate of the reset transistor T4 receives the drive initialization gate signal sn1, its source receives the drive initialization voltage VREFN1, and its drain is connected to the connection point S4. The drive initialization transistor T4 can be turned on in response to the drive initialization gate signal SN1 to transmit the drive initialization voltage VREFN1 to the connection point S4. When the compensation transistor T3 is turned on, the voltage at the connection point S4 can be transmitted to the control terminal S2 of the drive module 421 through the compensation transistor T3 to control the gate voltage of the drive transistor T1.

[0072] The light-emitting control module 428 and the driving module 421 are connected in series between the first power supply voltage terminal ELVDD and the first terminal of the light-emitting unit 410. The light-emitting control module 428 is configured to control the driving module 421 to drive the light-emitting unit 410 to emit light in response to the light-emitting control signal EM being turned on.

[0073] As one implementation method, such as Figure 7 As shown, the light-emitting control module 428 includes a first light-emitting control transistor T5 and a second light-emitting control transistor T6. The first light-emitting control transistor T5 includes a gate, a source, and a drain. The gate of the first light-emitting control transistor T5 receives the light-emitting signal em, its source receives the first power supply voltage elvdd, and its drain is connected to the source of the driving transistor T1 through the first terminal S3 of the driving module 421. The first light-emitting control transistor T5 can be turned on in response to the light-emitting signal em to transmit the first power supply voltage elvdd to the source of the driving transistor T1 through the first terminal S3 of the driving module 421. The second light-emitting control transistor T6 includes a gate, a source, and a drain. The gate of the second light-emitting control transistor T6 also receives the light-emitting signal em, and its source is connected to the second terminal S5 of the driving module 421. The second terminal S5 of the driving module 421 is used to connect to the drain of the driving transistor T1. The drain of the second light-emitting control transistor T6 is connected to the anode of the light-emitting unit 410 through the connection point S1. The second light-emitting control transistor T5 can be turned on in response to the light-emitting signal em to transmit the voltage at the drain of the driving transistor T1 to the anode + of the light-emitting unit 410 through the connection point S1.

[0074] Optionally, the transistors included in the compensation module and the reset module are all N-type transistors, while the transistors included in the drive module, the initialization module, the bias module, the data writing module, and the light emission control module are all P-type transistors.

[0075] See also Figure 5 , Figures 7-9The storage module 429 can be a storage capacitor Cst. The storage capacitor Cst is connected to the control terminal S2 and the ELVDD terminal of the drive module 421 for charging and discharging.

[0076] This application embodiment also provides a display panel, which includes any of the pixel circuits described above.

[0077] This application also provides a display device, which includes: a plurality of pixel circuits, a scanning circuit, a plurality of preset scan lines, and a first voltage terminal.

[0078] The multiple pixel circuits are arranged in an array, and each pixel circuit is equipped with the impedance control module described above. The impedance of the impedance control module is adjustable.

[0079] The scanning circuit is connected to the pixel circuit of the corresponding row via the corresponding preset scan line.

[0080] The first voltage terminal is connected to the pixel circuit and / or the impedance control module. The pixel circuit is used to transmit the voltage on the first voltage terminal to the pixel circuit in response to the pulse signal on the preset scan line.

[0081] Optionally, during at least a portion of the time period, the voltage at the first voltage terminal is written into the voltage transmission path of the pixel circuit, which includes the load control module.

[0082] In some embodiments, the impedance of the impedance control module is different during a first time period and a second time period within at least one screen refresh cycle.

[0083] Optionally, there may be multiple impedance control modules, with each pixel circuit having a corresponding impedance control module.

[0084] Optionally, at least one row of pixel circuits or one column of pixel circuits may share a single impedance control module.

[0085] Optionally, multiple pixel circuits arranged in an array share a single impedance control module.

[0086] Optionally, the pixel circuit includes: The driving module is connected between the first power supply voltage terminal and the first terminal of the light-emitting unit, and is configured to provide driving current to the light-emitting unit.

[0087] An initialization module, connected between the initialization voltage terminal and the first terminal of the light-emitting unit, is configured to be turned on in response to an initialization gate signal, so that the light-emitting unit is connected to the initialization voltage. The first voltage terminal includes an initialization voltage terminal. The signals transmitted by the preset scan line include the initialization gate signal.

[0088] Optionally, the display area of ​​the display device includes Q first areas and W second areas arranged alternately along the column direction, where Q is greater than W and Q and W are positive integers.

[0089] Within a screen refresh cycle, during the first time period, the voltage on the first voltage terminal is transmitted simultaneously to the Q intervals of the first zone.

[0090] In a second time period, different from the first time period, voltages on the first voltage terminals are simultaneously transmitted to W spaced-apart second zones. The impedance of the impedance control module corresponding to the Q first zones in the first time period is less than the impedance of the impedance control module corresponding to the W second zones in the second time period.

[0091] The above text combined Figures 1 to 9 The device embodiments of this application have been described in detail below, in conjunction with... Figure 10 The method embodiments of this application are described in detail below. It should be understood that the description of the method embodiments corresponds to the description of the apparatus embodiments; therefore, any parts not described in detail can be referred to the foregoing apparatus embodiments.

[0092] like Figure 10 As shown in the figure, this application embodiment also provides a pixel circuit driving method 1000. This driving method is implemented using any of the pixel circuits described above.

[0093] like Figure 10 As shown, the pixel circuit driving method 1000 includes step S1010.

[0094] In step S1010: During the first and second time periods within at least one screen refresh cycle, the impedance of the impedance control module is made different.

[0095] For example, during the initialization phase, the initialization module is turned on using the initialization gate signal so that the initialization voltage is provided to the light-emitting unit through the initialization module. When the number of effective pulses of the initialization gate signal changes, the impedance of the impedance control module is adjusted to change.

[0096] It should be noted that, in the embodiments of this application, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0097] It should be understood that when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above the other layer or region, or that it contains other layers or regions between it and the other layer or region. Furthermore, if the component is flipped over, that layer or region will be located "below" or "under" the other layer or region.

[0098] It should be understood that the term "and / or" used in the embodiments of this application is merely a description of the relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in the embodiments of this application generally indicates that the preceding and following associated objects have an "or" relationship.

[0099] In the embodiments of this application, the term "electrical connection" can refer to two components being directly electrically connected, or it can refer to two components being electrically connected via one or more other components.

[0100] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A pixel circuit, characterized in that, include: A driving module is connected between a first power supply voltage terminal and a first terminal of a light-emitting unit, and is configured to provide driving current to the light-emitting unit; An initialization module is connected between the initialization voltage terminal and the first terminal of the light-emitting unit, and is configured to be turned on in response to an initialization gate signal so that the first terminal of the light-emitting unit is connected to the initialization voltage; An impedance control module is connected to the initial voltage, and the impedance of the impedance control module is adjustable. The impedance control module includes multiple impedance paths connected in parallel, including a first impedance path and a second impedance path. The number of light-emitting units is multiple, forming multiple rows of light-emitting units. The impedance control module is configured as follows: When the number of rows of light-emitting units connected to the initial voltage is m, both the first impedance path and the second impedance path are controlled to be turned on. When the number of rows of light-emitting units connected to the initial voltage is n, one of the first impedance path and the second impedance path is controlled to be turned on; Where m is greater than n.

2. The pixel circuit according to claim 1, characterized in that, Each impedance path includes a resistive element and a switching element connected in series.

3. The pixel circuit according to claim 2, characterized in that, The resistances of the resistive elements in the impedance path may be the same or different.

4. The pixel circuit according to claim 2, characterized in that, The switching element includes a transistor.

5. The pixel circuit according to claim 1, characterized in that, The impedance control module is connected in series with the initialization module.

6. The pixel circuit according to claim 1, characterized in that, The impedance of the impedance control module is different during the first and second time periods within at least one screen refresh cycle.

7. The pixel circuit according to claim 6, characterized in that, The number of light-emitting units connected to the initial voltage differs between the first time period and the second time period.

8. The pixel circuit according to claim 6, characterized in that, The number of light-emitting units connected to the initialization voltage in the first time period is greater than the number of light-emitting units connected to the initialization voltage in the second time period, and the impedance of the impedance control module in the first time period is less than the impedance of the impedance control module in the second time period.

9. The pixel circuit according to claim 6, characterized in that, The number of rows of light-emitting units connected to the initial voltage differs between the first time period and the second time period.

10. The pixel circuit according to claim 9, characterized in that, The number of rows of light-emitting units that are connected to the initialization voltage in the first time period is greater than the number of rows of light-emitting units that are connected to the initialization voltage in the second time period, and the impedance of the impedance control module in the first time period is less than the impedance of the impedance control module in the second time period.

11. The pixel circuit according to claim 9, characterized in that, Within one of the screen refresh cycles, the initialization gate signal includes multiple pulse signals.

12. The pixel circuit according to claim 6, characterized in that, A screen refresh cycle includes an active phase and a blanking phase, wherein the first time period is located in the active phase and the second time period is located in the blanking phase.

13. The pixel circuit according to claim 12, characterized in that, A screen refresh cycle includes a write frame, the active phase is within the write frame, and at least a portion of the blanking phase is located within the write frame.

14. The pixel circuit according to claim 12, characterized in that, A screen refresh cycle also includes a hold frame, which is located within the blanking phase.

15. The pixel circuit according to claim 1, characterized in that, A screen refresh cycle includes an active phase and a blanking phase. The number of light-emitting unit rows connected to the initialization voltage is m in the active phase and n in the blanking phase.

16. The pixel circuit according to claim 1, characterized in that, The pixel circuit also includes: A bias module is connected between a bias voltage terminal and a first or second terminal of the drive module. The bias module is configured to be turned on in response to the initialization gate signal to provide a bias voltage to the drive module. A data writing module is connected between the data signal terminal and the first terminal of the driving module. The data writing module is configured to be turned on in response to a first scan signal to provide a data signal to the driving module. A compensation module is connected between the second terminal of the drive module and the control terminal of the drive module. The compensation module is configured to be turned on in response to a second scan signal to compensate the threshold voltage of the drive module. A reset module is connected between the drive initialization voltage terminal and the control terminal of the drive module. The reset module is configured to be turned on in response to a reset signal to provide a drive initialization voltage to the control terminal of the drive module. A light-emitting control module is provided, wherein the light-emitting control module and the driving module are connected in series between the first power supply voltage terminal and the first terminal of the light-emitting unit, and the light-emitting control module is configured to be turned on in response to a light-emitting control signal.

17. The pixel circuit according to claim 16, characterized in that, The transistors included in the compensation module and the reset module are all N-type transistors, while the transistors included in the driving module, the initialization module, the bias module, the data writing module, and the light emission control module are all P-type transistors.

18. A display device, characterized in that, include: Multiple pixel circuits are arranged in an array. Each pixel circuit is equipped with an impedance control module, and the impedance of the impedance control module is adjustable. The impedance control module includes multiple impedance paths connected in parallel. Each impedance path is equipped with a switching element. The multiple impedance paths include a first impedance path and a second impedance path. There are multiple light-emitting units, which form multiple rows of light-emitting units. The impedance control module is configured as follows: When the number of rows of light-emitting units connected to the initial voltage is m, both the first impedance path and the second impedance path are controlled to be turned on. When the number of rows of light-emitting units connected to the initial voltage is n, one of the first impedance path and the second impedance path is turned on. Where m is greater than n; A scanning circuit and multiple preset scan lines, wherein the scanning circuit is connected to the pixel circuit of the corresponding row via the corresponding preset scan lines; The first voltage terminal is connected to the pixel circuit and / or the impedance control module. The pixel circuit is used to transmit the voltage on the first voltage terminal to the pixel circuit in response to the pulse signal on the preset scan line.

19. The display device according to claim 18, characterized in that, The impedance of the impedance control module is different during the first and second time periods within at least one screen refresh cycle.

20. The display device according to claim 18, characterized in that, The number of impedance control modules is multiple, and each pixel circuit has one impedance control module.

21. The display device according to claim 18, characterized in that, At least one row of pixel circuits or one column of pixel circuits shares one impedance control module.

22. The display device according to claim 18, characterized in that, Multiple pixel circuits arranged in an array share a single impedance control module.

23. The display device according to claim 18, characterized in that, The pixel circuit includes: A driving module is connected between a first power supply voltage terminal and a first terminal of a light-emitting unit, and is configured to provide driving current to the light-emitting unit; An initialization module is connected between an initialization voltage terminal and a first terminal of the light-emitting unit, and is configured to be turned on in response to an initialization gate signal so that the light-emitting unit is connected to the initialization voltage; the first voltage terminal includes the initialization voltage terminal; the signal transmitted by the preset scan line includes the initialization gate signal.

24. The display device according to claim 18, characterized in that, The display area of ​​the display device includes Q first areas and W second areas arranged alternately along the column direction, where Q is greater than W, and Q and W are positive integers; Within a screen refresh cycle, in the first time period, the voltage on the first voltage terminal is transmitted simultaneously to the Q intervals of the first zone; In a second time period, which is different from the first time period, the voltage on the first voltage terminal is transmitted simultaneously to W second zones at intervals; wherein, the impedance of the impedance control module corresponding to Q first zones in the first time period is less than the impedance of the impedance control module corresponding to W second zones in the second time period.

25. A driving method for a pixel circuit, characterized in that, The driving method employs the pixel circuit according to any one of claims 1-17, and the driving method includes: In the first and second time periods within at least one screen refresh cycle, the impedance of the impedance control module is made different.

26. A display panel, characterized in that, include: The pixel circuit as described in any one of claims 1-17.

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