Chip backside detection method, apparatus, computing device, and storage medium

Abstract

This invention discloses a method, apparatus, computing device, and storage medium for back-side inspection of chips, relating to the field of visual inspection technology. The method includes: acquiring a macroscopic image of a wafer; performing path planning for the microscopic imaging positions of the wafer based on the macroscopic image to obtain path planning coordinates; controlling a microscopic imaging device to acquire microscopic images of the wafer based on the path planning coordinates, wherein the wafer includes multiple chips; segmenting the microscopic image to obtain multiple chip back-side images; performing inspection on each chip back-side image to determine the defect type and defect location on the back side of each chip, obtaining a back-side inspection result for each chip; and generating a wafer map image based on the back-side inspection results of all chips. According to the technical solution of this invention, automated microscopic imaging is achieved, improving the accuracy and efficiency of defect detection on the back side of chips, and the inspection results are visualized by generating a map image.

Description

Technical Field

[0001] This invention relates to the field of visual inspection technology, and in particular to a method, apparatus, computing device, and storage medium for inspecting the back of a chip. Background Technology

[0002] With the rapid development of third-generation semiconductor GaN materials, GaN-based LED chips have experienced explosive growth and rapid commercialization, laying the foundation for the realization and application of visible light communication. However, current back-side defect detection systems for GaN-based LED chips are ineffective, failing to accurately locate specific chips and reveal back-side defect characteristics. Therefore, back-side defect detection for GaN-based LED chips currently relies on manual visual inspection, a method that is not only inefficient but also susceptible to subjective interference from inspectors.

[0003] Therefore, a chip backside inspection method is needed to solve the problems existing in the above technical solutions. Summary of the Invention

[0004] Therefore, the present invention provides a chip backside inspection method and a chip backside inspection device to solve or at least alleviate the problems mentioned above.

[0005] According to one aspect of the present invention, a method for inspecting the back side of a chip is provided, executed in a computing device, comprising: acquiring a macroscopic image of a wafer; performing path planning for the microscopic imaging position of the wafer based on the macroscopic image to obtain path planning coordinates; controlling a microscopic imaging device to acquire a microscopic image of the wafer based on the path planning coordinates, the wafer including multiple chips; segmenting the microscopic image to obtain multiple chip back side images; performing inspection based on each chip back side image to determine the defect type and defect location on the back side of each chip, obtaining a back side inspection result for each chip; and drawing and generating a wafer map image based on the back side inspection results of all chips.

[0006] Optionally, in the chip backside detection method according to the present invention, before acquiring a macroscopic image of the wafer, the method further includes: controlling a first imaging device to acquire a backlight image of the wafer; determining the angle between each chip on the wafer and the horizontal direction based on the backlight image to determine the offset angle of the wafer; and controlling a driving device to rotate the wafer based on the offset angle to perform pose correction on the wafer.

[0007] Optionally, in the chip backside inspection method according to the present invention, drawing and generating a wafer map image based on the backside inspection results of all chips includes: determining and saving the microscopic image coordinates of each chip in the microscopic image; determining the global coordinates of each chip on the wafer based on the path planning coordinates and the microscopic image coordinates of each chip; and drawing and generating a wafer map image based on the global coordinates of each chip and the backside inspection results corresponding to each chip.

[0008] Optionally, in the chip backside inspection method according to the present invention, the wafer map image includes chip regions corresponding to each chip, and the chip regions are filled with colors based on the defect types of the chips.

[0009] Optionally, the chip backside inspection method according to the present invention further includes: obtaining barcode information from the macroscopic image so as to identify the wafer using the barcode information.

[0010] Optionally, in the chip backside detection method according to the present invention, obtaining barcode information from the macroscopic image includes: inputting the macroscopic image into a target detection model for processing to predict the target area where the barcode is located; rotating and scaling the barcode in the target area and extracting the barcode; and decoding the barcode to obtain barcode information.

[0011] Optionally, the chip backside detection method according to the present invention further includes: associating and storing the barcode information with the wafer map image so as to obtain the corresponding wafer map image based on the barcode information.

[0012] Optionally, in the chip backside inspection method according to the present invention, the path planning for the microscopic imaging position of the wafer based on the macroscopic image to obtain the path planning coordinates includes: extracting the wafer outline from the macroscopic image; and calculating the coordinates of each microscopic imaging position of the wafer based on the wafer outline to obtain the path planning coordinates.

[0013] Optionally, in the chip backside detection method according to the present invention, extracting the wafer outline from the macroscopic image includes: using a region growing algorithm to separate the wafer region from the background region in the macroscopic image to extract the wafer outline.

[0014] Optionally, in the chip backside inspection method according to the present invention, the defect type includes one or more of the following: back plating peeling, back plating discoloration, voids, scratches, and edge chipping.

[0015] Optionally, in the chip backside detection method according to the present invention, segmenting the microscopic image to obtain multiple chip backside images includes: segmenting the microscopic image using a coarse segmentation algorithm to obtain multiple chip backside images.

[0016] According to one aspect of the present invention, a chip backside inspection apparatus residing in a computing device is provided, comprising: an acquisition unit adapted to acquire a macroscopic image of a wafer, and to perform path planning on the microscopic imaging position of the wafer based on the macroscopic image to obtain path planning coordinates; a control unit adapted to control a microscopic imaging device to acquire a microscopic image of the wafer based on the path planning coordinates, the wafer including a plurality of chips; a segmentation unit adapted to segment the microscopic image to obtain a plurality of chip backside images; a detection unit adapted to perform detection based on each chip backside image to determine the defect type and defect location on the backside of each chip, and to obtain a backside inspection result for each chip; and a generation unit adapted to generate a wafer map image based on the backside inspection results of all chips.

[0017] According to one aspect of the present invention, a computing device is provided, comprising: at least one processor; and a memory storing program instructions, wherein the program instructions are configured to be executed by the at least one processor, the program instructions including instructions for performing the chip backside detection method as described above.

[0018] According to one aspect of the present invention, a readable storage medium storing program instructions is provided, which, when read and executed by a computing device, causes the computing device to perform the chip backside detection method as described above.

[0019] According to the technical solution of the present invention, a method for inspecting the back side of a chip is provided, applicable to GaN-based LED chips. The method involves planning a path for the microscopic imaging position of the wafer based on a macroscopic image of the wafer, obtaining path planning coordinates. Subsequently, a microscopic imaging device is controlled to acquire microscopic images of the wafer based on the path planning coordinates, and these images are segmented to obtain multiple back-side images of the chip. Then, inspection is performed on each back-side image to determine the defect type and location on the back side of each chip, obtaining the back-side inspection result for each chip. A wafer map image is generated based on the back-side inspection results of all chips. Thus, according to the technical solution of the present invention, automated microscopic imaging is achieved through path planning during the back-side inspection process, improving the accuracy and efficiency of defect detection on the back side of the chip. Furthermore, the inspection results for each back-side of the chip can be visualized as a map image.

[0020] Furthermore, during the inspection of the back side of the chip, the present invention also automatically corrects the wafer's pose by acquiring a backlight image of the wafer, thereby achieving automated acquisition of macroscopic imaging of the wafer and further improving the accuracy and efficiency of defect detection on the back side of the chip.

[0021] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and in order to make the above and other objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention are described below. Attached Figure Description

[0022] To achieve the foregoing and related objectives, certain illustrative aspects are described herein in conjunction with the following description and accompanying drawings. These aspects indicate various ways in which the principles disclosed herein may be practiced, and all aspects and their equivalents are intended to fall within the scope of the claimed subject matter. The foregoing and other objectives, features, and advantages of this disclosure will become more apparent from the following detailed description, taken in conjunction with the accompanying drawings. Throughout this disclosure, the same reference numerals generally refer to the same parts or elements.

[0023] Figure 1 A schematic diagram of a computing device 100 according to an embodiment of the present invention is shown;

[0024] Figure 2 A schematic flowchart of a chip backside inspection method 200 according to an embodiment of the present invention is shown;

[0025] Figure 3 , Figure 4 The diagrams show the pose correction station and the back detection station of the detection system 300 according to an embodiment of the present invention.

[0026] Figure 5 The illustration shows a schematic diagram of the effects of macroscopic and microscopic images according to an embodiment of the present invention;

[0027] Figure 6 A schematic diagram of a process for detecting barcodes on a wafer based on a barcode detection algorithm according to an embodiment of the present invention is shown;

[0028] Figure 7 A schematic diagram of the target detection module 700 according to an embodiment of the present invention is shown;

[0029] Figure 8 A schematic diagram illustrating path planning for the microscopic imaging position of a wafer based on a macroscopic image is shown in one embodiment of the present invention.

[0030] Figure 9A schematic diagram of a chip backside detection device 900 according to an embodiment of the present invention is shown. Detailed Implementation

[0031] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0032] Figure 1 A schematic diagram of a computing device 100 according to an embodiment of the present invention is shown. Figure 1 As shown, in a basic configuration, computing device 100 includes at least one processing unit 102 and system memory 104. According to one aspect, depending on the configuration and type of the computing device, the processing unit 102 may be implemented as a processor. System memory 104 includes, but is not limited to, volatile memory (e.g., random access memory), non-volatile memory (e.g., read-only memory), flash memory, or any combination of such memories. According to one aspect, system memory 104 includes an operating system 105.

[0033] According to one aspect, operating system 105 is, for example, suitable for controlling the operation of computing device 100. Furthermore, examples are practiced in conjunction with graphics libraries, other operating systems, or any other applications, and are not limited to any particular application or system. Figure 1 The basic configuration is illustrated by the components within the dashed lines. According to one aspect, the computing device 100 has additional features or functions. For example, according to one aspect, the computing device 100 includes additional data storage devices (removable and / or non-removable), such as disks, optical discs, or magnetic tapes. This additional storage... Figure 1 The middle part is shown by removable storage device 109 and non-removable storage device 110.

[0034] As stated above, according to one aspect, program module 103 is stored in system memory 104. According to one aspect, program module 103 may include one or more applications. The present invention does not limit the type of application; for example, applications may include: email and contact applications, word processing applications, spreadsheet applications, database applications, slideshow applications, drawing or computer-aided applications, web browser applications, etc.

[0035] According to one aspect, program module 103 includes a chip backside detection device 900, which contains a plurality of program instructions suitable for performing the chip backside detection method 200 of the present invention.

[0036] According to one aspect, examples can be practiced on circuits including discrete electronic components, packaged or integrated electronic chips containing logic gates, circuits utilizing microprocessors, or on a single chip containing electronic components or a microprocessor. For example, it can be practiced via wherein... Figure 1 Each or many of the components shown can be implemented as an example by integrating a System-on-a-Chip (SOC) on a single integrated circuit. According to one aspect, such an SOC device may include one or more processing units, graphics units, communication units, system virtualization units, and various application functions, all integrated (or “burned in”) as a single integrated circuit onto a chip substrate. When operating via the SOC, the functions described herein can be operated via dedicated logic integrated on a single integrated circuit (chip) with other components of the computing device 100. Embodiments of the invention can also be implemented using other techniques capable of performing logical operations (e.g., AND, OR, and NOT), including but not limited to mechanical, optical, fluid, and quantum technologies. Additionally, embodiments of the invention can be implemented within a general-purpose computer or in any other circuit or system.

[0037] According to one aspect, computing device 100 may also have one or more input devices 112, such as a keyboard, mouse, pen, voice input device, touch input device, etc. It may also include output devices 114, such as a display, speaker, printer, etc. The foregoing devices are examples and other devices may also be used. Computing device 100 may include one or more communication connections 116 that allow communication with other computing devices 118. Examples of suitable communication connections 116 include, but are not limited to: RF transmitter, receiver and / or transceiver circuitry; Universal Serial Bus (USB), parallel and / or serial ports.

[0038] As used herein, the term computer-readable medium includes computer storage medium. Computer storage medium can include volatile and non-volatile, removable and non-removable media implemented using any method or technology for storing information (e.g., computer-readable instructions, data structures, or program module 103). System memory 104, removable storage device 109, and non-removable storage device 110 are examples of computer storage media (i.e., memory storage). Computer storage media can include random access memory (RAM), read-only memory (ROM), electrically erasable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical storage, magnetic tape, magnetic tape, disk storage or other magnetic storage devices, or any other article of manufacture that can be used to store information and is accessible by computing device 100. According to one aspect, any such computer storage medium can be part of computing device 100. Computer storage media does not include carrier waves or other transmitted data signals.

[0039] According to one aspect, the communication medium is implemented by computer-readable instructions, data structures, program modules 103, or other data in a modulated data signal (e.g., a carrier wave or other transmission mechanism), and includes any information transmission medium. According to one aspect, the term "modulated data signal" describes a signal having one or more sets of characteristics or altered in a manner that encodes information in the signal. By way of example and not limitation, the communication medium includes wired media such as wired networks or direct wired connections, and wireless media such as acoustic, radio frequency (RF), infrared, and other wireless media.

[0040] In an embodiment of the present invention, a computing device 100 may be configured to execute a chip backside inspection method 200 according to the present invention. The computing device 100 includes one or more processors and one or more readable storage media storing program instructions, which, when configured to be executed by the one or more processors, cause the computing device to execute the chip backside inspection method 200 of the present invention. By executing the chip backside inspection method 200 of the present invention, the accuracy and efficiency of defect detection on the chip's appearance can be improved.

[0041] According to one embodiment of the present invention, a chip backside detection device 900 is deployed in a computing device 100, and the chip backside detection device 900 is configured to execute a chip backside detection method 200 according to the present invention. The chip backside detection device 900 includes a plurality of program instructions for executing the chip backside detection method 200 of the present invention, which can instruct a processor to execute the chip backside detection method 200 according to the present invention.

[0042] Figure 2 A schematic flowchart of a chip backside inspection method 200 according to an embodiment of the present invention is shown. The chip backside inspection method 200 is adapted to be executed in a computing device (e.g., the aforementioned computing device 100), specifically in a chip backside inspection apparatus 900 of the computing device 100.

[0043] According to the chip backside inspection method 200 of the present invention, multiple chips on a wafer can be automatically imaged, and defects can be detected on the backside of each chip. Specifically, the chip to be inspected may be a GaN-based LED chip.

[0044] like Figure 2 As shown, method 200 begins with step 210.

[0045] First, in step 210, a macroscopic image of the wafer is acquired. Based on the macroscopic image, a path is planned for the microscopic imaging position of the wafer to obtain the path planning coordinates. Here, a macroscopic imaging device can be controlled to acquire and obtain the macroscopic image of the wafer.

[0046] It should be noted that the computing device 100 may perform pose correction on the wafer before executing step 210. According to embodiments of the present invention, pose correction on the wafer can be performed automatically, and specific embodiments will be described below.

[0047] Subsequently, in step 220, the wafer movement is controlled according to the path planning coordinates, and a microscopic imaging device is controlled to acquire microscopic images of the wafer, which includes multiple chips. Specifically, a predetermined number of chips can be arranged on the wafer.

[0048] It should be noted that the above path planning coordinates include the coordinates of the positions where the wafer is subjected to multiple microscopic imaging operations. The computing device 100 can control the wafer to move to the corresponding position for microscopic imaging each time based on the coordinates of each microscopic imaging position in the path planning coordinates (that is, control the microscopic imaging device to collect microscopic images of the wafer at the corresponding position), and finally complete the collection of multiple microscopic images of the wafer.

[0049] Next, in step 230, all the microscopic images are segmented to obtain multiple back-side images of the chip. Here, each back-side image corresponds to a single chip.

[0050] In one embodiment, a coarse segmentation algorithm can be used to segment the microscopic image to obtain multiple images of the back of the chip.

[0051] In addition, incomplete images of the back of the chip can be removed based on the chip's reasonable area and aspect ratio.

[0052] Next, in step 240, detection is performed based on the back image of each chip to determine the defect type and defect location on the back of each chip, and the back detection result of each chip is obtained.

[0053] In some embodiments, the defect type may include one or more of the following: back plating peeling, back plating discoloration, voids, scratches, and edge chipping. When performing inspection based on each chip backside image, each of the above defect types can be inspected sequentially based on the chip backside image to determine whether each of the above defect types exists on the corresponding chip backside.

[0054] In some specific embodiments, the detection method for back plating peeling defects is as follows: Based on the chip back image, the area of ​​the epitaxial region is calculated, and the presence of back plating peeling defects is determined by area comparison. Specifically, the area of ​​the blue region in the epitaxial region of the chip back image is calculated, and the proportion of the blue region to the epitaxial region area is used to determine whether back plating peeling defects exist. The detection method for back plating color defects is as follows: Based on the chip back image, the area of ​​the epitaxial region other than blue is calculated, and the proportion of the other color regions to the epitaxial region area is used to determine whether back plating color defects exist. The detection method for void defects is as follows: Based on the chip back image, constrained by roundness, color, area, and unevenness, spots that meet the conditions are found in the epitaxial region, and the presence of void defects is determined accordingly. The detection method for scratch defects is as follows: The chip back image is processed by differential analysis, filtering, binarization, and contour finding, and the presence of scratch defects is determined based on the contour length. The detection method for chipping defects is as follows: the back image of the chip is angle-corrected, the minimum bounding rectangle of the epitaxial region is determined and filled after correction, and the difference is calculated with the original back image of the chip before correction. The chipping defects are determined based on the abnormal length of 4 consecutive points.

[0055] Specifically, when detecting any of the above-mentioned defect types based on the chip's backside image, if the corresponding defect is detected (i.e., it is determined that the chip's backside defect type exists), the detection process can be terminated, and the defect type and location can be output as the chip's backside detection result and saved. If no corresponding defect is detected after detecting all of the above-mentioned defect types, a normal result is output as the chip's backside detection result and saved.

[0056] Finally, in step 250, a wafer map image is generated based on the backside inspection results of all chips.

[0057] Thus, by viewing the wafer map image generated according to the present invention, the back-side defects of each chip on the wafer can be observed, thereby realizing the visualization of the back-side inspection results of the chips.

[0058] In one embodiment, in step 250, the microscopic image coordinates of each chip in the microscopic image can be determined and saved. Subsequently, the global coordinates of each chip on the wafer are determined based on the path planning coordinates (coordinates of each microscopic imaging position) and the microscopic image coordinates of each chip.

[0059] Furthermore, a wafer map image can be generated based on the global coordinates of each chip and the corresponding backside inspection results. Specifically, the wafer map image can be generated based on the global coordinates of each chip and the corresponding defect type.

[0060] In one specific embodiment, when generating a wafer map image based on the global coordinates of each chip and the backside detection results of each chip, an initial wafer map image can first be drawn based on the global coordinates of each chip. Then, the chip area in the initial wafer map image can be filled with the corresponding color (each defect type corresponds to a color) according to the defect type on the backside of each chip to generate the final wafer map image.

[0061] In other words, the wafer map image includes the chip area corresponding to each chip, and the chip area is filled with a color based on the defect type of the chip.

[0062] Figure 3 , Figure 4 The diagrams show the pose correction station and the back detection station of the detection system 300 according to one embodiment of the present invention.

[0063] like Figure 3 and Figure 4 As shown, the detection system 300 includes a microscopic imaging device and a macroscopic imaging device. Specifically, the detection system 300 includes... Figure 3 The position correction station shown is... Figure 4 The diagram shows a back-side inspection station. This station is equipped with microscopic and macroscopic imaging devices for imaging the wafer. The pose correction station is equipped with a backlight imaging device for backlight imaging of the wafer.

[0064] Furthermore, the detection system 300 also includes the computing device of the present invention (…). Figure 3(Not shown in the image). The computing device 100 can be communicatively connected to a backlight imaging device, a microscopic imaging device, and a macroscopic imaging device. In this way, the computing device 100 can control the backlight imaging device to acquire backlight images of the wafer, control the microscopic imaging device to acquire microscopic images of the wafer, and control the macroscopic imaging device to acquire macroscopic images of the wafer. Furthermore, the computing device 100 can acquire the backlight images acquired by the backlight imaging device, acquire the microscopic images of the wafer acquired by the microscopic imaging device, and acquire the macroscopic images of the wafer acquired by the macroscopic imaging device.

[0065] here, Figure 5 The illustration shows a schematic diagram of the effects of macroscopic and microscopic images according to an embodiment of the present invention.

[0066] According to one embodiment of the present invention, the wafer can be pose-corrected by the following method before performing step 210.

[0067] At the pose correction station of the detection system 100, the computing device 100 can control the backlight imaging device (at the pose correction station) to acquire the backlight image of the wafer, ensuring that the acquired backlight image of the wafer contains the back contours of all chips (GaN-based LED chips). Here, the wafer is placed on a blue film, and the blue film is placed on a platform. Subsequently, the angle between each chip on the wafer and the horizontal direction can be determined based on the backlight image, and the wafer offset angle can be determined based on the angles between all chips and the horizontal direction. Specifically, an adaptive thresholding algorithm can be used to segment the backlight image into foreground and background, removing incomplete chip contours at the image edges while filling in complete contours. By extracting all complete contours and calculating the angles between all complete contours and the horizontal direction, and removing outliers according to statistical principles, the average of the angles between the remaining complete contours and the horizontal direction is calculated to determine the wafer offset angle.

[0068] Then, the drive device (on the pose correction station) can be controlled to rotate the wafer based on the offset angle to correct the wafer's pose. Next, the backlight image of the wafer can be captured again to verify whether the wafer's pose correction has reached the ideal level. If it has not, the wafer's pose correction can be performed based on the captured backlight image.

[0069] In one implementation, the backlight imaging device includes a backlight imaging camera and a backlight imaging lens. Combined with a backlight source, it can perform backlight imaging on the wafer to acquire a backlight image of the wafer.

[0070] In one implementation, the driving device at the pose correction station may include a retractable cylinder, a fixture, and a motor (specifically, a DD motor). When controlling the driving device to rotate the wafer according to the offset angle, the retractable cylinder can be controlled to drive the fixture to clamp the blue film under the wafer. Then, the motor can be controlled to rotate the wafer according to the offset angle to achieve pose correction of the wafer.

[0071] In one embodiment, the back-side inspection station of the inspection system 300 includes a marble platform, on which a cross slide (an XY-axis cross slide, which can move along the X-axis and Y-axis respectively under the drive of an X-axis linear motor and a Y-axis linear motor) is deployed. After the wafer's pose is corrected, the computing device 100 can control (driven by linear motors) the movement of the cross slide to move the wafer (the blue film and the wafer on the carrier platform) to the back-side inspection station, thereby controlling the macroscopic imaging device to acquire macroscopic images of the wafer.

[0072] In one implementation, the platform may include a vacuum adsorption stage and optical glass, with a backlight deployed below the optical glass.

[0073] In one implementation, the macroscopic imaging device includes a macroscopic imaging camera, a macroscopic imaging lens, and a corresponding ring light source, the ring light source being used to provide ring light for macroscopic imaging. The microscopic imaging device includes a microscopic imaging camera, a microscopic imaging lens, and a corresponding coaxial light source, the coaxial light source providing frontal point light for microscopic imaging.

[0074] In one implementation, a column is provided on a marble platform, and the macroscopic imaging device can be installed on one side of the column. A Z-axis linear motor can be installed on the other side of the column. The Z-axis linear motor can be connected to the microscopic imaging device via a frame, so that the computing device 100 can adjust the height of the microscopic imaging camera, microscopic imaging lens and coaxial light source in the microscopic imaging device by controlling the Z-axis linear motor to achieve the focusing function during microscopic imaging.

[0075] In one embodiment, in step 220, the computing device 100 can control the movement of the cross slide according to the path planning coordinates, so as to move the wafer to the corresponding position for micro imaging each time according to the path planning coordinates (including the coordinates of the positions for multiple micro imaging of the wafer) (i.e., control the micro imaging device to collect micro images of the wafer at the corresponding positions), and finally complete the collection of multiple micro images of the wafer.

[0076] In some embodiments, a barcode is affixed to the wafer. After acquiring a macroscopic image of the wafer, the computing device 100 can also extract barcode information from the macroscopic image to identify the wafer using the barcode information, which can be used to trace the wafer.

[0077] Figure 6 A schematic diagram of a process for detecting barcodes on a wafer based on a barcode detection algorithm according to an embodiment of the present invention is shown.

[0078] like Figure 6 As shown, barcodes on a wafer can be detected using the YOLOv5 barcode detection algorithm. Specifically, a macroscopic image can be input into a (trained) target detection model for processing to predict the target area where the barcode is located. Then, the barcode in the target area can be rotated and scaled to extract the barcode pattern. By decoding the barcode, the barcode information can be obtained and subsequently output. Here, the barcode information is, for example, [example barcode information]. Figure 6 The example shown is WJ812H0082280075, but this is only one example, and the present invention is not limited thereto. Figure 6 The specific barcode and barcode information shown.

[0079] In addition, in the method 200 of the present invention, the barcode information corresponding to the wafer can be associated with and stored with the wafer map image, so that the corresponding wafer map image can be queried and obtained according to the barcode information.

[0080] Figure 7 A schematic diagram of the target detection module 700 according to an embodiment of the present invention is shown.

[0081] like Figure 7 As shown, in one embodiment, the barcode detection model includes a feature extraction module 710, a feature fusion module 720, and a target prediction module 730 coupled in sequence. The macroscopic image input to the target detection model is processed sequentially by the feature extraction module 710, the feature fusion module 720, and the target prediction module 730 to output the target area where the barcode is located.

[0082] Figure 8 A schematic diagram is shown illustrating path planning for the microscopic imaging position of a wafer based on a macroscopic image, according to one embodiment of the present invention.

[0083] like Figure 8 As shown, path planning for the microscopic imaging position of the wafer is performed based on the macroscopic image, which can be achieved using the following method (path planning algorithm).

[0084] First, the wafer outline is extracted from the macroscopic image. In one implementation, a region growing algorithm can be used to separate (segment) the wafer region from the background region in the macroscopic image to extract the wafer outline.

[0085] Next, the coordinates of each microscopic imaging position on the wafer can be calculated based on the wafer profile to obtain the path planning coordinates (initial path planning coordinates).

[0086] It should be noted here that the overall wafer outline is approximately circular. Because the wafer's pose has been pre-corrected, ensuring that the chip edges are parallel to the edges of the macroscopic image, the minimum bounding rectangle of the wafer outline can be directly extracted from the macroscopic image when extracting the wafer outline (e.g., ...). Figure 8 (As shown). Furthermore, based on the known chip size and the spacing between chips, the grid size for each microscopic imaging of the wafer, as well as the distance the chip moves each time (specifically, the distance the cross slide moves each time) can be determined. By calculating the grid coordinates for each microscopic imaging of the wafer, path planning is completed, and the path planning coordinates are obtained.

[0087] In another embodiment, after obtaining the path planning coordinates (initial path planning coordinates), microscopic imaging can be used to correct the initial path planning coordinates. Specifically, after the computing device 100 controls the microscopic imaging device to acquire a microscopic image of the wafer for the first time based on the initial path planning coordinates, the computing device 100 can calculate the coordinate offset based on the first acquired microscopic image, and correct the initial path planning coordinates based on the coordinate offset to obtain the final path planning coordinates (including the corrected coordinates of each microscopic imaging position). This ensures that the acquired microscopic image contains a complete image of the back side of all chips on the wafer.

[0088] In one implementation, after acquiring the first microscopic image of the wafer, this microscopic image (field of view) can include back-side images of a specific number of chips. Subsequently, starting from the initial coordinates of the minimum bounding rectangle of the wafer outline, the microscopic field of view is swept until the bottommost complete chip first appears in the field of view, obtaining a base point. Similarly, a second base point is obtained when the leftmost complete chip first appears in the field of view. The actual starting point of the path planning can be determined based on these two base points. By comparing the actual starting point with the initial coordinates of the aforementioned minimum bounding rectangle, the coordinate offset can be determined. Finally, the initial path planning coordinates can be corrected based on this coordinate offset, and the final path planning coordinates can be obtained after coordinate transformation. The final path planning coordinates are saved for subsequent calculation of the global coordinates of each chip.

[0089] Figure 9 A schematic diagram of a chip backside inspection apparatus 900 according to an embodiment of the present invention is shown. The chip backside inspection apparatus 900 resides in a computing device 100 and can be configured to perform the chip backside inspection method 200 of the present invention.

[0090] like Figure 9As shown, the chip backside detection device 900 includes an acquisition unit 910, a control unit 920, a segmentation unit 930, a detection unit 940, and a generation unit 950, which are coupled in sequence.

[0091] The acquisition unit 910 acquires a macroscopic image of the wafer and performs path planning for the microscopic imaging position of the wafer based on the macroscopic image to obtain path planning coordinates. The control unit 920 controls the microscopic imaging device to acquire microscopic images of the wafer, which includes multiple chips, based on the path planning coordinates. The segmentation unit 930 segments the microscopic image to obtain multiple back-side images of the chips. The detection unit 940 performs detection based on each chip's back-side image to determine the defect type and location on the back side of each chip, obtaining the back-side detection result for each chip. The generation unit 950 generates a wafer map image based on the back-side detection results of all chips.

[0092] It should be noted that the acquisition unit 910, control unit 920, segmentation unit 930, detection unit 940, and generation unit 950 are respectively used to execute the aforementioned steps 210 to 250. Here, the specific execution logic of the acquisition unit 910, control unit 920, segmentation unit 930, detection unit 940, and generation unit 950 can be found in the description of steps 210 to 250 in method 200 above, and will not be repeated here.

[0093] The chip backside inspection method 200 according to the present invention can be used for GaN-based LED chips. It involves planning a path for the microscopic imaging position of the wafer based on a macroscopic image of the wafer, obtaining path planning coordinates. Subsequently, a microscopic imaging device is controlled to acquire microscopic images of the wafer based on the path planning coordinates, and these microscopic images are segmented to obtain multiple chip backside images. Then, inspection is performed on each chip backside image to determine the defect type and location on the backside of each chip, obtaining the backside inspection result for each chip. A wafer map image is generated based on the backside inspection results of all chips. Thus, according to the technical solution of the present invention, automated microscopic imaging is achieved through path planning during the chip backside inspection process, improving the accuracy and efficiency of defect detection on the chip backside. Furthermore, the inspection results for each chip backside can be visualized as a map image.

[0094] Furthermore, during the inspection of the back side of the chip, the present invention also automatically corrects the wafer's pose by acquiring a backlight image of the wafer, thereby achieving automated acquisition of macroscopic imaging of the wafer and further improving the accuracy and efficiency of defect detection on the back side of the chip.

[0095] The various techniques described herein can be implemented in combination with hardware or software, or a combination thereof. Thus, the methods and apparatus of the present invention, or certain aspects or portions thereof, can take the form of program code (i.e., instructions) embedded in a tangible medium, such as a removable hard disk, USB flash drive, floppy disk, CD-ROM, or any other machine-readable storage medium, wherein when the program is loaded into and executed by a machine such as a computer, the machine becomes an apparatus for practicing the present invention.

[0096] A8. The method as described in any one of A1-A7, wherein path planning for the microscopic imaging position of the wafer based on the macroscopic image to obtain path planning coordinates includes: extracting the wafer outline from the macroscopic image; and calculating the coordinates of each microscopic imaging position of the wafer based on the wafer outline to obtain path planning coordinates.

[0097] A9. The method as described in A8, wherein extracting the wafer outline from the macroscopic image includes: using a region growing algorithm to separate the wafer region from the background region in the macroscopic image to extract the wafer outline.

[0098] A10, the method of any one of A1-A9, wherein the defect type includes one or more of the following: back plating peeling, back plating discoloration, voids, scratches, and edge chipping.

[0099] A11. The method of any one of A1-A10, wherein segmenting the microscopic image to obtain multiple chip backside images includes: segmenting the microscopic image using a coarse segmentation algorithm to obtain multiple chip backside images.

[0100] When the program code is executed on a programmable computer, the mobile terminal generally includes a processor, a processor-readable storage medium (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device. The memory is configured to store program code; the processor is configured to execute the chip backside detection method and / or grasping control method of the present invention according to instructions in the program code stored in the memory.

[0101] By way of example, and not limitation, readable media include readable storage media and communication media. Readable storage media stores information such as computer-readable instructions, data structures, program modules, or other data. Communication media generally embodies computer-readable instructions, data structures, program modules, or other data in the form of modulated data signals such as carrier waves or other transmission mechanisms, and includes any information delivery medium. Any combination of the above is also included within the scope of readable media.

[0102] In the specification provided herein, the algorithms and displays are not inherently related to any particular computer, virtual system, or other device. Various general-purpose systems can also be used with the examples of this invention. The required structure for constructing such systems is apparent from the above description. Furthermore, this invention is not directed to any particular programming language. It should be understood that the contents of the invention described herein can be implemented using various programming languages, and the above description of specific languages ​​is for the purpose of disclosing the best mode of implementation of the invention.

[0103] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0104] Similarly, it should be understood that, in order to streamline this disclosure and aid in understanding one or more of the various aspects of the invention, in the description of exemplary embodiments of the invention above, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof.

[0105] Those skilled in the art will understand that modules, units, or components of the devices disclosed in the examples herein can be arranged in the devices described in this embodiment, or alternatively, can be located in one or more devices different from the devices in this example. The modules in the foregoing examples can be combined into a single module or, in addition, can be divided into multiple sub-modules.

[0106] Those skilled in the art will understand that the modules in the device of the embodiment can be adaptively changed and placed in one or more devices different from that embodiment. Modules, units, or components in the embodiment can be combined into a single module, unit, or component, and further, they can be divided into multiple sub-modules, sub-units, or sub-components.

[0107] Furthermore, those skilled in the art will understand that although some embodiments described herein include certain features included in other embodiments but not others, combinations of features from different embodiments are meant to be within the scope of the invention and form different embodiments.

[0108] Furthermore, some of the embodiments described herein are methods or combinations of method elements that can be implemented by a processor of a computer system or by other means of performing the functions. Therefore, a processor having the necessary instructions for implementing the methods or method elements forms means for implementing the methods or method elements. Furthermore, the elements described herein in the apparatus embodiments are examples of means for implementing the functions performed by the objective elements for carrying out the invention.

[0109] As used herein, unless otherwise specified, the use of ordinal numbers such as “first,” “second,” “third,” etc., to describe ordinary objects merely indicates different instances of similar objects and is not intended to imply that the objects being described must have a given order in time, space, ordering, or any other manner.

[0110] Although the invention has been described with respect to a limited number of embodiments, those skilled in the art will understand from the foregoing description that other embodiments are conceivable within the scope of the invention described herein. Furthermore, it should be noted that the language used in this specification has been chosen primarily for readability and edibility purposes, and not for the purpose of explaining or limiting the subject matter of the invention.

Claims

1. A method for detecting the back side of a chip, executed in a computing device, comprising: A macroscopic image of the wafer is acquired, the wafer outline is extracted from the macroscopic image, and the coordinates of each microscopic imaging position of the wafer are calculated based on the wafer outline to obtain path planning coordinates, which include the coordinates of multiple microscopic imaging positions of the wafer. Controlling a microscopic imaging device to acquire microscopic images of a wafer based on the path planning coordinates includes: controlling the microscopic imaging device to acquire microscopic images of the wafer at corresponding positions based on the coordinates of each microscopic imaging position in the path planning coordinates, wherein the wafer includes multiple chips. The microscopic image is segmented to obtain multiple back-side images of the chips on the wafer, each corresponding to a different chip. Detection is performed based on the back image of each chip to determine the defect type and location on the back of each chip, and the back detection result of each chip is obtained; The microscopic image coordinates of each chip in the microscopic image are determined and saved. Based on the path planning coordinates and the microscopic image coordinates of each chip, the global coordinates of each chip on the wafer are determined. Based on the global coordinates of each chip and the backside inspection results of each chip, a wafer map image is generated. The wafer map image includes the chip area corresponding to each chip, and the chip area is filled with a color corresponding to the defect type of the chip.

2. The method of claim 1, wherein, Before obtaining a macroscopic image of the wafer, the following steps are also included: Control the first imaging device to acquire backlight images of the wafer; The angle between each chip on the wafer and the horizontal direction is determined based on the backlight image to determine the wafer offset angle. The offset angle is used to control the drive device to rotate the wafer in order to correct the wafer's position.

3. The method of claim 1, wherein, Also includes: Barcode information is obtained from the macroscopic image in order to identify the wafer using the barcode information.

4. The method of claim 3, wherein, Obtaining barcode information from the macroscopic image includes: The macroscopic image is input into the target detection model for processing to predict the target area where the barcode is located; The barcode in the target area is rotated and scaled, and the barcode is extracted. The barcode is decoded to obtain barcode information.

5. The method of claim 3, wherein, Also includes: The barcode information is associated with and stored with the wafer map image so that the corresponding wafer map image can be obtained based on the barcode information.

6. The method of any one of claims 1-5, wherein, Extracting the wafer profile from the macroscopic image includes: The wafer region in the macroscopic image is separated from the background region using a region growing algorithm to extract the wafer outline.

7. The method of any one of claims 1-5, wherein, The defect types include one or more of the following: back plating peeling, back plating discoloration, voids, scratches, and edge chipping.

8. The method of any one of claims 1-5, wherein, The microscopic image is segmented to obtain multiple images of the back of the chip, including: The microscopic image is segmented using a coarse segmentation algorithm to obtain multiple images of the back of the chip.

9. A chip backside inspection apparatus, residing in a computing device, adapted to perform the method as described in any one of claims 1-8, the apparatus comprising: The acquisition unit is adapted to acquire a macroscopic image of the wafer, and to perform path planning for the microscopic imaging position of the wafer based on the macroscopic image to obtain the path planning coordinates; The control unit is adapted to control the microscopic imaging device to acquire microscopic images of a wafer, which includes multiple chips, according to the path planning coordinates. A segmentation unit is adapted to segment the microscopic image to obtain multiple chip back images; The detection unit is adapted to perform detection based on the back image of each chip to determine the defect type and defect location on the back of each chip, and obtain the back detection result of each chip; The generation unit is adapted to generate a wafer map image based on the backside inspection results of all chips.

10. A computing device, comprising: At least one processor; as well as A memory storing program instructions, wherein the program instructions are configured to be executed by the at least one processor, the program instructions including instructions for performing the method as described in any one of claims 1-8.

11. A readable storage medium storing program instructions that, when read and executed by a computing device, cause the computing device to perform the method as described in any one of claims 1-8.

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