Calculators and related methods

Abstract

This application discloses a calculator and its related methods. The calculator is used to accelerate the calculation of 2 N Number theory transformation of 2D polynomials. The calculator includes a first coefficient memory, a second coefficient memory, a twitch factor memory, multiple processing units, and a data flow controller. The data flow controller is used to control the multiple processing units to access the addresses of the first and second coefficient memories and the twitch factor memory when the processing units perform multiple coefficient operations. In odd-numbered coefficient operations, 2 M Each processing unit executes 2 (N‑M‑1) The first calculation program reads coefficients from the first coefficient memory and performs modulo operations, and then executes 2... (N‑M‑1) The first write operation writes the output coefficients generated by the calculation to the second coefficient memory. In even-numbered coefficient operations, 2 M Each processing unit executes 2 (N‑M‑1) The second calculation program reads coefficients from the second coefficient memory and performs modulo operations, and executes 2 (N‑M‑1) The second write procedure writes the output coefficients generated by the operation into the first coefficient memory.

Description

Technical Field

[0001] This application relates to a calculator, and more particularly to a calculator capable of accelerating number theory transformations. Background Technology

[0002] Because artificial intelligence models, such as neural networks, can analyze massive amounts of data and extract meaningful information, they are beneficial to the development of many industries. However, running AI models often requires large amounts of expensive computing hardware resources, which not every company or research institution can afford. Therefore, to enable more industries to benefit from the data analysis capabilities of AI, server manufacturers have begun to offer remote computing services. In other words, users can upload the data they want to calculate or analyze to the cloud, and the server provider can remotely provide the computing service, ultimately sending the results back to the user.

[0003] However, user-provided data may be confidential, thus posing security risks for such services. To address this, homomorphic encryption has been introduced to encrypt data. Homomorphic encryption allows service providers to perform specific algebraic operations on the encrypted ciphertext, and the decrypted encrypted data will yield the same result as the plaintext data. In other words, service providers can perform specific operations, such as linear calculations, directly on the ciphertext without knowing its content, thereby enhancing security. However, the ciphertext generated by homomorphic encryption is often in polynomial format, leading to complex polynomial multiplication operations during computation, requiring more time and hardware resources for service providers. Therefore, improving the computational efficiency of homomorphic encryption has become a pressing issue in this field. Summary of the Invention

[0004] One of the purposes of this application is to disclose a calculator and related calculation methods to solve the above-mentioned problems.

[0005] One embodiment of this application provides a calculator for calculating 2 N The number theory transformation is performed on the 2D polynomial, where N is an integer greater than 1. The calculator includes a first coefficient memory, a second coefficient memory, and a 2D polynomial. M A processing unit and a data flow controller. The first coefficient memory is used to store the 2 during the initial period. N 2-dimensional polynomial N The rotation factor memory is used to store (2) coefficients. N -1) rotation factors. The 2 MEach processing unit performs N coefficient operations in parallel, where M is an integer greater than 1 and less than N. The dataflow controller controls the two... M Each processing unit accesses the addresses of the first coefficient memory, the second coefficient memory, and the rotation factor memory. In each odd-numbered coefficient operation, the 2... M Each processing unit executes 2 (N-M-1) The first calculation procedure reads 2 from the first coefficient memory. N A first coefficient and at least one first rotation factor read from the rotation factor memory and modulo operation performed, and the 2 M Each processing unit executes 2 (N-M-1) The first write to the program to generate 2 from the calculation N The first output coefficient is written to the second coefficient memory. In each even-numbered coefficient operation, the 2 M Each processing unit executes 2 (N-M-1) The second calculation procedure reads 2 from the second coefficient memory. N The second coefficient and at least one second rotation factor read from the rotation factor memory and modulo operation are performed, and the 2 M Each processing unit executes 2 (N-M-1) The second write program is used to process the 2 generated by the operation. N The second output coefficient is written into the first coefficient memory.

[0006] Another embodiment of this application provides a calculation method. The method includes, during an initial period, calculating the 2... N 2-dimensional polynomial N The coefficients are stored in the first coefficient memory, and the coefficients corresponding to the 2 are stored in the first coefficient memory. N (2)-dimensional polynomial N -1) twitch factors are stored in the twitch factor memory; during computation, 2 M Each processing unit performs N coefficient operations in parallel, including: in each odd-numbered coefficient operation, making the 2 M Each processing unit executes 2 (N-M-1) The first calculation procedure reads 2 from the first coefficient memory. N A first coefficient and at least one first rotation factor read from the rotation factor memory and perform modulo operation, and make the 2 M Each processing unit executes 2 (N-M-1) The first write to the program to generate 2 from the calculation N The first output coefficient is written into the second coefficient memory, and in each even-numbered coefficient operation, the 2... M Each processing unit executes 2 (N-M-1)The second calculation procedure reads 2 from the second coefficient memory. N A second coefficient and at least one second rotation factor read from the rotation factor memory and perform modulo operation, and make the 2 M Each processing unit executes 2 (N-M-1) The second write program is used to process the 2 generated by the operation. N A second output coefficient is written into the first coefficient memory. Here, N is an integer greater than 1, and M is an integer greater than 1 and less than N.

[0007] In summary, the calculator and calculation method of this application can perform modular arithmetic operations in number theory transformations in parallel through multiple processing units, and can access data in two coefficient memories in a specific order, thereby simplifying the wiring between the processing units and the coefficient memories and improving the overall computing performance. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of an embodiment of the calculator of this application.

[0009] Figure 2 This is an embodiment of the number theory transformation algorithm of this application.

[0010] Figure 3 This is a flowchart of an embodiment of the calculation method of this application.

[0011] Figure 4 yes Figure 1 The diagram showing the correspondence between the processing unit, the first coefficient memory, and the second coefficient memory.

[0012] Figures 5 to 8 These are schematic diagrams illustrating the process of the processing unit reading coefficients from the first coefficient storage block during the first calculation program, from the first to the fourth iteration.

[0013] Figures 9 to 12 These are schematic diagrams illustrating how the processing unit writes the output coefficients into the second coefficient storage block during the first to fourth write operations.

[0014] Figure 13 yes Figure 1 A schematic diagram of an embodiment of a rotation factor memory.

[0015] Figure 14 yes Figure 1 The timing diagram for the processing unit reading the spin factor from the spin factor memory.

[0016] Figure 15 yes Figure 1 A schematic diagram of an embodiment of the processing unit.

[0017] Figure 16 yes Figure 1A schematic diagram of an embodiment of the coefficient exchange unit. Detailed Implementation

[0018] The following disclosure provides various implementations or examples that can be used to achieve different features of this disclosure. Specific examples of components and configurations described below are for simplification purposes. It is understood that these descriptions are illustrative only and are not intended to limit the scope of this disclosure. For example, in the following description, forming a first feature on or over a second feature may include, in some embodiments, the first and second features being in direct contact with each other; and may also include, in some embodiments, additional components being formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, component symbols and / or reference numerals may be reused in multiple embodiments of this disclosure. Such reuse is for the purpose of brevity and clarity and does not in itself represent a relationship between the different embodiments and / or configurations discussed.

[0019] While the numerical ranges and parameters used to define the broader scope of this application are approximate values, the relevant values ​​in the specific embodiments have been presented as precisely as possible. However, any numerical value inevitably contains standard deviations due to individual test methods. Here, "approximately" generally means that the actual value is within plus or minus 10%, 5%, 1%, or 0.5% of a particular value or range. Alternatively, the term "approximately" may mean that the actual value falls within the acceptable standard error of the average, as determined by those skilled in the art to which this application pertains. It is understood that, except for experimental examples, or unless explicitly stated otherwise, all ranges, quantities, values, and percentages used herein (e.g., to describe material usage, duration, temperature, operating conditions, quantity ratios, and the like) are modified with "approximately". Therefore, unless otherwise stated, the numerical parameters disclosed in this specification and the accompanying claims are approximate values ​​and are subject to change as needed. At a minimum, these numerical parameters should be understood as the indicated significant digits and values ​​obtained by applying general rounding. In this context, a range of values ​​is expressed as a distance from one endpoint to the other or between the two endpoints; unless otherwise stated, all ranges of values ​​herein include the endpoints.

[0020] Figure 1 This is a schematic diagram of an embodiment of the calculator 100 of this application. The calculator 100 can be used to calculate 2 N A number-theoretic transformation is performed on a polynomial P1 of dimension N, where N is an integer greater than 1. Calculator 100 includes a first coefficient memory 110, a second coefficient memory 120, a rotation factor memory 130, and a 2... M A processing unit 140 and a data flow controller 150.

[0021] The first coefficient memory 110 can store 2 during the initial period. N 2-dimensional polynomial P1 N The coefficients P[0] to P[2] are given. N -1], and can store the data output by the processing unit 140 during the operation. The second coefficient memory 120 can store the data output by the processing unit 140 during the operation, while the rotation factor memory 130 can store the (2) required for number theory transformation of polynomial P1. N -1) rotation factors ω[1] to ω[2] N -1]. Generally, the rotation factor ω[1] to ω[2] N -1] can be calculated in advance based on the algorithm of number theory transformation.

[0022] In addition, 2 M Each processing unit 140 can perform modular arithmetic operations required for number theory transformations based on the coefficients stored in the first coefficient memory 110 or the second coefficient memory 120 and the rotation factor stored in the rotation factor memory 130, while the data flow controller 150 can control 2 M Each processing unit 140 accesses the addresses of the first coefficient memory 110, the second coefficient memory 120, and the rotation factor memory 130 to ensure that 2 M Each processing unit 140 is able to obtain the correct coefficients for calculation.

[0023] In this embodiment, the calculator 100 can perform number theory transformations using an iterative approach, for example, by using the algorithm proposed by Cooley and Tukey. Figure 2 This is an embodiment of the number-theoretic transformation algorithm of this application. Figure 2 In this context, q is the predetermined modulus. Based on... Figure 2 The algorithm, for 2 N For a polynomial P1 of dimension 1, the first for loop will execute N times, meaning that the calculator 100 will perform N coefficient operations to continuously update the coefficients of polynomial P1. In the second for loop, the calculator 100 will first determine the twist factor S required for the next modulo operation and the number of modulo operations to be performed using the twist factor. Then, in the third for loop, the calculator 100 will select the corresponding two coefficients and the twist factor S determined in the second for loop to perform modulo operations to update the coefficients in polynomial P1.

[0024] For example, in the first coefficient operation, the rotation factor ω[1] will be used to perform 2 (N-1) The second modulus operation, and in the second coefficient operation, the rotation factor ω[2] will be used to perform 2. (N-2)The modulo operation will be performed twice, and the rotation factor ω[3] will be used to perform 2 (N-2) The modulus operation is performed several times, and so on. In this case, in each coefficient operation, the calculator 100 will adjust the 2 according to the corresponding rotation factor. N Perform modulo operations on the input coefficients and produce 2. N Each output coefficient.

[0025] In this embodiment, 2 M Each processing unit 140 can perform modulo operations in N coefficient operations in parallel, for example... Figure 2 The calculations within the third-level for loop. That is, each processing unit 140 reads two coefficients and one twitch factor for modulo operations each time. Therefore, in each coefficient operation, 2... M Each processing unit 140 will execute 2 in parallel. (N-M-1) This calculation procedure completes the calculation for all 2. N Modular operation of coefficients.

[0026] Since the total number of coefficients read and generated in each coefficient operation is fixed (2) N Therefore, in this embodiment, the first coefficient memory 110 and the second coefficient memory 120 may each have enough to store 2 (units), so that they can store 2 (units). N The data flow controller 150 can alternately cause the processing unit 140 to read coefficients from either the first coefficient memory 110 or the second coefficient memory 120, and write the calculation results to the other of the first coefficient memory 110 and the second coefficient memory 120. For example, in the first coefficient calculation operation, the data flow controller 150 can control the processing unit 140 to read 2 coefficients from the first coefficient memory 110. N The coefficients P[0] to P[2] of the polynomial P1 N -1], and after the calculation, the control processing unit 140 stores the calculation result in the second coefficient memory 120. Next, in the second coefficient calculation operation, the data flow controller 150 can control the processing unit 140 to read the previously calculated coefficients from the second coefficient memory 120, and after the calculation, the control processing unit 140 stores the calculation result in the first coefficient memory 110 for use in the next coefficient calculation operation. That is, in odd-numbered coefficient calculation operations, the data flow controller 150 can control the processing unit 140 to read coefficients from the first coefficient memory 110 for calculation, and store the calculation result in the second coefficient memory 120; while in even-numbered coefficient calculation operations, the data flow controller 150 can control the processing unit 140 to read coefficients from the second coefficient memory 120 for calculation, and store the calculation result in the first coefficient memory 110.

[0027] Furthermore, since the algorithm for number-theoretic transformations is fixed, the order in which the coefficients of each term are accessed remains fixed and known when performing number-theoretic transformations on different polynomials. In this case, by appropriately arranging the reading and writing order of the coefficients, it is possible to read the first coefficient memory 110 from the same address and write the output coefficients to the same address in the second coefficient memory 120 in each odd-numbered coefficient operation. Similarly, in each even-numbered coefficient operation, the second coefficient memory 120 can also be read from the same address and the output coefficients written to the same address in the first coefficient memory 110. This simplifies the process. M Each processing unit 140 performs access operations on the first coefficient memory 110 and the second coefficient memory 120, thereby simplifying the operation of the calculator 100 and improving efficiency. M Performance when 140 processing units perform operations in parallel.

[0028] Figure 3 This is a flowchart of an embodiment of the calculation method 200 of this application. In this embodiment, the calculation method 200 can be applied to the calculator 100 and may include steps S210 to S290.

[0029] In this embodiment, steps S210 and S220 can be executed during initialization before the operation. In step S210, 2 N 2-dimensional polynomial P1 N The coefficients P[0] to P[2] are given. N -1] can be stored in the first coefficient memory 110, and in step S220, corresponding to 2 N (2) of the polynomial P1 N -1) rotation factors ω[1] to ω[2] N -1] can then be stored in the rotation factor memory 130.

[0030] During the calculation, calculator 100 will utilize 2 M Each processing unit executes steps S240 to S280 to complete N coefficient calculation operations, and after completing N coefficient calculation operations, proceeds to step S290 to end the calculation.

[0031] In step S240, the calculator 100 can first determine whether the coefficient operation currently being performed is an odd number of times (e.g., the first, third, or fifth time) or an even number of times (e.g., the second, fourth, or sixth time). In step S240, if the calculator 100 determines that the coefficient operation currently being performed is an odd number of times, it can continue to execute steps S250 and S260; if the calculator 100 determines that the coefficient operation currently being performed is an even number of times, it can continue to execute steps S270 and S280.

[0032] like Figure 3 As shown, in each odd-numbered coefficient operation, 2 M Each processing unit can execute 2 in parallel in step S250. (N-M-1) The first calculation program reads 2 from the first coefficient memory 110. N The first coefficient and spin factor memory 130 reads at least one first spin factor and performs modulo arithmetic, and can execute 2 in parallel with step S260. (N-M-1) The first write to the program to generate 2 from the calculation N The first output coefficient is written to the second coefficient memory 120. Conversely, in each even-numbered coefficient operation, 2 M Each processing unit can execute 2 in parallel in step S270. (N-M-1) The second calculation procedure reads 2 from the second coefficient memory 120. N The second coefficient and spin factor memory 130 reads at least one second spin factor and performs modulo arithmetic, and can execute 2 in parallel with step S280. (N-M-1) The second write program is used to process the 2 generated by the operation. N The second output coefficient is written into the first coefficient memory 110.

[0033] According to the algorithm of number theory transformation, the first calculation procedure in the odd-order coefficient operation and the second calculation procedure in the even-order coefficient operation essentially include the same operations, the only difference being the coefficients and rotation factors read. Furthermore, each time the first calculation procedure in the odd-order coefficient operation or the second calculation procedure in the even-order coefficient operation is executed, each processing unit 140 performs modulo operations based on two coefficients and one rotation factor to produce two output coefficients. In this case, to allow 2 M Each processing unit can effectively perform parallel operations, and the first coefficient memory 110 may include 2 (M+1) There are 1 first coefficient storage block, and each first coefficient storage block can store 2 (N-M-1) There are 120 coefficients. Similarly, the second coefficient memory 120 may also include 2 coefficients. (M+1) There are two second coefficient storage blocks, and each second coefficient storage block can store 2 (N-M-1)Each coefficient is represented by a number of coefficients. In this way, each processing unit 140 can read the required coefficients from the corresponding two first coefficient storage blocks or two second coefficient storage blocks each time the first calculation program or the second calculation program is performed.

[0034] Figure 4 This is a diagram showing the correspondence between the processing unit 140, the first coefficient memory 110, and the second coefficient memory 120 of this application. Figure 4 In this embodiment, N can be, for example, 5, and M can be, for example, 2. That is, the calculator 100 can include four processing units 1401, 1402, 1403, and 1404, and can be used to perform number theory transformations on a 32-dimensional polynomial P1. In this case, the first coefficient memory 110 can include eight first coefficient storage blocks 1121, 1122, ..., 1128, and each first coefficient storage block 1121 to 1128 can store four coefficients; therefore, in step S210, each first coefficient storage block 1121 to 1128 will be able to store four of the 32 coefficients of the 32-dimensional polynomial P1. Similarly, the second coefficient memory 120 can include eight second coefficient storage blocks 1221, 1222, ..., 1228.

[0035] In this case, in each first calculation procedure of step S250, each processing unit 1401 to 1404 reads one first coefficient from each of the two first coefficient storage blocks 1121 to 1128, and in each second calculation procedure of step S270, each processing unit 1401 to 1404 reads one first coefficient from each of the two second coefficient storage blocks 1221 to 1228.

[0036] Furthermore, in each of the first write procedures in step S260, each processing unit 1401 to 1404 may also write the two first output coefficients generated by the operation to the two second coefficient storage blocks in the second coefficient storage blocks 1221 to 1228, and in each of the second write procedures in step S280, each processing unit 1401 to 1404 may write the two second output coefficients generated by the operation to the two first coefficient storage blocks 1121 to 1128.

[0037] In some embodiments, to further simplify the access operations of processing units 1401 to 1404 to the first coefficient memory 110 and the second coefficient memory 120, the calculator 100 can store the 32 coefficients P[0] to P

[31] of the polynomial P1 and the output coefficients generated by each coefficient operation in a specific order. That is, in each first calculation program in step S250, each processing unit 1401 to 1404 can read two first coefficients from the corresponding two first coefficient memory blocks according to the same address, and in each first write program in step S260, each processing unit 1401 to 1404 can also write two first output coefficients to the two second coefficient memory blocks according to the same address. Similarly, in each second calculation procedure in step S270, each processing unit 1401 to 1404 can read two second coefficients from the corresponding two second coefficient storage blocks according to the same address, and in each second write procedure in step S280, each processing unit 1401 to 1404 can also write two second output coefficients to the two first coefficient storage blocks according to the same address.

[0038] Figures 5 to 8 These are schematic diagrams showing the reading of coefficients from the first coefficient storage blocks 1121 to 1128 by processing units 1401 to 1404 in the first calculation program of the first to fourth steps of step S250.

[0039] like Figure 5 As shown, when the first calculation program is executed for the first time, the processing unit 1401 can read coefficients P[0] and P

[16] from the address A

[00] of the first coefficient storage blocks 1121 and 1125 respectively; the processing unit 1402 can read coefficients P[4] and P

[20] from the address A

[00] of the first coefficient storage blocks 1122 and 1126 respectively; the processing unit 1403 can read coefficients P[8] and P

[24] from the address A

[00] of the first coefficient storage blocks 1123 and 1127 respectively; and the processing unit 1404 can read coefficients P

[12] and P

[28] from the address A

[00] of the first coefficient storage blocks 1124 and 1128 respectively.

[0040] like Figure 6As shown, during the second execution of the first calculation program, processing unit 1401 can read coefficients P[2] and P

[18] from address A

[10] of the first coefficient storage blocks 1121 and 1125 respectively; processing unit 1402 can read coefficients P[6] and P

[22] from address A

[10] of the first coefficient storage blocks 1122 and 1126 respectively; processing unit 1403 can read coefficients P

[10] and P

[26] from address A

[10] of the first coefficient storage blocks 1123 and 1127 respectively; and processing unit 1404 can read coefficients P

[14] and P

[30] from address A

[10] of the first coefficient storage blocks 1124 and 1128 respectively.

[0041] like Figure 7 As shown, during the third execution of the first calculation program, processing unit 1401 can read coefficients P[1] and P

[17] from address A

[01] of the first coefficient storage blocks 1121 and 1125 respectively; processing unit 1402 can read coefficients P[5] and P

[21] from address A

[01] of the first coefficient storage blocks 1122 and 1126 respectively; processing unit 1403 can read coefficients P[9] and P

[25] from address A

[01] of the first coefficient storage blocks 1123 and 1127 respectively; and processing unit 1404 can read coefficients P

[13] and P

[29] from address A

[01] of the first coefficient storage blocks 1124 and 1128 respectively.

[0042] like Figure 8 As shown, during the fourth execution of the first calculation program, processing unit 1401 can read coefficients P[3] and P

[19] from address A

[11] of the first coefficient storage blocks 1121 and 1125 respectively; processing unit 1402 can read coefficients P[7] and P

[23] from address A

[11] of the first coefficient storage blocks 1122 and 1126 respectively; processing unit 1403 can read coefficients P

[11] and P

[27] from address A

[11] of the first coefficient storage blocks 1123 and 1127 respectively; and processing unit 1404 can read coefficients P

[15] and P

[31] from address A

[11] of the first coefficient storage blocks 1124 and 1128 respectively.

[0043] In some embodiments, during the second calculation process from the first to the fourth iteration of step S270, processing units 1401 to 1404 may also perform calculations according to... Figures 5 to 8 The addresses and order shown indicate the coefficients to be read from the second coefficient storage blocks 1221 to 1228.

[0044] Figures 9 to 12 These are schematic diagrams showing how processing units 1401 to 1404 write the output coefficients into the second coefficient storage blocks 1221 to 1228 during the first to fourth write operations in step S260.

[0045] like Figure 9 As shown, when the first write program is executed for the first time, the processing unit 1401 can write the first output coefficients C[0] and C[4] generated by the previous operation to the address A

[00] of the second coefficient storage blocks 1221 and 1222 respectively. The processing unit 1402 can write the first output coefficients C[8] and C

[12] generated by the previous operation to the address A

[00] of the second coefficient storage blocks 1223 and 1224 respectively. The processing unit 1403 can write the first output coefficients C

[16] and C

[20] generated by the previous operation to the address A

[00] of the second coefficient storage blocks 1225 and 1226 respectively. The processing unit 1404 can write the first output coefficients C

[24] and C

[28] generated by the previous operation to the address A

[00] of the second coefficient storage blocks 1227 and 1228 respectively.

[0046] like Figure 10 As shown, when the first write program is executed for the second time, the processing unit 1401 can write the first output coefficients C[1] and C[5] generated by the previous operation to the address A

[01] of the second coefficient storage blocks 1221 and 1222 respectively. The processing unit 1402 can write the first output coefficients C[9] and C

[13] generated by the previous operation to the address A

[01] of the second coefficient storage blocks 1223 and 1224 respectively. The processing unit 1403 can write the first output coefficients C

[17] and C

[21] generated by the previous operation to the address A

[01] of the second coefficient storage blocks 1225 and 1226 respectively. The processing unit 1404 can write the first output coefficients C

[25] and C

[29] generated by the previous operation to the address A

[01] of the second coefficient storage blocks 1227 and 1228 respectively.

[0047] like Figure 11 As shown, when the first write procedure is executed for the third time, the processing unit 1401 can write the first output coefficients C[2] and C[6] generated by the previous operation to the address A

[10] of the second coefficient storage blocks 1221 and 1222 respectively; the processing unit 1402 can write the first output coefficients C

[10] and C

[14] generated by the previous operation to the address A

[10] of the second coefficient storage blocks 1223 and 1224 respectively; the processing unit 1403 can write the first output coefficients C

[18] and C

[22] generated by the previous operation to the address A

[10] of the second coefficient storage blocks 1225 and 1226 respectively; and the processing unit 1404 can write the first output coefficients C

[26] and C

[30] generated by the previous operation to the address A

[10] of the second coefficient storage blocks 1227 and 1228 respectively.

[0048] like Figure 12As shown, during the fourth execution of the first write procedure, processing unit 1401 can write the first output coefficients C[3] and C[7] generated by the previous operation to the address A

[11] of the second coefficient storage blocks 1221 and 1222 respectively; processing unit 1402 can write the first output coefficients C

[11] and C

[15] generated by the previous operation to the address A

[11] of the second coefficient storage blocks 1223 and 1224 respectively; processing unit 1403 can write the first output coefficients C

[19] and C

[23] generated by the previous operation to the address A

[11] of the second coefficient storage blocks 1225 and 1226 respectively; and processing unit 1404 can write the first output coefficients C

[27] and C

[31] generated by the previous operation to the address A

[11] of the second coefficient storage blocks 1227 and 1228 respectively.

[0049] In some embodiments, during the first to fourth second write operations in steps S280, processing units 1401 to 1404 may also perform operations according to... Figures 9 to 12 The addresses and order shown indicate that the two second output coefficients are written to the first coefficient storage blocks 1121 to 1128.

[0050] In addition, such as Figures 5 to 12 As shown, in this embodiment, each processing unit 1401 to 1404 accesses two first coefficient storage blocks and two second coefficient storage blocks in a fixed manner. For example, in each first calculation program, processing unit 1401 reads coefficients from first coefficient storage blocks 1121 and 1125 in a fixed manner, and in each first write program, writes the output coefficients to second coefficient storage blocks 1221 and 1222 in a fixed manner. Similarly, processing unit 1401 can read coefficients from second coefficient storage blocks 1221 and 1225 in a fixed manner in each second calculation program, and write the output coefficients to first coefficient storage blocks 1121 and 1122 in a fixed manner in each second write program. In this case, each processing unit 1401 to 1404 only needs to be coupled to a few specific coefficient storage blocks, instead of being coupled to all coefficient storage blocks 1121 to 1128 and 1221 to 1228, thereby simplifying the internal circuit complexity of the calculator 100.

[0051] Furthermore, such as Figures 5 to 12As shown, in each first calculation program, processing units 1401 to 1404 read the first coefficient storage blocks 1121 to 1128 based on the same address, and in each first write program, processing units 1401 to 1404 read the second coefficient storage blocks 1221 to 1228 based on the same address. In this case, the first coefficient storage blocks 1121 to 1128 can receive the same address signal, and the second coefficient storage blocks 1221 to 1228 can also receive the same address signal. In some embodiments, the address terminals of the first coefficient storage blocks 1121 to 1128 can be coupled to the same address line, and the address terminals of the second coefficient storage blocks 1221 to 1228 can also be coupled to the same address line, thereby further simplifying the internal circuitry complexity of the calculator 100.

[0052] In this embodiment, the calculator 100 can access the first coefficient memory 110 and the second coefficient memory 120 in a specific order to simplify the process. M In addition to simplifying the connection lines between the processing unit 140 and the first coefficient memory 110 and the second coefficient memory 120, it can also store the rotation factors ω[1] to ω[2] required in the number theory transformation algorithm in a specific order. N -1].

[0053] in accordance with Figure 2 The number-theoretic transformation algorithm shown uses twice the number of rotation factors in each coefficient operation compared to the previous operation. However, since the calculator 100 can only utilize a maximum of 2 rotation factors at a time... M Each processing unit 140 performs modular arithmetic in parallel, meaning that the calculator 100 will only use a maximum of 2 units at a time. M There are 10 rotation factors. Therefore, in this embodiment, the rotation factor memory 130 may include the same number of rotation factor storage blocks as the processing unit 140.

[0054] Furthermore, when the number of rotation factors required for this coefficient operation is not greater than the total number of calculations required for each coefficient operation, 2... (N-M-1) At that time, 2 M Each processing unit 140 can use a single rotation factor in each first or second calculation procedure, while different rotation factors can be used in different first or second calculation procedures. In this case, 2 M Each processing unit 140 can still read the corresponding rotation factor from the same rotation factor storage block.

[0055] However, when the number of rotation factors required for coefficient operations exceeds the total number of calculations required for each coefficient operation,(N-M-1) In each calculation process, different processing units 140 may simultaneously need to use different rotation factors to perform modular arithmetic to maintain the efficiency of parallel operations. In this case, with each rotation factor storage block having only one read / write port, 2 M Each processing unit 140 must read the required rotation factor from different rotation factor storage blocks.

[0056] In this case, in order to maintain the parallel operation performance of the processing unit 140 and the hardware utilization of the rotation factor memory 130, the rotation factor memory 130 may have 2 M One rotation factor storage block, including storable (2) (N-M) -1+2 (N-M-1) The first twitch factor storage block with (×M) twitch factors, and 2 (M-i) One is used for storage (2) (N-M-1) The storage block for the i-th twiddle factor of (×i) twiddle factors, where i is any integer from 1 to M. Thus, in the first (NM) coefficient operations of N coefficient operations, 2 M Each processing unit 140 can read at least one rotation factor from the first rotation factor storage block, and in the k-th coefficient operation from the end of the N coefficient operation, 2 M Each processing unit 140 can be self-contained from 2 M 2 in each rotation factor storage block (M-K+1) Read 2 from each rotation factor storage block (N-K) There are 1 to M selection factors, where k is any integer from 1 to M.

[0057] Figure 13 This is a schematic diagram of an embodiment of the rotation factor memory 130 of this application. Figure 14 This is a timing diagram of the processing units 1401 to 1404 of this application reading the spin factor from the spin factor memory 130. Figure 13 In the embodiment, M is 2 and N is 5. Therefore, the rotation factor memory 130 may include four rotation factor storage blocks 1321, 1322, 1323 and 1324. The first rotation factor storage block 1321 can be used to store 15 rotation factors, the second rotation factor storage block 1322 can be used to store 8 rotation factors, and the third rotation factor storage blocks 1323 and 1324 can be used to store 4 rotation factors.

[0058] In this case, such as Figure 14As shown, in the first coefficient operation SA, since only one rotation factor is needed, in the four first calculation procedures PD1A, PD2A, PD3A and PD4A of the first coefficient operation SA, the processing units 1401 to 1404 can read the rotation factor ω from the rotation factor storage block 1321 [1].

[0059] In the second coefficient operation SB, since only two rotation factors are needed, processing units 1401 to 1404 can read rotation factors ω from rotation factor storage block 1321 in the four first calculation programs PD1B and PD2B of the second coefficient operation SB[2]. In the first calculation programs PD3B and PD4B, processing units 1401 to 1404 can read rotation factors ω from rotation factor storage block 1321[3]. Similarly, in the four first calculation programs PD1C, PD2C, PD3C and PD4C of the third coefficient operation SC, processing units 1401 to 1404 can sequentially read rotation factors ω[4], ω[5], ω[6] and ω[7] from rotation factor storage block 1321.

[0060] Next, in the fourth coefficient operation SD, the number of rotation factors required exceeds the total number of calculations required for each coefficient operation. (N-M-1) When the number of rotation factors required is greater than 4, in the four first calculation procedures PD1D, PD2D, PD3D and PD4D of the fourth coefficient operation SD, the processing units 1401 and 1403 can sequentially read rotation factors ω[8], ω[9], ω

[10] and ω

[11] from the rotation factor storage block 1321, while the processing units 1402 and 1404 can sequentially read rotation factors ω

[12] , ω

[13] , ω

[14] and ω

[15] from the rotation factor storage block 1322.

[0061] Finally, in the four first calculation procedures PD1E, PD2E, PD3E and PD4E of the fifth coefficient operation SE, the processing unit 1401 can sequentially read the rotation factors ω

[16] , ω

[17] , ω

[18] and ω

[19] from the rotation factor storage block 1321, the processing unit 1402 can sequentially read the rotation factors ω

[20] , ω

[21] , ω

[22] and ω

[23] from the rotation factor storage block 1322, the processing unit 1403 can sequentially read the rotation factors ω

[24] , ω

[25] , ω

[26] and ω

[27] from the rotation factor storage block 1323, and the processing unit 1404 can sequentially read the rotation factors ω

[28] , ω

[29] , ω

[30] and ω

[31] from the rotation factor storage block 1324.

[0062] In this way, the parallel operation performance of the processing unit 140 can be maintained, and the unnecessary increase in the capacity of the rotation factor memory 130 can be avoided.

[0063] Furthermore, in each calculation procedure in steps S250 and 270, each processing unit 1401 to 1404 will execute as follows: Figure 2 The calculations performed within the third-level for loop. Figure 15 This is a schematic diagram of an embodiment of the processing unit 1401 of this application. In this embodiment, processing units 1402 to 1404 may have the same structure as processing unit 1401 and may operate according to the same principle.

[0064] like Figure 15 As shown, the processing unit 1401 may include a modular multiplication unit 142, a modular addition unit 144, a modular subtraction unit 146, and a coefficient exchange unit 148. In this embodiment, when the processing unit 1401 executes the first calculation program, it can read two first coefficients from the first coefficient storage blocks 1121 and 1125 in the first coefficient memory 110, and read the corresponding first rotation factor from the rotation factor memory 130, and then use the modular multiplication unit 142, the modular addition unit 144, and the modular subtraction unit 146 to execute the calculation program. Figure 2 Modulo operations within the third nested for loop.

[0065] For example, in the first calculation procedure of the first coefficient operation, the processing unit 1401 can read two first coefficients P[0] and P

[16] from the first coefficient storage blocks 1121 and 1125, and can read the corresponding first rotation factor ω[1] from the rotation factor memory 130. The modular multiplication unit 142 can perform modular multiplication on the first coefficient P

[16] and the first rotation factor ω[1] according to the preset modulus q to generate the first value V. Then, the modular addition unit 144 can perform modular addition on the first coefficient P[0] and the first value V according to the preset modulus q to generate the first coefficient to be rounded P'

[16] , and the modular subtraction unit 146 can perform modular subtraction on the first coefficient P[0] and the first value V according to the preset modulus to generate the second coefficient to be rounded P'[0].

[0066] In this embodiment, in order to maintain the storage order of the coefficients in the second coefficient memory 120 so that in the calculation program of the second coefficient operation, the processing units 1401 to 1404 can still follow the order as follows: Figures 5 to 8The coefficients are read from the second coefficient memory 120 according to the address and order shown. The processing unit 1401 does not directly execute the first write program and write the coefficients P'[0] and P'

[16] directly into the second coefficient memory 120 after generating the coefficients to be adjusted P'[0] and P'

[16] . Instead, the processing unit 1401 can reorder the output order of the multiple first coefficients to be adjusted generated by the modulo addition unit 144 and the multiple second coefficients to be adjusted generated by the modulo subtraction unit 146 through the coefficient exchange unit 148 to execute the subsequent multiple first write programs.

[0067] Figure 16 This is a schematic diagram of an embodiment of the coefficient switching unit 148 of this application. The coefficient switching unit 148 includes registers REG1, REG2, REG3, and REG4, and multiplexers MUX1 and MUX2. Register REG1 has an input terminal and an output terminal, and the input terminal of the first register REG1 is coupled to the modulus addition unit 144. Register REG2 has an input terminal and an output terminal, and the input terminal of register REG2 is coupled to the modulus subtraction unit 146. Register REG3 has an input terminal and an output terminal, and the input terminal of register REG3 is coupled to the output terminal of register REG2. Multiplexer MUX1 has a first input terminal, a second input terminal, and an output terminal. The first input terminal of multiplexer MUX1 is coupled to the output terminal of register REG1, and the second input terminal of multiplexer MUX1 is coupled to the output terminal of register REG3. Register REG4 has an input terminal and an output terminal. The input terminal of register REG4 is coupled to the output terminal of multiplexer MUX1, and the output terminal of register REG4 is used to output the first calibrated output coefficient. Multiplexer MUX2 has a first input terminal, a second input terminal, and an output terminal. The first input terminal of multiplexer MUX2 is coupled to the output terminal of register REG1, the second input terminal of multiplexer MUX2 is coupled to the output terminal of register REG3, and the output terminal of multiplexer MUX2 is used to output the second calibrated output coefficient.

[0068] In this embodiment, multiplexer MUX1 alternately outputs the data received at its first and second input terminals. Furthermore, when multiplexer MUX1 outputs the data received at its first input terminal, multiplexer MUX2 outputs the data received at its second input terminal; conversely, when multiplexer MUX1 outputs the data received at its second input terminal, multiplexer MUX2 outputs the data received at its first input terminal.

[0069] In this case, the coefficient exchange unit 148 will alternately output the coefficients to be rounded obtained by the processing unit 1401 in the calculation program. For example, if the processing unit 1401, in the four first calculation programs of the first coefficient operation, performs the calculation as follows: Figures 5 to 8 The order shown generates unbalanced coefficients P'[0] and P'

[16] based on coefficients P[0] and P

[16] , unbalanced coefficients P'[2] and P'

[18] based on coefficients P[2] and P

[18] , unbalanced coefficients P'[1] and P'

[17] based on coefficients P[1] and P

[17] , and unbalanced coefficients P'[3] and P'

[19] based on coefficients P[3] and P

[19] . After the coefficient exchange unit 148 reorders the output order of the unbalanced coefficients generated in the calculation program, the processing unit 1401 will write the first four times in the first coefficient operation into the program, such as... Figures 9 to 12 In the order shown, the coefficients to be rounded, P'[0] and P'[2], are written as the first output coefficients C[0] and C[4] to the second coefficient storage blocks 1221 and 1222, the coefficients to be rounded, P'

[16] and P'

[18] , are written as the first output coefficients C[1] and C[5] to the second coefficient storage blocks 1221 and 1222, the coefficients to be rounded, P'[1] and P'[3], are written as the first output coefficients C[2] and C[6] to the second coefficient storage blocks 1221 and 1222, and the coefficients to be rounded, P'

[17] and P'

[19] , are written as the first output coefficients C[3] and C[7] to the second coefficient storage blocks 1221 and 1222.

[0070] In this way, in the second coefficient calculation operation, the processing unit 1401 can also follow the same method. Figures 5 to 8 The addresses and order shown indicate that the coefficients required for modulo operations are obtained from the second coefficient storage blocks 1221 and 1225. In other words, processing units 1401 to 1404 can rearrange the order of the output coefficients using the coefficient exchange unit 148, so that in each calculation procedure, processing units 1401 to 1404 can retrieve the coefficients according to... Figures 5 to 8 The addresses and sequences shown are used to retrieve the corresponding coefficients from the first coefficient memory 110 or the second coefficient memory 120 for modulo-digital operations, and based on... Figures 9 to 12 The addresses and order shown are used to write to the first coefficient memory 110 or the second coefficient memory 120. However, this application is not limited thereto; in some other embodiments, processing units 1401 to 1404 may also write to the first coefficient memory 110 or the second coefficient memory 120 according to the given addresses and order. Figures 5 to 12Different orders can be used to read from or write to the first coefficient memory 110 or the second coefficient memory 120, and the design of the coefficient exchange unit 148 can be changed accordingly so that the processing units 1401 to 1404 can access the first coefficient memory 110 or the second coefficient memory 120 according to the same order and address in each coefficient operation.

[0071] In summary, the calculator and calculation method of this application can perform modular arithmetic operations in number theory transformations in parallel through multiple processing units, and can access data in two coefficient memories in a specific order, thereby simplifying the wiring between the processing units and the coefficient memories and improving the overall computing performance.

[0072] The foregoing description briefly outlines the features of certain embodiments of this application, enabling those skilled in the art to more fully understand the various forms of this disclosure. Those skilled in the art will readily recognize that this disclosure serves as a basis for designing or modifying other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should understand that these equivalent embodiments remain within the spirit and scope of this disclosure, and various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A calculator, characterized in that, Used for 2 N The calculator performs number-theoretic transformations on a 2D polynomial, where N is an integer greater than 1. A first coefficient memory is used to store the 2 during the initial period. N 2-dimensional polynomial N One coefficient; Second coefficient memory; Rotation factor memory, used to store (2 N -1) rotation factors; 2 M Each processing unit performs N coefficient operations in parallel, where M is an integer greater than 1 and less than N; and Data flow controller, used to control the 2 M Each processing unit accesses the addresses of the first coefficient memory, the second coefficient memory, and the rotation factor memory; in: In each odd-numbered coefficient operation: The 2 M Each processing unit executes 2 (N-M-1) The first calculation procedure reads 2 from the first coefficient memory. N A first coefficient and at least one first rotation factor read from the rotation factor memory and perform modular arithmetic; and The 2 M Each processing unit executes 2 (N-M-1) The first write to the program to generate 2 from the calculation N The first output coefficient is written into the second coefficient memory; and In each even-numbered coefficient operation: The 2 M Each processing unit executes 2 (N-M-1) The second calculation procedure reads 2 from the second coefficient memory. N A second coefficient and at least one second rotation factor read from the rotation factor memory and performed modular arithmetic; and The 2 M Each processing unit executes 2 (N-M-1) The second write program is used to process the 2 generated by the operation. N The second output coefficient is written into the first coefficient memory.

2. The calculator as described in claim 1, characterized in that: The first coefficient memory includes 2 (M+1) Each first coefficient storage block is used to store 2, and each second coefficient storage block is used to store 2. (N -M-1) One coefficient; and The second coefficient memory includes 2 (M+1) Each of the two second coefficient storage blocks is used to store 2. (N -M-1) Each coefficient.

3. The calculator as described in claim 2, characterized in that: In each first calculation procedure, each processing unit is from the 2 (M+1) Each of the two first coefficient storage blocks in the first coefficient storage block reads one first coefficient; and In each second calculation procedure, each processing unit is from the 2 (M+1) Each of the two second coefficient storage blocks in the second coefficient storage block reads one second coefficient.

4. The calculator as described in claim 3, characterized in that: In each first calculation procedure, each processing unit reads one of the first coefficients from each of the two first coefficient storage blocks according to the same address; and In each second calculation procedure, each processing unit reads one second coefficient from each of the two second coefficient storage blocks according to the same address.

5. The calculator as described in claim 2, characterized in that: In each first write procedure, each processing unit writes the two first output coefficients generated by the operation to the 2 (M+1) Two second coefficient storage blocks in one second coefficient storage block; and In each second calculation procedure, each processing unit writes the two second output coefficients generated by the calculation to the 2 (M+1) Two first coefficient storage blocks in a first coefficient storage block.

6. The calculator as described in claim 5, characterized in that: In each first calculation procedure, each processing unit writes the two first output coefficients to the two second coefficient storage blocks according to the same address; and In each second calculation procedure, each processing unit writes the two second output coefficients to the two first coefficient storage blocks according to the same address.

7. The calculator as described in claim 1, characterized in that: In each first calculation procedure, each processing unit performs modulo operations based on two first coefficients read from the first coefficient memory and a first rotation factor read from the rotation factor memory; and In each second calculation procedure, each processing unit performs modulo operations based on two second coefficients read from the second coefficient memory and a second rotation factor read from the rotation factor memory.

8. The calculator as described in claim 7, characterized in that, The 2 M The first processing unit in the processing units includes: Modular multiplication unit, used to perform modular multiplication of one of the two first coefficients with the first rotation factor according to a preset modulus to generate a first value; Modular addition unit, used to perform modular addition operation on the other of the two first coefficients and the first value according to the preset modulus to generate a first coefficient to be rounded; Modulus subtraction unit, configured to perform a modulus subtraction operation on the other of the two first coefficients and the first value according to the preset modulus to generate a second coefficient to be rounded; and The coefficient exchange unit is used to reorder the output order of the plurality of first coefficients to be adjusted generated by the modulus addition unit and the plurality of second coefficients to be adjusted generated by the modulus subtraction unit in order to execute the subsequent plurality of first write procedures.

9. The calculator as described in claim 8, characterized in that, The coefficient exchange unit includes: A first register has an input terminal and an output terminal, wherein the input terminal of the first register is coupled to the module addition unit; The second register has an input terminal and an output terminal, wherein the input terminal of the second register is coupled to the module reduction unit; A third register has an input terminal and an output terminal, wherein the input terminal of the third register is coupled to the output terminal of the second register; A first multiplexer has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the first multiplexer is coupled to the output terminal of the first register, and the second input terminal of the first multiplexer is coupled to the output terminal of the third register. A fourth register has an input terminal and an output terminal. The input terminal of the fourth register is coupled to the output terminal of the first multiplexer, and the output terminal of the fourth register is used to output a first calibrated output coefficient. The second multiplexer has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the second multiplexer is coupled to the output terminal of the first register, the second input terminal of the second multiplexer is coupled to the output terminal of the third register, and the output terminal of the second multiplexer is used to output a second calibrated output coefficient. in: The first multiplexer alternately outputs the data received at the first input terminal and the second input terminal of the first multiplexer; When the first multiplexer outputs the data received at its first input, the second multiplexer outputs the data received at its second input; and When the first multiplexer outputs the data received at the second input terminal of the first multiplexer, the second multiplexer outputs the data received at the first input terminal of the second multiplexer.

10. The calculator as described in claim 1, characterized in that... The rotation factor memory includes 2 M One rotation factor storage block, the 2 M Each rotation factor storage block has one for storing (2) (N-M) -1+2 (N-M-1) The first twitch factor storage block containing (×M) twitch factors, and 2 (M-i) One is used for storage (2) (N-M-1) The storage block for the i-th rotation factor of (×i) rotation factors, where i is any integer from 1 to M.

11. The calculator as described in claim 10, characterized in that... In the first (NM) coefficient operations of the N coefficient operations, the 2 M Each processing unit reads at least one rotation factor from the first rotation factor storage block, and in the k-th coefficient operation from the end of the N coefficient operation, the 2 M Each processing unit is from the 2 M 2 in each rotation factor storage block (M-K+1) Read 2 from each rotation factor storage block (N-K) There are 1 to M selection factors, where k is any integer from 1 to M.

12. A calculation method, characterized in that, Used for 2 N The method for number-theoretic transformations of dimensional polynomials includes: During the initial period: The 2 N 2-dimensional polynomial N Each coefficient is stored in the first coefficient memory; and The corresponding to the 2 N (2)-dimensional polynomial N -1) rotation factors are stored in the rotation factor memory; During the operation, using 2 M Each processing unit performs N coefficient operations in parallel, including: In each odd-numbered coefficient operation: Make the 2 M Each processing unit executes 2 (N-M-1) The first calculation procedure reads 2 from the first coefficient memory. N A first coefficient and at least one first rotation factor read from the rotation factor memory and perform modular arithmetic; and Make the 2 M Each processing unit executes 2 (N-M-1) The first write to the program to generate 2 from the calculation N The first output coefficient is written into the second coefficient memory; and In each even-numbered coefficient operation: Make the 2 M Each processing unit executes 2 (N-M-1) The second calculation procedure reads 2 from the second coefficient memory. N A second coefficient and at least one second rotation factor read from the rotation factor memory and performed modular arithmetic; and Make the 2 M Each processing unit executes 2 (N-M-1) The second write program is used to process the 2 generated by the operation. N The second output coefficient is written into the first coefficient memory; Where N is an integer greater than 1, and M is an integer greater than 1 and less than N.

13. The method as described in claim 12, characterized in that: The first coefficient memory includes 2 (M+1) The first coefficient storage block and the second coefficient memory include 2 (M+1) A second coefficient storage block; and The 2 N The 2-dimensional polynomial N The step of storing the 2 coefficients into the first coefficient memory includes making the 2 (M+1) Each of the first coefficient storage blocks stores 2 (N-M-1) Each coefficient.

14. The method as described in claim 13, characterized in that: Make the 2 M Each processing unit executes the 2 (N-M-1) The steps of the first calculation procedure include, in each first calculation procedure, causing each processing unit to start from the 2 (M+1) Each of the two first coefficient storage blocks in a first coefficient storage block reads one first coefficient; and Make the 2 M Each processing unit executes the 2 (N-M-1) The steps of the second calculation procedure include, in each second calculation procedure, causing each processing unit to start from the 2 (M+1) Each of the two second coefficient storage blocks in the second coefficient storage block reads one second coefficient.

15. The method as described in claim 14, characterized in that: In each first calculation procedure, each processing unit reads one of the first coefficients from each of the two first coefficient storage blocks according to the same address; and In each second calculation procedure, each processing unit reads one second coefficient from each of the two second coefficient storage blocks according to the same address.

16. The method as described in claim 13, characterized in that: Make the 2 M Each processing unit executes the 2 (N-M-1) The steps of the first write procedure include, in each first write procedure, causing each processing unit to write the two first output coefficients generated by the operation to the 2 (M+1) Two second coefficient storage blocks in one second coefficient storage block; and Make the 2 M Each processing unit executes the 2 (N-M-1) The second writing procedure includes, in each second calculation procedure, causing each processing unit to write the two second output coefficients generated by the calculation to the 2 (M+1) Two first coefficient storage blocks in a first coefficient storage block.

17. The method as described in claim 13, characterized in that: In each first calculation procedure, each processing unit writes the two first output coefficients to the two second coefficient storage blocks according to the same address; and In each second calculation procedure, each processing unit writes the two second output coefficients to the two first coefficient storage blocks according to the same address.

18. The method as described in claim 12, characterized in that: Make the 2 M Each processing unit executes the 2 (N-M-1) The steps of the first calculation procedure include, in each first calculation procedure, causing each processing unit to perform a modulo operation based on two first coefficients read from the first coefficient memory and a first rotation factor read from the rotation factor memory; and Make the 2 M Each processing unit executes the 2 (N-M-1) The steps of the second calculation procedure include, in each second calculation procedure, causing each processing unit to perform a modulo operation based on two second coefficients read from the second coefficient memory and a second rotation factor read from the rotation factor memory.

19. The method as described in claim 18, characterized in that... The step of enabling each processing unit to perform modular arithmetic based on the two first coefficients read from the first coefficient memory and the first rotation factor read from the rotation factor memory includes: Based on a preset modulus, one of the two first coefficients is multiplied by the first rotation factor to generate a first value. Based on the preset modulus, perform a modulo addition operation between the other of the two first coefficients and the first value to generate a first coefficient to be rounded; and Based on the preset modulus, a modulo subtraction operation is performed between the other of the two first coefficients and the first value to generate a second coefficient to be rounded; The method further includes: The output order of multiple first unintegrated coefficients and multiple second unintegrated coefficients generated by each processing unit in multiple calculation programs is reordered to execute multiple subsequent first write programs.

20. The method as described in claim 12, characterized in that... The rotation factor memory includes 2 M One rotation factor storage block, and corresponding to the 2 N The (2)-dimensional polynomial N The step of storing -1) twitch factors into the twitch factor memory includes: In the 2 M The first rotation factor storage block in the 2 rotation factor storage blocks stores (2) (N-M) -1+2 (N-M-1) ×M) rotation factors; and In 2 (M-i) The i-th twitch factor storage block stores (2) (N-M-1) (×i) rotation factors, where i is any integer from 1 to M.

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