A memory neural network circuit with emotion consistency and masking effect

Abstract

The application provides a memory neural network circuit with emotion consistency and masking effect, wherein a non-conditional stimulus signal is connected with two learning modules and two inhibition modules respectively, a positive conditional stimulus signal is connected with a learning module and two inhibition modules respectively, a negative conditional stimulus signal is connected with another learning module and the input ends of two inhibition modules respectively, an emotion stimulus signal is connected with the input end of an emotion module, the output end of the emotion module is connected with the input ends of two inhibition modules respectively, the output end of a learning module is connected with the input end of another feedback module, the output end of another feedback module is connected with the input end of an inhibition module, and the output end of the inhibition module is connected with the input end of another learning module. The application combines emotion with the masking effect in Pavlov's classical conditioning reflex, and realizes the generation and recovery of different emotions, the influence of different emotion states on the masking process, and the function of blocking caused by long-term masking.

Description

Technical Field

[0001] This invention relates to the technical field of neural network circuits, and more particularly to a memory neural network circuit with emotion consistency and masking effect. Background Technology

[0002] In 1971, Chinese-American scientist Shao-Tang Tsai proposed, based on the principle of circuit symmetry, the existence of a device that could represent the relationship between charge and magnetic flux, and named it the memristor. In 2008, Hewlett-Packard Laboratories created a physical memristor based on TiO2, and since then, research on memristors has become very popular. Memristors have characteristics such as small size, low power consumption, nonlinearity, non-volatility, and variable resistance, which are very similar to brain synapses. Therefore, they are widely used in the field of artificial neural networks to simulate the brain's conditioned reflexes and emotional learning functions.

[0003] Masking is a typical cue competition effect in Pavlovian classical conditioning. It occurs in the process of conditioning when two or more conditioned stimuli are simultaneously paired with the same unconditioned stimulus. When the two conditioned stimuli have the same salience, they will mask each other, meaning that the associative strength obtained by the two conditioned stimuli is similar, but weaker than the associative strength obtained when each conditioned stimulus is paired alone with the unconditioned stimulus. When the two conditioned stimuli have different saliences, the less salience stimulus will be masked by the more salience stimulus, meaning that the associative strength obtained by the less salience stimulus is weaker than the associative strength obtained by the stimulus alone. Some scholars have proposed neural network circuits to simulate the masking process when the salience of two conditioned stimuli is different and to simulate the brain's emotional learning, but they have not considered combining emotion and the masking effect, as well as the differences in the speed of different emotions' generation and recovery. The neural network circuit proposed in this invention solves these problems. Summary of the Invention

[0004] To address the technical issues of existing neural networks not considering the integration of emotions with the masking effect in classical conditioning and the differences in the generation and recovery speeds of different emotions, this invention proposes a memory neural network circuit with emotion consistency and a masking effect. The learning module enables associative memory between conditioned and unconditioned stimuli; the emotion module enables the generation and recovery of different emotions; the inhibition module implements the masking process under different emotional states; and the feedback module realizes the long-term effect of masking, with long-term masking leading to blockage.

[0005] To achieve the above objectives, the technical solution of the present invention is implemented as follows: a memory neural network circuit with emotional consistency and masking effect, comprising input signal terminals N1-N4, a learning module I, an emotion module, an inhibition module I, a feedback module I, an inhibition module II, a feedback module II, and a learning module II. The input signal terminal N1, representing the unconditioned stimulus signal, is connected to the input terminals of learning module I, inhibition module I, inhibition module II, and learning module II, respectively. The input signal terminal N2, representing the positive conditioned stimulus signal, is connected to the input terminals of learning module I, inhibition module I, and inhibition module II, respectively. The input signal terminal N3, representing the negative conditioned stimulus signal, is connected to the input terminals of learning module II, inhibition module I, and inhibition module II, respectively. The input terminals of Block I and Inhibition Module II are connected. The input signal terminal N4, representing the emotional stimulus signal, is connected to the input terminal of the Emotion Module. The output terminal of the Emotion Module is connected to the input terminals of Inhibition Module I and Inhibition Module II respectively. One output terminal of Learning Module II is connected to the input terminal of Feedback Module I. The output terminal of Feedback Module I is connected to the input terminal of Inhibition Module I. The output terminal of Inhibition Module I is connected to the input terminal of Learning Module I. One output terminal of Learning Module I is connected to the input terminal of Feedback Module II. The output terminal of Feedback Module II is connected to the input terminal of Inhibition Module II. The input signal terminal N1, another output terminal of Learning Module I, and another output terminal of Learning Module II are connected to OR gate D respectively. 21 The input terminal of the OR gate D 21 The output terminal outputs a signal indicating that the learning process is complete.

[0006] Preferably, both learning module I and learning module II include a voltage control circuit and a synaptic neuron circuit. The input terminal of the voltage control circuit of learning module I is connected to the output terminal, input signal terminal N1, and input signal terminal N2 of inhibition module I, respectively. The input terminal of the voltage control circuit of learning module II is connected to the output terminal, input signal terminal N1, and input signal terminal N3 of inhibition module II, respectively. The output terminal of the voltage control circuit is connected to the input terminal of the synaptic neuron circuit. One output terminal of the synaptic neuron circuit outputs a feedback signal, and the other output terminal outputs a signal representing the completion of learning. One output terminal of the synaptic neuron circuit of learning module I is connected to the input terminal of feedback module II, and one output terminal of the synaptic neuron circuit of learning module II is connected to the input terminal of feedback module I. The other output terminals of the synaptic neuron circuits of both learning module I and learning module II are connected to an OR gate D. 21 Connect to the input terminal.

[0007] Preferably, the voltage control circuit includes a first logic unit, a second logic unit, a first voltage control unit, a second voltage control unit, and a first addition unit. The input terminals of the first logic unit and the second logic unit are both connected to input signal terminals N1 and N2 or N3. The output terminal of the first logic unit is connected to the input terminal of the first voltage control unit, and the output terminal of the second logic unit is connected to the input terminal of the second voltage control unit. The output terminals of the first voltage control unit and the second voltage control unit are both connected to one input terminal of the first addition unit. The output terminal of suppression module I or suppression module II is connected to the other input terminal of the first addition unit. The output terminal of the first addition unit is connected to the input terminal of the synaptic neuron circuit.

[0008] Preferably, the synaptic neuron circuit includes a first memristor, a first operational amplifier, a first mathematical operation unit, a second adder unit, a first comparator, a first NMOS transistor, and a first NOT gate. The output of the first adder unit is connected to the positive terminal of the first memristor and one input terminal of the first mathematical operation unit. The negative terminal of the first memristor is connected to one end of a first resistor and the inverting input terminal of the first operational amplifier. The other end of the first resistor is connected to the output of the first operational amplifier. The non-inverting input of the first operational amplifier is grounded. The output of the first operational amplifier is connected to the other input terminal of the first mathematical operation unit. The output of the first mathematical operation unit outputs a feedback signal, and the first... The output of a mathematical operation unit is connected to one input of a second addition operation unit; input signal terminal N2 or input signal terminal N3 is connected to the input of a first NOT gate, the output of the first NOT gate is connected to the other input of the second addition operation unit, the output of the second addition operation unit and the first voltage source are both connected to the input of a first comparator, the output of the first comparator is connected to the gate of a first NMOS transistor, the source of the first NMOS transistor is connected to the positive terminal of the second voltage source, the drain of the first NMOS transistor is connected to one end of a second resistor, and the other end of the second resistor and the negative terminal of the second voltage source are both grounded; the drain of the first NMOS transistor outputs a signal representing the completion of learning.

[0009] Preferably, both feedback module I and feedback module II include a second memristor, a third memristor, a second NMOS transistor, a third NMOS transistor, a second comparator, and a third comparator. The feedback signal output by the synaptic neuron circuit of learning module I is connected to one input terminal of the second and third comparators of feedback module II, respectively. The feedback signal output by the synaptic neuron circuit of learning module II is connected to one input terminal of the second and third comparators of feedback module I, respectively. The other input terminal of the second comparator is connected to the positive terminal of the third voltage source. The output terminal of the second comparator is connected to the gate of the second NMOS transistor. The drain of the second NMOS transistor is connected to the positive terminal of the fifth voltage source. The source of the second NMOS transistor is connected to one end of the third resistor and the positive terminal of the second memristor, respectively. The negative terminal of the second memristor is connected to the fourth resistor. One end of the third comparator is connected to the positive terminal of the fourth voltage source. The output terminal of the third comparator is connected to the gate of the third NMOS transistor. The drain of the third NMOS transistor is connected to the positive terminal of the sixth voltage source. The source of the third NMOS transistor is connected to one end of the fifth resistor and the positive terminal of the third memristor. The negative terminal of the third memristor is connected to one end of the sixth resistor. The negative terminal of the third memristor is connected to the other input terminal of the suppression module I or suppression module II as an output terminal. The negative terminals of the third, fourth, fifth, and sixth voltage sources, the other end of the third resistor, one end of the fourth resistor, the other end of the fifth resistor, and the other end of the sixth resistor are all grounded.

[0010] Preferably, the emotion module includes a signal judgment circuit, a ninth pressure control unit, a tenth pressure control unit, an eleventh pressure control unit, a twelfth pressure control unit, a first synaptic neuron circuit, a second synaptic neuron circuit, a seventh addition unit, an eighth comparator, a ninth comparator, and a ninth logic unit. The input signal terminal N4 is connected to the input terminal of the signal judgment circuit. The output terminal of the signal judgment circuit is connected to the input terminals of the ninth pressure control unit, the NOT gate D6, the eleventh pressure control unit, and the NOT gate D7, respectively. The output terminal of the NOT gate D6 is connected to the input terminal of the tenth pressure control unit, and the output terminal of the NOT gate D7 is connected to the input terminal of the twelfth pressure control unit. The output terminals of the ninth and tenth pressure control units are both connected to the first synaptic neuron circuit. The input terminals of the first and second synaptic neuron circuits are connected to each other. The output terminals of the eleventh and twelfth voltage control units are both connected to the input terminals of the second synaptic neuron circuit. The output terminals of the first and second synaptic neuron circuits are both connected to the input terminals of the seventh addition unit. The output terminals of the seventh addition unit are connected to the input terminals of the eighth and ninth comparators, respectively. The output terminals of the eighth comparator are connected to the input terminals of the suppression module I, the suppression module II, and the ninth logic unit, respectively. The output terminals of the ninth comparator are connected to the input terminals of either the suppression module I or the suppression module II, and the ninth logic unit, respectively. The output terminals of the ninth logic unit are connected to the input terminals of both the suppression module I and the suppression module II.

[0011] Preferably, the signal judgment circuit includes a sixth comparator and a seventh comparator. The input terminals of the sixth and seventh comparators are both connected to the input signal terminal N4. The output terminal of the sixth comparator is connected to the input terminal of the ninth voltage control unit and the input terminal of the NOT gate D6, respectively. The output terminal of the seventh comparator is connected to the input terminal of the eleventh voltage control unit and the input terminal of the NOT gate D7, respectively.

[0012] The first synaptic neuron circuit includes a memristor M2, an operational amplifier OP8, and a mathematical operation unit ABM2. The output terminals of the ninth and tenth voltage-controlled units are both connected to the positive terminal of the memristor M2. The positive terminal of the memristor M2 is connected to one input terminal of the mathematical operation unit ABM2, and the negative terminal of the memristor M2 is connected to a resistor R. 25 One end is connected to the inverting input of operational amplifier OP8, and resistor R 25 The other end is connected to the output of operational amplifier OP8. The non-inverting input of operational amplifier OP8 is grounded. The output of operational amplifier OP8 is connected to the other input of mathematical operation unit ABM2. The output of mathematical operation unit ABM2 is connected to one input of the seventh addition unit.

[0013] The second synaptic neuron circuit includes memristor M3 and operational amplifier OP. 11 The positive terminal of memristor M3 is connected to the output terminal of the eleventh voltage-controlled unit, the output terminal of the twelfth voltage-controlled unit, and one input terminal of the mathematical operation unit ABM3, respectively. The negative terminal of memristor M3 is connected to resistor R. 26 One end and operational amplifier OP 11 Connect the inverting input terminal to the resistor R. 26 The other end is connected to the operational amplifier OP. 11 Connect the output terminal of the operational amplifier OP to the output terminal. 11 The non-inverting input terminal is grounded, and the operational amplifier OP... 11 The output terminal of the mathematical operation unit ABM3 is connected to another input terminal of the mathematical operation unit ABM3, and the output terminal of the mathematical operation unit ABM3 is connected to another input terminal of the seventh addition operation unit.

[0014] Preferably, both suppression module I and suppression module II include a third voltage control unit, a fourth voltage control unit, a fifth voltage control unit, a voltage control switch I, a voltage control switch II, a third addition operation unit, a first proportional amplifier, a second proportional amplifier, and a fourth addition operation unit. The input signal terminals N1, N2, and N3 are all connected to the input terminals of AND gate D5. The output terminal of AND gate D5 is connected to one input terminal of the first AND gate, the second AND gate, and the third AND gate, respectively. The other input terminal of the first AND gate of suppression module I and the other input terminal of the second AND gate of suppression module II are also connected. All are connected to the output of the eighth comparator. The other input of the first AND gate of suppression module II and the other input of the second AND gate of suppression module I are both connected to the output of the ninth comparator. The other input of the third AND gate is connected to the output of the ninth logic unit. The output of the first AND gate is connected to the input of the third voltage-controlled unit. The output of the third voltage-controlled unit is connected to the input of the third adder unit and the first contact of the voltage-controlled switch I. The second contact of the voltage-controlled switch I is connected to one end of the seventh resistor and the input of the first proportional amplifier. The positive... The phase input terminal is connected to the negative terminal of the second memristor of feedback module I or feedback module II; the inverting input terminal of voltage-controlled switch I and the other end of the seventh resistor are both grounded; the output terminal of the first proportional amplifier is connected to the input terminal of the fourth adder unit; the output terminal of the second AND gate is connected to the input terminal of the fourth voltage-controlled unit, and the output terminal of the fourth voltage-controlled unit is connected to the input terminal of the third adder unit; the output terminal of the third AND gate is connected to the input terminal of the fifth voltage-controlled unit, and the output terminal of the fifth voltage-controlled unit is connected to the input terminal of the third adder unit and the second contact of voltage-controlled switch II, respectively. The first contact of voltage-controlled switch I is connected to one end of the eighth resistor and the input of the second proportional amplifier. The positive input of voltage-controlled switch II is connected to the negative terminal of the third memristor of feedback module I or feedback module II. The inverting input of voltage-controlled switch II and the other end of the eighth resistor are both grounded. The output of the second proportional amplifier is connected to the input of the fourth adder unit. The output of the third adder unit is connected to the input of the fourth adder unit. The output of the fourth adder unit is connected to the input of the voltage control circuit of learning module I or learning module II.

[0015] Preferably, the first logic unit includes a second NOT gate and a fourth AND gate, with input signal terminal N1 connected to the input terminal of the second NOT gate, input signal terminal N2 or input signal terminal N3 connected to one input terminal of the fourth AND gate, the output terminal of the second NOT gate connected to the other input terminal of the fourth AND gate, and the output terminal of the fourth AND gate connected to the input terminal of the first voltage control unit; the second logic unit includes a fifth AND gate, with input signal terminal N1 connected to one input terminal of the fifth AND gate, input signal terminal N2 or input signal terminal N3 connected to the other input terminal of the fifth AND gate, and the output terminal of the fifth AND gate connected to the input terminal of the second voltage control unit;

[0016] The ninth logic unit includes a third NOT gate, a fourth NOT gate, and a sixth AND gate. The input of the third NOT gate is connected to the output of the eighth comparator, the input of the fourth NOT gate is connected to the output of the ninth comparator, the outputs of the third NOT gate and the fourth NOT gate are both connected to the input of the sixth AND gate, and the output of the sixth AND gate is connected to the input of the third AND gate of the suppression module I and the suppression module II, respectively.

[0017] Both the first proportional amplifier and the second proportional amplifier include a second operational amplifier. The non-inverting input terminal of the second operational amplifier is grounded, and the inverting input terminal of the second operational amplifier is connected to one end of the ninth resistor and the tenth resistor, respectively. The other end of the ninth resistor is the input terminal, and the other end of the tenth resistor is connected to the output terminal of the second operational amplifier. The output terminal of the second operational amplifier is connected to the input terminal of the fourth addition unit.

[0018] Preferably, the first, second, third, fourth, and seventh addition units each include a third operational amplifier. The non-inverting input of the third operational amplifier is used as an input terminal and is connected to one end of the twelfth resistor. The inverting input of the third operational amplifier is connected to one end of the thirteenth resistor and one end of the fourteenth resistor, respectively. The other end of the fourteenth resistor is connected to the output terminal of the third operational amplifier. The output terminal of the third operational amplifier outputs the signal after addition. The other ends of the twelfth and thirteenth resistors are both grounded.

[0019] The first, second, third, fourth, fifth, ninth, tenth, eleventh, and twelfth voltage control units all include a voltage control switch. The positive input terminal of the voltage control switch is the input terminal. The second contact of the voltage control switch is connected to the positive terminal of the seventh voltage source. The first contact of the voltage control switch is the output terminal and is connected to one end of the fifteenth resistor. The inverting input terminal of the voltage control switch, the negative terminal of the seventh voltage source, and the other end of the fifteenth resistor are all grounded.

[0020] The first comparator, the second comparator, the third comparator, the seventh comparator, and the ninth comparator all include a fourth operational amplifier. The non-inverting input of the fourth operational amplifier is connected to the positive terminal of the eighth voltage source, the negative terminal of the eighth voltage source is grounded, the inverting input of the fourth operational amplifier serves as the input terminal, and the output terminal of the fourth operational amplifier outputs the compared signal.

[0021] The sixth and eighth comparators each include a fifth operational amplifier. The non-inverting input of the fifth operational amplifier is used as the input terminal, and the inverting input terminal of the fifth operational amplifier is connected to the positive terminal of the ninth voltage source. The negative terminal of the ninth voltage source is grounded, and the output terminal of the fifth operational amplifier outputs the compared signal.

[0022] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0023] (1) By combining emotion with the masking effect, the conditioned stimuli are given positive and negative meanings. The process of mutual masking of two conditioned stimuli in the absence of emotion and unidirectional masking of two conditioned stimuli in the presence of positive and negative emotions is realized through the emotion module and the inhibition module, respectively. This is more comprehensive and more in line with biological characteristics than the neural network circuit with masking function that does not consider emotion.

[0024] (2) The long-term effect of masking is considered. Long-term masking leads to blockage. That is, when the two conditional stimuli are different in salience, long-term masking will further suppress the associative intensity of the lower salience stimulus, eventually causing its associative intensity to drop below the threshold and no longer cause drooling.

[0025] (3) The generation and recovery of different emotions were considered. The positive emotion of happiness is generated quickly and the emotion recovers quickly after the stimulus disappears; the negative emotion of sadness is generated slowly and the emotion recovers slowly after the stimulus disappears, which is consistent with biological characteristics.

[0026] This invention achieves differentiation in the generation and recovery of different emotions through an emotion module. Furthermore, through inhibition and learning modules, it assigns positive and negative meanings to two conditioned stimuli, then simulates the mutual masking of the two conditioned stimuli in an emotionless state, as well as the unidirectional masking under positive and negative emotions, and the recovery process from masking. Finally, this invention realizes the long-term effect of masking through a feedback module. Long-term masking leads to blockage; that is, when the salience of the two conditioned stimuli differs, prolonged masking further inhibits the associative strength of the less salience stimulus, eventually reducing its associative strength below a threshold, thus ceasing to cause salivation. Conversely, when the salience of the two conditioned stimuli is equal, prolonged masking does not change the associative strength of either stimulus. This invention combines emotion with the masking effect in Pavlovian classical conditioning, realizing the generation and recovery of different emotions, the influence of different emotional states on the masking process, and the function of long-term masking leading to blockage. The designed circuit is more comprehensive and more in line with biological characteristics, contributing to the construction of more intelligent neural network circuits. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is the circuit schematic diagram of the present invention.

[0029] Figure 2 for Figure 1 The circuit diagram of learning module I is shown.

[0030] Figure 3 for Figure 1 The circuit diagram of suppression module I is shown.

[0031] Figure 4 for Figure 1 The circuit diagram of feedback module I is shown.

[0032] Figure 5 for Figure 1 The circuit diagram of the emotion module is shown.

[0033] Figure 6 The following are simulation results of the two conditioned stimuli of the present invention paired individually with the same unconditioned stimulus, wherein (a) is the curve of N1, (b) is the curve of N2, (c) is the curve of N3, (d) is the curve of M1 and M2, and (e) is the curve of the output signal.

[0034] Figure 7The simulation results of the generation and recovery of happy and sad emotions in this invention are shown in the figure, where (a) is the curve of N4, and (b) is the curve of V. M2 The curve, (c) is V M3 The curves are: (d) is the curve of M2, (e) is the curve of M2, and (f) is the curve of U1 and U2.

[0035] Figure 8 The figure shows the simulation results of two-conditional stimulus occlusion and recovery from occlusion in the emotionless state of the present invention, where (a) is the curve of N1, (b) is the curve of N2, (c) is the curve of N3, (d) is the curve of M1, (e) is the curve of M8, and (f) is the curve of the output signal.

[0036] Figure 9 The following are simulation results of the two-conditional stimulus masking and recovery from masking under positive and negative emotions according to the present invention. In (I), (a) is the curve of N1, (b) is the curve of N2, (c) is the curve of N3, (d) is the curve of N1 and U1, (e) is the curve of M1 and M8, and (f) is the curve of the output signal; in (II), (a) is the curve of N1, (b) is the curve of N2, (c) is the curve of N3, (d) is the curve of N4 and U1, (e) is the curve of M1 and M8, and (f) is the curve of the output signal.

[0037] Figure 10 The following are simulation results of long-term occlusion under positive and negative emotions according to the present invention. In (I), (a) is the curve of N1, (b) is the curve of N2, (c) is the curve of N3, (d) is the curve of N4 and U1, (e) is the curve of M1 and M8, and (f) is the curve of the output signal; in (II), (a) is the curve of N1, (b) is the curve of N2, (c) is the curve of N3, (d) is the curve of N4 and U1, (e) is the curve of M1 and M8, and (f) is the curve of the output signal. Detailed Implementation

[0038] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0039] like Figure 1As shown, a memory neural network circuit with emotion consistency and masking effect includes input signal terminals N1-N4, learning module I, emotion module, inhibition module I, feedback module I, inhibition module II, feedback module II, and learning module II. Input signal terminal N1, representing the unconditioned stimulus signal, is connected to the input terminals of learning module I, inhibition module I, inhibition module II, and learning module II, respectively. Input signal terminal N2, representing the positive conditioned stimulus signal, is connected to the input terminals of learning module I, inhibition module I, and inhibition module II, respectively. Input signal terminal N3, representing the negative conditioned stimulus signal, is connected to the input terminals of learning module II, inhibition module I, and inhibition module II, respectively. The input terminals are connected as follows: the input signal terminal N4, representing the emotional stimulus signal, is connected to the input terminal of the emotion module; the output terminal of the emotion module is connected to the input terminals of inhibition module I and inhibition module II, respectively; one output terminal of learning module II is connected to the input terminal of feedback module I; the output terminal of feedback module I is connected to the input terminal of inhibition module I; the output terminal of inhibition module I is connected to the input terminal of learning module I; one output terminal of learning module I is connected to the input terminal of feedback module II; and the output terminal of feedback module II is connected to the input terminal of inhibition module II. The input signal terminal N1, another output terminal of learning module I, and another output terminal of learning module II are connected to OR gate D. 21 The input terminal of the OR gate D 21 The output terminal outputs a signal indicating that the learning process is complete.

[0040] The learning module is designed to enable associative learning between conditioned and unconditioned stimuli, as well as testing when only a conditioned or unconditioned stimulus is applied. The emotion module is designed to change the circuit's emotional state by applying different emotional stimuli, and to restore the circuit to an emotionless state after the stimulus disappears. The inhibition module applies an inhibitory voltage to both learning modules when both unconditioned and two conditioned stimuli are input simultaneously; the inhibitory voltage varies depending on the emotional state. The feedback module outputs a feedback signal to the inhibition module based on the synaptic strength of the learning modules, thereby changing the inhibitory module's operating state. Input terminal N1 receives the unconditioned stimulus; input terminals N2 and N3 receive the positive and negative conditioned stimuli, respectively; and input terminal N4 receives the emotional stimulus. In the specific implementation, the unconditioned stimulus and the two conditioned stimuli use an amplitude of 5V, while the emotional stimulus signal uses amplitudes of 1V and -1V, representing positive and negative emotional stimuli, respectively. A three-input OR gate D... 21 The output terminal is the output signal terminal.

[0041] Input signal terminals N1 and N2 are both connected to the input terminals of learning module I, and input signal terminals N1 and N3 are connected to learning module II. The synaptic weights of the learning module will change according to the input signals. Taking learning module I as an example, when only input signal N1 or N2 is input, the circuit is in the test state, and the resistance value of memristor M1 does not change, that is, the synaptic weight corresponding to the positive condition stimulus remains unchanged. When input signals N1 and N2 are input simultaneously, the circuit is in the learning state, and the resistance value of memristor M1 decreases, that is, the synaptic weight corresponding to the positive condition stimulus increases. At the same time, the suppression voltage output by suppression module I will also affect the change of synaptic weights of learning module I in the learning state, making the rate of increase of synaptic weights slower or causing the synaptic weights to decrease. Input signal terminal N4 is connected to the input terminal of the emotion module. When a signal representing a positive emotion stimulus is input, the output terminal U1 of the emotion module will output a high level after 1 second, indicating that the circuit has entered a positive emotion state. When the stimulus signal disappears, the output terminal U1 of the emotion module will output a low level after 1 second, and the output terminal U3 will output a high level, indicating that the circuit has returned to an emotionless state. When a signal representing a negative emotion stimulus is input, the output terminal U2 of the emotion module will output a high level after 2 seconds, indicating that the circuit has entered a negative emotion state. When the stimulus signal disappears, the output terminal U2 of the emotion module will output a low level after 2 seconds, and the output terminal U3 will output a high level, indicating that the circuit has returned to an emotionless state. Input signal terminals N1-N3, the output terminals U1-U3 of the emotion module, and the output terminal of the feedback module are all connected to the inhibition module. When signals N1-N3 are input simultaneously, the inhibition module is in working condition, applying different inhibition voltages to the learning module based on the output signals of the emotion module and the feedback signals output by the feedback module.

[0042] like Figure 2 As shown, learning module I includes voltage control circuit I and synaptic neuron circuit I. Input signal terminals N1 and N2 are connected to the input terminals of voltage control circuit I, and the output terminal of voltage control circuit I is connected to the input terminal of synaptic neuron circuit I. Synaptic neuron circuit I outputs a feedback signal F1 and a signal OUT1 representing the completion of learning. Feedback signal F1 is connected to the input terminal of feedback module II, and the output terminal U4 of inhibition module I is connected to the input terminal of voltage control circuit I. Specifically, the output terminal of the mathematical operation unit ABM1 in synaptic neuron circuit I is connected to the input terminal of the second addition operation unit and the input terminals of the fourth and fifth comparators in feedback module II, respectively. When the synaptic weight in synaptic neuron circuit I rises to a certain value, the fourth or fifth comparator outputs a high level, activating feedback module II and causing it to output a feedback signal to inhibition module II. The output terminal of the fourth addition operation unit in inhibition module I is connected to the input terminal of the first addition operation unit in voltage control module I, thereby changing the voltage applied to memristor M1.

[0043] Voltage control circuit I includes a first logic unit, a second logic unit, a first voltage control unit, a second voltage control unit, and a first adder unit. The inputs of both the first and second logic units are connected to input signals N1 and N2. The output of the first logic unit is connected to the input of the first voltage control unit, and the output of the second logic unit is connected to the input of the second voltage control unit. The outputs of both the first and second voltage control units are connected to one input terminal of the first adder unit. The output terminal of suppression module I is connected to the other input terminal of the first adder unit. The first logic unit outputs a high level when only the positive conditional stimulus signal N2 is input, thereby activating the first voltage control unit. The first voltage control unit then supplies the output voltage V1 of voltage source V1 to the first adder unit. The second logic unit outputs a high level when both the unconditional stimulus signal N1 and the positive conditional stimulus signal N2 are input simultaneously, thereby activating the second voltage control unit. The second voltage control unit outputs voltage V2 to the first adder unit, and the first adder unit outputs V2. op1 =V1+V2+U4, where U4 is the suppression voltage output by suppression module I. The output of voltage control circuit I is connected to the input of synaptic neuron circuit I, and is used to change the synaptic weights in synaptic neuron circuit I.

[0044] Synaptic neuron circuit I includes memristor M1, resistor R9, operational amplifier OP2, mathematical operation unit ABM1, second addition operation unit, first comparator, NMOS transistor T1, DC voltage source V4, and resistor R. 15 The positive terminals of NOT gate D4 and memristor M1 are connected to the output of voltage control circuit I and one input of mathematical operation unit ABM1, respectively. The negative terminal of memristor M1 is connected to the inverting input of operational amplifier OP2 and one end of resistor R9, respectively. The non-inverting input of operational amplifier OP2 is grounded. The other end of resistor R9 is connected to the output of operational amplifier OP2 and the other input of mathematical operation unit ABM1. The output of mathematical operation unit ABM1 is connected to one input of the second adder and the input of suppression module II. The input of NOT gate D4 is connected to input signal terminal N2. The output of NOT gate D4 is connected to the other input of the second adder. The output of the second adder is connected to the input of the first comparator. The output of the first comparator is connected to the gate of NMOS transistor T1. The negative terminal of DC voltage source V4 is grounded. The positive terminal of DC voltage source V4 is connected to the source of NMOS transistor T1. Resistor R... 15 One end is connected to the drain of NMOS transistor T1, and resistor R 15 The other end is grounded. The output of the mathematical operation unit ABM1 is Vout = -V IN2 / V IN1=M1 / R9=M1 / 1000, where 1000 represents the resistance value of resistor R9. When voltage control circuit I outputs V op1 When the positive threshold voltage of memristor M1 is reached, the resistance of memristor M1 will decrease, therefore the output of mathematical operation unit ABM1 will also decrease. op1 When the output voltage is less than the negative threshold voltage of memristor M1, the resistance of memristor M1 increases, and therefore the output of mathematical operation unit ABM1 also increases. Thus, the output of mathematical operation unit ABM1 reflects the change in the resistance of memristor M1. The output of the second adder unit is V. op3 =V ABM1 +V D4 V D4 The output voltage of NOT gate D4 is 0V when the input signal N2 is high and 5V when the input signal N2 is low. This ensures that learning module I will not output a high level when there is no positive conditional stimulus input. The output of the second addition unit is compared with the DC voltage source V3 in the first comparator to determine whether the synaptic weight corresponding to the positive conditional stimulus has risen above the threshold. If it is above the threshold, the first comparator outputs a high level, the gate-source voltage difference of NMOS transistor T1 is above the threshold, and it is in the conducting state, outputting voltage V4 to OR gate D. 21 This indicates that the learning is complete.

[0045] The first logic unit includes a NOT gate D1 and an AND gate D2. The input of NOT gate D1 is connected to the input signal terminal N1, and the output of NOT gate D1 is connected to the first input terminal of AND gate D2. The second input terminal of AND gate D2 is connected to the input signal terminal N2, and the output terminal of AND gate D2 is connected to the input terminal of the first voltage-controlled unit. When the input signal N1 is low and the input signal N2 is high, NOT gate D1 outputs a high level. When both input terminals of AND gate D2 are high, AND gate D2 outputs a high level. Otherwise, AND gate D2 outputs a low level. The second logic unit includes an AND gate D3. The first input terminal of AND gate D3 is connected to the input signal terminal N1, and the second input terminal of AND gate D3 is connected to the input signal terminal N2. The output terminal of AND gate D3 is connected to the input terminal of the second voltage-controlled unit. When both input signals N1 and N2 are high, AND gate D3 outputs a high level. Otherwise, AND gate D3 outputs a low level.

[0046] The first voltage-controlled unit includes a voltage-controlled switch S1, a DC voltage source V1, and a resistor R1. The positive input terminal of the voltage-controlled switch S1 is connected to the output terminal of the AND gate D2 of the first logic unit. The first contact of the voltage-controlled switch S1 is connected to the resistor R1, the output terminal of the second voltage-controlled unit, and the input terminal of the first addition unit. The second contact of the voltage-controlled switch S1 is connected to the positive terminal of the DC voltage source V1, the negative terminal of the DC voltage source V1 is grounded, and the inverting input terminal of the voltage-controlled switch S1 is grounded. When the output of the AND gate D2 in the first logic unit is greater than the threshold value of the voltage-controlled switch S1, the first contact of the voltage-controlled switch S1 will output the voltage of the voltage source V1. The second voltage-controlled unit includes a voltage-controlled switch S2, a DC voltage source V2, and a resistor R2. The positive input terminal of the voltage-controlled switch S2 is connected to the output terminal of the second logic unit. The first contact of the voltage-controlled switch S2 is connected to the resistor R2, the output terminal of the first voltage-controlled unit, and the input terminal of the first addition unit. The second contact of the voltage-controlled switch S2 is connected to the positive terminal of the DC voltage source V2, the negative terminal of the DC voltage source V2 is grounded, and the inverting input terminal of the voltage-controlled switch S2 is grounded. The second voltage-controlled unit outputs the voltage of the power supply V2 through the first contact of the voltage-controlled switch S2 when the output of the AND gate D3 in the second logic unit exceeds the threshold value of the voltage-controlled switch S2.

[0047] The first addition unit includes operational amplifier OP1 and resistors R3-R7. The non-inverting input of operational amplifier OP1 is connected to one end of resistors R3, R4, and R5, respectively. The other ends of resistors R3 and R4 serve as inputs to the addition unit, and the other end of resistor R3 is connected to the first contacts of voltage-controlled switches S1 and S2, respectively. The other end of resistor R4 is connected to the output of suppression module I, and the other end of resistor R5 is grounded. The inverting input of operational amplifier OP1 is connected to one end of resistors R6 and R7, respectively. The other end of resistor R6 is grounded, and the other end of resistor R7 is connected to the output of operational amplifier OP1. The output of operational amplifier OP1 serves as the output of the first addition unit. The function of the first addition unit is to sum the voltages of the first and second voltage-controlled units and the suppression voltage output by suppression module I and apply it to the memristor M1 corresponding to the synaptic neuron circuit I. The second addition unit includes operational amplifier OP3 and resistors R... 10 -R 14 The non-inverting input terminal of operational amplifier OP3 is connected to resistor R. 10 R 11 and R 12 One end is connected to the resistor R. 10 and R 11 The other end serves as the input terminal of the addition unit, and the resistor R 10 The other end is connected to the output of the mathematical operation unit ABM1, and the resistor R 11The other end is connected to the output terminal of the co-NOT gate D4, and the resistor R 12 The other end is grounded, and the inverting input of operational amplifier OP3 is connected to resistor R. 13 and R 14 One end is connected to the resistor R. 13 The other end is grounded, and the resistor R 14 The other end is connected to the output of operational amplifier OP3, which serves as the output of the second adder unit. The function of the second adder unit is to sum the voltage output of mathematical operation unit ABM1 and the voltage output of NOT gate D4 and apply it to the input of the first comparator, comparing it with the voltage V3.

[0048] The first comparator includes an operational amplifier OP4 and a DC voltage source V3. The positive terminal of the DC voltage source V3 is connected to the non-inverting input of the operational amplifier OP4, and the negative terminal of the DC voltage source V3 is grounded. The inverting input of the operational amplifier OP4 is connected to the output of the operational amplifier OP3, and the output of the operational amplifier OP4 is connected to the gate of the NMOS transistor T1, serving as the comparator output. The first comparator compares the output voltage of the second adder unit with the voltage V3 of the DC voltage source V3 to determine whether the synaptic strength in the synaptic neuron circuit I has risen above a threshold. If it is above the threshold, a high level is output; otherwise, a low level is output.

[0049] like Figure 3 As shown, the suppression module I includes a third logic unit, a fourth logic unit, a fifth logic unit, a third voltage control unit, a fourth voltage control unit, a fifth voltage control unit, and a voltage control switch S. 10 Pressure control switch S 11 Resistance R 33 Resistance R 34 The system comprises a third addition unit, a first proportional amplifier, a second proportional amplifier, and a fourth addition unit. The input signal terminals N1-N3 and the output of the emotion module are all connected to the input terminals of the third, fourth, and fifth logic units. The output terminal of the third logic unit is connected to the input terminal of the third voltage control unit. The output terminal of the third voltage control unit is connected to both the input terminal of the third addition unit and the voltage control switch S. 10 The first contact is connected to the voltage-controlled switch S. 10 The second contact is respectively connected to resistor R 33 One end is connected to the input terminal of the first proportional amplifier, and the resistor R 33The other end is grounded. The output of the first proportional amplifier is connected to the input of the fourth adder unit. The output of the fourth logic unit is connected to the input of the fourth voltage control unit. The output of the fourth voltage control unit is connected to the input of the third adder unit. The output of the fifth logic unit is connected to the input of the fifth voltage control unit. The output of the fifth voltage control unit is connected to both the input of the third adder unit and the voltage control switch S. 11 The second contact is connected to the voltage-controlled switch S. 11 The first contact is connected to resistor R. 34 One end of the amplifier is connected to the input terminal of the second proportional amplifier, and the resistor R 34 The other end is grounded. The output of the second proportional amplifier is connected to the input of the fourth adder unit, and the output of the third adder unit is connected to the input of the fourth adder unit. The output of the fourth adder unit is the output of the suppression module I. The voltage-controlled switch S... 10 and pressure control switch S 11 Used to control the on / off state of its branch, thereby controlling the suppression voltage output by suppression module I. (Using voltage-controlled switch S) 10 For example, when it is in the off state and the circuit is in a negative emotional state, the output voltage of the fourth adder unit is V. 13 That is, the suppression voltage output by suppression module I is V. 13 When it is in the ON state and the circuit is in a negative state, the output voltage of the fourth adder unit is V. 13 +V 13 *(-R) 42 / R 39 That is, the suppression voltage output by suppression module I becomes V. 13 +V 13 *(-R) 42 / R 39 ).

[0050] The third logic unit includes AND gate D. 11 And a three-input AND gate D5, the three input terminals of the three-input AND gate D5 are connected to the input signal terminals N1-N3 respectively, and the output terminal of the three-input AND gate D5 is connected to the AND gate D5. 11 Connected to the first input terminal, AND gate D 11 The second input is connected to the output of the eighth comparator of the emotion module, and is connected to gate D. 11 The output terminal is connected to the input terminal of the third voltage control unit. When all input signals N1-N3 are high, i.e., when both conditioned stimuli are simultaneously paired with the unconditioned stimulus, the three-input AND gate D5 outputs a high level. When the three-input AND gate D5 outputs a high level and the eighth comparator of the emotion module outputs a high level, i.e., the circuit is in a negative emotional state, the AND gate D... 11 The output is high, meaning the third logic unit outputs a high level; otherwise, the AND gate D...11 All outputs are low. The fourth logic unit includes an AND gate D. 12 And a three-input AND gate D5, the output of the three-input AND gate D5 and the AND gate D 12 Connected to the first input terminal, AND gate D 12 The second input is connected to the output of the ninth comparator of the emotion module, and is connected to gate D. 12 The output terminal is connected to the input terminal of the fourth voltage-controlled unit. When the three-input AND gate D5 outputs a high level and the ninth comparator of the emotion module outputs a high level, i.e., the circuit is in a positive emotional state, the AND gate D... 12 The output is high, meaning the fourth logic unit outputs a high level; otherwise, the AND gate D... 12 All outputs are low. The fifth logic unit includes an AND gate D. 13 And the output of the three-input AND gate D5, and the output of the three-input AND gate D... 13 Connected to the first input terminal, AND gate D 13 The second input terminal is connected to the output terminal of the ninth logic unit of the emotion module, and is connected to gate D. 13 The output terminal is connected to the input terminal of the fifth voltage control unit. When the three-input AND gate D5 outputs a high level and the ninth logic unit of the emotion module outputs a high level, i.e., the circuit is in an emotionless state, the AND gate D... 13 The output is high, meaning the fifth logic unit outputs a high level; otherwise, the AND gate D... 13 All output a low level.

[0051] The third voltage control unit includes a voltage control switch S7 and a DC voltage source V. 13 Resistance R 27 The positive input terminal of the voltage-controlled switch S7 is connected to the output terminal of the third logic unit, and the first contact of the voltage-controlled switch S7 is connected to the resistor R. 27 One end, voltage-controlled switch S 10 The first contact of the voltage-controlled switch S7 is connected to the input terminal of the third addition unit, and the second contact of the voltage-controlled switch S7 is connected to the DC voltage source V. 13 Positive terminal connected, DC voltage source V 13 The negative terminal is grounded, and the inverting input terminal of the voltage-controlled switch S7 is grounded. The third voltage-controlled unit is when the AND gate D in the third logic unit... 11 When the output exceeds the threshold of the voltage-controlled switch S7, the first contact of the voltage-controlled switch S7 will output power V. 13 The voltage. The fourth voltage control unit includes a voltage control switch S8 and a DC voltage source V. 14 Resistance R 28 The positive input terminal of the voltage-controlled switch S8 is connected to the output terminal of the fourth logic unit, and the first contact of the voltage-controlled switch S8 is connected to the resistor R. 28 The second contact of the voltage-controlled switch S8 is connected to the input terminal of the third addition unit and the DC voltage source V.14 The positive terminal is connected to the DC voltage source V. 14 The negative terminal is grounded, and the inverting input terminal of the voltage-controlled switch S8 is grounded. The fourth voltage-controlled unit is when the AND gate D in the fourth logic unit... 12 When the output exceeds the threshold of the voltage-controlled switch S8, the first contact of the voltage-controlled switch S8 will output power V. 14 The voltage. The fifth voltage control unit includes a voltage control switch S9 and a DC voltage source V. 15 Resistance R 29 The positive input terminal of the voltage-controlled switch S9 is connected to the output terminal of the fifth logic unit, and the first contact of the voltage-controlled switch S9 is connected to the resistor R. 29 Pressure control switch S 11 The first contact of the voltage-controlled switch S9 is connected to the input terminal of the third addition unit, and the second contact of the voltage-controlled switch S9 is connected to the DC voltage source V. 15 Positive terminal connected, DC voltage source V 15 The negative terminal is grounded, the inverting input of the voltage-controlled switch S9 is grounded, and the fifth voltage-controlled unit is when the AND gate D in the fifth logic unit is grounded. 13 When the output exceeds the threshold of voltage-controlled switch S9, the first contact of voltage-controlled switch S9 will output power V. 15 The voltage.

[0052] The third addition unit includes an operational amplifier (OP). 12 Resistance R 30 Resistance R 31 Resistance R 32 Resistance R 36 Resistance R 37 Resistance R 40 Operational amplifier (OP) 12 The non-inverting input terminal is connected to resistor R respectively. 30 Resistance R 31 Resistance R 32 and resistance R 36 One end is connected to the resistor R. 30 Resistance R 31 Resistance R 32 The other end serves as the input terminal of the addition unit and is connected to the output terminals of the third to fifth voltage control units respectively. Resistor R 36 The other end is grounded, operational amplifier OP 12 The inverting input terminal is connected to resistor R respectively. 37 and R 40 One end is connected to the resistor R. 37 The other end is grounded, and the resistor R 40 The other end is connected to the operational amplifier OP. 12 Connect the output terminal of the operational amplifier OP to the output terminal. 12The output terminal serves as the output terminal of the third adder unit. The function of the third adder unit is to sum the voltages of the third, fourth, and fifth voltage-controlled units and apply the sum to one input terminal of the fourth adder unit. The fourth adder unit includes an operational amplifier (OP). 15 Resistance R 43 Resistance R 46 Resistance R 47 Resistance R 49 Resistance R 50 Resistance R 51 Operational amplifier (OP) 15 The non-inverting input terminal is connected to resistor R respectively. 43 Resistance R 46 Resistance R 47 and resistance R 49 One end is connected to the resistor R. 43 Resistance R 46 Resistance R 47 The other end serves as the input terminal of the addition unit, and the resistor R 49 The other end is grounded, operational amplifier OP 15 The inverting input terminal is connected to resistor R respectively. 50 and resistance R 51 One end is connected to the resistor R. 50 The other end is grounded, and the resistor R 51 The other end is connected to the operational amplifier OP. 15 Connect the output terminal of the operational amplifier OP to the output terminal. 15 The output terminal serves as the output terminal of the fourth adder unit. The function of the fourth adder unit is to sum the output voltages of the first and second proportional amplifiers and the output voltage of the third adder unit, and use this sum as the suppression voltage applied to the input terminal of the first adder unit in the voltage control circuit I.

[0053] The first proportional amplifier includes the operational amplifier OP. 13 Resistance R 39 and resistance R 42 Operational amplifier (OP) 13 The inverting input terminal is connected to resistor R respectively. 39 and resistance R 42 One end is connected to the resistor R. 39 The other end is the input terminal of the first proportional amplifier and the voltage-controlled switch S. 10 The second contact is connected, and the resistor R 42 The other end is connected to the operational amplifier (OP). 13 Connect the output terminal of the operational amplifier OP to the output terminal. 13 The non-inverting input terminal is grounded, and the operational amplifier OP... 13The output terminal serves as the output terminal of the first proportional amplifier and is connected to the resistor R of the fourth adder unit. 46 The other end is connected. The function of the first proportional amplifier is to proportionally calculate the output voltage of the third voltage-controlled unit and then output it to the input terminal of the fourth adder unit. The second proportional amplifier includes an operational amplifier OP. 14 Resistance R 41 and resistance R 44 Operational amplifier (OP) 14 The inverting input terminal is connected to resistor R respectively. 41 and resistance R 44 One end is connected to the resistor R. 41 The other end is the input terminal of the second proportional amplifier and the voltage-controlled switch S. 11 The second contact is connected, and the resistor R 44 The other end is connected to the operational amplifier (OP). 14 Connect the output terminal of the operational amplifier OP to the output terminal. 14 The non-inverting input terminal is grounded, and the operational amplifier OP... 14 The output terminal of the second proportional amplifier is connected to the input terminal of the fourth adder unit. The function of the second proportional amplifier is to perform proportional calculation on the output voltage of the fifth voltage-controlled unit and then output it to the input terminal of the fourth adder unit.

[0054] like Figure 4 As shown, feedback module I includes resistor R 35 Resistance R 38 Memristor M4, memristor M5, NMOS transistor T2, NMOS transistor T3, DC voltage source V 16 DC voltage source V 17 Resistance R 45 Resistance R 48 The second comparator and the third comparator are connected. The input of the second comparator is connected to the output of the mathematical operation unit ABM4, and the output of the second comparator is connected to the gate of NMOS transistor T2. The drain of NMOS transistor T2 is connected to the DC voltage source V. 16 The positive terminal is connected, and the DC voltage source V 16 The negative terminal is grounded, and the source of NMOS transistor T2 is connected to resistor R. 45 One end is connected to the positive terminal of memristor M4, and the resistor R 45 The other end is grounded, and the negative terminal of memristor M4 is connected to resistor R. 35 and pressure control switch S 10 Connect the positive input terminal, resistor R 35 The other end is grounded, and the voltage-controlled switch S 10 The inverting input is grounded. The input of the third comparator is connected to the output of the mathematical operation unit ABM4, and the output of the third comparator is connected to the gate of NMOS transistor T3. The drain of NMOS transistor T3 is connected to the DC voltage source V. 17The positive terminal is connected, and the DC voltage source V 17 The negative terminal is grounded, and the source of NMOS transistor T3 is connected to resistor R. 48 Connect the positive terminal of memristor M5, and resistor R 48 The other end is grounded, and the negative terminal of memristor M5 is connected to resistor R. 38 and pressure control switch S 11 Connect the positive input terminal, resistor R 38 The other end is grounded, and the voltage-controlled switch S 11 The inverting input is grounded. Feedback module I applies a feedback signal to inhibition module I based on the synaptic weights in synaptic neuron circuit II, thereby changing its output inhibition voltage. Memristor M4 and resistor R... 35 And memristor M5, resistor R 38 They all form a voltage divider circuit, which acts as a buffer.

[0055] The second comparator includes an operational amplifier (OP). 16 and DC voltage source V 18 DC voltage source V 18 The positive terminal and the operational amplifier OP 16 Connect the non-inverting input terminal to the DC voltage source V. 18 The negative terminal is grounded, and the operational amplifier OP... 16 The inverting input terminal is used as the comparator input terminal, and the operational amplifier OP... 16 The output terminal of the first comparator is used as the output terminal of the second comparator. The second comparator compares the output voltage of the mathematical operation unit ABM1 with the voltage V. 18 Compare, if it is less than voltage V 18 The output is high if the output is low, and low otherwise. The third comparator includes an operational amplifier (OP). 17 and DC voltage source V 19 DC voltage source V 19 The positive terminal and the operational amplifier OP 17 Connect the non-inverting input terminal to the DC voltage source V. 19 The negative terminal is grounded, and the operational amplifier OP... 17 The inverting input terminal is used as the comparator input terminal, and the operational amplifier OP... 17 The output terminal of the first comparator is used as the output terminal of the comparator. The third comparator compares the output voltage of the mathematical operation unit ABM4 with the voltage V. 19 Compare, if it is less than voltage V 19 If the output is high, it will output a high level; otherwise, it will output a low level.

[0056] like Figure 5As shown, the emotion module includes a signal judgment circuit, a ninth voltage control unit, NOT gate D6, a tenth voltage control unit, an eleventh voltage control unit, NOT gate D7, a twelfth voltage control unit, a first synaptic neuron circuit, a second synaptic neuron circuit, a seventh addition unit, an eighth comparator, a ninth comparator, and a ninth logic unit. The input signal terminal N4 is connected to the input terminal of the signal judgment circuit. The output terminal of the signal judgment circuit is connected to the input terminals of the ninth voltage control unit, NOT gate D6, the eleventh voltage control unit, and NOT gate D7, respectively. The output terminal of NOT gate D6 is connected to the input terminal of the tenth voltage control unit, and the output terminal of NOT gate D7 is connected to the input terminal of the twelfth voltage control unit. The output terminals of the ninth and tenth voltage control units are both connected to the first synaptic neuron circuit. The circuit is connected to the input terminals of the multi-element circuit. The output terminals of the eleventh and twelfth voltage control units are both connected to the input terminals of the second synaptic neuron circuit. The output terminals of the first and second synaptic neuron circuits are both connected to the input terminals of the seventh addition unit. The output terminal of the seventh addition unit is connected to the input terminals of the eighth and ninth comparators, respectively. The output terminal of the eighth comparator is connected to the input terminals of the third, seventh, and ninth logic units, respectively. The ninth comparator is connected to the input terminals of the fourth, eighth, and ninth logic units, respectively. The output terminal of the ninth logic unit is connected to the input terminals of the fifth and sixth logic units, respectively.

[0057] The signal judgment circuit includes a sixth comparator and a seventh comparator. The inputs of both the sixth and seventh comparators are connected to the input signal terminal N4. The output of the sixth comparator is connected to the input of the ninth voltage control unit and the input of the NOT gate D6, respectively. The output of the seventh comparator is connected to the input of the eleventh voltage control unit and the input of the NOT gate D7, respectively. The function of the signal judgment module is to determine the signal type using the sixth and seventh comparators, and then control the on / off states of the ninth, tenth, eleventh, and twelfth voltage control units, thereby changing the voltage applied to the first and second synaptic neuron circuits and controlling the generation and recovery of emotions.

[0058] The first synaptic neuron circuit includes memristor M2 and resistor R. 25 Operational amplifier OP8, mathematical operation unit ABM2, and memristor M2 are connected. The positive terminal of memristor M2 is connected to the output of the ninth voltage-controlled unit, the output of the tenth voltage-controlled unit, and one input of mathematical operation unit ABM2. The negative terminal of memristor M2 is connected to resistor R. 25 One end is connected to the inverting input of operational amplifier OP8, and resistor R 25The other end is connected to the output of operational amplifier OP8. The non-inverting input of operational amplifier OP8 is grounded. The output of operational amplifier OP8 is connected to the other input of mathematical operation unit ABM2. The output of mathematical operation unit ABM2 is connected to the input of the seventh addition unit. Memristor M2, operational amplifier OP8, and mathematical operation unit ABM2 together form a resistance detection unit. The output of this unit represents the resistance change of memristor M2. The second synaptic neuron circuit includes memristor M3 and resistor R. 26 Operational amplifier (OP) 11 The mathematical operation unit ABM3 has its positive terminal connected to the output terminals of the eleventh and twelfth voltage-controlled units and one input terminal of the mathematical operation unit ABM3, respectively. The negative terminal of the memristor M3 is connected to the resistor R. 26 and operational amplifier OP 11 The inverting input terminal is connected to the other end of resistor R26, and the other end of resistor R26 is connected to the operational amplifier OP. 11 Connect the output terminal of the operational amplifier OP to the output terminal. 11 The non-inverting input terminal is grounded, and the operational amplifier OP... 11 The output terminal of the mathematical operation unit ABM3 is connected to another input terminal of the mathematical operation unit ABM3, and the output terminal of the mathematical operation unit ABM3 is connected to the input terminal of the seventh addition operation unit.

[0059] The ninth voltage control unit includes a voltage control switch S3, a DC voltage source V7, and a resistor R. 16 The positive input terminal of the voltage-controlled switch S3 is connected to the output terminal of the sixth comparator, and the first contact of the voltage-controlled switch S3 is connected to the resistor R. 16 The voltage-controlled switch S3 is connected to the input terminal of the first synaptic neuron circuit. Its second contact is connected to the positive terminal of the DC voltage source V7, while the negative terminal of V7 is grounded. The inverting input terminal of the voltage-controlled switch S3 is also grounded. The ninth voltage-controlled unit outputs the voltage of power supply V7 from the first contact of the voltage-controlled switch S3 when the output voltage of the sixth comparator exceeds the threshold voltage of the voltage-controlled switch S3. The tenth voltage-controlled unit includes a voltage-controlled switch S4, a DC voltage source V8, and a resistor R. 17 The positive input terminal of the voltage-controlled switch S4 is connected to the output terminal of the NOT gate D6, and the first contact of the voltage-controlled switch S4 is connected to the resistor R. 17 The first voltage-controlled unit is connected to the input terminal of the first synaptic neuron circuit. The second contact of the voltage-controlled switch S4 is connected to the positive terminal of the DC voltage source V8, the negative terminal of the DC voltage source V8 is grounded, and the inverting input terminal of the voltage-controlled switch S4 is grounded. The tenth voltage-controlled unit outputs the voltage of power supply V8 from the first contact of the voltage-controlled switch S4 when the output voltage of the NOT gate D6 exceeds the threshold voltage of the voltage-controlled switch S4. The eleventh voltage-controlled unit includes a voltage-controlled switch S5, a DC voltage source V9, and a resistor R. 18The positive input terminal of the voltage-controlled switch S5 is connected to the output terminal of the seventh comparator, and the first contact of the voltage-controlled switch S5 is connected to the resistor R. 18 The second contact of the voltage-controlled switch S5 is connected to the input terminal of the second synaptic neuron circuit. The negative terminal of the DC voltage source V9 is grounded, and the inverting input terminal of the voltage-controlled switch S5 is grounded. The eleventh voltage-controlled unit outputs the voltage of the power supply V9 ​​through the first contact of the voltage-controlled switch S5 when the output voltage of the seventh comparator is greater than the threshold voltage of the voltage-controlled switch S5. The twelfth voltage-controlled unit includes the voltage-controlled switch S6 and the DC voltage source V9. 10 Resistance R 19 The positive input terminal of the voltage-controlled switch S6 is connected to the output terminal of the NOT gate D7, and the first contact of the voltage-controlled switch S6 is connected to the resistor R. 19 The circuit input terminal of the second synaptic neuron is connected, and the second contact of the voltage-controlled switch S6 is connected to the DC voltage source V. 10 Positive terminal connected, DC voltage source V 10 With the negative terminal grounded and the inverting input of voltage-controlled switch S6 grounded, the twelfth voltage-controlled unit activates the first contact of voltage-controlled switch S6 to output power V when the output voltage of NOT gate D7 exceeds the threshold voltage of voltage-controlled switch S6. 10 The voltage.

[0060] The seventh addition unit includes operational amplifier OP7 and resistor R. 20 -R 24 The non-inverting input terminal of operational amplifier OP7 is connected to resistor R. 20 Resistance R 21 and resistance R 23 One end is connected to the resistor R. 20 Resistance R 23 The other end serves as the input terminal of the addition unit, and the resistor R 21 The other end is grounded, and the inverting input of operational amplifier OP7 is connected to resistor R. 22 and R 24 One end is connected to the resistor R. 22 The other end is grounded, and the resistor R 24 The other end is connected to the output of operational amplifier OP7, which serves as the output of the seventh adder unit. The function of the seventh adder unit is to sum the output voltages of mathematical operation units ABM2 and ABM3 and apply them to the inputs of the eighth and ninth comparators.

[0061] The sixth comparator includes an operational amplifier OP5 and a DC voltage source V5. The positive terminal of the DC voltage source V5 is connected to the inverting input of the operational amplifier OP5, and the negative terminal of the DC voltage source V5 is grounded. The non-inverting input of the operational amplifier OP5 serves as the comparator input, and the output of the operational amplifier OP5 serves as the output of the sixth comparator. The seventh comparator includes an operational amplifier OP6 and a DC voltage source V6. The positive terminal of the DC voltage source V6 is connected to the non-inverting input of the operational amplifier OP6, and the negative terminal of the DC voltage source V6 is grounded. The inverting input of the operational amplifier OP6 serves as the comparator input, and the output of the operational amplifier OP6 serves as the output of the seventh comparator. The sixth and seventh comparators jointly compare the input emotional stimulus N4 with the voltage of their respective voltage sources. When the emotional stimulus signal N4 is greater than V5, the sixth comparator outputs a high level, representing a positive emotional stimulus. When the emotional stimulus signal N4 is less than V6, the seventh comparator outputs a high level, representing a negative emotional stimulus. In all other cases, it outputs a low level, thus determining the type of emotional stimulus. The eighth comparator includes operational amplifier OP9 and DC voltage source V. 11 DC voltage source V 11 The positive terminal is connected to the inverting input terminal of operational amplifier OP9, and the DC voltage source V 11 The negative terminal is grounded, the non-inverting input of operational amplifier OP9 serves as the comparator input, and the output of operational amplifier OP9 serves as the output of the eighth comparator. The ninth comparator includes operational amplifier OP9. 10 and DC voltage source V 12 DC voltage source V 12 The positive terminal and the operational amplifier OP 10 Connect the non-inverting input terminal to the DC voltage source V. 12 The negative terminal is grounded, and the operational amplifier OP... 10 The inverting input terminal is used as the comparator input terminal, and the operational amplifier OP... 10 The output of the seventh comparator is used as the output of the ninth comparator. The eighth and ninth comparators together compare the output voltage of the seventh adder with their respective voltage source voltages. When the output voltage is greater than V... 11 When the eighth comparator outputs a high level, it indicates that the circuit is in a sad state. When the output voltage is less than V... 12 When the circuit is in a happy emotional state, the ninth comparator outputs a high level, indicating that the circuit is in a happy emotional state. In other cases, it outputs a low level, indicating that the circuit is in an emotionless state. This is used to determine the type of emotion generated.

[0062] The ninth logic unit includes NOT gate D8, NOT gate D9, and AND gate D. 10 The input of NOT gate D8 is connected to the output of the eighth comparator, and the output of NOT gate D8 is connected to the output of AND gate D. 10The first input terminal is connected to the first input terminal, the input terminal of NOT gate D9 is connected to the output terminal of the eighth comparator, and the output terminal of NOT gate D9 is connected to the output terminal of AND gate D. 10 Connected to the second input terminal, AND gate D 10 The output terminals are connected to the input terminals of the fifth and sixth logic units, respectively. When both the eighth and ninth comparators output low levels, the ninth logic unit outputs a high level, indicating that the circuit is in a neutral state; otherwise, it outputs a low level.

[0063] Learning module II includes voltage control circuit II and synaptic neuron circuit II. Input signal terminals N1 and N3 are connected to the other input terminal of voltage control circuit II, respectively. The output terminal of voltage control circuit II is connected to the input terminal of synaptic neuron circuit II. Synaptic neuron circuit II outputs feedback signal F2 and a signal OUT2 representing learning completion. Feedback signal F2 is connected to the input terminal of feedback module I. Voltage control circuit II includes a tenth logic unit, an eleventh logic unit, a thirteenth voltage control unit, a fourteenth voltage control unit, and an eighth addition unit. The inputs of the tenth and eleventh logic units are connected to input signals N1 and N3, respectively. The output of the tenth logic unit is connected to the input of the thirteenth voltage control unit, and the output of the eleventh logic unit is connected to the input of the fourteenth voltage control unit. The outputs of the thirteenth and fourteenth voltage control units are each connected to one input terminal of the eighth addition unit. The output terminal of suppression module II is connected to the other input terminal of the eighth addition unit. The tenth logic unit outputs a high level when a negative conditional stimulus signal N3 is input alone, thereby activating the thirteenth voltage control unit, which outputs voltage V. 27 The eighth addition unit and the eleventh logic unit output a high level when both the unconditioned stimulus signal N1 and the negative conditioned stimulus signal N3 are simultaneously input, thereby activating the fourteenth voltage control unit, which outputs voltage V. 28 Up to the eighth addition unit; the output of the eighth addition unit is V. op24 =V 27 +V 28 +U5, where U5 is the suppression voltage output by suppression module II. The output of voltage control circuit II is connected to the input of synaptic neuron circuit II, used to change the synaptic weights in synaptic neuron circuit II. Synaptic neuron circuit II includes memristor M8 and resistor R. 88 Operational amplifier (OP) 26 Mathematical operation unit ABM4, ninth addition unit, tenth comparator, NMOS transistor T6, DC voltage source V 30 Resistance R 94 NOT gate D 20 The positive terminal of memristor M8 is connected to the output terminal of voltage control circuit II and one input terminal of mathematical operation unit ABM4, while the negative terminal of memristor M8 is connected to operational amplifier OP.26 The inverting input terminal and resistor R 88 Connected, operational amplifier OP 26 The non-inverting input terminal is grounded, and the resistor R 88 With operational amplifier OP 26 The output terminal of the NOT gate is connected to another input terminal of the mathematical operation unit ABM4. The output terminal of the mathematical operation unit ABM4 is connected to one input terminal of the ninth addition unit and one input terminal of the suppression module I. 20 The input terminal of the NOT gate is connected to the input signal N3. 20 The output terminal of the is connected to the other input terminal of the ninth adder unit. The output terminal of the ninth adder unit is connected to the input terminal of the tenth comparator. The output terminal of the tenth comparator is connected to the gate of the NMOS transistor T6. The DC voltage source V 30 The negative terminal is grounded, and the positive terminal is connected to the source of NMOS transistor T6. Resistor R... 94 Connected to the drain of NMOS transistor T6, resistor R 94 The other end is grounded. The output of the mathematical operation unit ABM4 is Vout = -V IN2 / V IN1 =M8 / 1000, when the voltage control circuit II outputs V op24 When the positive threshold voltage of memristor M8 is reached, the resistance of memristor M8 decreases, and therefore the output of ABM4 also decreases. When its output is less than the negative threshold voltage of memristor M8, the resistance of memristor M8 increases, and therefore the output of ABM4 also increases. Therefore, the output of the mathematical operation unit ABM4 reflects the change in the resistance of memristor M8. The output of the ninth addition unit is V. op26 =V ABM4 +V D20 Where V D20 NOT gate D 20 The output voltage of the NOT gate D is such that when the input signal N3 is high, the NOT gate D... 20 The output voltage is 0V. When the input signal N3 is low, the NOT gate D... 20 The output voltage is 5V, which ensures that learning module II will not output a high level when there is no negative condition input. The output of the ninth adder unit is connected to the DC voltage source V in the tenth comparator. 29 The comparison is performed to determine whether the synaptic weight corresponding to the negative condition stimulus has risen above a threshold. If it is above the threshold, the tenth comparator outputs a high level, the gate-source voltage difference of NMOS transistor T6 is above the threshold, and it is in the on state, outputting voltage V. 30 To or Gate D 21 This indicates that learning is complete. The tenth logic unit includes NOT gates D. 17 AND gate D 18 The eleventh logic unit includes AND gate D.19 The thirteenth pressure control unit includes a pressure control switch S. 17 DC voltage source V 27 and resistance R 77 The fourteenth pressure control unit includes a pressure control switch S. 18 DC voltage source V 28 and resistance R 78 The eighth addition unit includes an operational amplifier (OP). 24 Resistance R 79 -R 83 The ninth adder unit is used to sum the output voltages of the thirteenth and fourteenth voltage control units and the suppression voltage output by the suppression module II, and apply them to the synaptic neuron circuit II. 26 Resistance R 85 -R 89 Used to convert the output voltage of the mathematical operation unit ABM4 and the NOT gate D 20 The output voltages are summed and applied to the tenth comparator, which includes an operational amplifier (OP). 27 and DC voltage source V 29 Used to connect the output voltage of the mathematical operation unit with the DC voltage source V 29 The voltage is compared to determine whether the synaptic strength in the synaptic neuron circuit II has risen above the threshold. If it is above the threshold, a high level is output; otherwise, a low level is output.

[0064] Suppression module II includes a sixth logic unit, a seventh logic unit, an eighth logic unit, a sixth voltage control unit, a seventh voltage control unit, an eighth voltage control unit, and a voltage control switch S. 15 Pressure control switch S 16 Resistance R 58 Resistance R 59 The system comprises a fifth addition unit, a third proportional amplifier, a fourth proportional amplifier, and a sixth addition unit. The input signals N1-N3 and the output of the emotion module are all connected to the input terminals of the sixth, seventh, and eighth logic units. The output terminal of the sixth logic unit is connected to the input terminal of the sixth pressure control unit. The output terminal of the sixth pressure control unit is connected to both the input terminal of the fifth addition unit and the pressure control switch S. 15 The first contact is connected, and the pressure-controlled switch S 15 The second contact is connected to resistor R. 58 One end is connected to the input terminal of the third proportional amplifier, and resistor R 58The other end is grounded. The output of the third proportional amplifier is connected to the input of the sixth adder unit. The output of the seventh logic unit is connected to the input of the seventh voltage control unit. The output of the seventh voltage control unit is connected to the input of the fifth adder unit. The output of the eighth logic unit is connected to the input of the eighth voltage control unit. The output of the eighth voltage control unit is connected to both the input of the fifth adder unit and the voltage control switch S. 16 The second contact is connected to the voltage-controlled switch S. 16 The first contact is connected to resistor R. 59 One end is connected to the input terminal of the fourth proportional amplifier, and resistor R 59 The other end is grounded. The output of the fourth proportional amplifier is connected to the input of the sixth adder unit, and the output of the fifth adder unit is connected to the input of the sixth adder unit. The output of the sixth adder unit is the output of the suppression module II. The voltage-controlled switch S... 15 and S 16 Used to control the on / off state of its branch, thereby controlling the suppression voltage output by suppression module II. This is achieved using voltage-controlled switch S. 15 For example, when it is in the off state and the circuit is in an emotionless state, the output voltage of the sixth addition unit is V. 20 That is, the suppression voltage output by suppression module II is V. 20 When it is in the conducting state and the circuit is in an emotionless state, the output voltage of the sixth addition unit is V. 20 +V 20 *(-R) 67 / R 64 That is, the suppression voltage output by suppression module II becomes V. 20 +V 20 *(-R) 67 / R 64 The sixth logic unit includes an AND gate D. 14 And the three-input AND gate D5, the seventh logic unit includes AND gate D 15 And the three-input AND gate D5, the eighth logic unit includes AND gate D 16 The third input AND gate D5, and the sixth voltage control unit include a voltage control switch S. 12 DC voltage source V 20 and resistance R 52 The seventh pressure control unit includes a pressure control switch S. 13 DC voltage source V 21 and resistance R 53 The eighth pressure control unit includes a pressure control switch S. 14 DC voltage source V 22 and resistance R 54 The third proportional amplifier includes the operational amplifier OP. 19 Resistance R 64 and resistance R 67Used to amplify voltage-controlled switch S 15 The second contact outputs voltage, and the fourth proportional amplifier includes an operational amplifier (OP). 20 Resistance R 66 and resistance R 69 Used to amplify voltage-controlled switch S 16 The second contact outputs voltage, and the fifth adder unit includes an operational amplifier (OP). 18 Resistance R 55 Resistance R 56 Resistance R 57 Resistance R 61 Resistance R 62 Resistance R 65 It is used to sum the output voltages of the sixth, seventh, and eighth voltage control units and apply them to the sixth adder unit. The sixth adder unit includes an operational amplifier (OP). 21 Resistance R 68 Resistance R 71 Resistance R 72 Resistance R 74 Resistance R 75 Resistance R 76 It is used to sum the output voltages of the fifth addition unit and the third and fourth proportional amplifiers and apply them as a suppression voltage to the voltage control circuit II.

[0065] Feedback module II includes resistor R 60 Resistance R 63 Memristor M6, memristor M7, NMOS transistor T4, NMOS transistor T5, DC voltage source V 23 DC voltage source V 24 Resistance R 70 Resistance R 73 The fourth comparator and the fifth comparator are connected. The input of the fourth comparator is connected to the output of the mathematical operation unit ABM1, and the output of the fourth comparator is connected to the gate of NMOS transistor T4. The drain of NMOS transistor T4 is connected to the DC voltage source V. 23 The positive terminal is connected, and the DC voltage source V 23 The negative terminal is grounded, and the source of NMOS transistor T4 is connected to resistor R. 70 Connect the positive terminal of memristor M6, and resistor R 70 The other end is grounded, and the negative terminal of memristor M6 is connected to resistor R. 60 Resistor and voltage-controlled switch S 15 Connect the positive input terminal, resistor R 60 The resistor is grounded, and the voltage-controlled switch S is connected. 15 The inverting input is grounded. The input of the fifth comparator is connected to the output of the mathematical operation unit ABM1. The output of the fifth comparator is connected to the gate of NMOS transistor T5. The drain of NMOS transistor T5 is connected to the DC voltage source V.24 The positive terminal is connected, and the DC voltage source V 24 The negative terminal is grounded, and the source of NMOS transistor T5 is connected to resistor R. 73 The resistor and memristor M7 are connected to the positive terminal, and the resistor R 73 The other end is grounded, and the negative terminal of memristor M7 is connected to resistor R. 63 Resistor and voltage-controlled switch S 16 Connect the positive input terminal, resistor R 63 The other end is grounded, and the voltage-controlled switch S 16 The inverting input is grounded. Feedback module II applies a feedback signal to inhibition module II based on the synaptic weights in synaptic neuron circuit I, thereby changing its output inhibition voltage. Memristor M6 and resistor R... 60 And memristor M7, resistor R 63 Each of these components forms a voltage divider circuit, serving as a buffer. The fourth comparator includes an operational amplifier (OP). 22 and DC voltage source V 25 DC voltage source V 25 The positive terminal and the operational amplifier OP 22 Connect the non-inverting input terminal to the DC voltage source V. 25 The negative terminal is grounded, and the operational amplifier OP... 22 The inverting input terminal is used as the comparator input terminal, and the operational amplifier OP... 22 The output of the first comparator is used as the comparator output. The fifth comparator includes an operational amplifier (OP). 23 and DC voltage source V 26 DC voltage source V 26 The positive terminal and the operational amplifier OP 23 Connect the non-inverting input terminal to the DC voltage source V. 26 The negative terminal is grounded, and the operational amplifier OP... 23 The inverting input terminal is used as the comparator input terminal, and the operational amplifier OP... 23 The output terminal is used as the comparator output terminal. The fourth and fifth comparators both compare the output voltage of the mathematical operation unit ABM1 with the voltage of their respective voltage sources. When the voltage is less than V... 25 When the voltage is less than V, the fourth comparator outputs a high level. 26 When the signal is high, the fifth comparator outputs a high level; otherwise, it outputs a low level.

[0066] Figure 6 This is a simulation result of learning two conditioned stimuli individually. N1 is the unconditioned stimulus, N2 is the positive conditioned stimulus, N3 is the negative conditioned stimulus, M1 is the change in the resistance of memristor M1 (the reciprocal of which represents the synaptic weight of the positive conditioned stimulus), M8 is the change in the resistance of memristor M8 (the reciprocal of which also represents the synaptic weight of the positive conditioned stimulus), and OUT is the output drooling signal. Figure 6It can be seen that 0-6s is the initial testing process, during which only the unconditioned stimulus can cause drooling; neither of the two conditioned stimuli, appearing alone, can cause drooling. 6-16s is the learning process of the positive conditioned stimulus alone; the positive conditioned stimulus and the unconditioned stimulus signal appear together, causing the memristor M1 resistance to decrease, indicating that the synaptic weight corresponding to the positive conditioned stimulus increases. After five pulses of learning, the M1 resistance decreases from 4.9 to 1.5. 16-25s is the learning process of the negative conditioned stimulus alone; similarly, after five pulses of learning, the M8 resistance decreases from 4.9 to 1.5. 26-30s is the second testing process; after separate learning, both conditioned stimuli, appearing alone, can cause drooling.

[0067] Figure 7 This is a simulation result of the generation and recovery of happy and sad emotions, where N4 is the emotional stimulus, -1V and +1V represent negative and positive emotional stimuli, respectively, and V... M2 V is the voltage applied across the memristor M2. M3 The voltage applied across memristor M3 is M2, the resistance of memristor M2 changes, the resistance of memristor M3 changes, U1 is the output voltage of the emotion module, i.e., the output voltage of operational amplifier OP9, representing the happy emotional state, and U2 is the other output voltage of the emotion module, i.e., the voltage of operational amplifier OP9. 10 The output voltages of U1 and U2 represent the state of sadness. When both U1 and U2 are zero, it represents the state of no emotion. From 0 to 6 seconds, the process of generating a happy emotion occurs. After 1 second of positive emotional stimulation, U1 outputs a high level, and the circuit switches from the state of no emotion to the state of happiness. From 6 to 12 seconds, the process of recovering a happy emotion occurs. After 1 second of the positive emotional stimulation disappears, U1 outputs a low level, and the circuit returns from the state of happiness to the state of no emotion. From 12 to 20 seconds, the process of generating a sad emotion occurs. After 2 seconds of negative emotional stimulation, U2 outputs a high level, and the circuit switches from the state of no emotion to the state of sadness. From 20 to 28 seconds, the process of recovering a sad emotion occurs. After 2 seconds of the negative emotional stimulation disappears, U2 outputs a low level, and the circuit returns from the state of sadness to the state of no emotion. In other words, the generation and recovery speeds of happy emotions are relatively fast, while the generation and recovery speeds of sad emotions are relatively slow.

[0068] Figure 8This is a simulation result of mutual occlusion of two conditioned stimuli and recovery from occlusion under an emotionless state. N1 represents the unconditioned stimulus, N2 and N3 represent the positive and negative conditioned stimuli, respectively. M1 represents the change in the resistance of memristor M1, with the reciprocal of M1 representing the synaptic weight of the positive conditioned stimulus. M8 represents the change in the resistance of memristor M8, with the reciprocal of M8 representing the synaptic weight of the negative conditioned stimulus. OUT represents the output drooling signal. The initial test period is 0-6 seconds; only the unconditioned stimulus can induce drooling. Neither of the two conditioned stimuli, appearing alone, will induce drooling. The masking process lasts from 6 to 18 seconds. At 16 seconds, the resistance values ​​of both synapses decrease to 2.5. From 16 to 18 seconds, the resistance values ​​remain unchanged, indicating that the synaptic strength of the two synapses cannot be further increased, reaching a maximum of 2.5. Since 2.5 is greater than the 1.5 corresponding to the individual learning process, it indicates that the two conditioned stimuli are mutually masking. The second test lasts from 18 to 22 seconds. After the masking process, both conditioned stimuli can still cause drooling. The process from 22 to 32 seconds is the recovery process of the positive conditioned stimulus from masking. Removing the negative conditioned stimulus allows the positive conditioned stimulus to continue pairing with the unconditioned stimulus alone, which can give the masked positive conditioned stimulus sufficient associative strength. The process from 32 to 42 seconds is the recovery process of the negative conditioned stimulus from masking. Similar to the previous stage, removing the positive conditioned stimulus allows the negative conditioned stimulus to continue pairing with the unconditioned stimulus alone, which can give the masked negative conditioned stimulus sufficient associative strength. The third test lasts from 42 to 46 seconds. Both conditioned stimuli can still cause drooling after the recovery from masking.

[0069] Figure 9(a) shows the simulation results of two-conditional stimulus masking and recovery from masking under positive emotion. N1 is the unconditioned stimulus, N2 and N3 are the positive and negative conditioned stimuli respectively, N4 is the emotional stimulus, U1 is the output voltage of the emotion module representing the happy emotional state, M1 is the resistance change of memristor M1, M8 is the resistance change of memristor M8, and OUT is the output drooling signal. The initial test period is 0-6s, during which only the unconditioned stimulus can cause drooling; neither of the two conditioned stimuli, appearing alone, will cause drooling. The period from 6 to 8 seconds represents the positive emotion generation process. One second after the appearance of the positive emotion stimulus, the positive emotion of happiness is generated. The period from 8 to 20 seconds represents the masking process. At 16 seconds, the memristor M8 resistance decreases to 3.25, and the memristor M1 resistance decreases to 1.75. From 16 to 18 seconds, the memristor M8 resistance increases, indicating that the synaptic strength of the synapse corresponding to the negative conditioned stimulus cannot be further increased. The value of 3.25 is greater than the value of 1.5 corresponding to the learning process alone, indicating that the negative conditioned stimulus is masked by the positive conditioned stimulus. From 16 to 18 seconds, the memristor M1 resistance continues to decrease, but at 16 seconds, the value of 1.75 is greater than the value of 1.5 corresponding to the learning process alone. This indicates that the positive conditioned stimulus is also affected by the negative conditioned stimulus to some extent, and the learning speed slows down, which is consistent with the cue competition effect. The second test lasted 20-24 seconds. After the masking process, both conditioned stimuli could induce salivation. The second test lasted 24-34 seconds. The negative conditioned stimulus was restored from masking. The positive conditioned stimulus with higher salience was removed, and the negative conditioned stimulus was paired with the unconditioned stimulus alone. This allowed the masked negative conditioned stimulus to obtain sufficient associative strength. The third test lasted 34-38 seconds. Both conditioned stimuli could still induce salivation after being restored from masking. The fourth test lasted 38-41 seconds. The positive emotional stimulus disappeared for 1 second, and the emotional state returned from happy to a neutral state.

[0070] Figure 9(ii) Simulation results of two-conditional stimulus masking and recovery under negative emotions, where N1 is the unconditioned stimulus, N2 and N3 are the positive and negative conditioned stimuli respectively, N4 is the emotional stimulus, U1 is the output voltage of the emotion module representing the happy emotional state, M1 is the resistance change of memristor M1, M8 is the resistance change of memristor M8, and OUT is the output drooling signal. 0-6s is the initial test process; only the unconditioned stimulus can cause drooling, and neither of the two conditioned stimuli alone will cause drooling. The period from 6 to 8 seconds represents the generation of negative emotions. Two seconds after the appearance of the negative emotion stimulus, the sadness emotion representing negative emotions is generated. The period from 8 to 20 seconds represents the masking process. At 16 seconds, the memristor M1 resistance decreases to 3.25, and the memristor M8 resistance decreases to 1.75. From 16 to 18 seconds, the memristor M1 resistance increases, indicating that the synaptic strength of the synapse corresponding to the positive conditioned stimulus cannot be further increased. The value of 3.25 is greater than the value of 1.5 corresponding to the learning process alone, indicating that the positive conditioned stimulus is masked by the negative conditioned stimulus. From 16 to 18 seconds, the memristor M8 resistance continues to decrease, but at 16 seconds, the value of 1.75 is greater than the value of 1.5 corresponding to the learning process alone. This indicates that the negative conditioned stimulus is also affected by the positive conditioned stimulus to some extent, and the learning speed slows down, which is consistent with the cue competition effect. The second test lasted 20-24 seconds. After the masking process, both conditioned stimuli could induce salivation. The second test lasted 24-34 seconds. The positive conditioned stimulus was restored from masking. The negative conditioned stimulus with higher salience was removed, and the positive conditioned stimulus was paired with the unconditioned stimulus alone. This allowed the masked negative conditioned stimulus to obtain sufficient associative strength. The third test lasted 34-38 seconds. Both conditioned stimuli could still induce salivation after being restored from masking. The fourth test lasted 38-42 seconds. The negative emotional stimulus disappeared for 2 seconds, and the emotional state returned from sadness to a state of no emotion.

[0071] Figure 10Figure 1 shows the simulation results of drooling caused by prolonged occlusion of two conditioned stimuli under positive emotion. N1 is the unconditioned stimulus, N2 and N3 are the positive and negative conditioned stimuli respectively, N4 is the emotional stimulus, U1 is the output voltage of the emotion module representing the happy emotional state, M1 and M8 are the resistance changes of memristor M1 and M8 respectively, and OUT is the output drooling signal. The initial test process (0-6s) shows that only the unconditioned stimulus can cause drooling. The positive emotion generation process (6-8s) occurs one second after the positive emotion stimulus appears, representing the happy emotional state. The occlusion process (8-18s) shows that after 18s, the resistance of memristor M8 drops to 3.25 ohms, and the resistance of memristor M1 drops to 1.75 ohms. The resistance of memristor M8 cannot decrease further, indicating that the negative conditioned stimulus is occluded by the positive conditioned stimulus. The test process after short-term occlusion (18-22s) shows that both conditioned stimuli can cause drooling, indicating that after short-term occlusion, the occluded stimulus can cause drooling. Saliva production continued from 22 to 58 seconds. Memristor M8 resistance increased while memristor M1 resistance decreased, indicating that as the intensity of the positive conditioned stimulus association further increased, its significance would further increase, and the degree of inhibition of the negative conditioned stimulus would further strengthen, leading to a decrease in its association intensity, which gradually decreased below the threshold. From 58 to 62 seconds, the test process after long-term masking was completed. Applying the negative conditioned stimulus alone could not induce saliva production, indicating that long-term masking caused blockage. From 62 to 65 seconds, the emotional recovery process was completed. The emotional state recovered 1 second after the disappearance of the positive emotional stimulus, and the emotional state returned from happy to a state of no emotion.

[0072] Figure 10Figure (II) shows the simulation results of drooling caused by prolonged occlusion of two conditioned stimuli under negative emotions. N1 is the unconditioned stimulus, N2 and N3 are the positive and negative conditioned stimuli respectively, N4 is the emotional stimulus, U1 is the output voltage of the emotion module representing the happy emotional state, M1 and M8 are the resistance changes of memristor M1 and M8 respectively, and OUT is the output drooling signal. The initial test process (0-6s) shows that only the unconditioned stimulus can cause drooling. The negative emotion generation process (6-8s) shows that 2 seconds after the negative emotion stimulus appears, the sad emotion is generated. The occlusion process (8-18s) shows that after 18s, the resistance of memristor M1 drops to 3.25 ohms, and the resistance of memristor M8 drops to 1.75 ohms. The resistance of memristor M1 cannot decrease further, indicating that the positive conditioned stimulus is occluded by the negative conditioned stimulus. The test process after short-term occlusion (18-22s) shows that both conditioned stimuli can cause drooling, indicating that after short-term occlusion, the occluded stimulus can cause drooling. Saliva production continued from 22 to 58 seconds. Memristor M1 resistance increased while memristor M8 resistance decreased, indicating that as the intensity of the negative conditioned stimulus association further increased, its significance would further increase, and the degree of inhibition on the positive conditioned stimulus would further strengthen, leading to a decrease in its association intensity, which gradually decreased below the threshold. From 58 to 62 seconds, the test process after long-term masking was completed. Applying the positive conditioned stimulus alone could not induce saliva production, indicating that long-term masking caused blockage. From 62 to 66 seconds, the emotional recovery process was completed. The emotional state recovered 2 seconds after the negative emotional stimulus disappeared, and the emotional state returned from sadness to an emotionless state.

[0073] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A memory neural network circuit with emotional consistency and masking effect, characterized in that, The system includes input signal terminals N1-N4, learning module I, emotion module, inhibition module I, feedback module I, inhibition module II, feedback module II, and learning module II. Input signal terminal N1, representing the unconditioned stimulus signal, is connected to the input terminals of learning module I, inhibition module I, inhibition module II, and learning module II, respectively. Input signal terminal N2, representing the positive conditioned stimulus signal, is connected to the input terminals of learning module I, inhibition module I, and inhibition module II, respectively. Input signal terminal N3, representing the negative conditioned stimulus signal, is connected to the input terminals of learning module II, inhibition module I, and inhibition module II, respectively. Emotion stimulus signal... The input signal terminal N4 is connected to the input terminal of the emotion module. The output terminal of the emotion module is connected to the input terminals of inhibition module I and inhibition module II, respectively. One output terminal of learning module II is connected to the input terminal of feedback module I. The output terminal of feedback module I is connected to the input terminal of inhibition module I. The output terminal of inhibition module I is connected to the input terminal of learning module I. One output terminal of learning module I is connected to the input terminal of feedback module II. The output terminal of feedback module II is connected to the input terminal of inhibition module II. The input signal terminal N1, another output terminal of learning module I, and another output terminal of learning module II are respectively connected to OR gate D. 21 The input terminal of the OR gate D 21 The output terminal outputs a signal indicating that learning is complete. Both learning module I and learning module II include a voltage control circuit and a synaptic neuron circuit. The input terminal of the voltage control circuit of learning module I is connected to the output terminal, input signal terminal N1, and input signal terminal N2 of inhibition module I, respectively. The input terminal of the voltage control circuit of learning module II is connected to the output terminal, input signal terminal N1, and input signal terminal N3 of inhibition module II, respectively. The output terminal of the voltage control circuit is connected to the input terminal of the synaptic neuron circuit. One output terminal of the synaptic neuron circuit outputs a feedback signal, and the other output terminal outputs a signal representing the completion of learning. One output terminal of the synaptic neuron circuit of learning module I is connected to the input terminal of feedback module II, and one output terminal of the synaptic neuron circuit of learning module II is connected to the input terminal of feedback module I. The other output terminals of the synaptic neuron circuits of both learning module I and learning module II are connected to an OR gate D. 21 Connect to the input terminal; Both feedback module I and feedback module II include a second memristor, a third memristor, a second NMOS transistor, a third NMOS transistor, a second comparator, and a third comparator. The feedback signal output by the synaptic neuron circuit of learning module I is connected to one input terminal of the second and third comparators of feedback module II, respectively. The feedback signal output by the synaptic neuron circuit of learning module II is connected to one input terminal of the second and third comparators of feedback module I, respectively. The other input terminal of the second comparator is connected to the positive terminal of the third voltage source. The output terminal of the second comparator is connected to the gate of the second NMOS transistor. The drain of the second NMOS transistor is connected to the positive terminal of the fifth voltage source. The source of the second NMOS transistor is connected to one end of the third resistor and the positive terminal of the second memristor, respectively. The negative terminal of the second memristor is connected to one end of the fourth resistor. The negative terminal of the second memristor is connected as an output terminal to one input terminal of suppression module I or suppression module II; the other input terminal of the third comparator is connected to the positive terminal of the fourth voltage source, the output terminal of the third comparator is connected to the gate of the third NMOS transistor, the drain of the third NMOS transistor is connected to the positive terminal of the sixth voltage source, the source of the third NMOS transistor is connected to one end of the fifth resistor and the positive terminal of the third memristor, the negative terminal of the third memristor is connected to one end of the sixth resistor, and the negative terminal of the third memristor is connected as an output terminal to the other input terminal of suppression module I or suppression module II; the negative terminals of the third, fourth, fifth, and sixth voltage sources, the other end of the third resistor, one end of the fourth resistor, the other end of the fifth resistor, and the other end of the sixth resistor are all grounded; The emotion module includes a signal judgment circuit, a ninth pressure control unit, a tenth pressure control unit, an eleventh pressure control unit, a twelfth pressure control unit, a first synaptic neuron circuit, a second synaptic neuron circuit, a seventh addition unit, an eighth comparator, a ninth comparator, and a ninth logic unit. The input signal terminal N4 is connected to the input terminal of the signal judgment circuit. The output terminal of the signal judgment circuit is connected to the input terminals of the ninth pressure control unit, NOT gate D6, the eleventh pressure control unit, and NOT gate D7, respectively. The output terminal of NOT gate D6 is connected to the input terminal of the tenth pressure control unit, and the output terminal of NOT gate D7 is connected to the input terminal of the twelfth pressure control unit. The output terminals of the ninth and tenth pressure control units are both connected to the input terminal of the first synaptic neuron circuit. The input terminals are connected, and the output terminals of the eleventh and twelfth voltage control units are both connected to the input terminals of the second synaptic neuron circuit. The output terminals of the first and second synaptic neuron circuits are both connected to the input terminals of the seventh addition unit. The output terminals of the seventh addition unit are connected to the input terminals of the eighth and ninth comparators, respectively. The output terminals of the eighth comparator are connected to the input terminals of the suppression module I, the suppression module II, and the ninth logic unit, respectively. The output terminals of the ninth comparator are connected to the input terminals of either the suppression module I or the suppression module II, and the ninth logic unit, respectively. The output terminals of the ninth logic unit are connected to the input terminals of both the suppression module I and the suppression module II. Both suppression module I and suppression module II include a third voltage control unit, a fourth voltage control unit, a fifth voltage control unit, a voltage control switch I, a voltage control switch II, a third addition operation unit, a first proportional amplifier, a second proportional amplifier, and a fourth addition operation unit. Input signal terminals N1, N2, and N3 are all connected to the input terminals of AND gate D5. The output terminal of AND gate D5 is connected to one input terminal of the first AND gate, the second AND gate, and the third AND gate, respectively. The other input terminal of the first AND gate in suppression module I and the other input terminal of the second AND gate in suppression module II are both connected to the first AND gate, the second AND gate, and the third AND gate. The outputs of the eight comparators are connected together. The other inputs of the first AND gate of suppression module II and the second AND gate of suppression module I are both connected to the output of the ninth comparator. The other input of the third AND gate is connected to the output of the ninth logic unit. The output of the first AND gate is connected to the input of the third voltage-controlled unit. The output of the third voltage-controlled unit is connected to the input of the third adder unit and the first contact of voltage-controlled switch I. The second contact of voltage-controlled switch I is connected to one end of the seventh resistor and the input of the first proportional amplifier. The positive input of voltage-controlled switch I... The input terminal is connected to the negative terminal of the second memristor of feedback module I or feedback module II; the inverting input terminal of voltage-controlled switch I and the other end of the seventh resistor are both grounded; the output terminal of the first proportional amplifier is connected to the input terminal of the fourth adder unit; the output terminal of the second AND gate is connected to the input terminal of the fourth voltage-controlled unit, and the output terminal of the fourth voltage-controlled unit is connected to the input terminal of the third adder unit; the output terminal of the third AND gate is connected to the input terminal of the fifth voltage-controlled unit, and the output terminal of the fifth voltage-controlled unit is connected to the input terminal of the third adder unit and the second contact of voltage-controlled switch II, respectively. The first contact of voltage-controlled switch I is connected to one end of the eighth resistor and the input of the second proportional amplifier. The non-inverting input of voltage-controlled switch II is connected to the negative terminal of the third memristor of feedback module I or feedback module II. The inverting input of voltage-controlled switch II and the other end of the eighth resistor are both grounded. The output of the second proportional amplifier is connected to the input of the fourth adder unit. The output of the third adder unit is connected to the input of the fourth adder unit. The output of the fourth adder unit is connected to the input of the voltage control circuit of learning module I or learning module II.

2. The memory neural network circuit with emotional consistency and masking effect according to claim 1, characterized in that, The voltage control circuit includes a first logic unit, a second logic unit, a first voltage control unit, a second voltage control unit, and a first addition unit. The input terminals of the first logic unit and the second logic unit are both connected to input signal terminals N1 and N2 or N3. The output terminal of the first logic unit is connected to the input terminal of the first voltage control unit, and the output terminal of the second logic unit is connected to the input terminal of the second voltage control unit. The output terminals of the first voltage control unit and the second voltage control unit are both connected to one input terminal of the first addition unit. The output terminal of suppression module I or suppression module II is connected to the other input terminal of the first addition unit. The output terminal of the first addition unit is connected to the input terminal of the synaptic neuron circuit.

3. The memory neural network circuit with emotional consistency and masking effect according to claim 2, characterized in that, The synaptic neuron circuit includes a first memristor, a first operational amplifier, a first mathematical operation unit, a second adder unit, a first comparator, a first NMOS transistor, and a first NOT gate. The output of the first adder unit is connected to the positive terminal of the first memristor and one input terminal of the first mathematical operation unit. The negative terminal of the first memristor is connected to one end of a first resistor and the inverting input terminal of the first operational amplifier. The other end of the first resistor is connected to the output terminal of the first operational amplifier. The non-inverting input terminal of the first operational amplifier is grounded. The output terminal of the first operational amplifier is connected to the other input terminal of the first mathematical operation unit. The output terminal of the first mathematical operation unit outputs a feedback signal, and the first NMOS transistor... The output of the learning operation unit is connected to one input of the second addition operation unit; input signal terminal N2 or input signal terminal N3 is connected to the input of the first NOT gate, the output of the first NOT gate is connected to the other input of the second addition operation unit, the output of the second addition operation unit and the first voltage source are both connected to the input of the first comparator, the output of the first comparator is connected to the gate of the first NMOS transistor, the source of the first NMOS transistor is connected to the positive terminal of the second voltage source, the drain of the first NMOS transistor is connected to one end of the second resistor, and the other end of the second resistor and the negative terminal of the second voltage source are both grounded; the drain of the first NMOS transistor outputs a signal representing the completion of learning.

4. The memory neural network circuit with emotional consistency and masking effect according to any one of claims 1-3, characterized in that, The signal judgment circuit includes a sixth comparator and a seventh comparator. The input terminals of the sixth and seventh comparators are both connected to the input signal terminal N4. The output terminal of the sixth comparator is connected to the input terminal of the ninth voltage control unit and the input terminal of the NOT gate D6, respectively. The output terminal of the seventh comparator is connected to the input terminal of the eleventh voltage control unit and the input terminal of the NOT gate D7, respectively. The first synaptic neuron circuit includes a memristor M2, an operational amplifier OP8, and a mathematical operation unit ABM2. The output terminals of the ninth and tenth voltage-controlled units are both connected to the positive terminal of the memristor M2. The positive terminal of the memristor M2 is connected to one input terminal of the mathematical operation unit ABM2, and the negative terminal of the memristor M2 is connected to a resistor R. 25 One end is connected to the inverting input of operational amplifier OP8, and resistor R 25 The other end is connected to the output of operational amplifier OP8. The non-inverting input of operational amplifier OP8 is grounded. The output of operational amplifier OP8 is connected to the other input of mathematical operation unit ABM2. The output of mathematical operation unit ABM2 is connected to one input of the seventh addition unit. The second synaptic neuron circuit includes memristor M3 and operational amplifier OP. 11 The positive terminal of memristor M3 is connected to the output terminal of the eleventh voltage-controlled unit, the output terminal of the twelfth voltage-controlled unit, and one input terminal of the mathematical operation unit ABM3, respectively. The negative terminal of memristor M3 is connected to resistor R. 26 One end and operational amplifier OP 11 Connect the inverting input terminal to the resistor R. 26 The other end is connected to the operational amplifier OP. 11 Connect the output terminal of the operational amplifier OP to the output terminal. 11 The non-inverting input terminal is grounded, and the operational amplifier OP... 11 The output terminal of the mathematical operation unit ABM3 is connected to another input terminal of the mathematical operation unit ABM3, and the output terminal of the mathematical operation unit ABM3 is connected to another input terminal of the seventh addition operation unit.

5. The memory neural network circuit with emotional consistency and masking effect according to claim 4, characterized in that, The first logic unit includes a second NOT gate and a fourth AND gate. Input signal terminal N1 is connected to the input terminal of the second NOT gate, input signal terminal N2 or input signal terminal N3 is connected to one input terminal of the fourth AND gate, the output terminal of the second NOT gate is connected to the other input terminal of the fourth AND gate, and the output terminal of the fourth AND gate is connected to the input terminal of the first voltage control unit. The second logic unit includes a fifth AND gate. Input signal terminal N1 is connected to one input terminal of the fifth AND gate, input signal terminal N2 or input signal terminal N3 is connected to the other input terminal of the fifth AND gate, and the output terminal of the fifth AND gate is connected to the input terminal of the second voltage control unit. The ninth logic unit includes a third NOT gate, a fourth NOT gate, and a sixth AND gate. The input of the third NOT gate is connected to the output of the eighth comparator, the input of the fourth NOT gate is connected to the output of the ninth comparator, the outputs of the third NOT gate and the fourth NOT gate are both connected to the input of the sixth AND gate, and the output of the sixth AND gate is connected to the input of the third AND gate of the suppression module I and the suppression module II, respectively. Both the first proportional amplifier and the second proportional amplifier include a second operational amplifier. The non-inverting input terminal of the second operational amplifier is grounded, and the inverting input terminal of the second operational amplifier is connected to one end of the ninth resistor and the tenth resistor, respectively. The other end of the ninth resistor is the input terminal, and the other end of the tenth resistor is connected to the output terminal of the second operational amplifier. The output terminal of the second operational amplifier is connected to the input terminal of the fourth addition unit.

6. The memory neural network circuit with emotional consistency and masking effect according to claim 5, characterized in that, The first, second, third, fourth, and seventh addition units all include a third operational amplifier. The non-inverting input of the third operational amplifier is used as an input terminal and is connected to one end of the twelfth resistor. The inverting input of the third operational amplifier is connected to one end of the thirteenth resistor and one end of the fourteenth resistor, respectively. The other end of the fourteenth resistor is connected to the output terminal of the third operational amplifier. The output terminal of the third operational amplifier outputs the signal after addition processing. The other ends of the twelfth and thirteenth resistors are both grounded. The first, second, third, fourth, fifth, ninth, tenth, eleventh, and twelfth voltage control units all include a voltage control switch. The positive input terminal of the voltage control switch is the input terminal. The second contact of the voltage control switch is connected to the positive terminal of the seventh voltage source. The first contact of the voltage control switch is the output terminal and is connected to one end of the fifteenth resistor. The inverting input terminal of the voltage control switch, the negative terminal of the seventh voltage source, and the other end of the fifteenth resistor are all grounded. The first comparator, second comparator, third comparator, seventh comparator, and ninth comparator all include a fourth operational amplifier. The non-inverting input of the fourth operational amplifier is connected to the positive terminal of the eighth voltage source, the negative terminal of the eighth voltage source is grounded, the inverting input of the fourth operational amplifier is used as the input terminal, and the output terminal of the fourth operational amplifier outputs the compared signal. The sixth and eighth comparators each include a fifth operational amplifier. The non-inverting input of the fifth operational amplifier is used as the input terminal, and the inverting input terminal of the fifth operational amplifier is connected to the positive terminal of the ninth voltage source. The negative terminal of the ninth voltage source is grounded, and the output terminal of the fifth operational amplifier outputs the compared signal.

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