A clock synchronization method, a topology node device and a topology structure

Abstract

The application provides a clock synchronization method, a topology node device and a topology structure. An ordinary node device determines an error signal according to a master node timestamp and a local timestamp transmitted by a master node device. The ordinary node device adjusts a clock calibration circuit according to the error signal, so that the local clock is synchronized with the clock of the master node device. The clock calibration circuit is used for calibrating a local clock source of the ordinary node device. The clock is synchronized based on the node timestamp and the local timestamp, the frequency and time of each node device in the topology structure (for example, a vehicle-mounted audio network) are synchronized, and the topology structure has a low delay characteristic.

Description

Technical Field

[0001] This application relates to the field of communications, and more specifically, to a clock synchronization method, a topology node device, and a topology structure. Background Technology

[0002] With societal development, the variety of electronic devices has increased significantly. In many scenarios, a single electronic device cannot meet user needs, requiring multiple devices to be combined into a topology. Under the coordination of this topology, multiple electronic devices work collaboratively. Taking the Automotive Audio Network (AAN) as an example, an AAN is a serial communication network used to interconnect automotive audio devices, connecting automotive electronic devices such as the head unit, digital microphone, radio, power amplifier (PA), and emergency call / telematics module.

[0003] The clocks of all nodes in an in-vehicle audio network need to be consistent and synchronized. How to synchronize the clocks of all nodes in an in-vehicle audio network has become a challenging problem that has been of ongoing concern to those skilled in the art. Summary of the Invention

[0004] The purpose of this application is to provide a clock synchronization method, a topology node device, and a topology structure to at least partially improve the above-mentioned problems.

[0005] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows:

[0006] In a first aspect, embodiments of this application provide a clock synchronization method applied to ordinary node devices in a topology, the topology including a master node device and at least one ordinary node device, the method comprising:

[0007] The ordinary node device determines the error signal based on the master node timestamp and the local timestamp transmitted by the master node device;

[0008] The ordinary node device adjusts the clock calibration circuit according to the error signal to synchronize the local clock with the clock of the master node device.

[0009] The clock calibration circuit is used to calibrate the local clock source of the ordinary node device.

[0010] Optionally, after the ordinary node device determines the error signal based on the master node timestamp and the local timestamp transmitted by the master node device, the method further includes:

[0011] The ordinary node device determines whether the value of the error signal is less than a preset value;

[0012] When the value of the error signal is less than a preset value, the ordinary node device determines a comprehensive compensation signal based on the error signal and the corresponding delay compensation.

[0013] The ordinary node device adjusts the clock calibration circuit based on the comprehensive compensation signal.

[0014] Optionally, the step of adjusting the clock calibration circuit based on the integrated compensation signal in the ordinary node device includes:

[0015] The ordinary node device filters the comprehensive compensation signal using a digital low-pass filter;

[0016] The ordinary node device adjusts the feedback frequency division coefficient in the clock calibration circuit based on the filtering result, thereby completing the adjustment of the clock calibration circuit.

[0017] Optionally, if the value of the error signal is less than a preset value, the method further includes:

[0018] The ordinary node device sends a delay compensation request to the master node device.

[0019] The delay compensation acquisition request includes a historical timestamp, a first time point, and a second time point. The historical timestamp is any timestamp of the master node issued by the master node device. The first time point is the timestamp at which the ordinary node device obtains the historical timestamp. The second time point is the timestamp at which the ordinary node device issues the delay compensation acquisition request.

[0020] The ordinary node device receives the delayed response frame fed back by the master node device;

[0021] The delayed response frame includes delay compensation corresponding to the ordinary node, which is calculated using the historical timestamp, the first time point, the second time point, and the current master node timestamp.

[0022] Optionally, before the ordinary node device determines the error signal based on the master node timestamp and local timestamp transmitted by the master node device, the method further includes:

[0023] After obtaining the master node's timestamp, the ordinary node device triggers a local counter to collect the output of the clock calibration circuit in order to obtain the local timestamp.

[0024] Optionally, before the ordinary node device determines the error signal based on the master node timestamp and local timestamp transmitted by the master node device, the method further includes:

[0025] The ordinary node device obtains the master node timestamp from the broadcast data of the master node device.

[0026] Secondly, this application provides a topology node device, which is a common node device in a topology structure. The topology structure includes a master node device and at least one common node device. The topology node device includes a timestamp comparator, a local clock source, and a clock calibration circuit. The timestamp comparator and the local clock source are both connected to the clock calibration circuit.

[0027] The timestamp comparator is used to determine the error signal based on the master node timestamp transmitted by the master node device and the local timestamp.

[0028] The timestamp comparator is also used to adjust the clock calibration circuit according to the error signal so that the local clock is synchronized with the clock of the master node device.

[0029] The clock calibration circuit is used to calibrate the local clock source of the ordinary node device.

[0030] Optionally, the topology node device further includes a time lock indication module, a delay compensation module, and a fusion module. The time lock indication module is connected to the timestamp comparator and the delay compensation module, respectively, and the fusion module is connected to the timestamp comparator, the delay compensation module, and the clock calibration circuit, respectively.

[0031] The time lock indicator module is used to determine whether the value of the error signal is less than a preset value;

[0032] When the value of the error signal is less than a preset value, the time lock indication module sends a trigger signal to the delay compensation module.

[0033] The delay compensation module is used to obtain the delay compensation of the topology node device when the trigger signal is received, and transmit the delay compensation to the fusion module;

[0034] The fusion module is used to determine a comprehensive compensation signal based on the error signal and the delay compensation;

[0035] The fusion module is also used to adjust the clock calibration circuit based on the integrated compensation signal.

[0036] Optionally, the topology node device further includes a digital low-pass filter, which is connected to the fusion module and the clock calibration circuit respectively;

[0037] The digital low-pass filter is used to filter the comprehensive compensation signal;

[0038] The digital low-pass filter is used to adjust the feedback frequency division coefficient in the clock calibration circuit based on the filtering result, thereby completing the adjustment of the clock calibration circuit.

[0039] Optionally, the topology node device further includes a local counter, which is connected to the timestamp comparator and the clock calibration circuit, respectively;

[0040] The local counter is used to collect the output of the clock calibration circuit after the topology node device obtains the master node timestamp, so as to obtain the local timestamp, and transmit the local timestamp to the timestamp comparator.

[0041] Thirdly, embodiments of this application provide a clock synchronization method applied to a topology, the topology including a master node device and at least one ordinary node device, the method comprising:

[0042] The master node device broadcasts broadcast data containing the master node timestamp;

[0043] The ordinary node device obtains the master node timestamp from the broadcast data of the master node device;

[0044] The ordinary node device determines the error signal based on the master node timestamp and the local timestamp transmitted by the master node device;

[0045] The ordinary node device adjusts the clock calibration circuit according to the error signal to synchronize the local clock with the clock of the master node device.

[0046] The clock calibration circuit is used to calibrate the local clock source of the ordinary node device.

[0047] Fourthly, embodiments of this application provide a topology structure, which includes a master node device and at least one ordinary node device;

[0048] The master node device is used to broadcast broadcast data containing the master node timestamp;

[0049] The ordinary node device is used to obtain the master node timestamp from the broadcast data of the master node device;

[0050] The ordinary node device is also used to determine the error signal based on the master node timestamp and the local timestamp transmitted by the master node device;

[0051] The ordinary node device is also used to adjust the clock calibration circuit according to the error signal so that the local clock is synchronized with the clock of the master node device;

[0052] The clock calibration circuit is used to calibrate the local clock source of the ordinary node device.

[0053] Compared to existing technologies, the clock synchronization method, topology node device, and topology structure provided in this application involve ordinary node devices determining an error signal based on the master node timestamp and local timestamp transmitted by the master node device; the ordinary node device then adjusts a clock calibration circuit based on the error signal to synchronize its local clock with the master node device's clock; wherein, the clock calibration circuit is used to calibrate the local clock source of the ordinary node device. Clock synchronization based on node timestamps and local timestamps ensures that the frequencies and times of all node devices in the topology structure (e.g., an in-vehicle audio network) are synchronized, guaranteeing low latency characteristics for the topology structure.

[0054] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0055] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0056] Figure 1 This is a schematic diagram of the serial topology provided in the embodiments of this application;

[0057] Figure 2 This is a schematic diagram of the ring topology provided in the embodiments of this application;

[0058] Figure 3 This is one of the structural schematic diagrams of the topology node device provided in the embodiments of this application;

[0059] Figure 4 This is the second schematic diagram of the structure of the topology node device provided in the embodiments of this application;

[0060] Figure 5 One of the flowcharts of the clock synchronization method provided in the embodiments of this application;

[0061] Figure 6 A second schematic flowchart illustrating the clock synchronization method provided in this application embodiment;

[0062] Figure 7 A schematic diagram of the sub-steps of S308 provided in the embodiments of this application;

[0063] Figure 8 The third schematic flowchart of the clock synchronization method provided in the embodiments of this application;

[0064] Figure 9 The fourth flowchart illustrates the clock synchronization method provided in the embodiments of this application.

[0065] Figure 10 The fifth flowchart illustrates the clock synchronization method provided in the embodiments of this application.

[0066] In the diagram: 10-Ordinary node device; 11-Master node device; 101-Time stamp comparator; 102-Local clock source; 103-Clock calibration circuit; 104-Time lock indicator module; 105-Delay compensation module; 106-Fusion module; 107-Digital low-pass filter; 108-Local counter. Detailed Implementation

[0067] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0068] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0069] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0070] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0071] In the description of this application, it should be noted that the terms "upper", "lower", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship that the product of this application is usually placed in. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0072] In the description of this application, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0073] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0074] Automotive Audio Networks (AANs) are a type of network topology where the clocks of ordinary node devices need to be synchronized with the clock of the master node device. The traditional approach is to recover a received synchronization signal from frame synchronization information as a reference, and then use a phase-locked loop (PLL) to multiply the frequency to generate a high-frequency clock for synchronization. For an automotive audio network with a bus length of up to 30 meters, the delay due to the length of the line alone can reach 150 nanoseconds. This delay information is unknown to a traditional PLL, leading to degraded clock synchronization performance and high latency.

[0075] To overcome the above problems, this application provides a topology. Please refer to... Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of the vehicle serial topology provided in the embodiments of this application. Figure 2 This is a schematic diagram of the ring topology provided in an embodiment of this application.

[0076] like Figure 1 and Figure 2 As shown, the topology includes a master node device 11 and at least one ordinary node device 10, which are connected in sequence.

[0077] Optionally, such as Figure 1 As shown, the topology is a serial topology, with the downstream port of the master node device 11 connected to the first ordinary node device 10 (i.e., Figure 1 The upstream port of the first ordinary node device 10 is connected to the upstream port of the (i-1)th ordinary node device 10, and the downstream port of the nth ordinary node device 10 (i.e., Figure 1 The downstream port of the 3rd ordinary node device in the process is left floating, 2≤i≤n, where n is the number of ordinary node devices.

[0078] Optionally, such as Figure 2 As shown, the topology is a ring topology, and the downstream port of the master node device 11 is connected to the first ordinary node device 10 (i.e., Figure 2 The upstream port of the first ordinary node device 10 is connected to the upstream port of the (i-1)th ordinary node device 10, and the downstream port of the nth ordinary node device 10 (i.e., Figure 2 The downstream port of the 3rd ordinary node device is connected to the upstream port of the master node device 11, where 2≤i≤n and n is the number of ordinary node devices.

[0079] It should be noted that, Figure 1 and Figure 2 The example uses n=3, but this is not a limitation.

[0080] It should be understood that Figure 1 and Figure 2 The topology shown can be, but is not limited to, an in-vehicle audio network. When it is an in-vehicle audio network, other devices connected to the ordinary node device 10 through its local port can be, but are not limited to, digital microphones, radios, power amplifiers (PAs), and emergency call / telematics devices. The master node device 11 connected to the master control device through its local port can be, but is not limited to, a vehicle head unit.

[0081] In the clock synchronization of the topology provided in this application embodiment, in order to synchronize the frequency and time of each node device in the topology (e.g., vehicle audio network), a timestamp method is used for synchronization: that is, the master node device 11 encapsulates the master node timestamp in the downlink data frame, the ordinary node device 10 extracts the master node timestamp, compares it with the local timestamp of the ordinary node device 10 to generate an error signal, and adjusts the feedback coefficient SDM (Sigma-Delta Modulator) of the phase-locked loop (PLL) based on the error signal to generate a synchronized clock.

[0082] To achieve clock synchronization, this application provides a topology node device, which belongs to... Figure 1 and Figure 2 The topology shown includes a common node device 10, and the topology includes a master node device 11 and at least one common node device 10.

[0083] Please refer to Figure 3 , Figure 3 This is one of the structural schematic diagrams of the topology node device provided in the embodiments of this application. For example... Figure 3 As shown, the topology node device includes a timestamp comparator 101, a local clock source 102, and a clock calibration circuit 103. Both the timestamp comparator 101 and the local clock source 102 are connected to the clock calibration circuit 103.

[0084] The timestamp comparator 101 is used to determine the error signal based on the master node timestamp and the local timestamp (LocalTS) transmitted by the master node device.

[0085] The timestamp comparator 101 is also used to adjust the clock calibration circuit 103 according to the error signal so that the local clock is synchronized with the clock of the master node device 11.

[0086] The clock calibration circuit 103 is used to calibrate the local clock source 102 of the ordinary node device.

[0087] Optionally, the clock calibration circuit 103 can be a fractional-order phase-locked loop, which is locked to a calibrated local clock source 102.

[0088] A fractional-order frequency-locked loop can include a reference frequency divider, a frequency and phase detector, a low-pass filter, a voltage-controlled oscillator, a feedback fractional-order frequency divider, and an output frequency divider.

[0089] Please refer to Figure 4 , Figure 4 This is a second schematic diagram of the structure of the topology node device provided in the embodiments of this application. Figure 4 As shown, the topology node device also includes a time lock indication module 104, a delay compensation module 105, and a fusion module 106. The time lock indication module 104 is connected to the timestamp comparator 101 and the delay compensation module 105, respectively. The fusion module 106 is connected to the timestamp comparator 101, the delay compensation module 105, and the clock calibration circuit 103, respectively.

[0090] The time lock indicator module 104 is used to determine whether the value of the error signal is less than a preset value.

[0091] If so, it means that the clock frequency and phase of the ordinary node device 10 and the master node device 11 are basically the same. In this case, the line delay between the master node device 11 and the ordinary node device 10 can be compensated.

[0092] In one embodiment, the master node timestamp in the downlink data frame sent by the master node device 11 and received by the ordinary node device 10 represents the time information when the master node device 11 sent the downlink data frame. When the ordinary node device 10 receives the downlink data frame and parses out the master node timestamp, it needs to synchronize its own clock to the master node timestamp. However, after the downlink data frame is transmitted through the line between the master node device 11 and the ordinary node device 10, when the ordinary node device 10 receives the downlink data frame, the current clock of the master node device 11 needs to be compensated for the line delay between the master node device 11 and the ordinary node device 10 to accurately obtain the data.

[0093] In another embodiment, before clock synchronization, such as during the initial power-on phase, the clock of the ordinary node device 10 deviates significantly from the clock of the master node device 11. When the ordinary node device 10 receives a downlink data frame containing the master node's timestamp, a phase-locked loop (PLL) needs to perform a lengthy tracking process to calibrate its clock to be approximately similar to the master node's timestamp. However, at this time, the clock of the master node device 11 has already changed. In one embodiment, the process of the master node device 11 sending downlink data frames is periodic. When the time-locking indication module 104 determines that the error signal value is less than a preset value, indicating that the clock of the ordinary node device 10 has been adjusted to be approximately similar to the master node's timestamp contained in the current downlink data frame, a delay compensation process is triggered. That is, when the clock of the ordinary node device 10 deviates significantly from the clock of the master node device 11, it is necessary to receive the master node's timestamp from different downlink data frames multiple times, so delay compensation is temporarily not performed to save time and processing resources.

[0094] When the value of the error signal is less than a preset value, the time lock indicator module 104 sends a trigger signal to the delay compensation module 105.

[0095] The delay compensation module 105 is used to obtain the delay compensation of the topology node device when a trigger signal is received, and transmit the delay compensation to the fusion module 106.

[0096] Optionally, upon receiving a trigger signal, the delay compensation module 105 sends a delay compensation acquisition request to the master node device 11 through the corresponding topology node device.

[0097] The delay compensation acquisition request includes a historical timestamp, a first time point, and a second time point. The historical timestamp is any timestamp of the master node issued by the master node device 11. The first time point is the timestamp at which the ordinary node device obtains the historical timestamp. The second time point is the timestamp at which the ordinary node device issues the delay compensation acquisition request.

[0098] The topology node device receives a delayed response frame from the master node device 11.

[0099] The delayed response frame includes delay compensation for ordinary nodes, which is calculated using historical timestamps, the first time point, the second time point, and the current master node timestamp. The current master node timestamp is the timestamp at which the master node device 11 received the delay compensation request.

[0100] Optionally, the formula for delay compensation is as follows:

[0101] ΔT2=[(ts4-ts1)-(ts3-ts2)] / 2;

[0102] Wherein, ΔT2 represents delay compensation, ts1 represents historical timestamp, ts4 represents current master node timestamp, ts3 represents second time point, and ts2 represents first time point.

[0103] MO Node Delay Compensation is the transmission time of the line between the master node device 11 and the ordinary node device 10.

[0104] The fusion module 106 is used to determine the comprehensive compensation signal based on the error signal and the delay compensation.

[0105] Optionally, the fusion module 106 is used to add the error signal and the delay compensation, and use the sum of the two as the comprehensive compensation signal.

[0106] The fusion module 106 is also used to adjust the clock calibration circuit 103 based on the integrated compensation signal.

[0107] Alternatively, please continue to refer to Figure 4 The topology node device also includes a digital low-pass filter 107, which is connected to the fusion module 106 and the clock calibration circuit 103, respectively.

[0108] The digital low-pass filter 107 is used to filter the comprehensive compensation signal.

[0109] The digital low-pass filter 107 is used to adjust the feedback frequency division coefficient SDM (Sigma-Delta Modulator) in the clock calibration circuit 103 according to the filtering result, thereby completing the adjustment of the clock calibration circuit 103.

[0110] It should be understood that the digital low-pass filter 107 can also directly perform low-pass filtering on the error signal between the master node timestamp and the local timestamp, and then control the feedback division coefficient SDM (Sigma-DeltaModulator) of the fractional frequency division phase-locked loop, thereby completing the adjustment of the clock calibration circuit 103.

[0111] Please continue to refer to this. Figure 4 In one possible implementation, the topology node device also includes a local counter 108, which is connected to both the timestamp comparator 101 and the clock calibration circuit 103.

[0112] The local counter 108 is used to collect the output of the clock calibration circuit 103 after the topology node device obtains the master node timestamp, so as to obtain the local timestamp and transmit the local timestamp to the timestamp comparator 101.

[0113] It should be noted that the accuracy of the local timestamp (Local TS) depends on the operating frequency of the counter. To minimize time errors, the operating frequency of the counter should be as high as possible. The scheme in this application uses a 491.52MHz clock to achieve an accuracy of 2ns.

[0114] Optionally, when the topology node device receives broadcast data containing the master node's timestamp from the master node device 11, it parses the broadcast data to extract the master node's timestamp.

[0115] It should be understood that, Figure 3 and Figure 4 The structure shown is only a partial schematic diagram of the topology node device; the topology node device may also include components such as... Figure 3 and Figure 4 The more or fewer components shown, or having the same Figure 1 The different configurations shown. Figure 3 and Figure 4 The components shown can be implemented using hardware, software, or a combination thereof.

[0116] The clock synchronization method provided in this application embodiment can be applied to, but is not limited to, [various applications]. Figure 1 and Figure 2 The ordinary node device in the topology shown can be Figure 3 and Figure 4 For the specific process of the topology node devices shown, please refer to [reference needed]. Figure 5 The clock synchronization methods include S303 and S309, which are described in detail below.

[0117] S303, the ordinary node device determines the error signal based on the master node timestamp and the local timestamp transmitted by the master node device.

[0118] S309, ordinary node devices adjust the clock calibration circuit according to the error signal to synchronize the local clock with the clock of the master node device.

[0119] The clock calibration circuit 103 is used to calibrate the local clock source 102 of the ordinary node device.

[0120] exist Figure 5 Building upon this foundation, this application also provides a possible implementation method for further improving clock synchronization accuracy and ensuring low latency characteristics. Please refer to [link / reference]. Figure 6 Following S303, clock synchronization methods also include S304, S307, and S308, which are described in detail below.

[0121] S304, the ordinary node device determines whether the value of the error signal is less than a preset value. If yes, proceed to S307; otherwise, proceed to S309.

[0122] S307, when the value of the error signal is less than the preset value, the ordinary node device determines the comprehensive compensation signal based on the error signal and the corresponding delay compensation.

[0123] S308, a common node device based on a clock calibration circuit adjusted by a comprehensive compensation signal.

[0124] exist Figure 6 Based on the above, this application embodiment also provides a possible implementation of the content in S308, please refer to... Figure 7 S308 includes S308-1 and S308-2, which are described in detail below.

[0125] S308-1, ordinary node equipment uses a digital low-pass filter to filter the comprehensive compensation signal.

[0126] S308-2, ordinary node equipment adjusts the feedback frequency division coefficient in the clock calibration circuit according to the filtering results, thereby completing the adjustment of the clock calibration circuit.

[0127] exist Figure 6 Based on this, regarding how to obtain delay compensation, this application embodiment also provides a possible implementation method, please refer to... Figure 8 When the error signal value is less than the preset value, the clock synchronization method also includes S305 and S306, which are described in detail below.

[0128] S305, the ordinary node device sends a delay compensation request to the master node device.

[0129] The delay compensation acquisition request includes a historical timestamp, a first time point, and a second time point. The historical timestamp is any timestamp of the master node issued by the master node device. The first time point is the timestamp at which the ordinary node device obtains the historical timestamp. The second time point is the timestamp at which the ordinary node device issues the delay compensation acquisition request.

[0130] S306, Ordinary node devices receive delayed response frames from master node devices.

[0131] The delayed response frame includes delay compensation for ordinary nodes, which is calculated using historical timestamps, the first time point, the second time point, and the current master node timestamp.

[0132] exist Figure 5 Based on this, regarding how to obtain the master node timestamp and local timestamp, this application embodiment also provides a possible implementation method, please refer to... Figure 9 The clock synchronization methods also include S301 and S302, which are described in detail below.

[0133] S301, ordinary node devices obtain the master node timestamp from the broadcast data of the master node device.

[0134] It should be understood that the node timestamp is encapsulated in the broadcast data of the master node device.

[0135] S302: After obtaining the master node's timestamp, the ordinary node device triggers the local counter to collect the output of the clock calibration circuit in order to obtain the local timestamp.

[0136] It should be noted that the clock synchronization method provided in this embodiment can perform the functions of each component shown in the above-described topology node device embodiment to achieve the corresponding technical effects. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the above embodiments.

[0137] The clock synchronization method provided in this application embodiment can be applied to, but is not limited to, [various applications]. Figure 1 and Figure 2 For the topology shown and the specific process, please refer to [link / reference]. Figure 10 The clock synchronization methods include S201, S301, S303 and S309, which are described in detail below.

[0138] S201, the master node device broadcasts broadcast data containing the master node timestamp.

[0139] S301, ordinary node devices obtain the master node timestamp from the broadcast data of the master node device.

[0140] S303, ordinary node devices determine error signals based on the master node timestamp and local timestamp transmitted by the master node device.

[0141] S309, ordinary node devices adjust the clock calibration circuit according to the error signal to synchronize the local clock with the clock of the master node device.

[0142] The clock calibration circuit 103 is used to calibrate the local clock source 102 of the ordinary node device.

[0143] Optionally, when the master node device 11 receives a delay compensation request, it can obtain the delay compensation through the historical timestamp, the first time point, the second time point, and the current master node timestamp, and then send the corresponding delay compensation back to the ordinary node device 10.

[0144] In one embodiment, after the ordinary power-saving device 10 has obtained a delay compensation once, the delay compensation is stored locally and directly called when delay compensation is needed in a subsequent instance. In another embodiment, the delay compensation value can be obtained by averaging the delay compensation values ​​calculated during multiple downlink data frame transmissions and receptions, and stored locally, and directly called when delay compensation is needed in a subsequent instance.

[0145] It should be noted that the clock synchronization method for topology structures provided in this embodiment can execute the method flow shown in the above-described method flow embodiment for topology node devices to achieve the corresponding technical effects. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the above embodiments.

[0146] Optionally, this application provides a topology, specifically, such as... Figure 1 and Figure 2 The topology shown includes a master node device 11 and at least one ordinary node device 10.

[0147] The master node device 11 is used to broadcast broadcast data containing the master node timestamp;

[0148] The ordinary node device 10 is used to obtain the master node timestamp from the broadcast data of the master node device.

[0149] Ordinary node device 10 is also used to determine error signals based on the master node timestamp and local timestamp transmitted by master node device 11.

[0150] The ordinary node device 10 is also used to adjust the clock calibration circuit 103 according to the error signal so that the local clock is synchronized with the clock of the master node device 11.

[0151] The clock calibration circuit 103 is used to calibrate the local clock source 102 of the ordinary node device.

[0152] It should be noted that the topology provided in this embodiment can execute the process examples of each component shown in the above-described embodiment of the clock synchronization method applied to the topology, in order to achieve the corresponding technical effects. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the above embodiments.

[0153] It is important to emphasize that low latency is crucial for audio systems, especially for in-vehicle noise reduction and road noise reduction systems. Time-synchronized in-vehicle audio transmission systems more effectively manage transmission latency and minimize latency uncertainty. This also makes it possible to accurately timestamp the collected data.

[0154] In summary, this application provides a clock synchronization method, a topology node device, and a topology. Ordinary node devices determine an error signal based on the master node's timestamp and local timestamp transmitted by the master node device. The ordinary node device adjusts its clock calibration circuit based on the error signal to synchronize its local clock with the master node device's clock. The clock calibration circuit calibrates the local clock source of the ordinary node device. Clock synchronization based on node timestamps and local timestamps ensures that the frequencies and times of all node devices in the topology (e.g., an in-vehicle audio network) are synchronized, guaranteeing low latency characteristics for the topology.

[0155] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0156] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this application. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A clock synchronization method, characterized in that, A method applied to a common node device in a topology, the topology including a master node device and at least one common node device, the method comprising: The ordinary node device determines the error signal based on the master node timestamp and the local timestamp transmitted by the master node device; The ordinary node device determines whether the value of the error signal is less than a preset value; When the value of the error signal is less than a preset value, the ordinary node device determines a comprehensive compensation signal based on the error signal and the corresponding delay compensation. The ordinary node device adjusts the clock calibration circuit based on the comprehensive compensation signal to synchronize the local clock with the clock of the master node device. The clock calibration circuit is used to calibrate the local clock source of the ordinary node device.

2. The clock synchronization method as described in claim 1, characterized in that, The step of adjusting the clock calibration circuit based on the integrated compensation signal in the ordinary node device includes: The ordinary node device filters the comprehensive compensation signal using a digital low-pass filter; The ordinary node device adjusts the feedback frequency division coefficient in the clock calibration circuit based on the filtering result, thereby completing the adjustment of the clock calibration circuit.

3. The clock synchronization method as described in claim 1, characterized in that, If the value of the error signal is less than a preset value, the method further includes: The ordinary node device sends a delay compensation request to the master node device. The delay compensation acquisition request includes a historical timestamp, a first time point, and a second time point. The historical timestamp is any timestamp of the master node issued by the master node device. The first time point is the timestamp at which the ordinary node device obtains the historical timestamp. The second time point is the timestamp at which the ordinary node device issues the delay compensation acquisition request. The ordinary node device receives the delayed response frame fed back by the master node device; The delayed response frame includes delay compensation corresponding to the ordinary node, which is calculated using the historical timestamp, the first time point, the second time point, and the current master node timestamp.

4. The clock synchronization method as described in claim 1, characterized in that, Before the ordinary node device determines the error signal based on the master node timestamp and local timestamp transmitted by the master node device, the method further includes: After obtaining the master node's timestamp, the ordinary node device triggers a local counter to collect the output of the clock calibration circuit in order to obtain the local timestamp.

5. The clock synchronization method as described in claim 1, characterized in that, Before the ordinary node device determines the error signal based on the master node timestamp and local timestamp transmitted by the master node device, the method further includes: The ordinary node device obtains the master node timestamp from the broadcast data of the master node device.

6. A topology node device, characterized in that, The device is a regular node in a topology structure, which includes a master node and at least one regular node. Each regular node includes a timestamp comparator, a local clock source, and a clock calibration circuit. Both the timestamp comparator and the local clock source are connected to the clock calibration circuit. The regular node also includes a time lock indicator module, a delay compensation module, and a fusion module. The time lock indicator module is connected to both the timestamp comparator and the delay compensation module, and the fusion module is connected to both the timestamp comparator, the delay compensation module, and the clock calibration circuit. The timestamp comparator is used to determine the error signal based on the master node timestamp transmitted by the master node device and the local timestamp. The time lock indicator module is used to determine whether the value of the error signal is less than a preset value; When the value of the error signal is less than a preset value, the time lock indication module sends a trigger signal to the delay compensation module. The delay compensation module is used to obtain the delay compensation of the topology node device when the trigger signal is received, and transmit the delay compensation to the fusion module; The fusion module is used to determine a comprehensive compensation signal based on the error signal and the delay compensation; The fusion module is also used to adjust the clock calibration circuit based on the integrated compensation signal so that the local clock is synchronized with the clock of the master node device. The clock calibration circuit is used to calibrate the local clock source of the ordinary node device.

7. The topology node device as described in claim 6, characterized in that, The topology node device also includes a digital low-pass filter, which is connected to the fusion module and the clock calibration circuit respectively. The digital low-pass filter is used to filter the comprehensive compensation signal; The digital low-pass filter is used to adjust the feedback frequency division coefficient in the clock calibration circuit based on the filtering result, thereby completing the adjustment of the clock calibration circuit.

8. The topology node device as described in claim 6, characterized in that, The topology node device also includes a local counter, which is connected to the timestamp comparator and the clock calibration circuit respectively; The local counter is used to collect the output of the clock calibration circuit after the topology node device obtains the master node timestamp, so as to obtain the local timestamp, and transmit the local timestamp to the timestamp comparator.

9. A clock synchronization method, characterized in that, Applied to a topology including a master node device and at least one ordinary node device, the method includes: The master node device broadcasts broadcast data containing the master node timestamp; The ordinary node device obtains the master node timestamp from the broadcast data of the master node device; The ordinary node device determines the error signal based on the master node timestamp and the local timestamp transmitted by the master node device; The ordinary node device determines whether the value of the error signal is less than a preset value; When the value of the error signal is less than a preset value, the ordinary node device determines a comprehensive compensation signal based on the error signal and the corresponding delay compensation. The ordinary node device adjusts the clock calibration circuit based on the comprehensive compensation signal to synchronize the local clock with the clock of the master node device. The clock calibration circuit is used to calibrate the local clock source of the ordinary node device.

10. A topological structure, characterized in that, The topology includes a master node device and at least one ordinary node device; The master node device is used to broadcast broadcast data containing the master node timestamp; The ordinary node device is used to obtain the master node timestamp from the broadcast data of the master node device; The ordinary node device is also used to determine the error signal based on the master node timestamp and the local timestamp transmitted by the master node device; The ordinary node device is also used to determine whether the value of the error signal is less than a preset value; The ordinary node device is also used to determine a comprehensive compensation signal based on the error signal and the corresponding delay compensation when the value of the error signal is less than a preset value. The ordinary node device is also used to adjust the clock calibration circuit based on the comprehensive compensation signal so that the local clock is synchronized with the clock of the master node device. The clock calibration circuit is used to calibrate the local clock source of the ordinary node device.

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