System and method for bypassing memory read request detection

Abstract

A system and method for analyzing a CXL microchip at a read bypass detection logic (115) to identify a bypass memory read request (108), and transmitting the identified bypass memory read request (108) directly to a transaction / application layer (135) of a CXL memory controller (100) via a read request bypass path (120), wherein the read request bypass path (120) excludes an arbitration / multiplexing layer (125) and a link layer (130) of the CXL memory controller (100), thereby reducing latency inherent in the CXL memory controller (100).

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Patent Application Serial No. 63 / 195,455 filed on June 1, 2021 and U.S. Non-Provisional Patent Application Serial No. 17 / 741,282 filed on May 10, 2022, the contents of each of which are incorporated herein by reference in their entirety. Background Art

[0003] Compute Express Link (CXL) is an open interconnect standard based on the Peripheral Component Interconnect Express (PCIe) Gen5 link infrastructure to provide efficient coherent memory access between a host (such as a CPU) and a device (such as a hardware accelerator or memory expansion device for processing intensive workloads).

[0004] One of the main benefits of CXL is to allow various CPUs to access various types of memory using the same method, thereby allowing various CPUs to utilize the same memory pool of the device. The read latency associated with memory access is critical to host CPU performance, and therefore, reducing the read latency associated with CXL-attached devices (such as double data rate (DDR) memory controllers) is highly beneficial.

[0005] Therefore, what is needed in the art is a system and method for improving read latency of a CXL attached memory controller. Summary of the invention

[0006] In various examples, the present invention provides a system and method for improving read latency of a CXL-attached memory controller.

[0007] In one example, a method for bypass memory read request detection is provided, the method comprising: receiving a plurality of data packets at a physical layer of a CXL memory controller; deriving a plurality of compute fast link (CXL) flow control units (flits) from the plurality of data packets received at the physical layer of the CXL memory controller; transmitting each of the received plurality of CXL flits to a read bypass detection logic of the CXL memory controller; and analyzing each of the plurality of CXL flits at the read bypass detection logic to identify bypass memory read requests from the plurality of CXL flits. In a specific example, analyzing each of the plurality of CXL flits at the read bypass detection logic of the CXL memory includes: detecting a master-slave (M2S) request with a memory read opcode in the CXL flits to identify the bypass memory read request. The method also includes transmitting the bypass memory read request directly to a transaction / application layer of the CXL memory controller via a read request bypass path, wherein the read request bypass path does not include an arbitration / multiplexing layer and a link layer of the CXL memory controller. When the read request queue of the CXL memory controller is empty, the method continues by generating a memory read command on an interface of a memory device attached to the CXL memory controller in response to a bypass memory read request received at a transaction / application layer of the CXL memory controller; receiving read data from the memory device at the transaction / application layer in response to the memory read command, and when there is a link layer memory read request at the transaction / application layer that matches the bypass memory read request that generated the memory read command, the method ends by forwarding the read data received at the transaction / application layer to the link layer of the CXL memory controller.

[0008] In an additional example, when there is no link layer memory read request at the transaction / application layer that matches the bypass memory read request that generates the memory read command, the method continues by discarding the read data received at the transaction / application layer. Additionally, when the read request queue of the CXL memory controller is not empty, the method continues by not generating a memory read command on an interface of a memory device attached to the CXL memory controller and discarding the bypass memory read request. If the address space of the bypass memory read request is invalid, the memory read command will also not be generated on the memory device interface and the bypass memory read request will be discarded.

[0009] In a specific example, the memory devices attached to the CXL memory controller are double data rate (DDR) memory devices.

[0010] In an additional example, a compute express link (CXL) memory controller is provided, the CXL memory controller including read bypass detection logic for receiving a plurality of CXL micros from a CXL physical layer of the CXL memory controller and analyzing each of the received plurality of CXL micros to identify bypass memory read requests from the plurality of CXL micros. In a specific example, the CXL memory controller analyzes each of the plurality of CXL micros by detecting a master-slave (M2S) request with a memory read opcode in the CXL micros to identify the bypass memory read request. The CXL memory controller also includes a read request bypass path including the read bypass detection logic and connecting the CXL physical layer to a transaction / application layer of the CXL memory controller, the read request bypass path bypassing an arbitration / multiplexing layer of the CXL memory controller and a link layer of the CXL memory controller. When the read request queue is empty, the transaction / application layer generates a memory read command on an interface of a memory device associated with the CXL memory controller in response to a bypass memory read request received at the transaction / application layer, receives read data from the memory device in response to the memory read command, and forwards the read data received at the transaction / application layer to the link layer when there is a link layer memory read request at the transaction / application layer that matches the bypass memory read request that generated the memory read command.

[0011] In an additional example, when there is no link layer memory read request matching the bypass memory read request generating the memory read command at the transaction / application layer, the CXL memory controller discards the read data received at the transaction / application layer. In addition, when the read request queue is not empty, the CXL memory controller does not generate a memory read command on the interface of the memory device and discards the bypass memory read request. When the address space of the bypass memory read request is invalid, the CXL memory controller also discards the bypass memory read request and does not generate a memory read command on the memory device interface.

[0012] Thus, these various examples provide improved systems and methods for reducing read latency for a CXL-attached memory controller. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate various examples and, together with the detailed description of the invention, serve to explain the principles discussed below. Unless otherwise specified, the drawings mentioned in this brief description should not be understood as being drawn to scale.

[0014] Figure 1is a block diagram illustrating an exemplary CXL memory controller including read bypass detection logic.

[0015] Figure 2 is a table showing the CXL.cache / CXL.mem flit header definition according to the CXL 2.0 specification.

[0016] Figure 3 is a table showing the encoding of the slot format fields according to the CXL 2.0 specification.

[0017] Figure 4 is a table showing the H2D / M2S slot format according to the CXL 2.0 specification.

[0018] Figure 5A is a flow chart illustrating an exemplary method for reducing read latency in a CXL memory controller.

[0019] Figure 5B yes Figure 5A Continuing with the flowchart of , an exemplary method for reducing read latency in a CXL memory controller is shown.

[0020] Fig. 6A is a flow chart illustrating an exemplary method for reducing read latency in a CXL memory controller and for selectively discarding bypass memory read requests.

[0021] Figure 6B yes Fig. 6A Continuing with the flowchart of , an exemplary method for reducing read latency in a CXL memory controller and for selectively discarding bypass memory read requests is shown.

[0022] Figure 7 is a flow chart illustrating an exemplary method for reducing read latency in a CXL memory controller and for selectively discarding link layer memory read requests.

[0023] Fig. 8A is a flow chart illustrating an exemplary method for reducing read latency in a CXL memory controller and for matching link layer memory read requests to bypass memory read requests.

[0024] Figure 8B yes Fig. 8A Continuation of the flowchart of , an exemplary method for reducing read latency in a CXL memory controller and for matching link layer memory read requests to bypass memory read requests is shown. DETAILED DESCRIPTION

[0025] Various examples will now be referred to in detail, which are shown in the accompanying drawings. Although various examples are discussed herein, it should be understood that these examples are not intended to be restrictive. On the contrary, the examples proposed are intended to cover alternative forms, modifications and equivalents that may be included in the spirit and scope of the various examples defined by the appended claims. In addition, in this specific embodiment, many specific details are set forth in order to provide a thorough understanding. However, examples can be put into practice without one or more of these specific details. In other cases, well-known methods, procedures, components and circuits are not described in detail to avoid unnecessary obscurity of the various aspects of the examples.

[0026] It should be understood that although the terms first, second, third (not limited thereto) may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another region, layer or part. Therefore, the first element, component, region, layer or part discussed below may be referred to as the second element, component, region, layer or part.

[0027] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those generally understood by those of ordinary skill in the art. It should also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0028] CXL has been developed as a standard to provide improved high-speed CPU-to-device and CPU-to-memory interconnects that will accelerate next-generation data center performance and emerging computing applications such as artificial intelligence, machine learning and other applications. CXL maintains memory coherency between the CPU memory space and the memory space of attached devices, which provides resource sharing, resulting in high performance, reduced complexity and lower total system cost.

[0029] CXL supports a set of protocols including input / output (I / O) semantics (CXL.io) that are similar to PCIe I / O semantics, cache protocol semantics (CXL.cache), and memory access semantics (CXL.mem). The CXL.io protocol is equivalent to PCIe transport over the CXL protocol, and CXL.mem is a memory access protocol that supports device-attached memory to provide a transactional interface between the CPU and the memory device. In some applications, the CXL protocol can be built on the well-established and widely adopted PCIe infrastructure (e.g., PCIe 5.0), thereby leveraging the PCIe physical interface and enhancing the protocol with CXL to provide memory consistency between the CPU memory and the accelerator device memory.

[0030] refer to Figure 1 The compute express link (CXL) memory controller 100 includes a read bypass detection logic 115 for receiving a plurality of CXL flits 108 from a CXL physical layer 110 of the CXL memory controller 100. The CXL flits 108 may be derived from packets received from a CPU or other host device via a PCIe / CXL serializer / deserializer (SerDes) interface 105.

[0031] A CXL flits (stream control unit) is a link layer data packet formatted for use on an interconnect link, such as a PCIe-based or CXL-based link. In a specific example, a known CXL flits consists of 528 bits, which includes 64 bytes of data, followed by a 2-byte cyclic redundancy check (CRC) to check the integrity of the data bytes. According to the CXL protocol, a CXL flits starts after a protocol identification (ProtID) field. The ProtID field is used by the CXL.mem arbitration / multiplexing layer 125 to direct the CXL flits to the CXL.mem link layer 130.

[0032] refer to Figure 2 , CXL.cache / CXL.mem flits include a header carrying type bit 200 and slot n information, which is used to determine whether the flits are protocol flits and whether they can include M2S Req (Master-Slave Request). Figure 3 and Figure 4 , if slot 0 has a field value of 3'b101 300, it indicates that the micro slice is in H5 format 400 and is carrying a CXL.mem Req.

[0033] The M2S Req itself is only 87 bits. Adding the 4 bytes of header bytes plus the 2 bytes of protocol ID means that a total of 135 bits (48 bits + 87 bits) must be collected to be able to detect a memory read request in a CXL microchip.

[0034] In standard operation of a CXL controller (which does not implement the read bypass path 120 of the present example but has other elements found in the CXL memory controller 100), a CXL flits that are carrying a memory read request (CXL.mem Req.) received at the physical layer of the CXL memory controller 110 is transmitted to the CXL.mem arbitration / multiplexing layer 125, and the CXL.mem arbitration / multiplexing layer 125 then transmits the CXL flits to the CXL.mem link layer 130. The CXL.mem link layer 130 checks each CXL flits to verify that they are not full data flits (i.e., do not contain headers) and that the CRC for the CXL flits is correct. If the CXL flits pass these verifications, the CXL.mem link layer 130 then transmits the read request to the CXL.mem transaction / application layer 135. The CXL.mem transaction / application layer 135 then generates a read command and forwards the read command to the memory controller and physical layer 140. The memory controller and physical layer 140 then generates a memory read command on the memory interface device 147. If the memory device 145 page is not already open, the memory controller and physical layer 140 also generates an activate command on the memory interface 147, which allows the CPU host to access the memory device 145 through the memory interface 147 under the control of the CXL memory controller 100. In this standard implementation, there is an undesirable delay in the read data path between the CXL physical layer 110 and the CXL.mem transaction / application layer 135.

[0035] like Figure 1 As shown, a read request bypass path 120 including a read bypass detection logic 115 is implemented in the CXL memory controller 110 to connect the CXL physical layer 110 to the transaction / application layer 135. As shown, the read request bypass path bypasses the CXL.mem arbitration / multiplexing layer 125 of the CXL memory controller 100 and the link layer 130 of the CXL memory controller 100. The read bypass detection logic 115 receives a plurality of CXL microslices 108 from the CXL physical layer 110, and analyzes each of the received plurality of CXL microslices 108 to identify bypass memory read requests from the plurality of CXL microslices 108. Detecting a master-slave (M2S) request with a memory read opcode in the CXL microslice 108 identifies the bypass memory read request of the CXL microslice 108. Upon detecting the bypass memory read requests from the plurality of CXL flit 108 , the read bypass detection logic 115 directly forwards the bypass memory read requests to the CXL.mem transaction / application layer 135 via the read request bypass path 120 .

[0036] The physical layer 110 of the CXL memory controller 100 receives the plurality of data packets 102 from the PCIe / CXL SerDes interface 105, derives the plurality of CXL flits 108, and transmits the plurality of CXL flits 108 to both the read bypass detection logic 115 and the CXL.mem arbitration / multiplexing layer 125 of the CXL memory controller 100. As described above, the CXL.mem arbitration / multiplexing layer 125 identifies one or more link layer memory read requests from the plurality of CXL flits, and transmits the one or more link layer memory read requests to the CXL.mem link layer 130. The CXL.mem link layer 130 performs a cyclic redundancy check (CRC) on each of the one or more link layer memory read requests, transmits the link layer memory read requests that pass the CRC to the CXL.mem transaction / application layer 135 of the CXL memory controller 100, and discards the link layer memory read requests that do not pass the CRC.

[0037] After receiving the bypass memory read request from the read bypass detection logic 115, the CXL.mem transaction / application layer 135 of the CXL memory controller 100 forwards the read command to the memory controller and physical layer 140. When the read request queue 137 is empty, the memory controller and physical layer 140 then generates a memory read command and a memory activate command on a memory interface 147 of a memory device 145 associated with the CXL memory controller 100 in response to the bypass memory read request received at the transaction / application layer 135 through the read request bypass path 135. The CXL.mem transaction / application layer 135 then receives read data from the memory device 145 through the memory interface 147 under the control of the memory controller and physical layer 140 in response to the memory read command. When there is a link layer memory read request at CXL.mem transaction / application layer 135 that matches the bypass memory read request that generates the memory read command, CXL.mem transaction / application layer 135 forwards the read data received at CXL.mem transaction / application layer 135 to CXL.mem link layer 130. In a specific example, memory controller and physical layer 140 may be a DDR memory controller and physical layer, memory interface 147 may be a DDR interface, and memory device 145 may be a DDR device.

[0038] When the read request queue 137 is not empty, the CXL.mem transaction / application layer 135 does not generate a memory read command in response to the bypass memory read request, and the bypass memory read request is discarded. The CXL specification defines an M2S Req / MemSpecReq request that can be used to issue a speculative read to a memory device. A memory speculative read can be issued to initiate a memory access before the CXL memory controller 100 has resolved any coherency issues in the memory device 145, in order to reduce latency. However, read data can only be returned from the memory device 45 in response to the speculative read if a matching MemRd request has been received at the CXL.mem transaction / memory layer 135 of the CXL memory controller 100. In operation, upon receiving a bypass memory read request at the CXL.mem transaction / application layer 135, the CXL.mem transaction / application layer 135 does not consume a request buffer entry. The request buffer entry is required for link layer flow control and is expected to be consumed by an upcoming link layer M2S request (i.e., a matching MemRd request received from the CXL.mem link layer 130). If the read request queue 137 is not empty, the transaction / application layer 135 discards the bypass memory read request as described above. If the read request queue 137 is empty, the bypass memory read command is forwarded directly to the memory controller and physical layer 140.

[0039] In addition, when there is no link layer memory read request matching the bypass memory read request at CXL.mem transaction / application layer 135, CXL.mem transaction / application layer 135 discards the read data received at CXL.mem transaction / application layer in response to the bypass memory read request. All bypass memory read requests received at CXL.mem transaction / application layer 135 are expected to be the same memory read request from link layer 130 in the near future. If CXL.mem transaction / application layer 135 receives a memory read request from link layer 130 and it matches a pending bypass memory read request at CXL.mem transaction / application layer 135, CXL.mem transaction / application layer 135 discards the memory read request from link layer 130 and recycles the link layer credits. Therefore, CXL.mem transaction / application layer 135 will forward the read data from memory device 145 to link layer 130 only if a matching memory read request from link layer 130 has been received at CXL.mem transaction / application layer 135. If a matching memory read request from link layer 130 has not been received at CXL.mem transaction / application layer 135, then read bypass detection logic 115 erroneously detects a bypass memory read request from a full-data flit, or CXL.mem link layer 130 detects a CRC error or another uncorrectable error that occurred in CXL.mem link layer 130. In these cases, CXL.mem transaction / application layer 135 discards the read data associated with the bypass memory read request. This situation is considered a non-fatal condition, and in response, CXL.mem transaction / application layer 135 generates a debug event.

[0040] The bytes following the ProtID may not contain a .mem flitter with a header slot, and the flitter will be considered an all-data flitter. In an all-data flitter, data may be aliased, causing read bypass detection logic 115 to detect a bypass memory read request that does not exist. In this case, when the bypass memory read request is forwarded to CXL.mem transaction / application layer 135, CXL.mem transaction / application layer 135 may process the bypass memory read request and issue a read command to memory interface 147. The read data received in response to the false detection will then be discarded by CXL.mem transaction / application layer 135. However, the probability of this type of false detection is very small, and therefore the impact on the bandwidth of memory device 145 due to the false detection is negligible.

[0041] CXL.mem transaction / application layer 135 also discards bypass memory read requests that do not fall within the valid address space of memory device 145 and does not generate a memory read command on memory device interface 147 when the address space of a bypass memory read request is invalid.

[0042] Figure 5A and Figure 5B A method for reducing the number of CXL memory controllers (such as, Figure 1 500 of a method for delaying reads in a CXL memory controller 100 of the present invention.

[0043] At operation 502, the method begins by receiving a plurality of data packets at a physical layer of a CXL memory controller. Figure 1 The physical layer 110 of the CXL memory controller 100 may receive the plurality of data packets 102 from the PCIe / CXL SerDes interface 105 .

[0044] At operation 505, the method continues by deriving a plurality of Compute Express Link (CXL) flow control units (flits) from a plurality of data packets received at a physical layer of a CXL memory controller. Figure 1 , the physical layer 110 of the CXL memory controller 100 may derive a plurality of flits 108 from the plurality of received data packets 102 .

[0045] At operation 510, the method continues by transmitting the received each of the plurality of CXL micros to a read bypass detection logic of the CXL memory controller, and at operation 515, by analyzing each of the plurality of CXL micros at the read bypass detection logic to identify bypass memory read requests from the plurality of CXL micros. Figure 1 The plurality of CXL flit 108 may be received at the read bypass detection logic 115 of the CXL memory controller 100 , and the read bypass detection logic 115 may analyze each of the plurality of CXL flit 108 at the read bypass detection logic 115 to identify bypass memory read requests from the plurality of CXL flit 108 .

[0046] The method continues at operation 520 by transmitting a bypass memory read request directly to a transaction / application layer of the CXL memory controller via a read request bypass path, wherein the read request bypass path does not include an arbitration / multiplexing layer and a link layer of the CXL memory controller. Figure 1, bypass memory read requests may be transmitted directly to the CXL.mem transaction / application layer 135 of the CXL memory controller 100 via the read request bypass path 120 , thereby bypassing the CXL.mem arbitration / multiplexing layer 125 and the CXL.mem link layer 130 .

[0047] At operation 525, the method continues by generating a memory read command on an interface of a memory device attached to the CXL memory controller in response to a bypass memory read request received at the transaction / application layer of the CXL memory controller when the read request queue of the CXL memory controller is empty. Figure 1 , when the read request queue 137 of the CXL memory controller 100 is empty, a read command may be generated by the CXL.mem transaction / application layer 135 in response to the bypass memory read request, and the read command may be forwarded to the memory controller and physical layer 140. The memory controller and physical layer 140 may then generate a memory read command on the memory interface 147 of the memory device 145 in response to the bypass memory read request received at the CXL.mem transaction / application layer 135 of the CXL memory controller 100. If the memory device page is not yet open, the memory controller and physical layer 140 may also generate an activate command on the memory interface 147 before generating the memory read command on the memory interface.

[0048] At operation 530, the method continues by receiving read data from the memory device at the transaction / application layer in response to the memory read command, and the method ends at operation 535 by forwarding the read data received at the transaction / application layer to the link layer of the CXL memory controller when there is a link layer memory read request at the transaction / application layer that matches the bypass memory read request that generated the memory read command. Optionally, if there is no link layer memory read request at the transaction / application layer that matches the bypass memory read request that generated the memory read command, the read data received at the transaction / application layer is discarded. Reference Figure 1 When there is a link layer memory read request at CXL.mem transaction / application layer 135 that matches the bypass memory read request that generates the memory read command, read data received from memory device 145 at CXL.mem transaction / application layer 135 in response to the memory read command is forwarded to CXL.mem link layer 130 of CXL memory controller 100 .

[0049] Fig. 6A and Figure 6B is a set of flow charts 600 illustrating exemplary methods for reducing read latency in a CXL memory controller and for selectively discarding bypass memory read requests.

[0050] At operation 605, the method begins by receiving a plurality of Compute Express Link (CXL) flow control units (flits) at a physical layer of a CXL memory controller. Figure 1 , the CXL physical layer 110 of the CXL memory controller 100 can receive a plurality of flits.

[0051] At operation 610, the method continues by transmitting the received each of the plurality of CXL micros to a read bypass detection logic of the CXL memory controller, and at operation 615, by analyzing each of the plurality of CXL micros at the read bypass detection logic to identify bypass memory read requests from the plurality of CXL micros. Figure 1 The plurality of CXL flit 108 may be received at the read bypass detection logic 115 of the CXL memory controller 100 , and the read bypass detection logic 115 may analyze each of the plurality of CXL flit 108 at the read bypass detection logic to identify bypass memory read requests from the plurality of CXL flit 108 .

[0052] The method continues at operation 620 by transmitting the bypass memory read request directly to the transaction / application layer of the CXL memory controller via a read request bypass path, wherein the read request bypass path does not include the arbitration / multiplexing layer and the link layer of the CXL memory controller. Figure 1 , bypass memory read requests may be transmitted directly to the CXL.mem transaction / application layer 135 of the CXL memory controller 100 via the read request bypass path 120 , thereby bypassing the CXL.mem arbitration / multiplexing layer 125 and the CXL.mem link layer 130 .

[0053] At operation 625, the method continues by determining whether the read request queue of the CXL memory controller is empty. If it is determined at operation 625 that the read request queue of the CXL memory controller is empty, the method continues at operation 630. If it is determined that the read request queue of the CXL memory controller is not empty, the method ends at operation 635 by not generating a memory read command on an interface of a memory device attached to the CXL memory controller in response to the bypass memory read request and discarding the bypass memory read request. Figure 1 , read request queue 137 may be determined by CXL.mem transaction / application layer 135 to be empty or not empty.

[0054] At operation 630, the method continues by determining whether the address space of the bypass memory read request is valid. If the address space is determined to be valid, the method then proceeds to Figure 6BThe method continues at operation 645. If it is determined that the address space of the bypass memory read request is invalid, the method ends at operation 640 by discarding the bypass memory read request. Figure 1 , the transaction / application layer 135 may determine whether the address space of the bypass memory read request is valid, and if not, discard the bypass memory read request.

[0055] The method continues at operation 645 by generating a memory read command on an interface of a memory device attached to the CXL memory controller in response to the bypass memory read request received at the transaction / application layer of the CXL memory controller, and continues at operation 650 by receiving read data from the memory device at the transaction layer in response to the memory read command. Figure 1 , a read command may be generated by the CXL.mem transaction / application layer 135 of the CXL memory controller 100 in response to receiving the bypass memory read request. The read command may then be forwarded to the memory controller and physical layer 140. The memory controller and physical layer 140 may then generate a memory read command on the interface 147 of the memory device 145. Thus, a memory read command is generated on the interface of the memory device attached to the CXL memory controller in response to the bypass memory read request received at the transaction / application layer 135 of the CXL memory controller 100, and read data from the memory device 145 may be received.

[0056] At operation 655, it is determined whether there is a link layer memory read request at the transaction / application layer that matches the bypass memory read request that generated the memory read command. If there is a matching link layer memory read request, the method ends at operation 660 by forwarding the read data received at the transaction / application layer to the link layer of the CXL memory controller 360. If there is no matching link layer memory read request, the method ends at operation 665 by discarding the read data received at the transaction / application layer. Figure 1 If there is a memory read request from CXL.mem link layer 130 that matches the bypass memory read request at CXL.mem transaction / application layer 135, then CXL.mem transaction / application layer 135 forwards the read data to CXL.mem link layer 130. Alternatively, if there is no matching link layer memory read request at CXL.mem transaction / application layer 135, then CXL.mem transaction / application layer 135 discards the read data from the memory device.

[0057] Figure 7is a flow chart illustrating an exemplary method 700 for reducing read latency in a CXL memory controller and for selectively discarding link layer memory read requests.

[0058] At operation 705, the method begins by transmitting a plurality of CXL flits received at a physical layer of a CXL memory controller to an arbitration / multiplexing layer of the CXL memory controller. Figure 1 , the CXL flits 108 received at the CXL physical layer 110 are transmitted to the CXL.mem arbitration / multiplexing layer 125 .

[0059] The method continues at operation 710 by identifying one or more link layer memory read requests from a plurality of CXL microslices at an arbitration / multiplexing layer of a CXL memory controller; continues at operation 715 by transmitting the identified one or more link layer memory read requests to a link layer of the CXL memory controller; continues at operation 720 by performing a cyclic redundancy check (CRC) on each of the identified and transmitted one or more link layer memory read requests; and continues at operation 725 by transmitting the link layer memory read requests that pass the CRC to a transaction / application layer of the CXL memory controller. The method ends at operation 730 by discarding the link layer memory read requests that do not pass the CRC. Reference Figure 1 , the CXL.mem arbitration / multiplexing layer 135 may identify one or more link layer memory read requests from the CXL flit 108 and transmit the identified one or more link layer memory read requests to the CXL.mem link layer 130. A CRC check may be performed on the identified one or more link layer memory read requests, and link layer memory read requests that fail the CRC may be discarded.

[0060] Fig. 8A and Figure 8B is a set of flow charts 800 illustrating methods for reducing read latency in a CXL memory controller and for matching link layer memory read requests to bypass memory read requests according to examples of the present invention.

[0061] At operation 805, the method begins by receiving a plurality of Compute Express Link (CXL) flow control units (flits) at a physical layer of a CXL memory controller. Figure 1 The CXL physical layer 110 of the CXL memory controller 100 may receive the plurality of microslices 108 .

[0062] At operation 810, the method continues by transmitting the received each of the plurality of CXL micros to a read bypass detection logic of the CXL memory controller, and at operation 815, by analyzing each of the plurality of CXL micros at the read bypass detection logic to identify bypass memory read requests from the plurality of CXL micros. Figure 1 The plurality of CXL flit 108 may be received at the read bypass detection logic 115 of the CXL memory controller 100 , and the read bypass detection logic 115 may analyze each of the plurality of CXL flit 108 at the read bypass detection logic 115 to identify bypass memory read requests from the plurality of CXL flit 108 .

[0063] The method continues at operation 820 by transmitting a bypass memory read request directly to a transaction / application layer of the CXL memory controller via a read request bypass path, wherein the read request bypass path does not include an arbitration / multiplexing layer and a link layer of the CXL memory controller. Figure 1 , bypass memory read requests may be transmitted directly to the CXL.mem transaction / application layer 135 of the CXL memory controller 100 via the read request bypass path 120 , thereby bypassing the CXL.mem arbitration / multiplexing layer 125 and the CXL.mem link layer 130 .

[0064] At operation 825, the method continues by generating a memory read command on an interface of a memory device attached to the CXL memory controller in response to a bypass memory read request received at a transaction / application layer of the CXL memory controller when the read request queue of the CXL memory controller is empty, and discarding the bypass memory read request when the read request queue of the CXL memory controller is not empty. Figure 1 , when the read request queue 137 of the CXL memory controller 100 is empty, a memory read command may be generated on the interface 147 of the memory device 145 in response to a bypass memory read request received at the transaction / application layer 135 of the CXL memory controller 100. Alternatively, when the read request queue 137 is not empty, the transaction / application layer 135 may discard the bypass memory read request before generating the memory read command on the interface 147 of the memory device 145.

[0065] At operation 830, the method continues by receiving read data from the memory device at the transaction / application layer in response to the memory read command, and the method ends at operation 835 by forwarding the read data received at the transaction / application layer to the link layer of the CXL memory controller when there is a link layer memory read request at the transaction / application layer that matches the bypass memory read request that generated the memory read command. Additionally, if there is no link layer memory read request at the transaction / application layer that matches the bypass memory read request that generated the memory read command, the read data received at the transaction / application layer is discarded. Figure 1 When there is a link layer memory read request matching the bypass memory read request generating the memory read command at CXL.mem transaction / application layer 135, read data received from memory device 145 at CXL.mem transaction / application layer 135 in response to the memory read command is forwarded to CXL.mem link layer 130 of CXL memory controller 100. Alternatively, when there is no link layer memory read request matching the bypass memory read request generating the memory read command at transaction / application layer 135, CXL.mem transaction / application layer 135 discards the read data.

[0066] In various examples, parts of the system of the present invention examples may be implemented in a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC). It will be appreciated by those skilled in the art that the various functions of the circuit elements may also be implemented as processing steps in a software program. Such software may be used, for example, in a digital signal processor, a network processor, a microcontroller, or a general purpose computer.

[0067] Unless specifically stated otherwise as apparent from the discussion, it should be understood that throughout this specification, discussions utilizing terms such as "receiving," "determining," "generating," "limiting," "sending," "counting," "classifying," and the like may refer to actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage, transmission, or display devices.

[0068] Examples of the present invention may be embodied on various computing platforms that perform actions in response to software-based instructions. The following provides a prerequisite foundation of information technology that can be used to implement examples of the present invention.

[0069] The method of the present invention example can be stored on a computer-readable medium, which can be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared or semiconductor system, device or equipment, or any suitable combination of the foregoing. A more specific example (non-exhaustive list) of a computer-readable storage medium will include the following: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer-readable storage medium can be any non-transient tangible medium that can contain or store a program for use by an instruction execution system, a device or equipment or used in combination with them.

[0070] A computer readable signal medium may include a data signal propagated, for example, in baseband or as part of a carrier wave, in which a computer readable program code is embodied. Such propagated signals may take any of a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer readable signal medium may be any computer readable medium that is not a computer readable storage medium, which may convey, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device. However, as indicated above, due to the circuit statutory subject matter limitations, claims as software products are those embodied in non-transitory software media such as a computer hard drive, flash-RAM, optical disk, etc.

[0071] The program code embodied on the computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, fiber optic cable, radio frequency, etc., or any suitable combination of the foregoing. The computer program code for performing the operations of various aspects of the examples of the present invention may be written using any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C#, C++, Visual Basic, and conventional procedural programming languages ​​such as the "C" programming language or similar programming languages.

[0072] The following is a description of various aspects of the examples of the present invention with reference to flowchart illustrations and / or block diagrams of methods, devices (systems) and computer program products. It should be understood that each frame of the flowchart and / or block diagram and the combination of frames in the flowchart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device for implementing the function / action specified in one or more flowcharts and / or block diagram frames.

[0073] These computer program instructions may also be stored in a computer-readable medium that can direct a computer, processor, or other programmable data processing device or other apparatus to function in a specific manner, so that the instructions stored in the computer-readable medium produce an article of manufacture including instructions for implementing the functions / actions specified in one or more flowcharts and / or block diagrams.

[0074] The computer program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operational steps are performed on the computer, other programmable apparatus, or other device to produce a computer-implemented process, whereby the instructions executed on the computer or other programmable apparatus provide a process for implementing the functions / actions specified in one or more flowcharts and / or block diagram blocks.

[0075] In addition, for the purpose of discussing and understanding examples, it should be understood that various terms are used by those skilled in the art to describe techniques and methods. In addition, in this specification, for the purpose of explanation, many specific details are set forth in order to provide a thorough understanding. However, it is obvious to those of ordinary skill in the art that examples of the present invention can be practiced without these specific details. In some cases, well-known structures and devices are shown in block diagram form, rather than in detail. These examples are described in sufficient detail to enable those of ordinary skill in the art to practice examples, and it should be understood that other examples can be utilized without departing from the scope, and logical, mechanical, electrical and other changes can be made.

Claims

1. A method for bypassing memory read request detection, the method comprising: receiving a plurality of data packets at a physical layer of a CXL memory controller; deriving a plurality of Compute Express Link CXL flits from the plurality of data packets received at the physical layer of the CXL memory controller; transmitting each of the received plurality of CXL flits to a read bypass detection logic of the CXL memory controller; analyzing each of the plurality of CXL microslices at the read bypass detection logic to identify a bypass memory read request from the plurality of CXL microslices; transmitting the bypass memory read request directly to a transaction layer and / or an application layer of the CXL memory controller via a read request bypass path, wherein the read request bypass path does not include an arbitration and multiplexing layer and a link layer of the CXL memory controller; generating a memory read command on an interface of a memory device attached to the CXL memory controller in response to the bypass memory read request received at the transaction layer and / or application layer of the CXL memory controller when a read request queue of the CXL memory controller is empty; receiving, at the transaction layer and / or application layer, read data from the memory device in response to the memory read command; as well as When there is a link layer memory read request at the transaction layer and / or application layer that matches the bypass memory read request that generates the memory read command, the read data received at the transaction layer and / or application layer is forwarded to the link layer of the CXL memory controller.

2. The method according to claim 1, comprising: When there is no link layer memory read request matching the bypass memory read request generating the memory read command at the transaction layer and / or application layer, the read data received at the transaction layer and / or application layer is discarded.

3. The method of claim 1 , wherein analyzing each of the plurality of CXL micros at the read bypass detection logic of the CXL memory comprises: A master-slave M2S request with a memory read opcode in the CXL microchip is detected to identify the bypass memory read request.

4. The method according to claim 1, comprising: When the read request queue of the CXL memory controller is not empty, the memory read command is not generated on the interface of the memory device attached to the CXL memory controller and the bypass memory read request is discarded. 5 . The method of claim 1 , comprising discarding the link layer memory read request that matches the bypass memory read request that generated the memory read command.

6. The method according to claim 1, comprising: When the address space of the bypass memory read request is invalid, the bypass memory read request at the transaction layer and / or application layer is discarded, and the memory read command is not generated on the memory device interface.

7. The method according to claim 1, comprising: An activate command is transmitted on the memory device interface prior to generating the memory read command on the memory device interface.

8. The method according to claim 1, comprising: transmitting the plurality of CXL flits received at the physical layer of the CXL memory controller to the arbitration and multiplexing layer of the CXL memory controller; identifying, at the arbitration and multiplexing layer of the CXL memory controller, one or more link layer memory read requests from the plurality of CXL flitches; transmitting the identified one or more link layer memory read requests to the link layer of the CXL memory controller; performing a cyclic redundancy check CRC on each of the identified and transmitted one or more link layer memory read requests; transmitting the link layer memory read request passing the CRC to the transaction layer and / or application layer of the CXL memory controller; as well as The link layer memory read requests that fail the CRC are discarded.

9. The method of claim 1, wherein the memory devices attached to the CXL memory controller are double data rate (DDR) memory devices.

10. A method for reading a memory device, the method comprising: receiving a plurality of compute fast link CXL flits at a physical layer of a CXL memory controller; transmitting each of the received plurality of CXL flits to a read bypass detection logic of the CXL memory controller; analyzing, at the read bypass detection logic, each of the received and transmitted plurality of CXL flits to identify a bypass memory read request from the plurality of CXL flits, wherein the bypass memory read request includes an address space; transmitting the bypass memory read request directly to a transaction layer and / or an application layer of the CXL memory controller via a read request bypass path, wherein the read request bypass path does not include an arbitration and multiplexing layer and a link layer of the CXL memory controller; When the address space of the bypass memory read request is invalid, discarding the bypass memory read request at the transaction layer and / or application layer; generating a memory read command on an interface of a memory device attached to the CXL memory controller in response to the bypass memory read request received at the transaction layer and / or application layer of the CXL memory controller when a read request queue of the CXL memory controller is empty, and discarding the bypass memory read request when the read request queue of the CXL memory controller is not empty; receiving, at the transaction layer and / or application layer, read data from the memory device in response to the memory read command; as well as forwarding the read data received at the transaction layer and / or application layer to the link layer of the CXL memory controller when there is a link layer memory read request matching the bypass memory read request generating the memory read command at the transaction layer and / or application layer, and discarding the read data received at the transaction layer and / or application layer when there is no link layer memory read request matching the bypass memory read request generating the memory read command at the transaction layer and / or application layer.

11. The method according to claim 10, comprising: transmitting the plurality of CXL flits received at the physical layer of the CXL memory controller to the arbitration and multiplexing layer of the CXL memory controller; identifying, at the arbitration and multiplexing layer of the CXL memory controller, one or more link layer memory read requests from the plurality of CXL flitches; transmitting the identified one or more link layer memory read requests to the link layer of the CXL memory controller; as well as performing a cyclic redundancy check CRC on each of the one or more link layer memory read requests; transmitting the link layer memory read request passing the CRC to the transaction layer and / or application layer of the CXL memory controller; as well as The link layer memory read requests that fail the CRC are discarded.

12. A Compute Express Link (CXL) memory controller, the CXL memory controller comprising: a read bypass detection logic to receive a plurality of CXL flits from a CXL physical layer of a CXL memory controller and analyze each of the received plurality of CXL flits to identify a bypass memory read request from the plurality of CXL flits; a read request bypass path, the read request bypass path including the read bypass detection logic, the read request bypass path connecting the CXL physical layer to a transaction layer and / or an application layer of the CXL memory controller, the read request bypass path bypassing an arbitration and multiplexing layer of the CXL memory controller and a link layer of the CXL memory controller; The transaction layer and / or application layer are used to: generating a memory read command on an interface of a memory device associated with the CXL memory controller in response to the bypass memory read request received at the transaction layer and / or application layer when the read request queue is empty; receiving read data from the memory device in response to the memory read command; as well as When there is a link layer memory read request at the transaction layer and / or application layer that matches the bypass memory read request that generates the memory read command, the read data received at the transaction layer and / or application layer is forwarded to the link layer.

13. The CXL memory controller of claim 12, wherein the read bypass detection logic is to analyze each of the plurality of CXL micros by detecting a master-slave M2S request with a memory read opcode in the CXL micro to identify the bypass memory read request.

14. The CXL memory controller of claim 12 , wherein the transaction layer and / or application layer is configured to discard the read data received at the transaction layer and / or application layer when there is no link layer memory read request matching the bypass memory read request that generated the memory read command at the transaction layer and / or application layer.

15. The CXL memory controller of claim 12, wherein the transaction layer and / or application layer is configured to not generate the memory read command on the interface of the memory device and discard the bypass memory read request when the read request queue is not empty.

16. The CXL memory controller of claim 12, wherein the transaction layer and / or application layer is configured to discard the link layer memory read request that matches the bypass memory read request that generated the memory read command.

17. The CXL memory controller of claim 12, wherein the transaction layer and / or application layer is configured to discard the bypass memory read request and not generate the memory read command on the memory device interface when an address space of the bypass memory read request is invalid.

18. The CXL memory controller of claim 12, wherein the transaction layer and / or application layer is operable to transmit an activate command on the memory device interface prior to generating the memory read command on the memory device interface.

19. The CXL memory controller of claim 12, comprising: the physical layer of the CXL memory controller, the physical layer to receive the plurality of CXL flits, transmit the plurality of CXL flits to the read bypass detection logic, and transmit the plurality of CXL flits to the arbitration and multiplexing layer of the CXL memory controller; the arbitration and multiplexing layer for identifying one or more link layer memory read requests from the plurality of CXL flitches and transmitting the one or more link layer memory read requests to the link layer; and The link layer is configured to perform a cyclic redundancy check (CRC) on each of the one or more link layer memory read requests, transmit the link layer memory read requests that pass the CRC to the transaction layer and / or application layer of the CXL memory controller, and discard the link layer memory read requests that fail the CRC.

20. The CXL memory controller of claim 12, wherein the memory devices are double data rate (DDR) memory devices.

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