Signal transmission circuit, control method, control circuit and communication system

Abstract

A signal transmission circuit, a control method, a control circuit and a communication system, the signal transmission circuit is used for transmitting signals between a first circuit and a second circuit, comprising a first connector, a re-timing circuit, a second connector and a control circuit. The first connector realizes signal transmission between the first circuit and the re-timing circuit; the re-timing circuit receives signals from the first connector (or the second connector), re-times and reshapes the signals, and then outputs the signals to the second connector (or the first connector); the second connector realizes signal transmission between the second circuit and the re-timing circuit; the control circuit outputs a first reset signal to the re-timing circuit after a first time delay, so that the first reset signal is pulled high after the clock signal of the first circuit is stable; at the same time, the first reset signal triggers firmware loading of the re-timing circuit, and the re-timing circuit completes firmware loading before a global reset signal arrives, so as to meet the power-on sequence of the re-timing circuit.

Description

Technical Field

[0001] This application relates to the field of testing technology, and more particularly to a signal transmission circuit, control method, control circuit, and communication system. Background Technology

[0002] With the development of big data, artificial intelligence, cloud computing, and other fields, the demand for high-speed data interaction between hardware devices has become increasingly urgent. High-speed bus technology provides the foundation for data interaction between hardware devices, and its continuous development has led to a constant increase in transmission rates. For example, Peripheral Component Interconnect Express (PCIe) technology has become the mainstream solution for high-speed buses due to its high transmission rate and low implementation cost. PCIe technology continues to evolve, for example, from PCIe 4.0 to PCIe 5.0, and towards PCIe 6.0, enabling another leap in the data interaction rate between hardware devices. However, this also brings with it the problem of signal attenuation that cannot be ignored.

[0003] Currently, a solution to this signal attenuation problem is a retimer board (which includes a retimer chip). However, this retimer board solution still faces the challenge of limiting motherboard selection in practical applications. Summary of the Invention

[0004] The purpose of this application is to provide a signal transmission circuit, control method, control circuit, and communication system to effectively solve the problem of limited motherboard selection.

[0005] The technical solution provided in this application is as follows:

[0006] A signal transmission circuit for transmitting signals between a first circuit and a second circuit, comprising:

[0007] The first connector is used to connect to the first circuit, receive a first signal from the first circuit, or output a fourth signal to the first circuit.

[0008] The second connector is used to connect to the second circuit and output a second signal to the second circuit; or to receive a third signal from the second circuit.

[0009] A retiming circuit, signal-connected to the first connector and the second connector, is used to receive the first signal from the first circuit from the first connector, retime and reshape the first signal to obtain the second signal and output it to the second connector; or, to receive the third signal from the second circuit from the second connector, retime and reshape the third signal to obtain the fourth signal and output it to the first connector.

[0010] A control circuit, connected to the retiming circuit, is used to output a first reset signal to the retiming circuit after a first time delay. The first reset signal is used to trigger firmware loading of the retiming circuit.

[0011] In some embodiments, the control circuit is further configured to determine the first delay, wherein the first delay is greater than the clock settling time of the first circuit; and the sum of the first delay and the firmware loading time is less than the global reset time of the first circuit.

[0012] In some embodiments, the signal transmission circuit further includes:

[0013] The third connector is connected to the control circuit signal; and

[0014] The control circuit is further configured to acquire the firmware through the third connector and provide the firmware to the retiming circuit.

[0015] In some implementations, the control circuit is further configured to retrieve the operation log of the retiming circuit and export it to the user terminal via the third connector.

[0016] In some embodiments, the control circuit is further configured to acquire the in-situ status of the second circuit via the second connector and feed back the in-situ status of the second circuit to the retiming circuit.

[0017] In some embodiments, the signal transmission circuit further includes:

[0018] A buffer is used to receive a clock signal and a second reset signal from the first circuit, and to split the received clock signal and the second reset signal to the retiming circuit and the second circuit.

[0019] This application also provides a communication system, including:

[0020] The first circuit, the second circuit, and the signal transmission circuit described in any of the above;

[0021] The signal transmission circuit is connected to the first circuit via the first connector; and the signal transmission circuit is connected to the second circuit via the second connector.

[0022] In some implementations, the communication system is a test system or a server system.

[0023] This application further provides a signal transmission control method, applied to the signal transmission circuit as described in any of the above claims, comprising:

[0024] Obtain the first time delay information of the first circuit;

[0025] Based on the first delay information, a first delay is determined, and after the first delay, a retiming circuit is triggered to load firmware to transmit signals.

[0026] This application further provides a signal transmission control circuit, applied to the signal transmission circuit described in any of the above claims, the control circuit comprising:

[0027] The acquisition unit is used to acquire the first time delay information of the first circuit.

[0028] The determining unit is configured to determine the first delay based on the first delay information;

[0029] The triggering unit is used to trigger the retiming circuit to load firmware after the first delay.

[0030] The technical advantages of this application are as follows:

[0031] 1. In this application, the control circuit outputs the first reset signal to the retiming circuit signal only after a first time delay to trigger the firmware loading of the control circuit. This delays the first reset signal of the retiming circuit, ensuring that the first reset signal of the retiming circuit is pulled high only after the clock signal of the first circuit has stabilized. This allows the retiming circuit to complete firmware loading before the global reset signal arrives, thus satisfying the power-on timing requirements of the retiming circuit. This solves the timing constraints of the signal transmission circuit during use, providing more options for the motherboard of storage test equipment. It also allows consumer motherboards, which were previously unsuitable for storage test equipment, to be used effectively, significantly reducing the cost of storage test equipment and demonstrating strong practicality.

[0032] 2. In this application, the third connector is connected to the control circuit, and the firmware of the retiming circuit is burned or upgraded through the control circuit. This allows the signal transmission circuit to perform firmware upgrades on the control circuit and the retiming circuit through the third connector alone, eliminating the external interface of the retiming circuit and reducing the physical interfaces of the signal transmission circuit. This results in higher product integration and lower production costs, which can further reduce the cost of storage test equipment.

[0033] 3. In this application, the control circuit can retrieve the operation log of the retiming circuit. Thus, when a storage test machine malfunctions during testing, the control circuit can retrieve the operation log of the retiming circuit to the user end for troubleshooting, quickly locate the source of the fault, shorten the fault analysis time of the storage test machine, save human resources, and improve the utilization rate of the storage test machine.

[0034] 4. In this application, the control circuit can obtain the in-situ state of the second circuit and control the retiming circuit to reset the corresponding port according to the in-situ state of the second circuit, so that the storage test equipment can support the hot-swap test of the back-end memory, shorten the test time of the storage test equipment and improve the test efficiency. Attached Figure Description

[0035] The present application will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0036] Figure 1 This is a schematic diagram of a communication system provided in an embodiment of this application;

[0037] Figure 2 This is a schematic diagram of a signal transmission circuit provided in an embodiment of this application;

[0038] Figure 3 This is a signal timing diagram in one application of a signal transmission circuit provided in the embodiments of this application;

[0039] Figure 4 This is a schematic diagram of another signal transmission circuit provided in an embodiment of this application.

[0040] Explanation of icon numbers:

[0041] 110. Motherboard; 120. Memory; 130. Retiming board; 140. Adapter;

[0042] 200, Signal transmission circuit; 210, First connector; 220, Second connector; 230, Retiming circuit; 240, Control circuit; 250, Third connector; 260, Buffer. Detailed Implementation

[0043] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application can also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0044] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the specific implementation methods of this application will be described below with reference to the accompanying drawings. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings and other implementation methods can be obtained based on these drawings without creative effort.

[0045] To keep the drawings concise, only the parts relevant to this application are shown schematically in each drawing, and they do not represent the actual structure of the product. In addition, to make the drawings concise and easy to understand, in some drawings, only one of the components with the same structure or function is shown schematically, or only one of them is labeled.

[0046] In this document, it should be noted that, unless otherwise explicitly specified and limited, the term "connection" should be interpreted broadly. For example, it can refer to a fixed connection, a detachable connection, or an integral connection; or it can refer to a mechanical connection or an electrical connection; or it can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0047] In the embodiments shown in the accompanying drawings, the directional indications (such as up, down, left, right, front, and back) are relative rather than absolute when describing the structure and movement of the various components, and are not intended to limit the direction of the product during actual use.

[0048] Furthermore, in the description of this application, ordinal numbers, such as "first" and "second," are used only to distinguish related objects and should not be construed as indicating or implying the relative importance or order between related objects.

[0049] High-speed data exchange between hardware devices can utilize high-speed bus technologies, such as Peripheral Component Interconnect Express (PCIe). With the continuous iteration of high-speed bus technology, transmission rates increase generation by generation, but this also brings signal attenuation problems. For example, signal attenuation has become increasingly severe in the iteration of the PCIe standard. To address this signal attenuation problem, a retimer card (130) can be connected between interacting hardware devices to retime and reshape signals.

[0050] The following description is in conjunction with the accompanying drawings:

[0051] Please refer to Figure 1This application provides a communication system comprising a motherboard 110 and a memory 120. The motherboard 110 communicates with the memory 120 via a high-speed bus, such as a PCIe bus. The motherboard 110 may house a processor. The memory 120 is, for example, a solid-state drive and is connected to an adapter 140 to adapt to the bus's interface protocol, such as the PCIe protocol. A retiming board 130 contains a retiming chip. When the motherboard 110 and the memory 120 are far apart, signal attenuation on the high-speed bus will affect communication between them. Therefore, the retiming board 130 is used to address this issue. However, the solution using the retiming board 130 still suffers from timing-related flexibility issues.

[0052] For example, when the above communication system is used in a storage test bench, the transmission distance between the motherboard 110 and the back-end memory 120 is relatively long, resulting in severe attenuation of the PCIe signal along the path. Therefore, a retiming card 130 is installed in the storage test bench to enhance the PCIe signal in the transmission line to compensate for the attenuation. However, due to the timing requirements of current retiming chips, some consumer motherboards 110 with short boot times cannot meet these timing requirements, necessitating the customization of a special version of the Basic Input Output System (BIOS). This makes the selection of motherboard 110 relatively limited and costly.

[0053] In view of the above technical problems, this application provides a signal transmission circuit 200, which uses a control circuit 240 to manage timing signals, so as to solve the timing limitation problem of the Retimer board during use, thereby providing more motherboard 110 selection possibilities and reducing the cost of using the Retimer board.

[0054] The following description is in conjunction with the accompanying drawings:

[0055] See Figure 2 This is a schematic diagram of a signal transmission circuit 200 provided in an embodiment of this application. The signal transmission circuit 200 is used to transmit signals between a first circuit and a second circuit, for example, to transmit a signal from the first circuit to the second circuit, or vice versa, primarily serving as a signal relay between the first and second circuits. Especially when the signal transmission distance between the first and second circuits is long, this signal transmission circuit 200 can be used to assist in signal transmission.

[0056] The first circuit is located in the first hardware device, and the second circuit is located in the second hardware device. In one application, the first hardware device is, for example, a motherboard 110, and the second hardware circuit is, for example, a memory 120; or, the first hardware device is, for example, a memory 120, and the second hardware circuit is, for example, a motherboard 110. This application is not limited to the type of hardware device and can also be applied to signal transmission between other types of hardware devices, and the first hardware device and the second hardware device may be of the same or different types.

[0057] Specifically, the signal transmission circuit 200 includes a first connector 210, a second connector 220, a retiming circuit 230, and a control circuit 240. The first connector 210 is used for signal connection to a first circuit, the second connector 220 is used for signal connection to a second circuit, the retiming circuit 230 is signal-connected to both the first connector 210 and the second connector 220, and the control circuit 240 is signal-connected to the retiming circuit 230. Specifically, the first connector 210 receives a first signal from the first circuit, the retiming circuit 230 receives the first signal from the first connector 210, retims and reshapes the first signal to obtain a second signal, and outputs it to the second connector 220, which then transmits it to the second circuit; the second connector 220 outputs the second signal to the second circuit; or, the second connector 220 receives a third signal from the second circuit, the retiming circuit 230 receives the third signal from the second connector 220, retims and reshapes the third signal to obtain a fourth signal, and outputs it to the first connector 210, which then transmits it to the first circuit.

[0058] This embodiment effectively reduces signal attenuation during signal transmission and increases signal transmission distance by setting a retiming circuit 230.

[0059] Furthermore, the control circuit 240 is signal-connected to the retiming circuit 230, and outputs a first reset signal to the retiming circuit 230 after a first time delay. This first reset signal is used to trigger the firmware loading of the retiming circuit 230.

[0060] As the transmission rate of high-speed buses increases generation by generation, signal attenuation becomes increasingly serious. For example, in the iteration of the PCIe standard, on the one hand, the continuous development of applications drives the iterative updates of the PCIe standard, continuously increasing its signal transmission rate, even doubling it; however, this significant increase in transmission rate also leads to more severe signal loss in the link. The signal transmission circuit provided in this embodiment can effectively solve the loss problem of PCIe signal links and improve the transmission distance of PCIe signals. In addition, through the timing management of the control circuit 240, the selection of the server motherboard 110 is more flexible, which helps to reduce costs. At this time, the circuit on the server can be the first circuit mentioned above, and the circuit on the back-end memory 120 can be the second circuit mentioned above; or, the circuit on the server can be the second circuit mentioned above, and the circuit on the back-end memory 120 can be the first circuit mentioned above.

[0061] The signal transmission circuit 200 provided in this embodiment can also be used in storage test benches, such as solid-state drive test benches. Because the transmission distance between the motherboard 110 and the back-end memory 120 in a storage test bench is relatively long, resulting in severe attenuation of the bus signal along the path, a signal transmission circuit 200 with a retiming circuit 230 is provided in the storage test bench to enhance the bus signal in the transmission line and compensate for the attenuation. In this case, the circuit on the motherboard 110 in the storage test bench can be understood as the first circuit described above, and the circuit on the back-end memory 120 is the second circuit described above; or, the circuit on the motherboard 110 in the storage test bench can be understood as the second circuit described above, and the circuit on the back-end memory 120 is the first circuit described above.

[0062] Furthermore, the signal transmission circuit 200 provided in this embodiment can be integrated into a timing board 130, i.e., a Retimer board.

[0063] However, because the Retimer chip on the Retimer board requires the global reset signal (PERST signal) on the first or second circuit to arrive after the firmware loading is complete, and the clock signal on the first circuit must be stable before the firmware loading, some first circuits with short power-on times cannot meet this timing requirement.

[0064] To address this, this embodiment connects the control circuit 240 to the retiming circuit 230 via a signal connection. After a first time delay, the control circuit 240 outputs a first reset signal to the retiming circuit 230. This first reset signal triggers the loading of the firmware (FW) in the retiming circuit 230. Thus, the control circuit 240 can delay the first reset signal of the retiming circuit 230, ensuring that the first reset signal is pulled high only after the clock signal of the first or second circuit has stabilized. This allows the retiming circuit 230 to complete firmware loading before the arrival of the second reset signal (which is the aforementioned global reset signal – PERST signal) from the first or second circuit, thereby satisfying the power-on timing of the retiming circuit 230 and resolving the timing constraints of the signal transmission circuit during use.

[0065] In this embodiment, the delay mentioned can be understood as a delay of a period of time, and "first" is used as a distinguishing description to differentiate this delay from other delays mentioned later.

[0066] In one implementation, the control circuit 240 can be integrated as a microcontroller unit (MCU). The retimer circuit 230 is equipped with a Retimer chip, and the first reset signal output by the MCU to the Retimer chip is a high level (or a low level). When the Retimer chip receives this high level (or low level), it will be triggered to load firmware.

[0067] Taking the signal transmission circuit 230 used in a storage-type test instrument as an example, the first circuit is the circuit on the motherboard 110. See [link / reference needed]. Figure 3 During the test, the tester will first press the power button on the motherboard 110 and then release it. The moment the power button is pressed, the power signal of the motherboard 110 will be pulled high immediately. Simultaneously, the clock signal of the motherboard 110 will stabilize after a period of time T. Furthermore, the global reset signal (PERST signal) of the motherboard 110 will be pulled high after a second delay. This second delay X is primarily determined by the motherboard 110 model; the specific duration of the second delay varies depending on the motherboard 110 model. For ease of explanation later, the specific duration of this second delay will be represented by X.

[0068] Let Y be the time for the retiming circuit 230 (e.g., the Retimer chip) to load the firmware. To ensure that the retiming circuit 230 can complete loading the firmware after the clock signal of the motherboard 110 stabilizes and before the PERST signal arrives, the reset signal of the retiming circuit 230 is delayed. For example, the MCU outputs a first reset signal to the Retimer chip after a first delay. For ease of description later, the specific duration of the first delay is represented by Z. Specifically, the reset signal of the retiming circuit 230 is pulled high by the control circuit 240 after a delay of Z. After the reset signal is pulled high, the retiming circuit 230 begins loading the firmware, and the loading is completed after a period of Y.

[0069] Under the control of the control circuit 240, the retiming circuit 230 can load the firmware after the clock signal of the motherboard 110 stabilizes and before the arrival of the PERST signal, thus satisfying the relationship: ZT>0, and Z+Y <X。

[0070] Therefore, in one specific embodiment, the first delay is greater than the clock settling time of the first circuit; and the sum of the first delay and the firmware loading time is less than the global reset time of the first circuit. This solves the timing constraints of the Retimer board during use, enabling the Retimer chip to adapt to various motherboard models 110 and achieve its adaptive function for different motherboards 110. This allows consumer motherboards 110, which were previously unusable in storage testing equipment, to be used appropriately, significantly reducing the cost of storage testing equipment and enhancing its practicality.

[0071] In one implementation, the first delay is determined by the control circuit 240. In one embodiment of this application, the control circuit 240 acquires the first delay information and determines the first delay based on the first delay information. Specifically, the user can directly input the first delay information on the user terminal according to the type of motherboard 110 inserted, and the user terminal interface provides it to the control circuit 240; or, the control circuit 240 obtains the first delay information from the motherboard 110 through the first connector 210, where the first delay information is motherboard 110 type information, and the control circuit 240 obtains the first delay based on the locally stored correspondence between motherboard 110 type and delay; or, the control circuit 240 obtains the first delay information from the motherboard 110 through the first connector 210, where the first delay information is other parameters that can reflect the type of motherboard 110 or parameters that reflect the clock stabilization time of the motherboard 110, and the control circuit 240 obtains the first delay based on the first delay information. These are all within the scope of protection of this application and will not be elaborated upon here.

[0072] In one implementation, the memory 120 can be a solid-state drive (SSD), in which case the storage test bench is a SSD test bench.

[0073] In one implementation, the first connector 210 is, for example, a standard X16 gold finger connector, through which the Retimer card is inserted into the slot of the motherboard 110; the second connector 220 is, for example, an MCIO connector to support higher versions of bus transmission, such as PCIe 5.0 and above.

[0074] When the second circuit is memory 120, the second connector 220 can not only be used to realize the signal connection with the second circuit, but also to feed back the in-situ status of memory 120 to control circuit 240.

[0075] For example, the MCU can feed back the acquired presence status of the backend solid-state drive to the Retimer chip. Specifically, the control circuit 240 can further acquire the presence status of the second circuit via the second connector 220 and feed it back to the retiming circuit 230. At this time, the control circuit 240 can control the retiming circuit 230 to reset the corresponding ports, enabling the solid-state drive testing equipment to support hot-swap testing of the backend solid-state drive and improving testing efficiency.

[0076] In one specific embodiment, see Figure 2 The signal transmission circuit 200 also includes a third connector 250, which is connected to the control circuit 240. The control circuit 240 obtains firmware through the third connector 250 and provides firmware to the retiming circuit 230.

[0077] For example, the third connector 250 is a Micro-USB connector, which is signal-connected to the MCU and suitable for interfacing with the user terminal. In this case, the user terminal's firmware file can be burned into the Retimer chip via the MCU through the Micro-USB connector.

[0078] Furthermore, the MCU can also retrieve the operating log of the Retimer chip and export it to the user terminal via a Micro-USB connector. Specifically, the control circuit 240 is further used to retrieve the operating log of the retiming circuit 230 and export it to the user terminal via the third connector 250. Thus, when a fault occurs on the solid-state drive (SSD) test bench during testing, the tester can use the operating log of the Retimer chip retrieved by the MCU to troubleshoot the fault, quickly locate the source of the fault, thereby further shortening the fault analysis time of the SSD test bench, saving manpower, improving the utilization rate of the SSD test bench, and further improving testing efficiency. The MCU module can retrieve the operating log of the Retimer chip via the I2C protocol; and the user terminal is the laptop or desktop computer used by the user during debugging.

[0079] In this embodiment, the Retimer chip is accessed through the MCU, enabling firmware upgrades and log downloads to be completed via the MCU. The MCU and the user terminal (such as a laptop or desktop computer) communicate via a Micro-USB connector. Therefore, this embodiment only requires a Micro-USB connector to perform firmware upgrades on the MCU and Retimer chip, eliminating the need for external interfaces on the Retimer chip itself. This reduces the number of physical interfaces on the Retimer board, resulting in higher product integration and lower production costs, thereby further reducing the cost of solid-state drive testing equipment.

[0080] In one implementation, see Figure 1 and Figure 4 The signal transmission circuit 200 may further include a buffer 260, which is signal-connected to the first connector 210, the retiming circuit 230 and the second connector 220, and is configured to receive the PERST signal and the clock signal from the first circuit, and to split the received PERST signal and the clock signal to the retiming circuit 230 and the second circuit.

[0081] Among them, the PERST signal and the clock signal are both important signals in the PCIe signal transmission protocol. The PERST signal indicates that the power supply of the first circuit has stabilized within the corresponding voltage range, while the clock signal plays a synchronization role during signal transmission.

[0082] In this embodiment, by setting buffer 260, the signals of the Retimer chip and the back-end memory 120 (i.e., solid-state drive) can be made from the same source during the test. Of course, in actual production, an adapter 140 can also be added between the second connector 220 and the solid-state drive. This adapter 140 can be set with four interfaces, each of which is used to connect to four different solid-state drives. In this case, buffer 140 can split the PERST signal and clock signal of the motherboard 110 into five paths, one path to the Retimer board and the other four paths to the back-end solid-state drives. With the four interfaces on the adapter 140, the PCIe x16 lane is split into four PCIe x4 lanes, improving the testing efficiency of the solid-state drive testing machine for x4 solid-state drives and shortening the testing time.

[0083] Of course, in actual production, the number of interfaces on the adapter 140 can also be one, which is x16 channels; or the number of interfaces on the adapter 140 can be two, which is x8 channels. We will not go into details here, as they are all within the protection scope of this application.

[0084] In one implementation, the retimer board 130 integrated in the signal transmission circuit 200 is equipped with a heat sink for dissipating heat from the Retimer chip and MCU, so that the Retimer chip and MCU can run for a long time in a stable working environment, thereby achieving long-term stable operation of the solid-state drive test machine.

[0085] This application also provides a signal transmission control method, which can be applied to the signal transmission circuit 200 provided in any of the above embodiments, and specifically includes the following steps: 1. Obtaining first delay information of the first circuit; 2. Determining the first delay based on the first delay information, and triggering the retiming circuit 230 to load firmware to transmit the signal after the first delay.

[0086] The application of this signal transmission control method is beneficial for the control circuit 240, i.e. MCU, provided in all the above embodiments, to perform delay processing on the first reset signal, so that the first reset signal of the retiming circuit 230 can be pulled high after the clock signal of the first circuit stabilizes, and the retiming circuit can complete the firmware loading before the second reset signal of the first circuit arrives, thereby satisfying the power-on timing of the retiming circuit 230, and thus solving the timing limitation problem of the signal transmission circuit 200 during use.

[0087] This application provides a signal transmission control circuit, applied to the signal transmission circuit 200 provided in any of the above embodiments. The control circuit includes an acquisition unit, a determination unit, and a triggering unit. The acquisition unit acquires first delay information of the first circuit; the determination unit determines the first delay based on the first delay information; and the triggering unit triggers a retiming circuit to load firmware after the first delay.

[0088] Specifically, the control circuit for this signal transmission is the control circuit 240 provided in all the above embodiments, which can be integrated into an MCU.

[0089] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0090] It should be noted that the above embodiments can be freely combined as needed. The above are merely preferred embodiments of this application. It should be pointed out that for those skilled in the art, several improvements and modifications can be made without departing from the principles of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A signal transmission circuit, characterized in that, For transmitting signals between the first circuit and the second circuit, including: The first connector is used to connect to the first circuit, receive a first signal from the first circuit, or output a fourth signal to the first circuit. The second connector is used to connect to the second circuit and output a second signal to the second circuit; or to receive a third signal from the second circuit. A retiming circuit, signal-connected to the first connector and the second connector, is used to receive the first signal from the first circuit from the first connector, retime and reshape the first signal to obtain the second signal and output it to the second connector; or, to receive the third signal from the second circuit from the second connector, retime and reshape the third signal to obtain the fourth signal and output it to the first connector. A control circuit, connected to the retiming circuit, is used to output a first reset signal to the retiming circuit after a first time delay. The first reset signal is used to trigger firmware loading of the retiming circuit.

2. The signal transmission circuit according to claim 1, characterized in that, The control circuit is further configured to determine the first delay, wherein the first delay is greater than the clock settling time of the first circuit; and the sum of the first delay and the firmware loading time is less than the global reset time of the first circuit.

3. The signal transmission circuit according to claim 1 or 2, characterized in that, Also includes: The third connector is connected to the control circuit signal; and The control circuit is further configured to acquire the firmware through the third connector and provide the firmware to the retiming circuit.

4. The signal transmission circuit according to claim 3, characterized in that, The control circuit is further used to retrieve the operation log of the retiming circuit and export it to the user terminal via the third connector.

5. The signal transmission circuit according to claim 1 or 2, characterized in that, The control circuit is further configured to acquire the in-situ status of the second circuit via the second connector and feed back the in-situ status of the second circuit to the retiming circuit.

6. The signal transmission circuit according to claim 1 or 2, characterized in that, Also includes: A buffer is used to receive a clock signal and a second reset signal from the first circuit, and to split the received clock signal and the second reset signal to the retiming circuit and the second circuit.

7. A communication system, characterized in that, include: The first circuit, the second circuit, and the signal transmission circuit according to any one of claims 1-6; The signal transmission circuit is connected to the first circuit via the first connector; and the signal transmission circuit is connected to the second circuit via the second connector.

8. The communication system according to claim 7, characterized in that, The communication system is a test system or a server system.

9. A signal transmission control method, characterized in that, Applied to the signal transmission circuit as described in any one of claims 1-6, the method comprises: Obtain the first time delay information of the first circuit; Based on the first delay information, a first delay is determined, and after the first delay, a retiming circuit is triggered to load firmware to transmit signals.

10. A signal transmission control circuit, characterized in that, Applied to the signal transmission circuit as described in any one of claims 1-6, the circuit comprises: The acquisition unit is used to acquire the first time delay information of the first circuit. The determining unit is configured to determine the first delay based on the first delay information; The triggering unit is used to trigger the retiming circuit to load firmware after the first delay.

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