Display panel, display device and driving method

Abstract

The present disclosure relates to a display panel, comprising a plurality of pixel islands, each of the pixel islands comprising M pixel units and N time-division multiplexing circuits, wherein M is a positive integer greater than 1, and N is a positive integer greater than 1; each of the time-division multiplexing circuits comprising m switch transistors for driving m pixel units, wherein m is less than M and m and M are in a non-multiple relationship; a virtual pixel unit is included in the M pixel units, and a first time-division multiplexing circuit is included in the N time-division multiplexing circuits, the first time-division multiplexing circuit comprising a virtual switch transistor connected in correspondence with the virtual pixel unit. The present disclosure also relates to a display device and a driving method.

Description

Technical Field

[0001] The present disclosure relates to the technical field of display product manufacturing, and in particular, to a display panel, a display device, and a driving method. Background Art

[0002] The pixel island design factor has more pixels than the conventional RGB arrangement and requires more Source numbers. The MUX (Multiplexer) design can effectively reduce the number of Source used. However, when the number of MUX channels is not a multiple of the number of Views included in a pixel island, if 2D / 3D display is to be compatible, multiple MUX combinations need to be used, such that a MUX circuit does not span two pixel islands. For example, MUX 1:2 and MUX 1:1. When different control signals are turned on, the corresponding data amounts are inconsistent, and it increases the difficulty of FPGA or TCON data processing. Summary of the Invention

[0003] In order to solve the above technical problems, the present disclosure provides a display panel, a display device, and a driving method, which solve the problem of increasing the difficulty of data processing caused by using different MUX combinations.

[0004] To achieve the above object, the technical solution adopted in the embodiments of the present disclosure is: a display panel includes multiple pixel islands, and each pixel island includes M pixel units and N time-division multiplexing circuits, where M is a positive integer greater than 1, and N is a positive integer greater than 1;

[0005] Each time-division multiplexing circuit includes m switching transistors for driving m of the pixel units, where m < M, and m and M are not in a multiple relationship;

[0006] Among the M pixel units, there are virtual pixel units, and among the N time-division multiplexing circuits, there is a first time-division multiplexing circuit, and the first time-division multiplexing circuit includes a virtual switching transistor connected corresponding to the virtual pixel unit.

[0007] Optionally, the gates of the m switching transistors in each time-division multiplexing circuit are connected to different control signal lines, the m switching transistors are marked as 1 - m according to a preset rule, and the gates of the switching transistors with the same mark in different time-division multiplexing circuits are connected to the same control signal line.

[0008] Optionally, the first electrodes of the m switching transistors in the same time-division multiplexing circuit are connected to the same data line of the data driving circuit.

[0009] Optionally, the m switching transistors are respectively connected to m control signal lines, so that when the m-th control signal line is turned on, one data line of the data driving circuit provides a data signal to the m-th switching transistor connected to the m-th control signal line.

[0010] Optionally, in the first time-division multiplexing circuit, the m-th switching transistor is the virtual switching transistor, and the m-th control signal line provides a virtual start signal for the virtual switching transistor so that the corresponding data line provides a virtual data signal.

[0011] Optionally, the pixel island includes two pixel groups: an odd-numbered pixel group and an even-numbered pixel group. The odd-numbered pixel group includes pixel units in an odd number of columns, and the even-numbered pixel group includes pixel units in an even number of columns.

[0012] The time-division multiplexing circuit includes a first switching transistor and a second switching transistor. The first switching transistor is connected to an odd-numbered column of pixel units, and the second switching transistor is connected to an even-numbered column of pixel units adjacent to the odd-numbered column of pixel units.

[0013] Optionally, it also includes a data driving circuit, which includes multiple data lines, each data line providing data signals to the m switching transistors in the time-division multiplexing circuit.

[0014] Optional,

[0015] In each of the time-division multiplexing circuits, the first switching transistor receives a first data signal, and the second switching transistor receives a second data signal;

[0016] The plurality of pixel islands include adjacent first pixel islands and second pixel islands, the pixel units adjacent to the first pixel island and the second pixel island are virtual pixel units, and the data signal received by the pixel unit adjacent to the virtual pixel unit in the first pixel island is the first data signal;

[0017] The data signal received by the pixel unit adjacent to the virtual pixel unit in the second pixel island is the second data signal.

[0018] Optionally, each pixel unit includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel.

[0019] This disclosure also provides a display device, including the display panel described above. The display panel is connected to a first circuit board via a flip-chip film. The first circuit board is connected to a second circuit board via a flexible circuit board. The second circuit board is provided with a display interface.

[0020] This disclosure also provides a driving method applied to the above-described display device, comprising:

[0021] A first control signal is provided through the first control signal line to control the switching transistors of the first position in the N time-division multiplexing circuits to turn on, so that the data signal is transmitted to the corresponding pixel unit.

[0022] A second control signal is provided through a second control signal line to control the switching transistors at the second positions in the N time-division multiplexing circuits to turn on, so that the data signal is transmitted to the corresponding pixel unit. The virtual switching transistor in the first time-division multiplexing circuit receives the virtual data signal.

[0023] Optionally, the display panel includes adjacent first pixel islands and second pixel islands, each of the time-division multiplexing circuits includes two switching transistors, and the driving method includes:

[0024] A first control signal is provided through a first control signal line, causing the first switching transistor in the N time-division multiplexing circuits in the first pixel island to receive the first data signal, and causing the third switching transistor in the N time-division multiplexing circuits in the second pixel island to receive the second data signal. The first switching transistor is connected to a pixel unit that is away from the second pixel island in a first direction, and the third switching transistor is connected to a pixel unit that is close to the first pixel island in the first direction. The first direction is parallel to the row direction of the pixel unit.

[0025] A second control signal is provided through a second control signal line, causing the second switching transistors in the N time-division multiplexing circuits in the first pixel island to receive the second data signal, and causing the fourth switching transistors in the N time-division multiplexing circuits in the second pixel island to receive the first data signal. The second switching transistors are connected to pixel units close to the second pixel island in the first direction, and the fourth switching transistors are connected to pixel units far from the first pixel island in the first direction. The virtual switching transistors in the first time-division multiplexing circuits corresponding to the first pixel island receive virtual data signals, and the virtual switching transistors in the first time-division multiplexing circuits corresponding to the second pixel island also receive virtual data signals.

[0026] The beneficial effects of this disclosure are: when using MUX circuits with different structures, the virtual switching transistors can be configured to ensure that the amount of data under different control signals is the same, thus satisfying the data-driven transmission rate and reducing the difficulty of data processing. Attached Figure Description

[0027] Figure 1 This diagram illustrates a time-division multiplexing circuit in related technologies.

[0028] Figure 2A schematic diagram illustrating the correspondence between the input of the DP module and pixel units in related technologies;

[0029] Figure 3 This diagram illustrates a time-division multiplexing circuit in an embodiment of this disclosure.

[0030] Figure 4 A schematic diagram illustrating the correspondence between the DP module input and pixel units in an embodiment of this disclosure;

[0031] Figure 5 This diagram illustrates the data output format in an embodiment of the present disclosure.

[0032] Figure 6 This is a waveform diagram illustrating the data signal provided by the V1line pattern data line in an embodiment of this disclosure.

[0033] Figure 7 This is a schematic diagram showing the structure of the display device in an embodiment of the present disclosure;

[0034] Figure 8 This diagram illustrates the signal transmission path in an embodiment of the present disclosure. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure are within the scope of protection of this disclosure.

[0036] In the description of this disclosure, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0037] refer to Figure 1 and Figure 2 When the number of views within a pixel island is not a multiple of the number of MUX (time-division multiplexing) paths (i.e., the number of switching transistors), existing pixel island designs use a combination of two or more MUXs to ensure 2D display, preventing the MUX circuit from spanning two pixel islands. For example... Figure 1As shown, a pixel island contains 11 Views and uses a combination of MUX 1:2 and MUX 1:1. There are the following problems with this structure:

[0038] Using MUX combinations with different structures greatly increases the difficulty of data processing in FPGA (Field Programmable Gate Array) or TCON (Timing Controller). Taking the DP (DisplayPort) interface as the system input example, the data is usually 24bit / Lane. For each pixel unit with 8bit data, each Lane transmits data of 3 sub-pixels; according to the amount of transmitted data, 1Lane / 2Lane / 4Lane is automatically selected. Assuming 2Lanes are selected, after passing through the "2-to-8" module, it becomes 8Lanes. 8Lanes can transmit a total of 24 sub-pixel data, but a pixel island only contains 11 pixel units (1 pixel unit includes 3 sub-pixels). As Figure 1 shown, the correspondence between the data output by the DP module and the pixel island is complex. Refer to Figure 2 , Figure 2 In [reference], in Lane4, it transmits the data of pixel units P10 and P11 in one pixel island, and also transmits the data of pixel unit P1 in another pixel island (it should be noted that Lane transmits data of 3 sub-pixels at a time, that is, Lane4 transmits the data of one sub-pixel in pixel unit P10, the data of one sub-pixel in pixel unit P11, and the data of one sub-pixel in pixel unit P1). Taking 22 pixel islands as a cycle, when processing data later, the minimum cycle data needs to be cached. The amount of cached data is large and it occupies a lot of resources.

[0039] The data output rule is: when MUX1 is turned on, all the data of MUX1 in one row is output in sequence; when MUX2 is turned on, the data of MUX2 in one row is output in sequence. The transmission rate of the Source Driver is limited, and usually a fixed rate output is selected. This requires that the amount of data transmitted when MUX1 and MUX2 are turned on is the same, but currently, the amount of data of MUX1 in one row is much more than that of MUX2.

[0040] To address the above problems, this embodiment provides a display panel, including multiple pixel islands. Each pixel island includes M pixel units and N time-division multiplexing circuits, where M is a positive integer greater than 1 and N is a positive integer greater than 1;

[0041] Each time-division multiplexing circuit includes m switching transistors for driving m of the pixel units, where m < M and m and M are not in a multiple relationship;

[0042] Among the M pixel units, there are virtual pixel units, and among the N time-division multiplexing circuits, there is a first time-division multiplexing circuit. The first time-division multiplexing circuit includes a virtual switching transistor connected corresponding to the virtual pixel unit.

[0043] The virtual pixel unit is connected to the virtual switch transistor and receives the corresponding virtual signal, so that the amount of data transmitted by the data driving circuit is consistent under different control signals, thus meeting the data driving transmission rate requirements.

[0044] refer to Figure 3 Due to the presence of the virtual pixel unit P12 and the corresponding virtual switching transistor, under the control of the time-division multiplexing circuit, when the MUX1 control signal line is turned on, data signals are provided to pixel units P1, P3, P5, P7, P9 and P11. When the MUX2 control signal line is turned on, data signals are provided to pixel units P2, P4, P6, P8, P10 and P12 (the signal provided to P12 is a virtual data signal). It can be seen that within 1H (one cycle), the amount of data output by the data driving circuit is consistent when the MUX1 control signal line is turned on and when the MUX2 control signal line is turned on, and it will not cause the failure to reach the Source Driver transmission rate to affect data output.

[0045] It should be noted that, Figure 3 To easily distinguish between the two pixel islands, the pixel units in one pixel island are labeled 1-12, and the pixel units in the other pixel island are labeled 13-24. Figure 4 In this method, each pixel unit in a pixel island is labeled with a number from 1 to 12, only the labeling format is different.

[0046] It should be noted that, Figure 4 The meaning referred to here is a sub-pixel in the corresponding pixel unit. For example, Lane 1 transmits data to a sub-pixel in pixel unit P1, a sub-pixel in pixel unit P2, and a sub-pixel in pixel unit P3. Each pixel unit includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel. Under the control of the corresponding control signal, the corresponding sub-pixel receives the data signal, that is, under the control of the dual control signal, the data signal is transmitted to the corresponding sub-pixel in the corresponding unit.

[0047] For example, the gates of the m switching transistors in each time-division multiplexing circuit are connected to different control signal lines, and the m switching transistors are marked as 1-m according to a preset rule. The gates of the switching transistors with the same marking in different time-division multiplexing circuits are connected to the same control signal line.

[0048] Each of the time-division multiplexing circuits includes m switching transistors, which are turned on under the control of different control signals to provide data signals to different pixel units, thereby achieving the function of time-division multiplexing. For example Figure 3In this circuit, each time-division multiplexing circuit includes two switching transistors, which are connected to two pixel units. The two switching transistors are turned on in a time-division manner under the control of different control signals, thereby enabling the data driving circuit to selectively provide data signals to different pixel units.

[0049] In different time-division multiplexing circuits, the positions of the switching transistors controlled by the same control signal can be the same or different, depending on the actual needs.

[0050] For example, the first electrodes of the m switching transistors in the same time-division multiplexing circuit are connected to the same data line of the data driving circuit.

[0051] By employing the above scheme, the data driving circuit can respond to different control signals to provide data signals to different pixel units, for example, Figure 3 Each time-division multiplexing circuit includes two switching transistors, and the data drive circuit can respond to different control signals to provide data signals to different switching transistors.

[0052] For example, m of the switching transistors are respectively connected to m control signal lines, so that when the m-th control signal line is turned on, a data line of the data driving circuit provides a data signal to the m-th switching transistor connected to the m-th control signal line.

[0053] For example, in the first time-division multiplexing circuit, the m-th switching transistor is the virtual switching transistor, and the m-th control signal line provides a virtual start signal for the virtual switching transistor so that the corresponding data line provides a virtual data signal.

[0054] For example, the pixel island includes two pixel groups: an odd-numbered pixel group and an even-numbered pixel group. The odd-numbered pixel group includes pixel units in an odd number of columns, and the even-numbered pixel group includes pixel units in an even number of columns.

[0055] When m=2 (i.e., when the time-division multiplexing circuit includes 2 switching transistors), the time-division multiplexing circuit includes a first switching transistor and a second switching transistor. The first switching transistor is connected to an odd-numbered column of pixel units, and the second switching transistor is connected to an even-numbered column of pixel units adjacent to the odd-numbered column of pixel units.

[0056] For example, the display panel further includes a data driving circuit, which includes multiple data lines, each data line providing data signals to the m switching transistors in the time-division multiplexing circuit.

[0057] For example, in each of the time-division multiplexing circuits, the first switching transistor receives a first data signal, and the second switching transistor receives a second data signal;

[0058] The plurality of pixel islands include adjacent first pixel islands and second pixel islands, the pixel units adjacent to the first pixel island and the second pixel island are virtual pixel units, and the data signal received by the pixel unit adjacent to the virtual pixel unit in the first pixel island is the first data signal;

[0059] The data signal received by the pixel unit adjacent to the virtual pixel unit in the second pixel island is the second data signal.

[0060] For example, each of the pixel units includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel.

[0061] Taking the transmission of 3 sub-pixel data per lane as an example, refer to... Figure 3 Each pixel island comprises multiple pixel units, and each pixel unit comprises multiple sub-pixels, such as red sub-pixels R, green sub-pixels G, and blue sub-pixels B. The red sub-pixels in the multiple pixel units are arranged in rows and controlled by the same control signal (named the red control signal), the green sub-pixels in the multiple pixel units are arranged in rows and controlled by the same control signal (named the green control signal), and the blue sub-pixels in the multiple pixel units are arranged in rows and controlled by the same control signal (named the blue control signal). For example, under the control of control signal MUX1 and the red control signal, data lines S1-S6 provide data signals to the red sub-pixels of P1, P3, P5, P7, P9 and P11 respectively; under the control of control signal MUX1 and the green control signal, data lines S1-S6 provide data signals to the green sub-pixels of P1, P3, P5, P7, P9 and P11 respectively; and under the control of control signal MUX1 and the blue control signal, data lines S1-S6 provide data signals to the blue sub-pixels of P1, P3, P5, P7, P9 and P11 respectively.

[0062] It should be noted that the pixel island design factor has more pixels than the conventional RGB arrangement, requiring more Sources. The MUX (Time-Division Multiplexing) design can effectively reduce the number of Sources used, but with the frame rate unchanged, more MUXs will result in less pixel charging time. Considering the case of insufficient charging, this proposal takes the MUX 1:2 design as an example.

[0063] The number of views contained within a pixel island depends not only on the pixel size but also on the number of lenses. To eliminate moiré patterns, current optical solutions require that the number of lenses and subpixels be non-common divisors; that is, 2D pixel units (one pixel island) cannot contain duplicate units. For example, when using a scheme where one pixel island corresponds to two lenses, the number of viewpoints within the pixel island cannot be 10. Otherwise, if View1-View5 correspond to one lens and View6-View10 correspond to another lens, different viewpoints corresponding to different lenses will be located in the same position. For instance, View1 and View6 would have the same relative position to their corresponding lenses, making it impossible to eliminate moiré patterns. Therefore, this embodiment uses one pixel island corresponding to two lenses and one pixel island containing 11 views as an example for detailed explanation, but it is not limited to this.

[0064] A pixel island includes 11 pixel units (corresponding to 11 viewpoints). Each time-division multiplexing circuit includes two switching transistors. The first electrodes of the two switching transistors are connected to the same data line. Switching transistors at the same position in different time-division multiplexing circuits are turned on simultaneously under the control of the same control signal. Specifically, taking two pixel islands as an example, the first pixel island includes pixel units P1-P12, where P12 is a virtual pixel unit. Six time-division multiplexing circuits are sequentially connected to the pixel unit to provide data signals to the pixel unit through data lines S1-S6, where S6 corresponds to P11 and P12. Under the control of control signal MUX1, data lines S1-S6 provide data signals to P1, P3, P5, P7, P9, and P11. Under the control of control signal MUX2, data lines S1-S6 provide data signals to P2, P4, P6, P8, P10, and P12, where S6 provides a virtual data signal to P12. This ensures that the amount of data is consistent when MUX1 and MUX2 are enabled, meeting the data-driven transmission rate requirements.

[0065] Similar to the first pixel island, the second pixel island includes 12 pixel units P13-P24, where P24 is a virtual pixel unit. Six time-division multiplexing circuits are sequentially connected to the pixel units to provide data signals to the pixel units via data lines S7-S12. S12 corresponds to P23 and P24. Under the control of the control signal MUX1, data lines S7-S12 provide data signals to P13, P15, P17, P19, P21, and P23. Under the control of the control signal MUX2, data lines S7-S12 provide data signals to P14, P16, P18, P20, P22, and P24. S12 provides a virtual data signal to P24. This ensures that the amount of data is consistent when MUX1 and MUX2 are enabled, meeting the data-driven transmission rate requirements.

[0066] When using the DP / HDMI interface as the system input, the data is typically 24 bits / lane, with each subpixel data being 8 bits. Therefore, each lane transmits 3 subpixel data. Selecting 2 lanes, after passing through a "2-to-8" module, the DP outputs 8 lanes (the "2-to-8" module achieves greater bandwidth transmission, but is not limited to this; for example, it can be converted to 16 lanes. Increasing the number of lanes under the same bandwidth can also reduce the main frequency and improve stability). A total of 24 data bits can be transmitted through 8 lanes. The DP module output data is buffered, and after buffering the minimum cycle data, data mapping is performed. Data mapping reassembles the 8 lane data and distributes it to each COF. For example, if there are 8 COFs, each COF has 8 lanes, then the Data... The mapping process converts the data into a 64-lane high-speed signal and sends it to each COF. The chip on the COF converts the high-speed signal into the voltage signal required by the panel. The first pixel island contains 12 pixel units P1-P12, and the second pixel island contains 12 pixel units P13-P24. Using the technical solution of this embodiment, the correspondence between lane transmission data and pixel units (sub-pixels in pixel units) is simplified. Lane 1-Lane 4 correspond to pixel units P1-P12, and Lane 5-Lane 8 correspond to pixel units P13-P24. (Refer to...) Figure 4 (It should be noted that the Lane transmits sub-pixel data. For example, Lane1 transmits the data of a sub-pixel in pixel unit P1, the data of a sub-pixel in pixel unit P2, and the data of a sub-pixel in pixel unit P3.) When mapping data, it is necessary to find the periodic pattern and buffer the data of a period to ensure that each data can be transmitted to the corresponding View. Using the above scheme, the minimum period is the data of 2 pixel islands. The FPGA does not need to add too much invalid data, which can effectively save FPGA resources.

[0067] Taking the V1line Pattern as an example, such as Figure 5 The display alternates between bright and dark columns. Note that because P12 is a virtual pixel unit, pixel unit P13 of the second pixel island should be dark. The source output repeats in units of two pixel islands. The source output waveform is as follows: Figure 6The output waveforms of S1 to S5 are the same, all alternating between bright and dark (L255→L0→L255→L0); in the pixel units P11 and P12 corresponding to S6, only P11 has valid data, and the data provided for pixel unit P12 is virtual data. Assuming that the dummy data is L255, then the waveform of S6 is all L255; similarly, the waveforms of S7 to S11 are the same, all alternating between bright and dark (L0→L255→L0→L255); S12 is similar to S6, but the data corresponding to P11 is L0, so when the provided dummy data is L255, the waveform is also alternating between bright and dark. Figure 6 The dummy data is marked with a dashed line.

[0068] refer to Figure 7 This disclosure also provides a display device, including the display panel 1 described above. The display panel 1 is connected to a first circuit board 3 via a flip-chip film 2. The first circuit board 3 is connected to a second circuit board 5 via a flexible circuit board 4. The second circuit board 5 is provided with a display interface 51.

[0069] The second circuit board is equipped with an FPGA module 10, which integrates a DP module 20. The FPGA module 10 also includes a buffer module 101 and a data processing module (Date mapping) 102. Figure 8 This indicates the signal transmission path. Data input from the DP interface (display interface 51) in 2 lanes is converted into 8 lanes by the 2-to-8 module. The data output from the DP module 20 is buffered and then data mapping is performed after caching the minimum cycle data. Data mapping reassembles the 8 lane data and distributes it to each COF. For example, if there are 8 COFs and each COF has 8 lanes, then data mapping will process the data into a 64 lane high-speed signal and give it to each COF. The chip on the COF converts the high-speed signal into the voltage signal required by the panel.

[0070] The display device can be any product or component with display function, such as an LCD TV, LCD monitor, digital photo frame, mobile phone, or tablet computer. The display device also includes a flexible circuit board, a printed circuit board, and a backplate.

[0071] This disclosure also provides a driving method applied to the above-described display device, comprising:

[0072] A first control signal is provided through the first control signal line to control the switching transistors of the first position in the N time-division multiplexing circuits to turn on, so that the data signal is transmitted to the corresponding pixel unit.

[0073] A second control signal is provided through a second control signal line to control the switching transistors at the second positions in the N time-division multiplexing circuits to turn on, so that the data signal is transmitted to the corresponding pixel unit. The virtual switching transistor in the first time-division multiplexing circuit receives the virtual data signal.

[0074] The display panel includes at least two adjacent first pixel islands and second pixel islands. Each time-division multiplexing circuit includes at least two switching transistors. In one embodiment, the display panel includes two adjacent first pixel islands and second pixel islands, and each time-division multiplexing circuit includes two switching transistors. The two switching transistors receive different data signals, and the corresponding pixel units display different information. For example, a V1line pattern (pixel units are alternately set with one column bright and one column dark) setting method is used. (Refer to...) Figure 5 The driving method includes:

[0075] A first control signal is provided through a first control signal line, causing the first switching transistors in the N time-division multiplexing circuits in the first pixel island to receive the first data signal (e.g., Figure 5 (The pixel unit P1 corresponding to S1 is displayed as lit), and causes the third switching transistor of the N time-division multiplexing circuits in the second pixel island to receive the second data signal (e.g., Figure 5 (The pixel unit P1 corresponding to S7 is displayed as dark). The first switching transistor is connected to the pixel unit that is far away from the second pixel island in the first direction. The third switching transistor is connected to the pixel unit that is close to the first pixel island in the first direction. The first direction is parallel to the row direction of the pixel unit.

[0076] A second control signal is provided via a second control signal line, causing the second switching transistors in the N time-division multiplexing circuits in the first pixel island to receive the second data signal (reference). Figure 5 (The pixel unit P2 corresponding to S1 in the image is displayed as dark), and causes the fourth switching transistor of the N time-division multiplexing circuits in the second pixel island to receive the first data signal (refer to...). Figure 5 In the first pixel island, the pixel unit P2 corresponding to S7 is displayed as lit. The second switching transistor is connected to the pixel unit closer to the second pixel island in the first direction, and the fourth switching transistor is connected to the pixel unit farther away from the first pixel island in the first direction. The virtual switching transistor in the first time-division multiplexing circuit corresponding to the first pixel island receives a virtual data signal (see reference). Figure 5 The virtual pixel unit P12 corresponding to S6 in the first time-division multiplexing circuit of the second pixel island receives the virtual data signal (see reference). Figure 5 The virtual pixel unit P12 corresponding to S12 in the middle.

[0077] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

Claims

1. A display panel, wherein, It includes multiple pixel islands, and each pixel island includes M pixel units and N time-division multiplexing circuits, where M is a positive integer greater than 1, and N is a positive integer greater than 1; Each of the time-division multiplexing circuits includes m switching transistors for driving m of the pixel units, where m < M, and m and M are not in a multiple relationship; Among the M pixel units, there are virtual pixel units, and among the N time-division multiplexing circuits, there is a first time-division multiplexing circuit, and the first time-division multiplexing circuit includes a virtual switching transistor connected corresponding to the virtual pixel unit; The multiple pixel islands include adjacent first pixel island and second pixel island, and the pixel unit adjacent to the second pixel island in the first pixel island is the virtual pixel unit, and the data signal received by the pixel unit adjacent to the virtual pixel unit in the first pixel island is the first data signal; The data signal received by the pixel unit adjacent to the virtual pixel unit in the second pixel island is the second data signal; Each Lane transmits data of 3 sub-pixels of one pixel unit.

2. The display panel according to claim 1, wherein, The gates of the m switching transistors in each time-division multiplexing circuit are connected to different control signal lines, the m switching transistors are labeled 1 - m according to a preset rule, and the gates of the switching transistors with the same label in different time-division multiplexing circuits are connected to the same control signal line.

3. The display panel according to claim 2, wherein, The first electrodes of the m switching transistors in the same time-division multiplexing circuit are connected to the same data line of the data driving circuit.

4. The display panel according to claim 3, wherein, The m switching transistors are respectively connected to m control signal lines, so that when the m-th control signal line is turned on, a data line of the data driving circuit provides a data signal to the m-th switching transistor connected to the m-th control signal line.

5. The display panel according to claim 4, wherein, In the first time-division multiplexing circuit, the m-th switching transistor is the virtual switching transistor, and the m-th control signal line provides a virtual start signal to the virtual switching transistor, so that the corresponding data line provides a virtual data signal.

6. The display panel according to claim 4, wherein, The pixel island includes two pixel groups, an odd pixel group and an even pixel group. The odd pixel group includes pixel units in odd columns, and the even pixel group includes pixel units in even columns; The time-division multiplexing circuit includes a first switching transistor and a second switching transistor. The first switching transistor is connected to a pixel unit in an odd column, and the second switching transistor is connected to a pixel unit in an even column adjacent to the pixel unit in the odd column.

7. The display panel according to claim 6, wherein, It further includes a data driving circuit, and the data driving circuit includes multiple data lines, and each data line provides a data signal to the m switching transistors in the time-division multiplexing circuit.

8. The display panel according to claim 7, wherein, The first switching transistor in each time-division multiplexing circuit receives the first data signal, and the second switching transistor receives the second data signal.

9. The display panel according to claim 1, wherein, Each pixel unit includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel.

10. A display device, wherein, The display panel includes any one of claims 1-9, wherein the display panel is connected to a first circuit board via a flip-chip film, the first circuit board is connected to a second circuit board via a flexible circuit board, and the second circuit board is provided with a display interface.

11. A driving method, wherein, Applied to the display device of claim 10, comprising: A first control signal is provided through the first control signal line to control the switching transistors of the first position in the N time-division multiplexing circuits to turn on, so that the data signal is transmitted to the corresponding pixel unit. A second control signal is provided through a second control signal line to control the switching transistors at the second positions in the N time-division multiplexing circuits to turn on, so that the data signal is transmitted to the corresponding pixel unit. The virtual switching transistor in the first time-division multiplexing circuit receives the virtual data signal.

12. The driving method according to claim 11, wherein, The display panel includes adjacent first pixel islands and second pixel islands, each of the time-division multiplexing circuits includes two switching transistors, and the driving method includes: A first control signal is provided through a first control signal line, causing the first switching transistor in the N time-division multiplexing circuits in the first pixel island to receive the first data signal, and causing the third switching transistor in the N time-division multiplexing circuits in the second pixel island to receive the second data signal. The first switching transistor is connected to a pixel unit that is away from the second pixel island in a first direction, and the third switching transistor is connected to a pixel unit that is close to the first pixel island in the first direction. The first direction is parallel to the row direction of the pixel unit. A second control signal is provided through a second control signal line, causing the second switching transistors in the N time-division multiplexing circuits in the first pixel island to receive the second data signal, and causing the fourth switching transistors in the N time-division multiplexing circuits in the second pixel island to receive the first data signal. The second switching transistors are connected to pixel units close to the second pixel island in the first direction, and the fourth switching transistors are connected to pixel units far from the first pixel island in the first direction. The virtual switching transistors in the first time-division multiplexing circuits corresponding to the first pixel island receive virtual data signals, and the virtual switching transistors in the first time-division multiplexing circuits corresponding to the second pixel island also receive virtual data signals.

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