An apparatus for reducing dead time in a time measurement system
By employing a delay chain and multi-module structure in the time measurement system, combined with high-speed sampling and low-speed processing, the timing risks of FPGA placement and routing caused by high-frequency clocks are resolved, achieving low dead time and high-performance time measurement.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI XINGMIAO OPTOELETRONIC TECH CO LTD
- Filing Date
- 2023-11-13
- Publication Date
- 2026-05-29
AI Technical Summary
When using delay chains for time measurement in a time measurement system, high operating frequency clocks may cause FPGA placement and routing timing to fail to meet requirements, affecting equipment performance and the accuracy of experimental results.
By employing a delay chain, a high-speed sampling clock module, an event acquisition module, multiple event recording modules, a low-speed processing clock module, and an event combination module, data sampling is performed at high speed and data processing is performed at low speed, thereby reducing dead time.
This reduces FPGA placement and routing timing risks with low dead time, improving device performance and the accuracy of experimental results.
Smart Images
Figure CN117389129B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of time measurement technology, and specifically relates to a device for reducing dead time in a time measurement system. Background Technology
[0002] High-precision time measurement technology is needed in many fields of modern science and technology, such as telecommunications, laser ranging, and satellite positioning. Its applications are particularly widespread in various fields of physics, such as nuclear physics, high-energy physics, and medical imaging physics. Time measurement generally includes two parts: time discrimination and time-to-digital converter (TDC).
[0003] Currently, in time measurement systems, one of the most important parameters is dead time, which is the shortest time required for the device to record a new pulse after recording one counting pulse. The existence of dead time can cause errors in the detector's counting results, affecting the accuracy of experimental results. The shorter the dead time, the more information can be recorded, the better the system performance, and the more accurate the experimental results. Therefore, during the development of time measurement equipment, efforts are made to minimize dead time as much as possible.
[0004] In time measurement using delay chains, the simplest and most direct way to reduce dead time is to sample the delay chain with a higher-speed clock, and then process the sampled bit stream (i.e., a data stream consisting of a string of binary bits reflecting the position of edge transition events). The processing adopts a pipelined approach, with each clock cycle processing the currently sampled bit stream information. Specifically, it extracts an edge transition (called an event) from each sampled bit stream, performs subsequent concatenation processing under a high-speed clock, and then sends it out, ultimately achieving time measurement (all processing under a high-speed clock). For example, a 250MHz clock can achieve a 4ns dead time; to achieve a 2ns dead time, a 500MHz clock is required. However, even in mid-to-high-end FPGAs (Field Programmable Gate Arrays), a 500MHz clock is considered a high operating frequency, which may lead to timing discrepancies during placement and routing. Summary of the Invention
[0005] The purpose of this invention is to provide a device for reducing dead time in a timing measurement system, in order to solve the risk that timing requirements may not be met during FPGA placement and routing when using delay chains to achieve low dead time in the process of timing measurement.
[0006] To achieve the above objectives, the present invention adopts the following technical solution:
[0007] In a first aspect, an apparatus for reducing dead time in a time measurement system is provided, comprising a delay chain, a high-speed sampling clock module, an event acquisition module, N event recording modules, a low-speed processing clock module, and an event combination module, wherein N represents a positive integer greater than or equal to 2;
[0008] The delay chain is used to perform delay processing on the input measured signal;
[0009] The high-speed sampling clock module is used to output a high-speed sampling clock signal;
[0010] The event acquisition module is connected to the delay chain and the high-speed sampling clock module, respectively. It is used to periodically sample the delay chain with the signal frequency of the high-speed sampling clock signal as the sampling operating frequency, so as to obtain a data stream consisting of a string of binary bits that reflects the position of the edge transition event. The position of the edge transition event refers to the position of two adjacent bits of binary number "01" or binary number "10" in the data stream.
[0011] The N event recording modules are respectively connected to the event acquisition module, and are used to record the data stream from the event acquisition module in turn.
[0012] The low-speed processing clock module is used to output a low-speed sampling clock signal, wherein the signal frequency of the low-speed sampling clock signal is one-Nth of the signal frequency of the high-speed sampling clock signal.
[0013] The event combination module is connected to the N event recording modules and the low-speed processing clock module, respectively. It is used to periodically and synchronously read the N data streams recorded in the N event recording modules at the signal frequency of the low-speed sampling clock signal as the processing operating frequency, and combine the N data streams to obtain the final time information reflecting the occurrence time of the edge transition event pulse. The occurrence time of the edge transition event pulse refers to the timestamp of the occurrence of the edge transition event pulse.
[0014] Based on the above-mentioned invention, a novel solution is provided that achieves low dead time while reducing the risk of timing non-compliance. This solution includes a delay chain, a high-speed sampling clock module, an event acquisition module, multiple event recording modules, a low-speed processing clock module, and an event combination module. The event acquisition module periodically samples the delay chain at a high-speed sampling frequency to obtain a data stream. The multiple event recording modules sequentially record the data streams from the event acquisition module. The event combination module periodically and synchronously reads the multiple data streams recorded in the multiple event recording modules at a low-speed processing frequency and combines these multiple data streams to obtain the final timing information. Because the data sampling part operates at a high frequency while the data processing part operates at a low frequency, the risk of timing non-compliance during FPGA placement and routing can be reduced by trading processing resources for time, achieving the goal of low dead time. This facilitates practical application and promotion.
[0015] In one possible design, the delay chain includes a plurality of first delay units connected in series, and the event acquisition module includes a plurality of first D flip-flops, wherein the plurality of first D flip-flops correspond one-to-one with the plurality of first delay units;
[0016] The input terminal of the first first delay unit in the series direction among the plurality of first delay units is used to receive the signal to be measured. The input terminal of the (k+1)th first delay unit in the series direction among the plurality of first delay units is connected to the output terminal of the kth first delay unit in the series direction among the plurality of first delay units. k represents a positive integer less than K, and K represents the total number of units in the plurality of first delay units.
[0017] For each of the plurality of first D flip-flops, the corresponding input terminal is connected to the output terminal of the corresponding delay unit, and the corresponding clock signal input terminal is connected to the clock signal output terminal of the high-speed sampling clock module.
[0018] The plurality of first D flip-flops are used to output the data stream.
[0019] In one possible design, the first delay unit is an AND gate circuit, wherein the first input terminal of the AND gate circuit is used to receive the signal under test, the second input terminal of the AND gate circuit is used to receive a high-level signal representing the binary number "1", and the input terminal of the AND gate circuit is used to output the delayed signal under test.
[0020] In one possible design, the first event recording module among the N event recording modules includes a plurality of second D flip-flops that correspond one-to-one with the plurality of first D flip-flops. For each of the plurality of second D flip-flops, the corresponding input terminal is connected to the output terminal of the corresponding flip-flop, and the corresponding clock signal input terminal is connected to the clock signal output terminal of the low-speed processing clock module.
[0021] The nth event recording module in the N event recording modules includes a second delay unit and a plurality of third D flip-flops that correspond one-to-one with the plurality of first D flip-flops, where n represents a positive integer greater than or equal to 2 and less than or equal to N, and the second delay unit is used to delay the input signal by (n-1) / f before outputting, where f represents the signal frequency of the high-speed sampling clock signal;
[0022] The input terminal of the second delay unit is connected to the clock signal output terminal of the low-speed processing clock module, and for each of the plurality of second D flip-flops, the corresponding input terminal is connected to the output terminal of the corresponding flip-flop, and the corresponding clock signal input terminal is connected to the output terminal of the second delay unit.
[0023] In one possible design, the second delay unit includes a plurality of inverters connected in series.
[0024] In one possible design, the high-speed sampling clock signal has a signal frequency of 500MHz and N is 2, while the low-speed sampling clock signal has a signal frequency of 250MHz.
[0025] In one possible design, the high-speed sampling clock signal has a frequency of 900MHz and N is 3, while the low-speed sampling clock signal has a frequency of 300MHz.
[0026] In one possible design, an application operation module is also included, which is connected to the low-speed processing clock module and the event combination module respectively. The application operation module is used to periodically perform at least one specific application operation based on the final time information, using the signal frequency of the low-speed sampling clock signal as the processing operating frequency, to obtain at least one specific application operation result that corresponds one-to-one with the at least one specific application operation.
[0027] In one possible design, the at least one specific application operation includes delay chain specific time calculation, delay chain correction calculation, and / or edge transition event delay calculation.
[0028] In one possible design, a host computer is also included, which is connected to the application computing module. The application computing module is further used to package and transmit the results of the at least one specific application computing to the host computer.
[0029] The beneficial effects of the above scheme are:
[0030] (1) This invention creatively provides a novel solution that reduces the risk of timing failure while achieving low dead time. The solution includes a delay chain, a high-speed sampling clock module, an event acquisition module, multiple event recording modules, a low-speed processing clock module, and an event combination module. The event acquisition module is used to periodically sample the delay chain at a high-speed sampling frequency to obtain a data stream. The multiple event recording modules are used to record the data streams from the event acquisition module in turn. The event combination module is used to periodically and synchronously read the multiple data streams recorded in the multiple event recording modules at a low-speed processing frequency, and combine these multiple data streams to obtain the final timing information. Since the data sampling part operates at a high frequency, while the data processing part still operates at a low frequency, the risk of timing failure during FPGA placement and routing can be reduced by trading processing resources for time while achieving low dead time. This facilitates practical application and promotion. Attached Figure Description
[0031] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0032] Figure 1 This is a schematic diagram of the structure of a device for reducing dead time in a time measurement system provided in an embodiment of this application.
[0033] Figure 2 This is a schematic diagram of the circuit structure of the delay chain and event acquisition module in the device provided in the embodiments of this application. Detailed Implementation
[0034] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the present invention will be briefly introduced below in conjunction with the accompanying drawings and descriptions of the embodiments or the prior art. Obviously, the following description of the structure of the accompanying drawings is only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. It should be noted that the description of these embodiments is for the purpose of helping to understand the present invention, but does not constitute a limitation of the present invention.
[0035] It should be understood that although the terms "first" and "second", etc., may be used herein to describe various objects, these objects should not be limited by these terms. These terms are only used to distinguish one object from another. For example, the first object may be referred to as the second object, and similarly, the second object may be referred to as the first object, without departing from the scope of the exemplary embodiments of the invention.
[0036] It should be understood that the term "and / or" that may appear in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, B exists alone, or A and B exist simultaneously. Another example is A, B and / or C, which can mean that any one of A, B, and C or any combination thereof exists. The term " / and" that may appear in this document describes another relationship between related objects, indicating that two relationships can exist. For example, A / and B can mean: A exists alone or A and B exist simultaneously. In addition, the character " / " that may appear in this document generally indicates that the related objects before and after it are in an "or" relationship.
[0037] Example:
[0038] like Figures 1-2 As shown, the apparatus for reducing dead time in a time measurement system provided in the first aspect of this embodiment includes, but is not limited to, a delay chain, a high-speed sampling clock module, an event acquisition module, N event recording modules, a low-speed processing clock module, and an event combination module, wherein N represents a positive integer greater than or equal to 2. The high-speed sampling clock module is used to output a high-speed sampling clock signal, and the low-speed processing clock module is used to output a low-speed sampling clock signal. The signal frequency of the low-speed sampling clock signal is one-Nth of the signal frequency of the high-speed sampling clock signal.
[0039] The specific value of N can be determined based on the low-speed processing requirements needed to achieve a low dead time, thereby reducing the risk of timing inconsistencies during FPGA placement and routing by trading processing resources for time. For example, if the high-speed sampling clock signal has a frequency of 500MHz, N is 2, and the low-speed sampling clock signal has a frequency of 250MHz, then the low-speed processing frequency of 250MHz can be used to achieve a low dead time of 2ns, thus reducing the risk of timing inconsistencies during FPGA placement and routing. As another example, if the high-speed sampling clock signal has a frequency of 900MHz, N is 3, and the low-speed sampling clock signal has a frequency of 300MHz, then the low-speed processing frequency of 300MHz can be used to achieve a low dead time of 1.111ns, thus also reducing the risk of timing inconsistencies during FPGA placement and routing.
[0040] The delay chain is used to perform delay processing on the input measured signal. For example... Figure 2 As shown, specifically, the delay chain includes, but is not limited to, a plurality of first delay units connected in series. The input terminal of the first first delay unit along the series direction is used to input the signal under test, and the input terminal of the (k+1)th first delay unit along the series direction is connected to the output terminal of the kth first delay unit along the series direction, where k represents a positive integer less than K, and K represents the total number of units in the plurality of first delay units. More specifically, as... Figure 2 As shown, the first delay unit employs an AND gate circuit. The first input terminal of the AND gate circuit is used to receive the signal under test, the second input terminal is used to receive a high-level signal representing the binary number "1", and the input terminal is used to output the delayed signal under test. This utilizes the delay phenomenon of the AND gate circuit to achieve the purpose of the first delay unit in applying a certain inherent delay to the input signal.
[0041] The event acquisition module is connected to the delay chain and the high-speed sampling clock module, respectively. It is used to periodically sample the delay chain using the signal frequency of the high-speed sampling clock signal as the sampling operating frequency, obtaining a data stream consisting of a string of binary bits that reflects the position of an edge-transition event. The edge-transition event position refers to the position of two adjacent bits (binary numbers "01" or "10") within the data stream. Figure 2As shown, specifically, the event acquisition module includes, but is not limited to, a plurality of first D flip-flops, wherein each of the plurality of first D flip-flops corresponds one-to-one with a plurality of first delay units; for each of the plurality of first D flip-flops, the corresponding input terminal is connected to the output terminal of the corresponding delay unit, and the corresponding clock signal input terminal is connected to the clock signal output terminal of the high-speed sampling clock module; the plurality of first D flip-flops are used to output the data stream.
[0042] The N event recording modules are each connected to the event acquisition module and are used to record the data stream from the event acquisition module in turn. The aforementioned recording of the data stream from the event acquisition module in turn means that within N high-frequency sampling periods, the n"th event recording module records the data stream sampled by the event acquisition module in the n"th high-frequency sampling period, where n" represents a positive integer less than or equal to N.
[0043] To achieve the goal of having the N event recording modules record the data stream from the event acquisition module in turn, preferably, the first event recording module among the N event recording modules includes a plurality of second D flip-flops corresponding one-to-one with the plurality of first D flip-flops, and for each of the plurality of second D flip-flops, the corresponding input terminal is connected to the output terminal of the corresponding flip-flop, and the corresponding clock signal input terminal is connected to the clock signal output terminal of the low-speed processing clock module; the nth event recording module among the N event recording modules includes a second delay unit and a plurality of third D flip-flops corresponding one-to-one with the plurality of first D flip-flops, where n represents a positive integer greater than or equal to 2 and less than or equal to N, the second delay unit is used to delay the input signal by (n-1) / f before outputting, where f represents the signal frequency of the high-speed sampling clock signal; the input terminal of the second delay unit is connected to the clock signal output terminal of the low-speed processing clock module, and for each of the plurality of second D flip-flops, the corresponding input terminal is connected to the output terminal of the corresponding flip-flop, and the corresponding clock signal input terminal is connected to the output terminal of the second delay unit. More specifically, the second delay unit includes multiple inverters connected in series, so that the delay phenomenon of the inverters can be used to achieve the purpose of the second delay unit to perform a certain inherent delay on the input signal.
[0044] The event combination module is connected to the N event recording modules and the low-speed processing clock module, respectively. It periodically and synchronously reads the N data streams recorded in the N event recording modules, using the signal frequency of the low-speed sampling clock signal as the processing operating frequency. Based on these N data streams, it combines them to obtain the final time information reflecting the occurrence time of the edge-jumping event pulse. The occurrence time of the edge-jumping event pulse refers to the timestamp of the edge-jumping event pulse. The specific process of combining the aforementioned data streams can be implemented by conventionally modifying existing post-processing techniques, and will not be elaborated here.
[0045] Therefore, through the detailed structural description of the aforementioned device for reducing dead time in a time measurement system, a new solution is provided that can reduce the risk of timing non-compliance while achieving the goal of low dead time. This solution includes a delay chain, a high-speed sampling clock module, an event acquisition module, multiple event recording modules, a low-speed processing clock module, and an event combination module. The event acquisition module periodically samples the delay chain at a high-speed sampling frequency to obtain a data stream. The multiple event recording modules record the data streams from the event acquisition module in turn. The event combination module periodically and synchronously reads the multiple data streams recorded in the multiple event recording modules at a low-speed processing frequency and combines these multiple data streams to obtain the final time information. Because the data sampling part operates at a high frequency while the data processing part operates at a low frequency, the risk of timing non-compliance during FPGA placement and routing can be reduced by trading processing resources for time, achieving the goal of low dead time. This facilitates practical application and promotion.
[0046] Preferably, the system further includes an application computation module connected to both the low-speed processing clock module and the event combination module. This application computation module uses the signal frequency of the low-speed sampling clock signal as its processing operating frequency and periodically performs at least one specific application computation based on the final time information to obtain at least one specific application computation result corresponding one-to-one with each computation. Specifically, the at least one specific application computation includes, but is not limited to, delay chain time calculation, delay chain correction calculation, and / or edge transition event delay calculation. The specific calculation processes for the aforementioned delay chain time calculation, delay chain correction calculation, and edge transition event delay calculation can be implemented using existing related algorithms. Since the specific application computation processing part also operates at a low frequency, it further reduces the risk of timing non-compliance during FPGA placement and routing by trading processing resources for time, while achieving the goal of low dead time.
[0047] Preferably, the system further includes a host computer connected to the application computing module, wherein the application computing module is also used to package and transmit the at least one specific application computing result to the host computer.
[0048] In summary, the device provided in this embodiment for reducing dead time in a time measurement system has the following technical effects:
[0049] (1) This embodiment provides a new solution that can reduce the risk of timing failure while achieving low dead time. It includes a delay chain, a high-speed sampling clock module, an event acquisition module, multiple event recording modules, a low-speed processing clock module, and an event combination module. The event acquisition module is used to periodically sample the delay chain at a high-speed sampling frequency to obtain a data stream. The multiple event recording modules are used to record the data streams from the event acquisition module in turn. The event combination module is used to periodically and synchronously read the multiple data streams recorded in the multiple event recording modules at a low-speed processing frequency, and combine the multiple data streams to obtain the final time information. Since the data sampling part operates at a high frequency, while the data processing part still operates at a low frequency, the risk of timing failure during FPGA placement and routing can be reduced by trading processing resources for time while achieving low dead time. This facilitates practical application and promotion.
[0050] Finally, it should be noted that the above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A device for reducing dead time in a time measurement system, characterized in that, It includes a delay chain, a high-speed sampling clock module, an event acquisition module, N event recording modules, a low-speed processing clock module, and an event combination module, where N represents a positive integer greater than or equal to 2; The delay chain is used to perform delay processing on the input measured signal; The high-speed sampling clock module is used to output a high-speed sampling clock signal; The event acquisition module is connected to the delay chain and the high-speed sampling clock module respectively. It is used to periodically sample the delay chain with the signal frequency of the high-speed sampling clock signal as the sampling working frequency to obtain a data stream consisting of a string of binary bits that reflects the position of the edge transition event. The position of the edge transition event refers to the position of two adjacent bits of binary number "01" or binary number "10" in the data stream. The N event recording modules are respectively connected to the event acquisition module, and are used to record the data stream from the event acquisition module in turn. The low-speed processing clock module is used to output a low-speed sampling clock signal, wherein the signal frequency of the low-speed sampling clock signal is one-Nth of the signal frequency of the high-speed sampling clock signal. The event combination module is connected to the N event recording modules and the low-speed processing clock module, respectively. It is used to periodically and synchronously read the N data streams recorded in the N event recording modules at the signal frequency of the low-speed sampling clock signal as the processing operating frequency, and combine the N data streams to obtain the final time information reflecting the occurrence time of the edge transition event pulse. The occurrence time of the edge transition event pulse refers to the timestamp of the occurrence of the edge transition event pulse.
2. The apparatus for reducing dead time in a time measurement system as described in claim 1, characterized in that, The delay chain includes a plurality of first delay units connected in series, and the event acquisition module includes a plurality of first D triggers, wherein the plurality of first D triggers correspond one-to-one with the plurality of first delay units; The input terminal of the first first delay unit in the series direction among the plurality of first delay units is used to receive the signal to be measured. The input terminal of the (k+1)th first delay unit in the series direction among the plurality of first delay units is connected to the output terminal of the kth first delay unit in the series direction among the plurality of first delay units. k represents a positive integer less than K, and K represents the total number of units in the plurality of first delay units. For each of the plurality of first D flip-flops, the corresponding input terminal is connected to the output terminal of the corresponding delay unit, and the corresponding clock signal input terminal is connected to the clock signal output terminal of the high-speed sampling clock module. The plurality of first D flip-flops are used to output the data stream.
3. The apparatus for reducing dead time in a time measurement system as described in claim 2, characterized in that, The first delay unit uses an AND gate circuit, wherein the first input terminal of the AND gate circuit is used to receive the signal under test, the second input terminal of the AND gate circuit is used to receive a high-level signal representing the binary number "1", and the input terminal of the AND gate circuit is used to output the delayed signal under test.
4. The apparatus for reducing dead time in a time measurement system as described in claim 2, characterized in that, The first event recording module among the N event recording modules includes a plurality of second D flip-flops that correspond one-to-one with the plurality of first D flip-flops. For each of the plurality of second D flip-flops, the corresponding input terminal is connected to the output terminal of the corresponding flip-flop, and the corresponding clock signal input terminal is connected to the clock signal output terminal of the low-speed processing clock module. The nth event recording module in the N event recording modules includes a second delay unit and a plurality of third D flip-flops that correspond one-to-one with the plurality of first D flip-flops, where n represents a positive integer greater than or equal to 2 and less than or equal to N, and the second delay unit is used to delay the input signal by (n-1) / f before outputting, where f represents the signal frequency of the high-speed sampling clock signal; The input terminal of the second delay unit is connected to the clock signal output terminal of the low-speed processing clock module, and for each of the plurality of second D flip-flops, the corresponding input terminal is connected to the output terminal of the corresponding flip-flop, and the corresponding clock signal input terminal is connected to the output terminal of the second delay unit.
5. The apparatus for reducing dead time in a time measurement system as described in claim 4, characterized in that, The second delay unit includes multiple inverters connected in series.
6. The apparatus for reducing dead time in a time measurement system as described in claim 1, characterized in that, The high-speed sampling clock signal has a frequency of 500MHz and N is 2, while the low-speed sampling clock signal has a frequency of 250MHz.
7. The apparatus for reducing dead time in a time measurement system as described in claim 1, characterized in that, The high-speed sampling clock signal has a frequency of 900MHz and N is 3, while the low-speed sampling clock signal has a frequency of 300MHz.
8. The apparatus for reducing dead time in a time measurement system as described in claim 1, characterized in that, It also includes an application computing module that is connected to the low-speed processing clock module and the event combination module respectively. The application computing module is used to periodically perform at least one specific application operation based on the final time information, using the signal frequency of the low-speed sampling clock signal as the processing operating frequency, to obtain at least one specific application operation result that corresponds one-to-one with the at least one specific application operation.
9. The apparatus for reducing dead time in a time measurement system as described in claim 8, characterized in that, The at least one specific application operation includes delay chain specific time calculation, delay chain correction calculation and / or edge transition event delay calculation.
10. The apparatus for reducing dead time in a time measurement system as described in claim 8, characterized in that, It also includes a host computer connected to the application computing module, wherein the application computing module is further used to package and transmit the at least one specific application computing result to the host computer.