Memory device and operating method thereof

Abstract

The present application relates to a memory device and an operating method thereof. A memory device includes a pre-charge time information storage section for storing information about a first pre-charge time at which a bit line control signal is applied and a second pre-charge time at which a source line control signal is applied, which are determined according to a degree of performing a program operation. The memory device further includes a pre-charge voltage controller for supplying the bit line control signal and the source line control signal to a page buffer and a source line driver, respectively, for a longer pre-charge time selected from the first pre-charge time and the second pre-charge time in a program operation.

Description

Technical Field

[0001] This disclosure generally relates to electronic devices, and more specifically, to a memory device and a method of operating the same. Background Technology

[0002] A semiconductor device is a device that uses the properties of semiconductors to store data. A semiconductor device can be part of a memory system used to store data under the control of a host device such as a computer or smartphone. The memory system can include the memory device for storing data and a memory controller for controlling the memory device. Memory devices can be classified as volatile memory devices or non-volatile memory devices.

[0003] Non-volatile memory devices are memory devices whose data is not lost even when power is interrupted. Non-volatile memory devices can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEROM), flash memory, etc.

[0004] Non-volatile memory devices perform programming operations to store data. Programming is performed by increasing the voltage of each bit line and source line to a target voltage and applying a programming voltage to the word line. When the number of bit lines whose voltage needs to be increased to the target voltage is large, or when the target voltage of the source lines needs to be increased to a large magnitude, a large current is simultaneously generated within the non-volatile memory device. Therefore, the amount of current generated can be adjusted by regulating the time it takes for the voltage of each bit line and source line to increase to the target voltage. Summary of the Invention

[0005] Some implementations provide a memory device and a method of operating the memory device, which can adjust the magnitude of the current generated during programming operations.

[0006] According to an embodiment of the present disclosure, a memory device includes: a precharge time information storage unit configured to store information about a first precharge time for applying a bit line control signal and a second precharge time for applying a source line control signal, determined according to the extent of performing a programming operation; and a precharge voltage controller configured to provide the bit line control signal and the source line control signal to a page buffer and a source line driver, respectively, during a programming operation within a longer precharge time selected from the first precharge time and the second precharge time.

[0007] According to another embodiment of this disclosure, a memory device includes: a precharge time information storage unit configured to store information regarding a first precharge time, determined according to the extent of performing a programming operation, whereby the voltage of a bit line increases to a first precharge voltage, and a second precharge time, whereby the voltage of a source line increases to a second precharge voltage; and a programming operation controller configured to control a programming operation such that, during the programming operation, the voltage of the bit line and the voltage of the source line increase to the first precharge voltage and the second precharge voltage, respectively, during either a first precharge time and a second precharge time.

[0008] According to this disclosure, a method of operating a memory device includes the following steps: storing information about a first precharge time, determined according to the extent of performing a programming operation, whereby the voltage of a bit line increases to a first precharge voltage, and a second precharge time, whereby the voltage of a source line increases to a second precharge voltage; increasing the voltage of the bit line and the voltage of the source line to the first precharge voltage and the second precharge voltage, respectively, during a precharge time selected from the first precharge time and the second precharge time; and applying a programming voltage to a word line connected to a memory cell. Attached Figure Description

[0009] Example embodiments will now be described more fully below with reference to the accompanying drawings; however, they may be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that those skilled in the art will be able to understand this disclosure.

[0010] In the accompanying drawings, dimensions may be exaggerated for clarity. It will be understood that when an element is referred to as being "between" two elements, it may be the only element between those two elements, or there may be one or more intermediate elements. Similar reference numerals always indicate similar elements.

[0011] Figure 1 This is a diagram illustrating a memory system including a memory device according to an embodiment of the present disclosure.

[0012] Figure 2 It is shown Figure 1 A diagram showing the structure of the memory device.

[0013] Figure 3 It is shown Figure 2 A diagram of any one of the multiple storage blocks shown.

[0014] Figure 4 It is a graph showing the threshold voltage distribution of memory cells according to the programming operation of the memory device.

[0015] Figure 5 This is a diagram illustrating the programming operations of a memory device.

[0016] Figure 6 This is a diagram illustrating the application of programming voltage during the programming operation of a memory device.

[0017] Figure 7 This is a diagram illustrating the pre-charging period included in the programming operation according to an embodiment of the present disclosure.

[0018] Figure 8 This is a diagram illustrating an example of bit line and source line interlocking operation during the precharge period according to an embodiment of the present disclosure.

[0019] Figure 9 This is a diagram illustrating an example of bit line and source line interlocking operation during the precharge period according to an embodiment of the present disclosure.

[0020] Figure 10 This is a diagram illustrating the application of a programming voltage according to an embodiment of the present disclosure.

[0021] Figure 11 This is a flowchart illustrating the programming operations of a memory device according to an embodiment of the present disclosure. Detailed Implementation

[0022] The specific structural and functional descriptions disclosed herein are merely illustrative, intended to illustrate possible implementations based on the concepts of this disclosure. Implementations based on the concepts of this disclosure may be carried out in various forms and should not be construed as limited to the specific implementations set forth herein.

[0023] Figure 1 This is a diagram illustrating a memory system 50 including a memory device according to an embodiment of the present disclosure.

[0024] Reference Figure 1 The memory system 50 may include a memory device 100 and a memory controller 200. The memory system 50 may be a means for storing data under the control of a host 300 (e.g., a mobile phone, smartphone, MP3 player, laptop computer, desktop computer, game console, TV, tablet PC, or in-vehicle infotainment system).

[0025] Depending on the host interface used for communication with host 300, memory system 50 can be manufactured as any of a variety of storage devices. For example, memory system 50 can be configured using any of the following types of storage devices: solid-state drives (SSDs), multimedia cards in the form of MMC, eMMC, RS-MMC and micro-MMC, secure digital cards in the form of SD, mini-SD and micro-SD, universal serial bus (USB) memory modules, universal flash memory (UFS) devices, PCMCIA card-type memory modules, peripheral component interconnect (PCI) card-type memory modules, high-speed PCI (PCI-E) card-type memory modules, compact flash (CF) cards, smart media cards (SMCs), and memory sticks.

[0026] The memory system 50 can be manufactured in any of a variety of package types. For example, the memory system 50 can be manufactured in any of a variety of package types such as POP, SIP, SOC, MCP, COB, WFP, and WSP.

[0027] The memory device 100 can store data. The memory device 100 can operate under the control of the memory controller 200. The memory device 100 may include a memory cell array (not shown), which includes a plurality of memory cells for storing data.

[0028] Each memory cell can be configured as any one of a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a three-level cell (TLC) storing three data bits, and a four-level cell (QLC) storing four data bits.

[0029] A memory cell array (not shown) may include multiple memory blocks. Each memory block may include multiple memory cells. A memory block may include multiple pages. In an embodiment, a page may be a unit for storing data in or retrieving data stored in the memory device 100. A memory block may be a unit for erasing data.

[0030] In embodiments, the memory device 100 may use Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SRAM, Low Power DDR (LPDDR), Rambus Dynamic Random Access Memory (RDRAM), NAND flash memory, Vertical NAND flash memory, NOR flash memory, Resistive Random Access Memory (RRAM), Phase Change Random Access Memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), Spin-Torque Random Access Memory (STT-RAM), etc. In this specification, for ease of description, the use of NAND flash memory is assumed and described.

[0031] Memory device 100 can receive commands and addresses from memory controller 200 and access address-selectable regions in the memory cell array. Memory device 100 can perform operations indicated by commands on address-selectable regions. For example, memory device 100 can perform write operations (programming operations), read operations, and erase operations. In a write operation, memory device 100 can program data in the address-selectable region. In a read operation, memory device 100 can read data from the address-selectable region. In an erase operation, memory device 100 can erase data stored in the address-selectable region.

[0032] In one embodiment, the memory device 100 may include a precharge time information storage unit 140 and a programming operation controller 150.

[0033] The precharge time information storage unit 140 can store information about the time when the precharge voltage is applied to the bit line and the source line during the precharge operation. The precharge operation can be an operation included in the programming operation. The precharge operation can be an operation that increases the voltage of the bit line and increases the voltage of the source line. The precharge time information storage unit 140 can store information about the time when the precharge voltage is applied to the bit line and the time when the precharge voltage is applied to the source line, which is determined according to the degree of performing the programming operation. In one embodiment, the degree of performing the programming operation can be the number of times multiple programming cycles are executed. In another embodiment, the degree of performing the programming operation can be the number of memory cells that are programmed to have a threshold voltage corresponding to the target programming state.

[0034] The programming operation controller 150 controls programming operations on memory cells. A programming operation can be an operation that stores data in the memory cell. Specifically, a programming operation can be an operation that increases the threshold voltage of the memory cell based on the data to be stored in the memory cell. When a programming operation is performed, the memory cell can have a threshold voltage corresponding to any one of a plurality of programming states. The plurality of programming states can be determined based on the number of data bits stored in a memory cell. For example, when a memory cell is programmed to store three bits of data in a three-level cell (TLC), the plurality of programming states can refer to an erase state and first programming states through seventh programming states. The threshold voltage of the memory cell after the programming operation is performed can be determined based on the data to be stored in the memory cell. The memory cell can have any one of a plurality of programming states as the target programming state based on the data to be stored therein.

[0035] In this implementation, the programming operation may include multiple programming cycles. Each programming cycle may include a programming voltage application operation and a verification operation. The programming voltage application operation may be an operation of increasing the threshold voltage of the memory cell using a programming voltage. The verification operation may be an operation of using a verification voltage to identify whether the threshold voltage of the memory cell has reached the threshold voltage corresponding to the target programming state.

[0036] The storage controller 200 controls the overall operation of the storage system 50.

[0037] When power is applied to the memory system 50, the memory controller 200 can execute firmware (FW). In one embodiment, the memory controller 200 can control communication between the host 300 and the memory device 100 by executing the FW. In another embodiment, the memory controller 200 can translate the logical block address of the host 300 into the physical block address of the memory device 100.

[0038] The storage controller 200 can control the storage device 100 to perform write operations, read operations, erase operations, etc., in response to requests from the host 300. During a write operation, the storage controller 200 can provide the storage device 100 with a write command, a physical block address, and data. During a read operation, the storage controller 200 can provide the storage device 100 with a read command and a physical block address. During an erase operation, the storage controller 200 can provide the storage device 100 with an erase command and a physical block address.

[0039] In this implementation, the storage controller 200 can autonomously generate commands, addresses, and data regardless of any requests from the host 300, and send these commands, addresses, and data to the storage device 100. For example, the storage controller 200 can provide the storage device 100 with commands, addresses, and data for performing read and write operations in conjunction with wear leveling, read recycling, garbage collection, etc.

[0040] In one implementation, the memory controller 200 can control at least two memory devices 100. The memory controller 200 can control the memory devices according to an interleaving scheme to improve operational performance. The interleaving scheme can be a scheme for controlling the overlapping of operations on at least two memory devices 100.

[0041] The host 300 can communicate with the memory system 50 using at least one of various communication methods such as Universal Serial Bus (USB), Serial AT Accessory (SATA), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), Firewire, Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCIe), High Speed ​​Non-Volatile Memory (NVMe), Universal Flash Memory (UFS), Secure Digital Card (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Loaded DIMM (LRDIMM).

[0042] In an implementation, memory system 50 may include buffer memory (not shown). For example, buffer memory may temporarily store data received from host 300 or memory device 100, or temporarily store metadata (e.g., a mapping table) of memory device 100. Buffer memory may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0043] Figure 2 It is shown Figure 1 A diagram showing the structure of the memory device.

[0044] Reference Figure 2 The memory device 100 may include a memory cell array 110, peripheral circuitry 120, and control logic 130.

[0045] Memory cell array 110 includes a plurality of memory blocks BLK1 to BLKi. The plurality of memory blocks BLK1 to BLKi are connected to row decoder 122 via local line LL. The plurality of memory blocks BLK1 to BLKi are connected to page buffer group 123 via bit lines BL1 to BLn. Each of the plurality of memory blocks BLK1 to BLKi includes a plurality of memory cells. In an embodiment, the plurality of memory cells are non-volatile memory cells. Memory cells connected to the same word line among the plurality of memory cells are defined as a page. That is, memory cell array 110 is configured with a plurality of pages. According to an embodiment of the present disclosure, each of the plurality of memory blocks BLK1 to BLKi included in memory cell array 110 may include a plurality of dummy cells. At least one dummy memory cell may be connected in series between a drain select transistor and a memory cell, and between a source select transistor and a memory cell.

[0046] Each memory cell of the memory device 100 can be configured as any one of a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a three-level cell (TLC) storing three data bits, and a four-level cell (QLC) storing four data bits.

[0047] Peripheral circuitry 120 drives memory cell array 110. For example, under the control of control logic 130, peripheral circuitry 120 can drive memory cell array 110 to perform programming, reading, and erasing operations. In another example, peripheral circuitry 120 can apply various operating voltages to local lines LL and bit lines BL1 to BLn or discharge the applied voltages under the control of control logic 130.

[0048] The peripheral circuitry 120 may include a voltage generation circuit 121, a row decoder 122, a page buffer group 123, a column decoder 125, an input / output circuit 126, a pass / fail check circuit 127, and a source line driver 128. The row decoder 122 is connected to the memory cell array 110 via local lines LL. Local lines LL may include drain select lines, word lines, and source select lines. According to embodiments of this disclosure, word lines may include normal word lines and dummy word lines. According to embodiments of this disclosure, local lines LL may also include transistor select lines.

[0049] The line decoder 122 operates under the control of the control logic 130. The line decoder 122 receives the address control signal AD_signals from the control logic 130.

[0050] The row decoder 122 decodes the row address in response to the address control signal AD_signals. The row decoder 122 can select at least one word line of the selected memory block by applying a voltage provided from the voltage generation circuit 121 to at least one word line according to the decoded row address.

[0051] During programming, the line decoder 122 can apply a programming voltage to the selected word line and a pass voltage with a level lower than the programming voltage to the unselected word line. During programming verification, the line decoder 122 can apply a verification voltage to the selected word line and a verification pass voltage with a level higher than the verification voltage to the unselected word line.

[0052] During a read operation, the line decoder 122 can apply a read voltage to the selected word line and apply a read pass voltage with a level higher than the read voltage to the unselected word line.

[0053] The erase operation of memory device 100 is performed on a block-by-block basis. During the erase operation, the address ADD input to memory device 100 includes the block address. Row decoder 122 can decode the block address and select a memory block based on the decoded block address.

[0054] The voltage generating circuit 121 uses the external power supply voltage supplied to the memory device 100 to generate multiple operating voltages Vop. The voltage generating circuit 121 operates under the control of the control logic 130.

[0055] In this embodiment, the voltage generating circuit 121 can generate an internal power supply voltage by adjusting the external power supply voltage. The internal power supply voltage generated by the voltage generating circuit 121 is used as the operating voltage of the memory device 100.

[0056] In this embodiment, the voltage generating circuit 121 can generate various operating voltages Vop for programming, reading, and erasing operations in response to the operation signal OP_CMD. The voltage generating circuit 121 can use both external and internal power supply voltages to generate multiple operating voltages Vop. The voltage generating circuit 121 can be configured to generate various voltages required in the memory device 100. For example, the voltage generating circuit 121 can generate multiple erase voltages, multiple programming voltages, multiple pass voltages, multiple select read voltages, and multiple unselect read voltages.

[0057] The voltage generating circuit 121 may include multiple pump capacitors for receiving internal power supply voltages to generate multiple operating voltages Vop with various voltage levels, and selectively enable the multiple pump capacitors under the control of control logic 130 to generate multiple operating voltages Vop.

[0058] The generated multiple operating voltages Vop can be supplied to the memory cell array 110 via the row decoder 122.

[0059] Page buffer group 123 may include first page buffer PB1 to nth page buffer PBn. First page buffer PB1 to nth page buffer PBn are respectively connected to memory cell array 110 via first bit line BL1 to nth bit line BLn. First page buffer PB1 to nth page buffer PBn operate under the control of control logic 130.

[0060] Page buffers PB1 through PBn communicate with column decoder 125 to receive data DATA. During programming, page buffers PB1 through PBn receive the data DATA to be stored via column decoder 125 and data line DL.

[0061] During programming, when a programming pulse is applied to the selected word line, the first page buffer PB1 through the nth page buffer PBn can transfer the data DATA received by the column decoder 125 to the memory cell of the selected page via bit lines BL1 through BLn. The memory cell of the selected page is programmed according to the transferred data DATA. Memory cells connected to bit lines to which a programming enable voltage (e.g., ground voltage) is applied can have an increased threshold voltage. The threshold voltage of memory cells connected to bit lines to which a programming disable voltage (e.g., power supply voltage) is maintained. During programming verification, the first page buffer PB1 through the nth page buffer PBn reads the data DATA stored in the selected memory cell from the selected memory cell via bit lines BL1 through BLn.

[0062] During a read operation, page buffer group 123 can read data DATA from the memory cell of the selected page via bit line BL and store the read data DATA in the first page buffer PB1 to the nth page buffer PBn.

[0063] During the erase operation, page buffer group 123 can float the bit line BL.

[0064] In one implementation, while data stored in some of the multiple page buffers included in the page buffer group 123 is programmed into the memory cell array 110, other page buffers can receive and store data from the memory controller. Figure 1 The new data is input as shown in Figure 200.

[0065] The column decoder 125 can transfer data between the input / output circuitry 126 and the page buffer group 123 in response to the column address CADD. For example, the column decoder 125 can exchange data with the page buffer group 123 via the data line DL, or with the input / output circuitry 126 via the column line CL.

[0066] Input / output circuit 126 can transmit data from the memory controller (…) Figure 1 The command CMD and address ADD (as shown in 200) are transmitted to control logic 130, or data DATA is exchanged with column decoder 125.

[0067] During a read or verification operation, the pass / fail check circuit 127 can generate a reference current in response to the enable bit VRY_BIT<#> generated by the control logic 130, and can output a pass signal PASS or a failure signal FAIL to the control logic 130 by comparing the sensed voltage VPB received from the page buffer group 123 with the reference voltage generated by the reference current. For example, when the sensed voltage VPB is higher than the reference voltage, the pass / fail check circuit 127 can output a pass signal PASS to the control logic 130. In another example, when the sensed voltage VPB is lower than the reference voltage, the pass / fail check circuit 127 can output a failure signal FAIL to the control logic 130.

[0068] The source line driver 128 can be connected to a memory cell included in the memory cell array 110 via the source line SL, and controls the voltage applied to the source line SL.

[0069] The source line driver 128 can receive a source line control signal CTRL_SL from the control logic 130 and can control the source line voltage applied to the source line SL based on the source line control signal CTRL_SL.

[0070] Control logic 130 can be connected to voltage generation circuit 121, row decoder 122, page buffer group 123, column decoder 125, and pass / fail check circuit 127. Control logic 130 controls the overall operation of memory device 100. Control logic 130 can operate in response to commands (CMD) transmitted from external devices. Control logic 130 can be implemented in hardware, software, or a combination of both. For example, control logic 130 can be control logic circuitry operating according to an algorithm and / or a processor executing control logic code.

[0071] Control logic 130 can control peripheral circuitry 120 by generating multiple signals in response to command CMD and address ADD. For example, control logic 130 can generate operation signal OP_CMD, address control signal AD_signals, page buffer control signal PBSIGNALS, enable bit VRY_BIT<#>, and source line control signal CTRL_SL in response to command CMD and address ADD. Control logic 130 can output operation signal OP_CMD to voltage generation circuit 121, address control signal AD_signals to line decoder 122, page buffer control signal PBSIGNALS to page buffer group 123, enable bit VRY_BIT<#> to pass / fail check circuit 127, and source line control signal CTRL_SL to source line driver 128. Additionally, control logic 130 can determine whether the verification operation passed or failed in response to the pass signal PASS or failure signal FAIL output from pass / fail check circuit 127.

[0072] Figure 1 The pre-charge time information storage unit 140 and the programming operation controller 150 shown may be included Figure 2 The control logic 130 shown.

[0073] The programming operation controller 150 controls the peripheral circuitry 120 to perform programming operations on memory cells. The programming operation controller 150 controls the peripheral circuitry 120 to apply the operating voltage Vop for programming operations to the row lines and bit lines BL1 to BLn. The programming operation controller 150 can determine, based on information about the precharge time stored in the precharge time information storage unit 140, the timing of applying the page buffer control signal PBSIGNALS to the page buffer group 123 and the timing of applying the source line control signal CTRL_SL to the source line driver 128 during the precharge operation.

[0074] Figure 3 It is shown Figure 2 The diagram shows any one of the multiple storage blocks BLK1 to BLKi.

[0075] Storage block BLKi representation Figure 2 Any one of the multiple storage blocks BLK1 to BLKi shown.

[0076] Reference Figure 3In a memory block BLKi, multiple word lines arranged parallel to each other can be connected between a first select line and a second select line. The first select line can be a source select line (SSL), and the second select line can be a drain select line (DSL). More specifically, a memory block BLKi may include multiple string STs connected between bit lines BL1 to BLn and the source line SL. Bit lines BL1 to BLn can be connected to string STs individually, and the source line SL can be connected together to string STs. String STs can be configured identically to each other; therefore, a string ST connected to the first bit line BL1 will be described in detail as an example.

[0077] A string ST may include a source selection transistor SST connected in series between the source line SL and the first bit line BL1, a plurality of memory cells MC1 to MC16, and a drain selection transistor DST. A string ST may include at least one source selection transistor SST and at least one drain selection transistor DST, and may include a number of memory cells greater than the number of memory cells MC1 to MC16 shown in the figure.

[0078] The source of the source select transistor SST can be connected to the source line SL, and the drain of the drain select transistor DST can be connected to the first bit line BL1. Memory cells MC1 to MC16 can be connected in series between the source select transistor SST and the drain select transistor DST. The gate of the source select transistor SST included in different string STs can be connected to the source select line SSL, the gate of the drain select transistor DST included in different string STs can be connected to the drain select line DSL, and the gate of the memory cells MC1 to MC16 included in different string STs can be connected to multiple word lines WL1 to WL16. A group of memory cells connected to the same word line among the memory cells included in different string STs can be referred to as a physical page PG. Therefore, the number of physical pages PG corresponding to the number of word lines WL1 to WL16 can be included in the memory block BLKi.

[0079] A memory cell can store one bit. A memory cell is usually called a single-level cell (SLC). A physical page (PG) can store one logical page (LPG) of data. An LPG of data can include a number of data bits corresponding to the number of cells in a physical page (PG).

[0080] A memory cell can store two or more bits of data. A physical page (PG) can store two or more LPGs of data.

[0081] Figure 4 It is a graph showing the threshold voltage distribution of memory cells according to the programming operation of the memory device.

[0082] exist Figure 4In the figure, the horizontal axis represents the threshold voltage Vth of the memory cell, and the vertical axis represents the number of memory cells (cell count).

[0083] Reference Figure 4 The threshold voltage distribution of a memory cell can be changed from the initial state to the final programmed state according to the programming operation.

[0084] exist Figure 4 In this paper, we assume and describe the case where a memory cell is programmed to store three bits of data using a TLC.

[0085] The initial state is the state before any programming operation is performed, and the threshold voltage distribution of the memory cell can be the erase state E.

[0086] The final programming state can be the threshold voltage distribution of the memory cell performing the programming operation. The threshold voltage of the memory cell performing the programming operation can have a threshold voltage corresponding to any of a plurality of programming states. For example, when a memory cell is programmed to store three bits of data in a TLC, the plurality of programming states can refer to erase state E and first programming states PV1 to seventh programming states PV7. In an implementation, the threshold voltage of the memory cell performing the programming operation can have a threshold voltage corresponding to any of the erase state E and first programming states PV1 to seventh programming states PV7. The threshold voltage of a memory cell in its initial state can be increased through a programming operation to the threshold voltage corresponding to any of the erase state E and first programming states PV1 to seventh programming states PV7.

[0087] Each memory cell can have any one of the following states as its target programming state: erase state E and first programming state PV1 to seventh programming state PV7. The target programming state can be determined based on the data to be stored in the memory cell. Through programming operations, each memory cell can have a threshold voltage corresponding to the final programming state in its final programming state.

[0088] Figure 5 This is a diagram illustrating the programming operations of a memory device.

[0089] exist Figure 5 In the graph, the horizontal axis represents time, and the vertical axis represents the voltage V applied to the word line. The voltage V applied to the word line can include the programming voltage Vpgm and the verification voltage V_vfy.

[0090] exist Figure 5 The present invention assumes and describes the case where a memory cell is programmed to store three bits of data in a TLC. However, the scope of this disclosure is not limited thereto; a memory cell may be programmed to store two bits or fewer of data, or four bits or more of data.

[0091] Reference Figure 1 and Figure 5 The programming operation of the memory device 100 may include multiple programming cycles PL1 to PLn. The memory device 100 may perform the programming operation by executing multiple programming cycles PL1 to PLn, such that the selected memory cell connected to the selected word line has a threshold voltage corresponding to any one of the multiple programming states. For example, when a memory cell is programmed as TLC, the memory device 100 may perform the programming operation by executing multiple programming cycles PL1 to PLn, such that the selected memory cell connected to the selected word line has a threshold voltage corresponding to any one of the erase state E and the first programming states PV1 to the seventh programming states PV7.

[0092] Each of the multiple programming cycles PL1 to PLn may include a programming voltage application operation PGM Step and a verification operation Verify Step.

[0093] The programming voltage application operation PGM Step can be an operation that applies a programming voltage to a selected word line connected to a selected memory cell. For example, memory device 100 may apply a first programming voltage Vpgm1 to the selected line connected to the selected memory cell. After the first programming voltage Vpgm1 is applied to the selected word line, the threshold voltage of each selected memory cell may have a threshold voltage corresponding to a target programming state among a plurality of programming states.

[0094] The Verify Step operation can be an operation that applies a verification voltage to a selected word line connected to a selected memory cell. The Verify Step operation can also be an operation that determines whether the threshold voltage of each selected memory cell has a threshold voltage corresponding to a target programming state among multiple programming states. The Verify Step operation can also be an operation that applies a verification voltage corresponding to the target programming state of each selected memory cell.

[0095] In an implementation, during the first programming cycle PL1, the memory device 100 may apply a first programming voltage Vpgm1 to a selected word line connected to a selected memory cell, and then apply a first verification voltage V_vfy1 to a seventh verification voltage V_vfy7. The memory device 100 may apply a verification voltage from the first verification voltage V_vfy1 to the seventh verification voltage V_vfy7 that corresponds to the target programming state of the memory cell to the selected word line. For example, the memory device 100 may use the first verification voltage V_vfy1 to perform a verification operation Verify Step on a memory cell whose target programming state is the first programming state. As the verification voltages V_vfy1 to V_vfy7 approach the seventh verification voltage V_vfy7 from the first verification voltage V_vfy1, the magnitudes of the verification voltages V_vfy1 to V_vfy7 may increase. Specifically, among the magnitudes of the verification voltages V_vfy1 to V_vfy7, the magnitude of the first verification voltage V_vfy1 may be the smallest, and the magnitude of the seventh verification voltage V_vfy7 may be the largest. The number of verification voltages is not limited to this implementation.

[0096] It can be determined that the threshold voltage of each memory cell that has passed the Verify Step using verification voltages V_vfy1 to V_vfy7 has a threshold voltage corresponding to the target programming state. Memory cells that have passed the Verify Step can be programmed disabled in the second programming cycle PL2. A programming disable voltage can be applied to the bit line connected to the programmed disabled memory cell.

[0097] It can be determined that the threshold voltage of the memory cell for which the Verify Step failed using verification voltages V_vfy1 to V_vfy7 does not have a threshold voltage corresponding to the target programming state. A second programming cycle PL2 can then be executed for the memory cell for which the Verify Step failed.

[0098] In the second programming cycle PL2, the memory device 100 may apply a second programming voltage Vpgm2, which is a unit voltage ΔVpgm higher than the first programming voltage Vpgm1, to the selected word line connected to the selected memory cell. Subsequently, the memory device 100 may perform the verification operation Verify Step of the second programming cycle PL2 in the same manner as the Verify Step of the first programming cycle PL1.

[0099] Subsequently, the memory device 100 may execute the next programming cycle a predetermined number of times in the same manner as the second programming cycle PL2.

[0100] In this implementation, a programming operation may fail if it is not completed within a predetermined number of programming cycles. A programming operation may pass if it is completed within a predetermined number of programming cycles. Whether a programming operation has been completed can be determined based on whether all verification steps for the selected memory cell have passed. If all verification steps for the selected memory cell have passed, the next programming cycle may not be executed.

[0101] In this implementation, the programming voltage can be applied according to an incremental step pulse programming (ISPP) scheme. The level of the programming voltage can be gradually increased or decreased as programming cycles PL1 to PLn are repeated. The number of times the programming voltage is used, the voltage level, and the voltage application time in each programming cycle can be determined in various ways under the control of the storage controller 200.

[0102] Figure 6 This is a diagram illustrating the application of programming voltage during the programming operation of a memory device.

[0103] Reference Figure 6 The programming operation may include multiple programming cycles PL1 to PLn. Each of the multiple programming cycles PL1 to PLn may include a programming voltage application operation PGM Step and a verification operation Verify Step. The programming voltage application operation PGMStep may include a precharge period, a programming pulse period Pgm Pulse, and a discharge period Discharge.

[0104] The time period t1 to t2 can be a precharge period. The precharge period can be the time during which the voltage of bit line BL and the voltage of source line SL are precharged. During the precharge period, the voltage of the bit line connected to the memory cell having a threshold voltage corresponding to the target programming state can be increased to a first precharge voltage Vpre1. The first precharge voltage Vpre1 ​​can be a programming disable voltage. In one embodiment, the first precharge voltage Vpre1 ​​can be a voltage higher than the ground voltage Gnd. In another embodiment, the first precharge voltage Vpre1 ​​can be a power supply voltage. The voltage of the bit line connected to the memory cell not having a threshold voltage corresponding to the target programming state can maintain the ground voltage Gnd. The ground voltage Gnd can be a programming enable voltage. In response to... Figure 2 The control logic 130 shown receives the page buffer control signal PBSIGNALS, and the voltage of the bit line can be increased to the first precharge voltage Vpre1.

[0105] During the precharge phase, the voltage of the source line SL can be increased to a second precharge voltage Vpre2. When the voltage of the source line SL increases to the second precharge voltage Vpre2, the channel potential of the memory cell can increase. Figure 2 The control logic 130 shown receives the source line control signal CTRL_SL and increases it to the second pre-charge voltage Vpre2. In one embodiment, the magnitude of the second pre-charge voltage Vpre2 may be equal to the magnitude of the first pre-charge voltage Vpre1. In another embodiment, the magnitude of the second pre-charge voltage Vpre2 may be lower than the magnitude of the first pre-charge voltage Vpre1.

[0106] The time period t2 to t3 can be the programming pulse period Pgm Pulse. The programming pulse period Pgm Pulse can be a period during which the threshold voltage of a selected memory cell among a plurality of memory cells increases. During the programming pulse period Pgm Pulse, the memory device 100 can apply a programming voltage Vpgm to the selected word line Sel_WL. During the programming pulse period Pgm Pulse, the memory device 100 can apply a pass voltage Vpass to the unselected word line Unsel_WL.

[0107] The time period t3 to t4 can be a discharge period. The discharge period can be a period during which the voltages of the unselected word line Unsel_WL and the source line SL decrease. During the discharge period, the memory device 100 can apply a ground voltage Gnd to the selected word line Sel_WL. During the discharge period, the memory device 100 can apply a ground voltage Gnd to the unselected word line Unsel_WL. During the discharge period, the voltage of the source line SL can decrease to the ground voltage Gnd.

[0108] Figure 7 This is a diagram illustrating the pre-charging period included in the programming operation according to an embodiment of the present disclosure.

[0109] Reference Figure 1 and Figure 7 The programming operation may include multiple programming cycles PL1 to PLn. Each of the multiple programming cycles PL1 to PLn may include a programming voltage application operation PGM Step and a verification operation Verify Step. The programming voltage application operation PGM Step may include a precharge period, a programming pulse period Pgm Pulse, and a discharge period Discharge. Figure 7 In this document, only the Precharge period during the PGM Step operation, when the programming voltage is applied, will be described.

[0110] During the precharge phase, memory device 100 may apply a bit line control signal PBSENSE to the page buffer. The magnitude of the bit line control signal PBSENSE may increase at a constant slope during the precharge phase. The bit line control signal PBSENSE may be a control signal for increasing the voltage of the bit lines connected to the page buffer. For example, the bit line control signal PBSENSE may be from... Figure 2 The control signals included in the page buffer control signal PBSIGNALS provided by the control logic 130 shown. In an embodiment, the voltage of the bit line may be increased to a first precharge voltage Vpre1 ​​in response to the bit line control signal PBSENSE.

[0111] During the precharge period, the memory device 100 may apply a source line control signal CTRL_SL to the source line driver. The source line control signal CTRL_SL may be a control signal for increasing the voltage of the source line connected to the source line driver. In an embodiment, the voltage of the source line may increase to a second precharge voltage Vpre in response to the source line control signal CTRL_SL.

[0112] The time period t1 to t2 can be the pre-charge period of the first programming cycle PL1.

[0113] Specifically, during time periods t1 to t11, the memory device 100 may apply a bit line control signal PBSENSE with a magnitude of a first bit line control voltage Vp1 to the page buffer. During time periods t11 to t12, the memory device 100 may increase the magnitude of the bit line control signal PBSENSE from the first bit line control voltage Vp1 to a second bit line control voltage Vp2. During time periods t11 to t12, the slope of the bit line control signal PBSENSE increasing from the first bit line control voltage Vp1 to the second bit line control voltage Vp2 may be a first slope ΔS1. During time periods t12 to t2, the memory device 100 may apply a bit line control signal PBSENSE with a magnitude of the second bit line control voltage Vp2 to the page buffer. The bit line control signal PBSENSE may be applied to the page buffer within the zeroth bit line precharge time Pret_bl0 corresponding to time periods t1 to t2. During time periods t1 to t2, the bit line voltage may be increased to a first precharge voltage Vpre1.

[0114] During time periods t1 to t2, memory device 100 may not apply a source line control signal CTRL_SL to the source line driver. For example, memory device 100 may apply a source line control signal with the magnitude of ground voltage Gnd to the source line driver. During time periods t1 to t2, the voltage of the source line may maintain the ground voltage Gnd in response to the source line control signal CTRL_SL.

[0115] The time period t3 to t4 can be the pre-charge period of the i-th programming cycle PLi.

[0116] Specifically, during time periods t3 to t4, the memory device 100 may apply a bit line control signal PBSENSE with a first bit line control voltage Vp1 to the page buffer. During time periods t31 to t32, the memory device 100 may increase the magnitude of the bit line control signal PBSENSE from the first bit line control voltage Vp1 to a second bit line control voltage Vp2. During time periods t31 to t32, the slope of the bit line control signal PBSENSE increasing from the first bit line control voltage Vp1 to the second bit line control voltage Vp2 may be a second slope ΔS2. The second slope ΔS2 may be less than the first slope ΔS1. During time periods t32 to t4, the memory device 100 may apply the bit line control signal PBSENSE with the second bit line control voltage Vp2 to the page buffer. The bit line control signal PBSENSE may be applied to the page buffer within the first bit line precharge time Pret_bl1 corresponding to time periods t3 to t4. The first bit line precharge time Pret_bl1 may be a longer time than the zeroth bit line precharge time Pret_bl0. During the time period t3 to t4, the voltage of the bit line can be increased to the first pre-charge voltage Vpre in response to the bit line control signal PBSENSE.

[0117] In programming operations, there may be multiple programming cycles containing numerous memory cells whose threshold voltages increase to a threshold voltage corresponding to the target programming state. A first precharge voltage Vpre1 ​​is applied to the bit lines connected to the memory cells whose threshold voltages have increased to the threshold voltage corresponding to the target programming state. That is, as the number of memory cells whose threshold voltages have increased to the threshold voltage corresponding to the target programming state increases, the number of bit lines to which the first precharge voltage is applied increases. Therefore, a large current can be generated simultaneously. Therefore, the amount of current generated can be adjusted by adjusting the slope of the bit line control signal PBSENSE.

[0118] During time periods t3 to t32, memory device 100 may apply a source line control signal CTRL_SL having a first source line control voltage Vc1 to the source line driver. During time periods t3 to t32, the voltage of the source line may increase to a second pre-charge voltage Vpre2 in response to the source line control signal CTRL_SL. The source line control signal CTRL_SL may be applied to the source line driver within a first source line pre-charge time Pret_sl1 corresponding to time periods t3 to t32. The voltage of the source line may increase to the second pre-charge voltage Vpre2 within the first source line pre-charge time Pret_sl1.

[0119] During the Precharge phase of the i-th programming cycle PLi, the first line precharge time Pret_bl1 for applying the bit line control signal PBSENSE and the first source line precharge time Pret_sl1 for applying the source line control signal CTRL_SL can be different from each other. Specifically, the first line precharge time Pret_bl1 can be longer than the first source line precharge time Pret_sl1. Because the Precharge phase of the i-th programming cycle PLi continues until the end of the application of the bit line control signal PBSENSE at time t4, the source line control signal CTRL_SL can be applied until time t4 after time t32.

[0120] The time period t5 to t6 can be the precharge period of the nth programming cycle PLn.

[0121] Specifically, during periods t5 to t51, the memory device 100 may apply a bit line control signal PBSENSE with a first bit line control voltage Vp1 to the page buffer. During periods t51 to t52, the memory device 100 may increase the magnitude of the bit line control signal PBSENSE from the first bit line control voltage Vp1 to a second bit line control voltage Vp2. During periods t51 to t52, the slope of the bit line control signal PBSENSE increasing from the first bit line control voltage Vp1 to the second bit line control voltage Vp2 may be a first slope ΔS1. During periods t52 to t53, the memory device 100 may apply a bit line control signal PBSENSE with a second bit line control voltage Vp2 to the page buffer. The bit line control signal PBSENSE may be applied to the page buffer within the zeroth bit line precharge time Pret_bl0 corresponding to periods t5 to t53. The time for applying the bit line control signal in the nth programming loop PLn may be shorter than the time for applying the bit line control signal in the ith programming loop PLi. During t5 to t53, the voltage of the bit line can be increased to the first precharge voltage Vpre1 ​​in response to the bit line control signal PBSENSE.

[0122] During time periods t5 and t6, the memory device 100 may apply a source line control signal CTRL_SL having the magnitude of a second source line control voltage Vc2 to the source line driver. The magnitude of the second source line control voltage Vc2 may be greater than the magnitude of the first source line control voltage Vc1. During time periods t5 and t6, the voltage of the source line may increase to a third precharge voltage Vpre3 in response to the source line control signal CTRL_SL. The magnitude of the third precharge voltage Vpre3 may be greater than the magnitude of the second precharge voltage Vpre2. The source line control signal CTRL_SL may be applied to the source line driver within a second source line precharge time Pret_sl2 corresponding to time periods t5 and t6. The voltage of the source line may increase to the third precharge voltage Vpre3 within the second source line precharge time Pret_sl2. Because the voltage increase of the source line in the nth programming loop PLn is greater than that in the ith programming loop PLi, the source line precharge time in the nth programming loop PLn can be longer than that in the ith programming loop PLi. The second source line precharge time Pret_sl2 can be longer than the zeroth bit line precharge time Pret_bl0. The precharge period Precharge in the nth programming loop PLn continues until the end of the application of the source line control signal CTRL_SL at time t6. Therefore, the bit line control signal PBSENSE can be applied until time t53, which is t6 after the current time.

[0123] In one embodiment, the memory device 100 may determine the timing of applying the bit line control signal based on the number of programming cycles executed. In another embodiment, the memory device 100 may determine the timing of applying the bit line control signal based on the number of memory cells having a threshold voltage corresponding to the target programming state during the programming operation. In yet another embodiment, the memory device 100 may determine the timing of applying the bit line control signal based on the number of bit lines increased to the first precharge voltage Vpre1 ​​during the programming operation.

[0124] In one implementation, the memory device 100 may determine the timing of applying the source line control signal based on the magnitude of the increase in source line voltage. For example, when the increase in source line voltage is small, the timing of applying the source line control signal may be shorter. In another example, when the increase in source line voltage is large, the timing of applying the source line control signal may be longer.

[0125] The memory device 100 can store information about the timing of applying bit line control signals and applying source line control signals, determined according to the degree of programming operation performed. For example, the degree of programming operation may refer to the number of times multiple programming cycles are executed. In another example, the degree of programming operation may refer to the number of memory cells having a threshold voltage corresponding to a target programming state. The memory device 100 can store information about the timing of applying bit line control signals and applying source line control signals. Figure 1 The pre-charge time information storage unit 140 is shown. (Refer to...) Figure 7 As described, the memory device 100 can apply bit line control signals to the page buffer during a bit line precharge time determined according to the extent of the programming operation performed, and can apply source line control signals to the source line driver during a source line precharge time determined according to the extent of the programming operation performed.

[0126] Multiple programming loops PL1 to PLn can be divided into initial time periods, intermediate time periods, and final time periods. For example, as... Figure 7 As shown, the initial time period can be the first programming loop PL1, the intermediate time period can be the i-th programming loop PLi, and the final time period can be the n-th programming loop PLn. During the intermediate time period, the bit line precharge time can be longer than the source line precharge time. During the final time period, the source line precharge time can be longer than the bit line precharge time.

[0127] Figure 8 This is a diagram illustrating an example of bit line and source line interlocking operation during the precharge period according to an embodiment of the present disclosure.

[0128] exist Figure 8 In the middle, omission and Figure 7 The description of the repeated parts is shown. In Figure 8 In this document, only the Precharge period in the Programming Voltage Application Operation PGM Step will be described.

[0129] Reference Figure 1 and Figure 8 The time period t3 to t4 can be the precharge period of the i-th programming cycle PLi.

[0130] Specifically, during time periods t3 to t4, memory device 100 may apply a bit line control signal PBSENSE to the page buffer. The bit line control signal PBSENSE may be applied to the page buffer during the first bit line precharge time Pret_bl1.

[0131] During time periods t3 to t4, memory device 100 may apply a source line control signal CTRL_SL having a first source line control voltage Vc1 to the source line driver. The source line control signal CTRL_SL may be applied to the source line driver during the first bit precharge time Pret_bl1 corresponding to time periods t3 to t4.

[0132] During the precharge period of the i-th programming cycle PLi, the memory device 100 can compare the bit line precharge time and the source line precharge time with each other. The memory device 100 can apply the bit line control signal PBSENSE and the source line control signal CTRL_SL to the page buffer and the source line driver, respectively, during a longer precharge time selected from the bit line precharge time and the source line precharge time. In an implementation similar to... Figure 7 In the i-th programming loop PLi shown, when the bit line precharge time is longer than the source line precharge time, the memory device 100 may apply the bit line control signal PBSENSE and the source line control signal CTRL_SL to the page buffer and the source line driver, respectively, within the first bit line precharge time Pret_bl1 in the i-th programming loop PLi. The bit line voltage may be increased to the first precharge voltage Vpre1 ​​within the first bit line precharge time Pret_bl1. The source line voltage may be increased to the second precharge voltage Vpre2 within the first bit line precharge time Pret_bl1.

[0133] The time period t5 to t6 can be the precharge period of the nth programming cycle PLn.

[0134] Specifically, during time periods t5 to t6, memory device 100 may apply a bit line control signal PBSENSE to the page buffer. The bit line control signal PBSENSE may be applied during the second source line precharge time Pret_sl2 corresponding to time periods t5 to t6.

[0135] During time periods t5 to t6, memory device 100 may apply a source line control signal CTRL_SL having a second source line control voltage Vc2 to the source line driver. The source line control signal CTRL_SL may be applied to the source line driver during the second source line precharge time Pret_sl2 corresponding to time periods t5 to t6.

[0136] During the precharge period of the nth programming cycle PLn, the memory device 100 can compare the bit line precharge time and the source line precharge time. In an implementation, similar to... Figure 7In the nth programming loop PLn shown, when the source line precharge time is longer than the bit line precharge time, the memory device 100 can apply the bit line control signal PBSENSE and the source line control signal CTRL_SL to the page buffer and the source line driver, respectively, within the second source line precharge time Pret_sl2 in the nth programming loop PLn. Figure 7 The precharge time Pret_bl0 of the zeroth bit line, as described in the document, is applied to the page buffer within the longer second source line precharge time Pret_Sl2. That is, in Figure 8 The slope of the bit line control signal PBSENSE increasing in the nth programming loop PLn shown can be less than that in... Figure 7 The slope of the bit line control signal PBSENSE increases in the nth programming loop PLn, as shown.

[0137] The voltage of the bit line can be increased to the first pre-charge voltage Vpre within the second source line pre-charge time Pret_sl2. The voltage of the source line can be increased to the third pre-charge voltage Vpre3 within the second source line pre-charge time Pret_sl2.

[0138] In one implementation, the memory device 100 may compare the bit line precharge time and the source line precharge time with each of a plurality of programming cycles. The memory device 100 may also apply bit line control signals and source line control signals to the page buffer and the source line driver during a longer precharge time selected from the bit line precharge time and the source line precharge time during each of the plurality of programming cycles.

[0139] Figure 9 This is a diagram illustrating an example of bit line and source line interlocking operation during the precharge period according to an embodiment of the present disclosure.

[0140] exist Figure 9 In the middle, omission and Figure 7 and Figure 8 The description of the repeated parts is shown. In Figure 9 In this document, only the Precharge period in the Programming Voltage Application Operation PGM Step will be described.

[0141] Reference Figure 1 and Figure 9 The time period t3 to t4 can be the precharge period of the i-th programming cycle PLi.

[0142] Specifically, during time periods t3 to t4, memory device 100 may apply a bit line control signal PBSENSE to the page buffer. The bit line control signal PBSENSE may be applied to the page buffer during the source line precharge time Pret_sl corresponding to time periods t3 to t4.

[0143] During time periods t3 to t4, memory device 100 may apply a source line control signal CTRL_SL having a second source line control voltage Vc2 to the source line driver. The source line control signal CTRL_SL may be applied to the source line driver during the source line precharge time Pret_sl corresponding to time periods t3 to t4.

[0144] In the implementation method, with Figure 7 The case shown is different from the one where the precharge time of the bit line in the i-th programming loop PLi is longer than the precharge time of the source line. Figure 9 In the i-th programming loop PLi shown, the source line precharge time can be longer than the bit line precharge time. The memory device 100 can apply the bit line control signal PBSENSE and the source line control signal CTRL_SL to the page buffer and source line driver, respectively, within the source line precharge time Pret_sl in the i-th programming loop PLi. The bit line voltage can be increased to a first precharge voltage Vpre1 ​​within the source line precharge time Pret_sl. The source line voltage can be increased to a third precharge voltage Vpre3 within the source line precharge time Pret_sl.

[0145] The time period t5 to t6 can be the precharge period of the nth programming cycle PLn.

[0146] Specifically, during time periods t5 to t6, memory device 100 may apply a bit line control signal PBSENSE to the page buffer. The bit line control signal PBSENSE may be applied to the page buffer during the source line precharge time Pret_sl corresponding to time periods t5 to t6.

[0147] During time periods t5 to t6, memory device 100 may apply a source line control signal having a second source line control voltage Vc2 to the source line driver. The source line control signal CTRL_SL may be applied to the source line driver during the source line precharge time Pret_sl corresponding to time periods t5 to t6. In the nth programming cycle PLn, memory device 100 may apply the bit line control signal PBSENSE and the source line control signal CTRL_SL to the page buffer and the source line driver, respectively, during the source line precharge time Pret_sl. The bit line voltage may be increased to a first precharge voltage Vpre1 ​​during the source line precharge time Pret_sl. The source line voltage may be increased to a third precharge voltage Vpre3 during the source line precharge time Pret_sl.

[0148] Figure 10 This is a diagram illustrating the application of a programming voltage according to an embodiment of the present disclosure.

[0149] Figure 1 The memory device 100 shown may include control logic 1000, voltage generator 1100, source line driver 1200, page buffer 1300, and memory cell array 1400.

[0150] Control logic 1000 can be implemented as Figure 2 This is a component of the control logic 130 shown. The voltage generator 1100 may include a voltage generation circuit 121 and a line decoder 122 (shown in...). Figure 2 The source line driver 1200 can be implemented as follows: Figure 2 One component of the source line driver 128 shown. The page buffer 1300 can be implemented as Figure 2 A component of the page buffer group 123 shown.

[0151] The control logic 1000 may include a programming operation controller 1010 and a precharge time information storage unit 1020. The programming operation controller 1010 can control the programming operation of the memory cell array 1400. The precharge time information storage unit 1020 can store information about the bit line precharge time and the source line precharge time, which are determined according to the degree of programming operation.

[0152] The programming operation controller 1010 may include a word line voltage controller 1011 and a precharge voltage controller 1012. The word line voltage controller 1011 controls the voltage to be applied to the word line connected to the memory cell. The word line voltage controller 1011 may provide a word line voltage control signal OP_CMD to the voltage generator 1100 for generating the voltage V_wl to be applied to the word line.

[0153] Based on the precharge time information Pret_inf provided from the precharge time information storage unit 1020, the precharge voltage controller 1012 can provide the source line control signal CTRL_SL and the bit line control signal PBSENSE to the source line driver 1200 and the page buffer 1300, respectively. The precharge time information Pret_inf can include information about the bit line precharge time and the source line precharge time.

[0154] In an implementation, in the first precharge mode, the precharge voltage controller 1012 can provide a bit line control signal PBSENSE to the page buffer 1300 during the bit line precharge time, and can provide a source line control signal CTRL_SL to the source line driver 1200 during the source line precharge time. That is, the precharge voltage controller 1012 can provide a bit line control signal PBSENSE to the page buffer 1300 during the bit line precharge time. Figure 7The bit line control signal PBSENSE and the source line control signal CTRL_SL are provided to the page buffer 1300 and the source line driver 1200, respectively, during the bit line precharge time and the source line precharge time determined according to the degree of programming operation performed.

[0155] In another embodiment, in the second pre-charge mode, the pre-charge voltage controller 1012 can, for example, [e.g., ...]. Figure 8 The bit line control signal PBSENSE and the source line control signal CTRL_SL are provided to the page buffer 1300 and the source line driver 1200, respectively, during the longer of the bit line precharge time and the source line precharge time, which are determined based on the degree of programming operation performed. The precharge voltage controller 1012 can compare the bit line precharge time and the source line precharge time with each other in each of a plurality of programming cycles. In an embodiment, the precharge voltage controller 1012 may include a precharge time comparator 1013 for comparing the bit line precharge time and the source line precharge time with each other in each of the plurality of programming cycles. The precharge time comparator 1013 can determine the longer precharge time selected from the bit line precharge time and the source line precharge time as the precharge time.

[0156] Voltage generator 1100 can generate a voltage V_wl to be applied to the word line in response to word line voltage control signal OP_CMD and provide the generated voltage V_wl to memory cell array 1400. The voltage V_wl to be applied to the word line can be a programming voltage or a pass voltage.

[0157] The source line driver 1200 can provide a second precharge voltage V_pre2 to the memory cell array 1400 in response to the source line control signal CTRL_SL. The voltage of the source line connected between the source line driver 1200 and the memory cell array 1400 can be increased to the second precharge voltage V_pre2 according to the source line control signal CTRL_SL.

[0158] Page buffer 1300 may provide a first precharge voltage V_pre1 to memory cell array 1400 in response to bit line control signal PBSENSE. The voltage of the bit line connected between page buffer 1300 and memory cell array 1400 may be increased to the first precharge voltage V_pre1 according to bit line control signal PBSENSE.

[0159] Figure 11 This is a flowchart illustrating the programming operation of a memory device according to the method of this disclosure.

[0160] Reference Figure 11In step S1101, the memory device 100 may store precharge information regarding a first precharge time and a second precharge time determined according to the extent of the programming operation performed. The first precharge time may be a bit line precharge time. The second precharge time may be a source line precharge time.

[0161] In step S1103, the memory device 100 may compare the first precharge time and the second precharge time with each other. If the first precharge time selected from the first precharge time and the second precharge time is longer, step S1105 may be executed. Alternatively, if the second precharge time selected from the first precharge time and the second precharge time is longer, step S1107 may be executed.

[0162] In step S1105, the memory device 100 may increase the voltage of the bit line to a first precharge voltage and the voltage of the source line to a second precharge voltage during the first precharge time. In an embodiment, the memory device 100 may apply the bit line control signal and the source line control signal to the page buffer and the source line driver, respectively, during the first precharge time.

[0163] In step S1107, the memory device 100 may increase the voltage of the bit line to the first precharge voltage and the voltage of the source line to the second precharge voltage during the second precharge time. In an embodiment, the memory device 100 may apply the bit line control signal and the source line control signal to the page buffer and the source line driver, respectively, during the second precharge time.

[0164] In step S1109, the memory device 100 may apply a programming voltage to a word line connected to a memory cell.

[0165] According to this disclosure, a memory device and a method of operating the memory device may be provided, which can adjust the magnitude of the current generated during programming operations.

[0166] Although this disclosure has been shown and described with reference to specific exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of this disclosure as defined by the appended claims and their equivalents. Therefore, the scope of this disclosure should not be limited to the exemplary embodiments described above, but should be determined not only by the appended claims but also by their equivalents.

[0167] In the above embodiments, all steps may be performed selectively, or some steps may be omitted. In various embodiments, the steps may not be performed in the described order, but may be rearranged. The embodiments disclosed in this specification and accompanying drawings are merely examples to facilitate understanding of this disclosure, and this disclosure is not limited thereto. That is, it should be apparent to those skilled in the art that various modifications can be made based on the technical scope of this disclosure.

[0168] Furthermore, embodiments of this disclosure have been described in the accompanying drawings and specification. Although specific terminology is used herein, it is for illustrative purposes only. Therefore, this disclosure is not limited to the embodiments described above, and many variations are possible within the spirit and scope of this disclosure. It will be apparent to those skilled in the art that various modifications can be made based on the technical scope of this disclosure in addition to the embodiments disclosed herein.

[0169] Cross-reference to related applications

[0170] This application claims priority to Korean Patent Application No. 10-2022-0085350, filed on July 12, 2022, with the Korean Intellectual Property Office, the full disclosure of which is incorporated herein by reference.

Claims

1. A memory device comprising: Memory cells, wherein the memory cells are respectively connected between the source line and the bit line; The precharge time information storage unit stores information about the first precharge time of the bit line control signal applied and the second precharge time of the source line control signal applied, which is determined according to the degree of programming operation performed. as well as A precharge voltage controller, during the programming operation, provides the bit line control signal and the source line control signal to the page buffer and the source line driver, respectively, during the longer precharge time selected from the first precharge time and the second precharge time. The extent to which the programming operation is performed is the number of times multiple programming loops included in the programming operation are executed or the number of memory cells among the memory cells that are programmed to have a threshold voltage corresponding to the target programming state.

2. The memory device according to claim 1, further comprising: A word line voltage controller that performs the programming operations including the plurality of programming cycles for storing data in the memory unit. The page buffer provides voltage to the bit line according to the bit line control signal, and The source line driver provides voltage to the source line according to the source line control signal.

3. The memory device according to claim 2, wherein, The magnitude of the bit line control signal increases at a constant slope during the longer precharge time.

4. The memory device according to claim 1, wherein, The precharge voltage controller further includes a precharge time comparator that determines the longer precharge time based on a result obtained by comparing the first precharge time and the second precharge time with each other.

5. The memory device according to claim 4, wherein, The multiple programming loops include an initial period, a middle period, and an ending period, and The pre-charge voltage controller provides the source line control signal to the source line driver during the intermediate period and the end period.

6. The memory device according to claim 5, wherein, The precharge time comparator determines the longer precharge time as the second precharge time during the middle period and the end period.

7. The memory device according to claim 5, wherein, The magnitude of the source line control signal increases based on the number of times the plurality of programming loops are executed.

8. The memory device according to claim 7, wherein, The precharge time comparator: The longer pre-charging time within the intermediate period is defined as the first pre-charging time, and The longer pre-charge time is determined as the second pre-charge time during the end phase.

9. A memory device comprising: Memory cells, which are respectively connected to the source line and the bit line; A precharge time information storage unit stores information about a first precharge time when the voltage of the bit line increases to a first precharge voltage, which is determined according to the degree of programming operation, and a second precharge time when the voltage of the source line increases to a second precharge voltage. as well as A programming operation controller controls the programming operation such that the voltage of the bit line and the voltage of the source line increase to a first pre-charge voltage and a second pre-charge voltage, respectively, during the programming operation, within any pre-charge time selected from a first pre-charge time and a second pre-charge time. The extent to which the programming operation is performed is the number of times multiple programming loops included in the programming operation are executed or the number of memory cells among the memory cells that are programmed to have a threshold voltage corresponding to the target programming state.

10. The memory device of claim 9, further comprising: The peripheral circuitry performs the programming operation that stores data in the memory cell.

11. The memory device according to claim 10, wherein, The programming operation controller controls the peripheral circuitry to increase the voltage of the source line from a predetermined programming cycle in the plurality of programming cycles to the second pre-charge voltage.

12. The memory device according to claim 11, wherein, The programming operation controller controls the peripheral circuit so that the voltage of the bit line and the voltage of the source line increase to the first pre-charge voltage and the second pre-charge voltage, respectively, during the second pre-charge time.

13. The memory device according to claim 11, wherein, The magnitude of the second pre-charge voltage increases based on the number of times the plurality of programming loops are executed.

14. The memory device according to claim 13, wherein, The multiple programming loops include an initial period, a middle period, and an ending period, and The programming operation controller controls the peripheral circuit so that the voltage of the bit line and the voltage of the source line increase to the first pre-charge voltage and the second pre-charge voltage respectively during the first pre-charge time in the intermediate period, and the voltage of the bit line and the voltage of the source line increase to the first pre-charge voltage and the second pre-charge voltage respectively during the second pre-charge time in the end period.

15. A method of operating a memory device, the method comprising the steps of: Store information about a first precharge time when the voltage of the bit line increases to a first precharge voltage, and a second precharge time when the voltage of the source line increases to a second precharge voltage, as determined by the extent of the programming operation performed; The voltage of the bit line and the voltage of the source line are increased to the first pre-charge voltage and the second pre-charge voltage, respectively, during any one of the pre-charge times selected from the first pre-charge time and the second pre-charge time. as well as Apply programming voltage to the word line connected to the memory cell. The extent to which the programming operation is performed is the number of times multiple programming loops included in the programming operation are executed or the number of memory cells among the memory cells that are programmed to have a threshold voltage corresponding to the target programming state.

16. The method according to claim 15, wherein, The voltage of the bit line and the voltage of the source line are increased to the first pre-charge voltage and the second pre-charge voltage, respectively, during the second pre-charge time.

17. The method according to claim 15, wherein, The magnitude of the second pre-charge voltage increases based on the number of times the plurality of programming loops are executed.

18. The method according to claim 17, wherein, The multiple programming loops include an initial period, a middle period, and an ending period, and In the step of increasing the voltage of the bit line and the voltage of the source line to the first pre-charge voltage and the second pre-charge voltage respectively during any one pre-charge time period, the voltage of the bit line and the voltage of the source line are increased to the first pre-charge voltage and the second pre-charge voltage respectively during the first pre-charge time period in the intermediate period, and the voltage of the bit line and the voltage of the source line are increased to the first pre-charge voltage and the second pre-charge voltage respectively during the second pre-charge time period in the end period.

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