Array substrate and display device

Abstract

This disclosure provides an array substrate and a display device, relating to the field of display technology. The array substrate includes a substrate and a plurality of sub-pixels and a plurality of gate line connections disposed on one side of the substrate. The gate line connections extend along a first direction, and the plurality of sub-pixels arranged along the first direction form a sub-pixel row. Each sub-pixel includes a switching transistor, which includes a channel and a gate line, with the gate line at least partially overlapping the channel. The gate line connections are disposed on the same layer as the gate lines, and the gate line connections electrically connect the gate lines of the plurality of switching transistors within the same sub-pixel row. At least a portion of the linewidths of the gate line connections are greater than the linewidths of the gate lines. The linewidth of the gate line connection refers to the dimension of the gate line connection perpendicular to its extension direction and parallel to the substrate, and the linewidth of the gate line refers to the dimension of the gate line perpendicular to its extension direction and parallel to the substrate.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to an array substrate and a display device. Background Technology

[0002] With the continuous development of the display panel industry, the number of products equipped with display panels is gradually increasing. To improve the user experience, various products equipped with display panels are showing a trend towards larger display panel sizes. However, larger display panel sizes can easily lead to problems such as no display or inconsistent display. Summary of the Invention

[0003] The embodiments of this disclosure provide an array substrate and a display device that reduce the resistance of the gate line interconnects and improve the display effect.

[0004] To achieve the above objectives, the embodiments of this disclosure adopt the following technical solutions:

[0005] On one hand, an array substrate is provided, including a substrate and a plurality of sub-pixels and a plurality of gate line connecting lines disposed on one side of the substrate, wherein the gate line connecting lines extend along a first direction and the plurality of sub-pixels arranged along the first direction constitute a sub-pixel row;

[0006] The sub-pixel includes a switching transistor, the switching transistor including a channel and a gate line, the gate line at least partially overlapping the channel;

[0007] The gate line connecting line is disposed on the same layer as the gate line, and the gate line connecting line is electrically connected to the gate lines of multiple switching transistors in the same sub-pixel row;

[0008] At least a portion of the gate line connection lines have a line width greater than the gate line's line width; wherein, the line width of the gate line connection line refers to the dimension of the gate line connection line perpendicular to its extension direction and parallel to the substrate, and the line width of the gate line refers to the dimension of the gate line perpendicular to its extension direction and parallel to the substrate.

[0009] In some embodiments, the gate line connecting line extends through the sub-pixel row along the first direction, and the gate line is connected to a first side of the gate line connecting line.

[0010] In some embodiments, the channel includes a first channel located on the first side and extending along the first direction, the first channel at least partially overlapping the gate line.

[0011] In some embodiments, the extension direction of the gate line intersects with the first direction.

[0012] In some embodiments, the array substrate includes two gate lines, which are spaced apart along the first direction.

[0013] In some embodiments, the gate line connection includes a plurality of first regions and a plurality of second regions, the first regions and the second regions being arranged alternately along the first direction, the first region being the gate line and at least partially overlapping the channel, and the line width of the second region being greater than the line width of the first region.

[0014] In some embodiments, the channel includes a third channel extending along a third direction and at least partially overlapping the gate line, the third direction intersecting the first direction.

[0015] In some embodiments, the channel further includes a fourth channel and a fifth channel, the fourth channel and the third channel being spaced apart along the first direction, the fourth channel at least partially overlapping the grid line, the fifth channel being located on the second side of the grid line, and the fifth channel connecting the third channel and the fourth channel.

[0016] In some embodiments, the array substrate further includes a pixel electrode located on a first side of the gate line connection line, the gate line connection line including a widened region opposite to the pixel electrode, and the line width of the widened region being greater than the line widths on both sides of the widened region.

[0017] In some embodiments, the array substrate includes an active layer, a first insulating layer, a first conductive layer and a second conductive layer sequentially stacked on the substrate, the channel is located in the active layer, the gate line and the gate line connection line are located in the first conductive layer, and the second conductive layer is provided with data lines extending along a second direction;

[0018] The first insulating layer is provided with a first via, the channel is electrically connected to the pixel electrode through the first via, a first gap is provided between the widened region and the edge opposite to the first via, and / or a second gap is provided between the widened region and the edge opposite to the data line.

[0019] In some embodiments, the first gap X1 ≥ 1.3 μm and the second gap X2 ≥ 3 μm.

[0020] In some embodiments, the widened region has two opposite sides along the first direction forming an obtuse angle with the first direction.

[0021] In some implementations, the line width of the gate wire connection is the same at all locations.

[0022] In some embodiments, the array substrate further includes a black matrix whose orthogonal projection onto the substrate overlaps the orthogonal projection of the gate line connection lines onto the substrate.

[0023] On the other hand, a display device is provided, including the aforementioned array substrate.

[0024] The array substrate and display device provided in this disclosure embodiment include a gate line connection line disposed on the same layer as the gate line, and the gate line connection line electrically connecting the gate lines of a plurality of switching transistors within the same sub-pixel row. At least a portion of the gate line connection line has a linewidth greater than that of the gate line. Because the linewidth of at least a portion of the gate line connection line is widened, the cross-sectional area of ​​the gate line connection line is increased, thereby reducing the load on the gate line connection line and improving the display quality of the display panel. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 An example application scenario diagram of a display device is shown;

[0027] Figure 2 A simplified diagram of a display panel is shown as an example;

[0028] Figure 3 An exemplary schematic diagram of a portion of the structure within the display area is shown;

[0029] Figure 4 An exemplary schematic diagram illustrates how the waveform of the scan signal within the gate line connection varies with the load;

[0030] Figure 5 An exemplary diagram of a partial area layout of a display panel is shown;

[0031] Figure 6 An exemplary layout of channels, grid lines, and grid line connections is shown;

[0032] Figure 7 An exemplary diagram of a partial area layout of a display panel is shown;

[0033] Figure 8 An example layout of a channel is shown;

[0034] Figure 9 An exemplary layout of another channel, grid line, and grid line connection is shown;

[0035] Figure 10 and Figure 11An exemplary structural diagram of the gate wire connection line is shown;

[0036] Figure 12 A partial structural layout of a display panel is shown as an example;

[0037] Figures 13 to 16 Simulation comparison diagrams of the display panel of the present disclosure embodiment and related technologies are shown;

[0038] Figure 17 An exemplary partial structural diagram of another display panel is shown;

[0039] Figure 18 A partial structural layout of a display panel is shown as an example;

[0040] Figure 19 An exemplary layout of gate line connectors and channels is shown;

[0041] Figure 20 An exemplary structural diagram of a channel is shown. Detailed Implementation

[0042] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0043] In the embodiments of this disclosure, the terms "first," "second," "third," and "fourth" are used to distinguish identical or similar items with essentially the same function and effect, solely for the purpose of clearly describing the technical solutions of the embodiments of this disclosure, and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.

[0044] In embodiments of this disclosure, "a plurality of" means two or more, and "at least one" means one or more, unless otherwise expressly and specifically defined.

[0045] In the embodiments of this disclosure, the terms "upper" and "lower" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this disclosure.

[0046] The transistors used in the embodiments of this disclosure can be thin-film transistors, field-effect transistors (e.g., oxide thin-film transistors), or other switching devices with similar characteristics. The embodiments of this disclosure all use thin-film transistors as an example. The control electrode of each transistor is the gate, the first electrode is one of the source and drain, and the second electrode is the other. Since the source and drain of a transistor can be structurally symmetrical, they can be structurally indistinguishable. In other words, the first and second electrodes of the transistors in the embodiments of this disclosure can be structurally indistinguishable.

[0047] Figure 1 An example application scenario diagram of a display device is shown. For example... Figure 1 As shown, some embodiments of this disclosure provide a display device 1000, which can be any device that displays text or images, whether in motion (e.g., video) or stationary (e.g., still images). More specifically, the embodiments are contemplated to be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging and aesthetic structures (e.g., displays of images of a piece of jewelry), etc. Figure 1 The following is an illustration of the display device 1000, which is an in-vehicle display.

[0048] The display device 1000 includes a display panel, which can be a liquid crystal display (LCD). The display panel can be an in-plane switching (IPS) liquid crystal display panel or an advanced super-dimensional switching (ADS) liquid crystal display panel. IPS or ADS are commonly used display modes for existing wide-viewing-angle liquid crystal display panels. Liquid crystal display panels using IPS or ADS modes can also be called horizontal electric field type liquid crystal display panels. The display panel provided in this embodiment is described using a horizontal electric field type liquid crystal display panel as an example.

[0049] The display device 1000 may also include a backlight module for providing a light source for the display panel. The backlight module may be an edge-lit backlight module, and may include, for example, a light source, a light guide plate, a reflector, and optical sheets.

[0050] In practical applications, the display device 1000 may also include a control board and a flexible circuit board, with the flexible circuit board electrically connected to the control board and the display panel, so that the control board provides drive signals to the display panel through the flexible circuit board.

[0051] The display panel of this disclosure will now be described in detail with reference to specific embodiments.

[0052] Example 1

[0053] Figure 2 A simplified diagram of a display panel is shown as an example. (e.g.) Figure 2 As shown, the display panel includes a display area AA and a non-display area NA electrically connected to the display area AA. The non-display area NA can be located on one side, two sides, or three sides of the display area AA, or the non-display area NA can be arranged around the display area AA. Figure 2 The diagram shows a scenario where the non-display area AA is positioned around the display area AA.

[0054] Figure 3 An exemplary schematic diagram of a portion of the structure within the display area is shown. For example... Figure 3 As shown, the display area AA contains multiple sub-pixels P1, multiple grid line connecting lines, and multiple data lines.

[0055] For example, multiple sub-pixels P1 can be arranged in an array. For instance, the array arrangement of multiple sub-pixels P1 forms multiple sub-pixel rows and multiple sub-pixel columns. Multiple sub-pixels P1 within a sub-pixel row are arranged along a first direction X, and multiple sub-pixels P1 within a sub-pixel column are arranged along a second direction Y. The first direction X and the second direction Y intersect each other. The angle between the first direction X and the second direction Y can be selected and set according to actual needs. For example, the angle between the first direction X and the second direction Y can be 85°, 88°, 90°, 92°, or 95°, etc.

[0056] For example, the gate line connection line GL extends along a first direction, and each sub-pixel row corresponds to one gate line connection line GL. The gate line connection line GL is electrically connected to multiple sub-pixels within the same sub-pixel row.

[0057] For example, the data line DL extends along the second direction, and each sub-pixel column corresponds to one data line DL. The data line DL is electrically connected to multiple sub-pixels within the same sub-pixel column.

[0058] Sub-pixel P1 includes a pixel electrode 81 and a common electrode. An electric field that drives the deflection of liquid crystal molecules can be formed between the pixel electrode 81 and the common electrode. Exemplarily, the pixel electrode 81 and the common electrode are arranged opposite to and spaced apart, with liquid crystal molecules disposed between them. When a driving voltage is applied to the pixel electrode 81 and the common electrode, an electric field perpendicular to the light-emitting surface is formed between them. Exemplarily, liquid crystal molecules are disposed on the side of the pixel electrode 81 and the common electrode facing the light-emitting surface. When a driving voltage is applied to the pixel electrode 81 and the common electrode, an electric field parallel to the light-emitting surface is formed between them.

[0059] Sub-pixel P1 also includes a switching transistor, which comprises a first electrode, a second electrode, and a gate line 43. The first electrode of the switching transistor is electrically connected to the data signal line, the second electrode is electrically connected to the pixel electrode 81, and the gate line 43 is electrically connected to the gate line connection line GL. During operation, the gate line 43 of the switching transistor receives a scan signal from the gate line connection line GL, causing the switching transistor to conduct. This allows the data signal in the data line DL to be written to the pixel electrode 81 through the switching transistor, thereby creating an electric field corresponding to the data signal between the pixel electrode 81 and the common electrode.

[0060] With the continuous development of the display panel industry, the number of products equipped with display panels is gradually increasing. To improve the user experience, various products equipped with display panels are showing a trend towards larger display panel sizes. Taking automotive display panels as an example, these mainly include the driver's instrument panel display, the central control display, and the passenger entertainment display. With the increasing intelligence of automobiles and the trend towards younger interior designs, some models are replacing the driver's instrument panel display, central control display, and passenger entertainment display with a single, integrated display panel, resulting in a longer display panel (for example, the display panel extending horizontally from the driver's seat to the passenger seat).

[0061] As the display panel becomes longer, the gate line connecting lines GL within the display panel also become longer, resulting in an increased load on the gate line connecting lines GL. This increased load on the gate line connecting lines GL leads to greater waveform variations in the scan signal within them. Figure 4 An exemplary schematic diagram illustrates how the waveform of the scan signal within the gate line GL varies with load. For example... Figure 4 As shown, the signal waveform deteriorates as the load on the gate line GL increases. Furthermore, the voltage difference between the end of the gate line GL near the GOA and the end far from the GOA is significant, resulting in different turn-on states for the switching transistors near and far from the GOA.

[0062] During the operation of the display panel, an electric field is generated between the pixel electrode 81 and the common electrode, driving the liquid crystal to deflect. Light emitted from the backlight module passes through the liquid crystal and is emitted from the light-emitting surface of the display panel to achieve image display. The magnitude of the write voltage of the pixel electrode 81 directly affects the degree of liquid crystal deflection, and thus affects the amount of light emitted. Data signals are written to the pixel electrode 81 through the switching transistor. Therefore, timely and sufficient opening of the switching transistor is crucial for the normal display of the display panel. When the resistance of the gate line connection GL is too high, the scanning signal in the gate line connection GL suffers severe attenuation and delay, causing the switching transistors near the GOA to have different on-states than those far from the GOA, resulting in problems such as no display or abnormal display.

[0063] To improve the display effect of the display panel, it is necessary to reduce the resistance of the gate interconnects (GL). According to the resistance calculation formula, there are three main methods to reduce resistance: selecting a material with low resistivity, reducing the length of the gate interconnects (GL), and increasing the cross-sectional area of ​​the gate interconnects (GL). However, the commonly used gate interconnect materials (GL) in the display field are Mo, Al, and Cu, and there is currently no material that simultaneously meets the requirements of low cost, high stability, and low resistivity. The length of the gate interconnects (GL) is directly related to the length of the display panel; increasing the display panel length directly leads to an increase in the length of the gate interconnects (GL). Limited by the display panel manufacturing process, the thickness of the gate interconnects (GL) cannot be further increased, and the width of the gate interconnects (GL) also needs to be determined based on the aperture ratio requirements of the display panel and the characteristics of the switching transistors.

[0064] Therefore, the display panel in this embodiment of the present disclosure reduces the resistance of the gate line connection line GL while meeting the requirements of the display panel aperture ratio and the characteristics of the switching transistor, thereby improving the display effect of the display panel.

[0065] The display panel may include an array substrate, a color filter substrate, and a liquid crystal layer. The array substrate and the color filter substrate are arranged in a cell, and the liquid crystal layer is located between the array substrate and the color filter substrate. When the display panel is a planar electric field type liquid crystal display panel, the switching transistor, gate connection line GL, pixel electrode 81, and common electrode may be located on the array substrate. For example, the array substrate includes a substrate and the switching transistor, gate connection line GL, pixel electrode 81, and common electrode disposed on the same side of the substrate.

[0066] The array substrate may include a substrate, an active layer, a first conductive layer, and a first insulating layer. The active layer, the first conductive layer, and the first insulating layer are stacked on the same side of the substrate, and the first insulating layer is located between the active layer and the first conductive layer.

[0067] The substrate is used to support and connect the various film layers of the array substrate; for example, the substrate is a glass substrate. The active layer is a semiconductor layer; for example, the active layer is a polycrystalline silicon layer. The first conductive layer is made of a conductor, such as a metal material like Mo, Al, or Cu. The first insulating layer is used to insulate between the active layer and the first conductive layer; for example, the first insulating layer is silicon nitride.

[0068] The switching transistor includes a channel 20 and a gate line 43. The channel 20 of the switching transistor is located in the active layer, and the gate line 43 is located in the first conductive layer, with the gate line 43 and the channel 20 at least partially overlapping. The switching transistor can be a top-gate structure, a bottom-gate structure, or both. In this embodiment, only a top-gate structure is described as an example, in which case the first conductive layer is located on the side of the active layer away from the substrate.

[0069] The gate line connection line GL is also located in the first conductive layer, and the gate line connection line GL is electrically connected to the gate lines 43 of multiple switching transistors in the same sub-pixel row, so as to simultaneously provide scanning signals to the gate lines 43 of multiple switching transistors in the same sub-pixel row through the gate line connection line GL.

[0070] In related technologies, the gate line connection GL has a uniform linewidth at all points, and it runs through the sub-pixel row along a first direction. The portion of the gate line connection GL that overlaps with the channel 20 also serves as the gate line 43 of the switching transistor. To ensure the switching transistor meets design characteristics, the ratio of the gate line width 43 to the channel line width 20 needs to meet certain conditions; that is, the gate line width 43 needs to be set relatively narrow, resulting in a narrower overall linewidth for the gate line connection GL and a higher resistance.

[0071] In this embodiment of the disclosure, the linewidth of at least a portion of the gate line connection GL is greater than the linewidth of the gate line 43. Because the linewidth of at least a portion of the gate line connection GL is widened, the cross-sectional area of ​​the gate line connection GL is increased, thereby reducing the resistance of the gate line connection GL and improving the display quality of the display panel.

[0072] Figure 5 An exemplary diagram of a partial area layout of a display panel is shown, for example... Figure 5 This shows the map of the region containing a sub-pixel row. It should be noted that, for ease of illustration, Figure 5Taking a subpixel row comprising two subpixels P1 as an example, the number of subpixels P1 within a subpixel row in practical applications can be determined based on the resolution of the display panel and the arrangement of the gate driving circuit. For example, if the resolution of the display panel is 1920*1080, and the gate driving circuit is only set on one side of the display panel, the number of subpixels P1 within a subpixel row can be 1920*3=5760; if the gate driving circuit is set on both opposite sides of the display panel, two subpixel rows can be included at the same horizontal position, and the number of subpixels P1 within each subpixel row can be 5760 / 2=2880.

[0073] like Figure 5 As shown, the gate line connection line GL passes through the sub-pixel row along a first direction. The gate line connection line GL includes a first side S1 and a second side S2 opposite to each other. The first side S1 of the gate line connection line GL is the side of the gate line connection line GL facing the pixel electrode 81, and the second side S2 of the gate line connection line GL is the side of the gate line connection line GL away from the pixel electrode 81.

[0074] The gate line 43 is located on the first side S1 of the gate line connection line GL and is electrically connected to the gate line connection line GL. Compared with related technologies, the gate line 43 is a structure that is drawn out separately from the gate line connection line GL, and is no longer part of the gate line connection line GL with a uniform width. Therefore, the line width of the gate line 43 and the line width of the gate line connection line GL can be set separately.

[0075] The linewidth of the gate line connection GL refers to the dimension of the gate line connection GL along its extension direction, which is perpendicular to the substrate. Figure 6 An exemplary layout of channel 20, gate line 43, and gate line connection line GL is shown. For example, as... Figure 6 As shown, the gate connection line GL extends along the first direction X, and the linewidth of the gate connection line GL refers to the dimension of the gate connection line GL along the second direction Y. The linewidth of the gate line 43 refers to the dimension of the gate line 43 along a direction perpendicular to its extension direction and parallel to the substrate. For example, continuing to refer to... Figure 6 The gate line 43 extends along the second direction Y, and the line width of the gate line 43 refers to the size of the gate line 43 along the first direction X.

[0076] In practical applications, to ensure the switching transistor meets the required characteristics, its aspect ratio needs to be fixed. The aspect ratio refers to the ratio L / W between the linewidth L of the gate line 43 and the linewidth W of the channel 20. Due to space constraints within the display panel, the linewidth L of the gate line 43 and the linewidth W of the channel 20 need to be relatively small.

[0077] In this embodiment, since the gate line 43 is a structure that is separately led out from the gate line connecting line GL, the line width of the gate line 43 and the line width of the gate line connecting line GL can be set separately. Setting the line width of the gate line connecting line GL to be larger than the line width of the gate line 43 can reduce the resistance of the gate line connecting line GL, thereby improving the display effect of the display panel.

[0078] The linewidth of the grid line GL can be determined based on the size of the black matrix (BM). The black matrix can be set on the color filter substrate and located between two adjacent sub-pixels P1 to block light, prevent light mixing between adjacent sub-pixels P1, and improve color contrast.

[0079] Figure 7 An exemplary diagram of a portion of a display panel layout is shown. Figure 7 The shaded area is the orthogonal projection of the black matrix onto the substrate. For example... Figure 7 As shown, the orthographic projection of the gate line GL onto the substrate lies within the orthographic projection range of the black matrix onto the substrate. The larger the linewidth of the gate line GL, the lower its resistance, and the better the display effect of the display panel. In practical applications, the lower edge of the gate line GL can be flush with the lower edge of the black matrix. Of course, due to unavoidable errors during the manufacturing process, the lower edge of the gate line GL can also slightly protrude from the lower edge of the black matrix.

[0080] Figure 8 An exemplary layout of a channel 20 is shown. For example... Figures 5 to 8 As shown, the channel 20 includes a first channel 21, which is located on the first side S1 and extends along a first direction. The first channel 21 at least partially overlaps with the gate line 43. Both the first channel 21 and the gate line connection line GL extend along the first direction to facilitate the routing of the first channel 21 and the gate line connection line GL.

[0081] For example, continue to refer to Figures 5 to 8 The channel 20 also includes a second channel 22 connected to the first channel 21. The second channel 22 extends along a second direction, and the orthographic projection of the second channel 22 onto the substrate is located within the orthographic projection range of the data line DL onto the substrate. The first channel 21 is electrically connected to the pixel electrode 81, and the second channel 22 is electrically connected to the data line DL.

[0082] Continue to refer to Figures 5 to 7 The extension direction of the gate line 43 can intersect with the first direction. For example, the gate line 43 extends along a second direction. The intersection of the extension direction of the gate line 43 with the first direction simplifies the structure of the gate line 43 and the gate line connecting line GL, reducing fabrication difficulty.

[0083] Of course, the gate line 43 can also extend along the first direction. For example, both the gate line 43 and the first channel 21 extend along the first direction, and the gate line 43 and the first channel 21 overlap. The gate line 43 is electrically connected to the gate line connection line GL through a transition line extending along the second direction.

[0084] The switching transistor can be a dual-gate structure or a single-gate structure. When the switching transistor is a dual-gate structure, the gate line 43 can include two gate lines 43, which are arranged at intervals along a first direction. The two gate lines 43 can have the same or different structures.

[0085] It should be noted that, Figures 5 to 7 In the example shown, the line width of the gate connection line GL is the same at all points, which makes the routing of the gate connection line GL easier. Of course, the line width of the gate connection line GL can also be different at different points.

[0086] Figure 9 An exemplary layout of another channel 20, gate line 43, and gate line connector GL is shown. Figure 9 As shown, a portion of the gate line connector GL has its linewidth widened to form a widened region 42. The increased linewidth of the widened region 42 further increases the cross-sectional area of ​​the gate line connector GL, reducing its resistance. The linewidth of the widened region 42 is greater than the linewidth of the adjacent unwidened region 41.

[0087] In practical applications, there is a gap between the pixel electrode 81 and the gate line connection line GL. Therefore, the widened region 42 can be opposite to the pixel electrode 81 to make full use of the gap between the pixel electrode 81 and the gate line connection line GL.

[0088] A portion of the gate line connecting line GL can extend toward the first side S1 to form a widened region 42, such as Figure 9 As shown. A portion of the gate line connecting line GL can also extend towards the second side S2 to form a widened region 42, and a portion of the gate line connecting line GL can also extend towards both the first side S1 and the second side S2 to form a widened region 42, as shown. Figure 10 As shown.

[0089] Figure 11 Several gate connection diagrams are illustrated as examples. For instance... Figure 11 As shown, the shape of the widened region 42 can be various, such as a rectangle, a rounded rectangle, or a trapezoid. This embodiment does not limit the shape of the widened region 42.

[0090] Continue to refer to Figure 11 The angle α between the two opposite edges of the widened region 42 along the first direction X and the first direction X can be an obtuse angle, thereby improving the etching accuracy of the gate line connection line GL during wet etching.

[0091] A first via H1 is provided in the region of the first insulating layer opposite to the channel 20, and the channel 20 is electrically connected to the pixel electrode 81 through the first via H1. Specifically, the channel 20 can be directly electrically connected to the pixel electrode 81 through the first via H1, or the channel 20 can be electrically connected to the adapter structure through the first via H1, and the adapter structure is electrically connected to the pixel electrode 81.

[0092] For example, a second conductive layer and a third conductive layer are sequentially disposed on the side of the first conductive layer away from the substrate. A second insulating layer is disposed between the first and second conductive layers, and a third insulating layer is disposed between the second and third conductive layers. The data line DL and the touch line Tx are located on the second conductive layer, and the pixel electrode 81 is located on the third conductive layer. The second conductive layer also includes a transition structure. The channel 20 is electrically connected to the transition structure through a first via H1. The third insulating layer has a second via, and the transition structure is electrically connected to the pixel electrode 81 through the second via.

[0093] A first gap is provided between the widened region 42 and the edge opposite to the first via H1 to prevent the widened region 42 from affecting the signal of the switching transistor. For example, continuing to refer to... Figure 9 Along the first direction, the gap between the two opposite edges of the first through hole H1 and the widened region 42 is the first gap.

[0094] The size of the first gap can be determined based on the magnitude of the error during the fabrication process. For example, the size of X1 satisfies the following formula:

[0095]

[0096] Wherein, ILD CDTolerance is the machining accuracy of the first via H1, ILD overlay is the alignment accuracy of the first insulating layer, Ngate CD Tolerance is the machining accuracy of the gate line 43, and Ngate overlay is the alignment accuracy of the first conductive layer. For example, X1 ≥ 1.3 μm.

[0097] A second gap is provided between the widened region 42 and the edge opposite to the data line DL to prevent the widened region 42 from affecting the signal of the switching transistor. Figure 12 An exemplary partial structural layout of a display panel is shown. For example, as shown... Figure 12 As shown, along the first direction, the gap between the two edges of the widened region 42 opposite to the data line DL is the second gap. For example, X2 ≥ 3μm.

[0098] In practical applications, the display panel in this embodiment, while maintaining the same aperture ratio, can reduce the resistance of the gate line connection line GL by 60% compared to the gate line connection line GL in related technologies. This allows the display panel to be used in high refresh rate scenarios or to increase its length in low refresh rate scenarios. Furthermore, when the resistance of the gate line connection line GL meets the requirements, the size of the black matrix can be reduced, thereby increasing the aperture ratio of the display panel. For example, in related technologies, the BM CD is 15.5μm, while in this embodiment, the BM CD can be 10.55μm, increasing the aperture ratio by 10%.

[0099] Furthermore, in practical evaluations using a product with a 152.1μm subpixel pitch and a resolution of 3K*2K, the reduction in the resistance of the gate line connector (GL) resulted in significant improvements in both the charging rate and the rising edge of the scan signal. Figures 13 to 16 As shown.

[0100] To improve the viewing angle of the display panel, the pixel electrode 81 is often designed with a certain tilt angle (e.g., the pixel electrode 81 is tilted 10° relative to the second direction Y). The data line DL and the touch line Tx are designed at the same angle as the pixel electrode 81. In this way, during the display stage, the common electrode (touch electrode) can shield the pixel electrode 81 from the influence of other coupled voltages within the display panel, thereby stabilizing the display image quality. Of course, the data line DL does not have to be parallel to the pixel electrode 81; for example, the data line DL can extend along the second direction Y. Figure 17 As shown.

[0101] Example 2

[0102] The main difference between Embodiment 2 and Embodiment 1 is that the structures of the gate line 43, the gate line connecting line GL, and the channel 20 in Embodiment 2 are different from those in Embodiment 1. The specific structures of the gate line 43, the gate line connecting line GL, and the channel 20 in Embodiment 2 are described in detail below with reference to the accompanying drawings.

[0103] Figure 18 An exemplary partial structural layout of a display panel is shown. Figure 19 An exemplary layout of the gate line connection GL and the channel 20 is shown. For example... Figure 18 and Figure 19 As shown, the gate line connection line GL includes multiple first regions 1 and multiple second regions 2. The first regions 1 and the second regions 2 are arranged alternately along a first direction. The first region 1 is a gate line 43 and overlaps with the channel 20 at least partially. The line width of the second region 2 is greater than the line width of the first region 1.

[0104] To ensure the switching transistor meets performance requirements, its aspect ratio needs to be fixed. The aspect ratio is the ratio L / W between the linewidth L of the gate line 43 and the linewidth W of the channel 20. Due to space constraints within the display panel, the linewidth L of the gate line 43 and the linewidth W of the channel 20 need to be relatively small.

[0105] The first region 1 serves as the gate line 43, which makes the line width of the first region 1 smaller, while the line width of the second region 2 can be set to be larger, thereby reducing the resistance of the gate line connection line GL and improving the display effect of the display panel.

[0106] Figure 20 An exemplary structural diagram of a channel 20 is shown. For example... Figure 20 As shown, the channel 20 may include a third channel 23, which extends along a third direction and at least partially overlaps with the gate line 43. The third direction intersects with the first direction. The third direction may be parallel to the second direction or may form a certain angle with the second direction.

[0107] Continue to refer to Figure 20 The channel 20 also includes a fourth channel 24 and a fifth channel 25. The fourth channel 24 and the third channel 23 are arranged at intervals along the first direction, and the fourth channel 24 at least partially overlaps with the gate line 43. The fifth channel 25 is located on the second side S2 of the gate line 43 and connects the third channel 23 and the fourth channel 24. That is, the channel 20 is generally U-shaped, and the two ends of the U-shape are electrically connected to the pixel electrode 81 and the data line DL, respectively.

[0108] A first gap is provided between the edge of the second region 2 and the edge opposite to the first via H1 to prevent the second region 2 from affecting the signal of the switching transistor. For example, continuing to refer to... Figure 18 and Figure 19 Along the first direction, the gap between the two opposite edges of the first via H1 and the second region 2 is the first gap.

[0109] The size of the first gap can be determined based on the magnitude of the error during the fabrication process. For example, the size of X1 satisfies the following formula:

[0110]

[0111] Wherein, ILD CDTolerance is the machining accuracy of the first via H1, ILD overlay is the alignment accuracy of the first insulating layer, Ngate CD Tolerance is the machining accuracy of the gate line 43, and Ngate overlay is the alignment accuracy of the first conductive layer. For example, X1 ≥ 1.3 μm.

[0112] A second gap is provided between the edge of the second region 2 and the edge opposite to the data line DL to prevent the second region 2 from affecting the signal of the switching transistor. For example, continuing to refer to... Figure 18 Along the first direction, the gap between the two edges of the second region 2 opposite to the data line DL is the second gap. For example, X2 ≥ 3μm.

[0113] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. An array substrate, characterized in that, It includes a substrate and a plurality of sub-pixels and a plurality of gate line connecting lines disposed on one side of the substrate, wherein the gate line connecting lines extend along a first direction and the plurality of sub-pixels arranged along the first direction constitute a sub-pixel row; The sub-pixel includes a switching transistor, the switching transistor including a channel and a gate line, the gate line at least partially overlapping the channel; The gate line connecting line is disposed on the same layer as the gate line, and the gate line connecting line is electrically connected to the gate lines of multiple switching transistors in the same sub-pixel row; At least a portion of the gate line connectors have a line width greater than the gate line width; wherein, the line width of the gate line connector refers to the dimension of the gate line connector along its extension direction and parallel to the substrate, and the line width of the gate line refers to the dimension of the gate line along its extension direction and parallel to the substrate. The grid line connection includes a first side and a second side opposite to each other, the channel includes a first channel located on the first side and extending along the first direction, and the first channel at least partially overlaps with the grid line.

2. The array substrate according to claim 1, characterized in that, The gate line connecting line passes through the sub-pixel row along the first direction, and the gate line is connected to the first side of the gate line connecting line.

3. The array substrate according to claim 2, characterized in that, The extension direction of the grid line intersects with the first direction.

4. The array substrate according to claim 3, characterized in that, The array substrate includes two gate lines, which are spaced apart along the first direction.

5. The array substrate according to claim 1, characterized in that, The gate line connection includes multiple first regions and multiple second regions, which are arranged alternately along the first direction. The first region is the gate line and at least partially overlaps with the channel. The line width of the second region is greater than that of the first region.

6. The array substrate according to claim 5, characterized in that, The channel includes a third channel that extends along a third direction and at least partially overlaps with the grid line, the third direction intersecting with the first direction.

7. The array substrate according to claim 6, characterized in that, The channel further includes a fourth channel and a fifth channel, the fourth channel and the third channel are arranged at intervals along the first direction, and the fourth channel overlaps with the grid line at least partially. The fifth channel is located on the second side of the grid line and connects the third channel and the fourth channel.

8. The array substrate according to any one of claims 1 to 7, characterized in that, The array substrate further includes a pixel electrode located on a first side of the gate line connection line. The gate line connection line includes a widened region opposite to the pixel electrode, and the line width of the widened region is greater than the line widths on both sides of the widened region.

9. The array substrate according to claim 8, characterized in that, The array substrate includes an active layer, a first insulating layer, a first conductive layer and a second conductive layer stacked sequentially on the substrate. The channel is located in the active layer, the gate line and the gate line connection line are located in the first conductive layer, and the second conductive layer is provided with a data line extending along a second direction. The first insulating layer is provided with a first via, the channel is electrically connected to the pixel electrode through the first via, a first gap is provided between the widened region and the edge opposite to the first via, and / or a second gap is provided between the widened region and the edge opposite to the data line.

10. The array substrate according to claim 9, characterized in that, The first gap X1 ≥ 1.3 μm, and the second gap X2 ≥ 3 μm.

11. The array substrate according to claim 8, characterized in that, The widened region has two opposite sides along the first direction that form an obtuse angle with the first direction.

12. The array substrate according to any one of claims 2 to 4, characterized in that, The line width is the same at all points where the grid lines connect.

13. The array substrate according to claim 1, characterized in that, The array substrate also includes a black matrix, the orthographic projection of which overlays the orthographic projection of the gate line connection on the substrate.

14. A display device, characterized in that, Includes the array substrate as described in any one of claims 1 to 13.

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