Display panel and display device

Abstract

This application provides a display panel and a display device. The display panel includes a display area and a non-display area adjacent to the display area. The bezel area includes a substrate and signal traces, a planarization layer, lead traces, and an encapsulation layer sequentially stacked on the substrate. The encapsulation layer includes a first inorganic layer disposed on the lead traces. The display area includes a substrate, a planarization layer, and an anode located on the side of the planarization layer away from the substrate. The lead traces extend from the side of the anode into the bezel area and are connected to the signal traces. This application provides a barrier layer between the lead traces and the first inorganic layer. The orthographic projection of the barrier layer on the lead traces covers the orthographic projection of the first inorganic layer on the lead traces, thereby avoiding the bombardment damage to the lead traces by high-energy plasma when the first inorganic layer is fabricated using plasma-enhanced chemical vapor deposition in the prior art, and thus avoiding the phenomenon of uneven thickness of the first inorganic layer.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] Currently, thin film encapsulation of organic light-emitting diode (OLED) devices mostly adopts an inorganic / organic multilayer stacked structure. Analysis has found that, with a fixed thickness, increasing the number of stacking layers can effectively improve the water and oxygen barrier effect. That is, the thickness of a single layer decreases while the number of interfaces increases, thus lengthening the diffusion path of water and oxygen and prolonging the time for water and oxygen intrusion. When the thickness of the inorganic layer increases, the internal stress and defect density of the film increase, which weakens the encapsulation performance. Adding an organic layer can release the stress of the inorganic film layer on the one hand, and cover the defect sites on the other hand, thus improving the water barrier performance of the entire structure.

[0003] In existing technologies, plasma-enhanced chemical vapor deposition (PECVD) is typically used to fabricate the inorganic layer in the encapsulation layer; please refer to... Figure 1 This is a schematic diagram of the structure of an existing display panel. In the existing display panel 1, the display area 1000 includes a substrate 10, a planarization layer 30, an anode 41, a pixel definition layer 50, a light-emitting layer 60, a cathode 70, and a light extraction layer 81. The border area 2000 includes the substrate 10 and signal traces 21, a planarization layer 30, and lead-out traces 42 sequentially disposed on the substrate 10. The lead-out traces 42 include an overlapping portion 421 and an exposed portion 422 disposed on the side of the overlapping portion 421 away from the display area. The orthographic projection of the light extraction layer 81 onto the substrate 10 covers the overlapping portion 421. The orthographic projection of the light extraction layer 81 on the substrate 10 does not overlap with the orthographic projection of the exposed portion 422 on the substrate 10. When the first inorganic layer 91 in the encapsulation layer 90 is actually fabricated, the exposed portion 422 will be bombarded by plasma. Metal ions in the lead-out trace 42 will be ejected by the plasma and adhere to the edge of the mask. The ejected metal ions will change the magnetic field, thereby affecting the distribution of plasma gas, which will lead to uneven film thickness at the edge of the mask, affecting the ability of the first inorganic layer 91 to block water and oxygen. Summary of the Invention

[0004] This application provides a display panel and display device to alleviate the shortcomings of related technologies.

[0005] To achieve the above functions, the technical solutions provided in this application are as follows:

[0006] This application provides a display panel, including a display area and a border area adjacent to the display area;

[0007] The border area includes a substrate, and signal traces, a planarization layer, lead-out traces and a packaging layer sequentially stacked on the substrate. The packaging layer includes a first inorganic layer disposed on the lead-out traces.

[0008] The display area includes the substrate, the planarization layer, and an anode located on the side of the planarization layer away from the substrate. The lead-out trace extends from one side of the anode into the frame area, and the lead-out trace is connected to the signal trace.

[0009] The display panel further includes a barrier layer located between the lead-out trace and the first inorganic layer, wherein the orthographic projection of the barrier layer on the substrate covers the orthographic projection of the lead-out trace on the substrate.

[0010] In the display panel provided in this application embodiment, the display panel includes a barrier portion disposed between the planarization layer and the encapsulation layer, the barrier portion being located on the side of the lead-out trace away from the display area;

[0011] Within the frame area, the barrier layer is in direct contact with the side of the retaining wall closest to the lead-out cable.

[0012] In the display panel provided in this application embodiment, the barrier portion includes a first barrier and a second barrier that are spaced apart, with the first barrier located on the side of the second barrier closer to the display area;

[0013] The height of the first retaining wall is greater than the thickness of the lead-out wire. The lead-out wire extends from one side of the anode to the first retaining wall, and the blocking layer is in direct contact with the side of the first retaining wall closest to the lead-out wire.

[0014] In the display panel provided in this application embodiment, the display area includes a pixel definition layer, a light-emitting layer, a common layer and a cathode that are sequentially stacked on the anode, and the first inorganic layer is located on the side of the cathode away from the common layer;

[0015] The blocking layer includes a light extraction layer located between the cathode and the first inorganic layer, and the orthogonal projection of the light extraction layer on the substrate covers the orthogonal projection of the light-emitting layer on the substrate.

[0016] In the display panel provided in this application embodiment, the light extraction layer extends from the display area to the first barrier wall, and the light extraction layer is in direct contact with the side of the first barrier wall near the lead-out trace;

[0017] The orthographic projection of the light extraction layer on the substrate covers the orthographic projection of the lead-out trace on the substrate.

[0018] In the display panel provided in this application embodiment, the lead-out trace includes an overlapping portion and an exposed portion disposed on the side of the overlapping portion away from the display area;

[0019] The light extraction layer extends from the display area toward the lead-out trace and directly contacts the overlapping portion. The orthogonal projection of the light extraction layer on the substrate covers the orthogonal projection of the overlapping portion on the substrate.

[0020] The blocking layer includes a blocking sub-layer that extends from one side of the light extraction layer to the first barrier, and the orthographic projection of the blocking sub-layer on the substrate covers a portion of the orthographic projection of the exposed portion on the substrate.

[0021] In the display panel provided in the embodiments of this application, the blocking layer includes a blocking sub-layer, which is located between the light extraction layer and the first inorganic layer. The blocking sub-layer extends from the display area to the first barrier, and the orthogonal projection of the blocking sub-layer on the substrate covers the orthogonal projection of the lead-out trace on the substrate.

[0022] In the display panel provided in the embodiments of this application, the material of the barrier sublayer is at least one of magnesium fluoride, aluminum fluoride, sodium fluoride, or lithium fluoride.

[0023] In the display panel provided in the embodiments of this application, the lead-out traces include a plurality of cutout holes, and the cutout holes penetrate the lead-out traces in a direction perpendicular to the substrate.

[0024] This application provides a display device, which includes any of the display panels described above.

[0025] The beneficial effects of this application are as follows: By providing a barrier layer between the lead-out trace and the first inorganic layer, the orthographic projection of the barrier layer on the substrate covers the orthographic projection of the lead-out trace on the substrate, thereby avoiding the bombardment damage to the lead-out trace by high-energy plasma when the first inorganic layer is fabricated using plasma-enhanced chemical vapor deposition in the prior art, and thus avoiding the phenomenon of uneven film thickness of the first inorganic layer. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a schematic diagram of the structure of an existing display panel;

[0028] Figure 2 This is a first cross-sectional schematic diagram of the display panel provided in an embodiment of this application;

[0029] Figure 3 This is a second cross-sectional schematic diagram of the display panel provided in an embodiment of this application;

[0030] Figure 4 This is a third cross-sectional schematic diagram of the display panel provided in an embodiment of this application;

[0031] Figure 5 This is a fourth cross-sectional schematic diagram of the display panel provided in the embodiments of this application;

[0032] Figure 6 This is a top view of the exposed portion provided in an embodiment of this application. Detailed Implementation

[0033] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In addition, it should be understood that the specific embodiments described herein are only for illustration and explanation of this application and are not intended to limit this application. In this application, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device.

[0034] In the description of this application, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features.

[0035] This application provides a display panel and a display device. These will be described in detail below. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments.

[0036] Please see Figures 2-6 This application provides a display panel and a display device. The display panel 2 includes a display area 1000 and a border area 2000 adjacent to the display area 1000. The border area 2000 includes a substrate 10 and signal traces 21, a planarization layer 30, lead traces 42, and an encapsulation layer 90 sequentially stacked on the substrate 10. The encapsulation layer 90 includes a first inorganic layer 91 disposed on the lead traces 42. The display area 1000 includes the substrate 10, the planarization layer 30, and an anode 41 located on the side of the planarization layer 30 away from the substrate 10. The lead traces 42 extend from one side of the anode 41 into the border area 2000 and are connected to the signal traces 21. The display panel 2 also includes a barrier layer 80 located between the lead traces 42 and the first inorganic layer 91. The orthographic projection of the barrier layer 80 on the substrate 10 covers the orthographic projection of the lead traces 42 on the substrate 10.

[0037] It should be noted that in existing technologies, plasma-enhanced chemical vapor deposition (PECVD) is typically used to fabricate the inorganic layer in the encapsulation layer. In actual fabrication, a mask is attached to the substrate to shield certain functional areas and avoid damaging the traces in those areas. The bezel area of ​​an existing display panel includes a substrate and signal traces, a planarization layer, and lead-out traces sequentially disposed on the substrate. The portion of the lead-out traces exposed outside the mask is bombarded by plasma. Metal ions in the lead-out traces are ejected by the plasma and adhere to the edge of the mask. The ejected metal ions alter the magnetic field, thereby affecting the distribution of the plasma gas. This results in uneven film thickness at the edge of the mask, affecting the inorganic layer's ability to block water and oxygen.

[0038] It is understood that, in this embodiment of the application, a barrier layer is provided between the lead-out trace and the first inorganic layer. The orthographic projection of the barrier layer on the substrate covers the orthographic projection of the lead-out trace on the substrate. This avoids the situation in the prior art where, when the first inorganic layer is fabricated using plasma-enhanced chemical vapor deposition, metal ions in the lead-out trace are easily bombarded by plasma and adhere to the edge of the photomask. The metal ions will change the magnetic field and affect the distribution of plasma gas, resulting in uneven film thickness at the edge of the photomask. This makes the film thickness of the first inorganic layer uniform, thereby improving the ability of the encapsulation layer to block water and oxygen.

[0039] The technical solution of this application will now be described in conjunction with specific embodiments.

[0040] Example 1

[0041] Please see Figure 2 This is a first cross-sectional schematic diagram of the display panel provided in the embodiments of this application.

[0042] This embodiment provides a display panel 2, which includes a display area 1000 and a border area 2000 adjacent to the display area 1000. It is understood that the display panel 2 can be a liquid crystal display panel or an active light-emitting display panel, such as an organic light-emitting diode (OLED) display panel, an active matrix organic light-emitting diode (AMOLED) display panel, a passive matrix organic light-emitting diode (AMOLED) display panel, and a quantum dot organic light-emitting diode (QLED) display panel. This embodiment uses an organic light-emitting diode display panel as an example to describe the technical solution of this application.

[0043] In this embodiment, the border area 2000 includes a substrate 10, and signal traces 21, a planarization layer 30, lead traces 42 and an encapsulation layer 90 sequentially stacked on the substrate 10. The encapsulation layer 90 includes a first inorganic layer 91 disposed on the lead traces 42. The display area 1000 includes the substrate 10, the planarization layer 30 and an anode 41 located on the side of the planarization layer 30 away from the substrate 10.

[0044] In this embodiment, the substrate 10 includes a substrate 11, a barrier layer 12, and an array substrate (not marked in the figure) stacked together. The substrate 11 can be a rigid substrate 11 or a flexible substrate 11. When the substrate 11 is a rigid substrate, the material can be metal or glass. When the substrate 11 is a flexible substrate, the material can include at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, polyurethane-based resin, cellulose resin, siloxane resin, polyimide-based resin, and polyamide-based resin. Preferably, the substrate 11 is a flexible substrate, and the material of the substrate 11 is polyimide. The material of the barrier layer 12 includes, but is not limited to, materials with water absorption properties such as silicon nitride (SiNX) and silicon oxide (SiOX). The array substrate can be a thin film transistor (TFT) array substrate. The TFT array substrate can be a top gate structure or a bottom gate structure. This embodiment does not impose specific limitations on this.

[0045] Furthermore, the display area 1000 also includes a pixel definition layer 50, a light-emitting layer 60, a common layer (not shown in the figure), and a cathode 70, which are sequentially stacked on the anode 41. The common layer includes one or more layers of a hole injection layer, a hole transport layer, an electron transport layer, or an electron injection layer. The material of the anode 41 includes, but is not limited to, indium tin oxide (ITO). The signal trace 21 can be a VSS trace or a VDD trace. The lead-out trace 42 extends from one side of the anode 41 into the frame area 2000. The planarization layer 30 includes a first via 31, and the lead-out trace 42 is connected to the signal trace 21 through the first via 31. In the display panel 2, the VDD trace is connected to the anode terminal of the display panel 2 for transmitting anodic voltage; the VSS trace is connected to the cathode terminal of the display panel 2 for transmitting cathodic voltage. This embodiment uses a VSS trace as an example for illustration.

[0046] In this embodiment, the display panel 2 includes a barrier portion 100 disposed between the planarization layer 30 and the encapsulation layer 90. The barrier portion 100 is located on the side of the lead-out trace 42 away from the display area 1000. It can be understood that in this embodiment, the barrier portion 100, the barrier layer 80, and the encapsulation layer 90 are used to effectively encapsulate the OLED device in the display area 1000 and the trace structure in the non-display area 1000. The main structure of the OLED device includes a stacked anode 41, a cathode 70, and a light-emitting layer 60 located between the anode 41 and the cathode 70. The anode 41 and the light-emitting layer 60 of each OLED device are spaced apart by a pixel definition layer 50. The cathode 70 of each OLED device is an integral structure, or the cathode 70 of several OLED devices is connected into an integral structure.

[0047] The barrier portion 100 is made of organic material, such as polyimide; the encapsulation layer 90 can be a single-layer structure or a multilayer structure. In this embodiment, the encapsulation layer 90 is a multilayer structure formed by alternating inorganic and organic material layers to illustrate the technical solution of this application. Specifically, in this embodiment, the encapsulation layer 90 includes a first inorganic layer 91, an organic layer 92, and a second inorganic layer 93 sequentially stacked on the cathode 70. The first inorganic layer 91 and the second inorganic layer both cover the barrier portion 100, and the organic layer 92 is located on the side of the barrier portion 100 closer to the display area 1000.

[0048] Further, in this embodiment, within the border area 2000, the blocking layer 80 directly contacts the side of the barrier portion 100 near the lead-out trace 42; specifically, the barrier portion 100 includes a first barrier 101 and a second barrier 102 spaced apart, the first barrier 101 being located on the side of the second barrier 102 near the display area 1000, wherein the height of the first barrier 101 is greater than the thickness of the lead-out trace 42, the lead-out trace 42 extending from one side of the anode 41 to the first barrier 101, the blocking layer 80 directly contacts the side of the first barrier 101 near the lead-out trace 42, and the orthographic projection of the blocking layer 80 on the substrate 10 covers the orthographic projection of the lead-out trace 42 on the substrate 10.

[0049] It is understood that in this embodiment, by setting the height of the first baffle 101 to be greater than the thickness of the lead-out trace 42, and the lead-out trace 42 extending from one side of the anode 41 to the first baffle 101, the area of ​​the lead-out trace 42 is reduced compared to the existing display panel 2, thereby reducing the total amount of material bombarded by plasma, and thus weakening the influence of the existing plasma-enhanced chemical vapor deposition method on the thickness of the first inorganic layer 91. At the same time, the barrier layer 80 is in direct contact with the side of the first baffle 101 near the lead-out trace 42, and the orthographic projection of the barrier layer 80 on the substrate 10 covers the orthographic projection of the lead-out trace 42 on the substrate 10, thereby avoiding the direct contact between the first inorganic layer 91 and the lead-out trace 42 in the prior art. The first inorganic layer 91 is usually produced by plasma-enhanced chemical vapor deposition. In Vapor Deposition (PECVD), the portion of the lead-out trace 42 exposed outside the photomask is subjected to high-energy plasma bombardment. Indium and tin ions in the lead-out trace 42 are easily ejected and adhere to the edge of the photomask. The metal ions change the magnetic field and affect the distribution of the plasma gas, resulting in uneven film thickness at the edge of the photomask.

[0050] Furthermore, in this embodiment, the blocking layer 80 includes a light extraction layer 81, which is located between the cathode 70 and the first inorganic layer 91. Within the display area 1000, the orthogonal projection of the light extraction layer 81 on the substrate 10 covers the orthogonal projection of the light-emitting layer 60 on the substrate 10. Further, the orthogonal projection of the light extraction layer 81 on the substrate 10 covers the orthogonal projection of the cathode 70 on the substrate 10, thereby avoiding the high-energy plasma bombardment damage to the cathode 70 when the first inorganic layer 91 is fabricated using plasma-enhanced chemical vapor deposition in the prior art, and thus avoiding the phenomenon of uneven film thickness of the first inorganic layer 91.

[0051] Specifically, in this embodiment, the light extraction layer 81 extends from the display area 1000 to the first barrier wall 101, and the light extraction layer 81 directly contacts the side of the first barrier wall 101 near the lead-out trace 42; wherein, the orthographic projection of the light extraction layer 81 on the substrate 10 covers the orthographic projection of the lead-out trace 42 on the substrate 10; it can be understood that, by setting the orthographic projection of the light extraction layer 81 on the substrate 10 to cover the orthographic projection of the lead-out trace 42 on the substrate 10, this embodiment avoids the bombardment damage to the lead-out trace 42 by high-energy plasma when the first inorganic layer 91 is fabricated using plasma-enhanced chemical vapor deposition in the prior art, thereby avoiding the phenomenon of uneven film thickness of the first inorganic layer 91; at the same time, within the display area 1000, the orthographic projection of the light extraction layer 81 on the substrate 10 covers the orthographic projection of the light-emitting layer 60 on the substrate 10, and the light extraction layer 81 can adjust the optical interference distance, suppress external light reflection, thereby improving the light extraction efficiency.

[0052] Example 2

[0053] Please see Figure 3 This is a second cross-sectional schematic diagram of the display panel provided in the embodiments of this application.

[0054] In this embodiment, the structure of the display panel is similar to / the same as the first structure of the display panel provided in the above embodiments. Please refer to the description of the display panel in the above embodiments for details, which will not be repeated here. The only difference between the two is:

[0055] In this embodiment, the lead-out trace 42 includes an overlapping portion 421 and an exposed portion 422 disposed on the side of the overlapping portion 421 away from the display area; the light extraction layer 81 extends from the display area 1000 toward the lead-out trace 42 and directly contacts the lead-out trace 42, and the orthographic projection of the light extraction layer 81 on the substrate 10 covers the orthographic projection of the overlapping portion 421 on the substrate 10; the blocking layer 80 includes a blocking sub-layer 82, which extends from one side of the light extraction layer 81 to the first barrier 101, and the orthographic projection of the blocking sub-layer 82 on the substrate 10 covers part of the orthographic projection of the exposed portion 422 on the substrate 10.

[0056] Further, in this embodiment, the border area 2000 includes a first border area 2100 and a second border area 2200, the first border area 2100 being located between the second border area 2200 and the display area 1000; the overlapping portion 421 is located within the first border area 2100, and the exposed portion 422 is located within the second border area 2200; specifically, the overlapping portion 421 extends from one side of the anode 41 into the first border area 2100, and the exposed portion 422 extends from one side of the overlapping portion 421 into the second border area 2200, the overlapping portion 421 and the exposed portion 422 being disposed on the same layer and connected to each other.

[0057] The light extraction layer 81 extends from the display area 1000 into the first frame area 2100. The light extraction layer 81 is in direct contact with the overlapping portion 421, and the orthographic projection of the light extraction layer 81 on the substrate 10 covers the orthographic projection of the overlapping portion 421 on the substrate 10. The blocking sub-layer 82 is disposed in the same layer as the light extraction layer 81. The blocking sub-layer 82 is in direct contact with the exposed portion 422, and the orthographic projection of the blocking sub-layer 82 on the substrate 10 covers the orthographic projection of the exposed portion 422 on the substrate 10. Specifically, the end of the blocking sub-layer 82 near the light extraction layer 81 is in direct contact with the light extraction layer 81, and the end of the blocking sub-layer 82 near the first barrier wall 101 is in direct contact with the first barrier wall 101.

[0058] Furthermore, the material of the barrier sublayer 82 is a metal halide, which includes, but is not limited to, at least one of magnesium fluoride (MgF2), aluminum fluoride (AlF3), sodium fluoride (NaF), or lithium fluoride (LiF); preferably, the material of the barrier sublayer 82 is lithium fluoride (LiF).

[0059] It is understood that in this embodiment, by setting the blocking sublayer 82 and the light extraction layer 81 on the same layer, the thickness of the display panel 2 is avoided by adding the blocking sublayer 82 between the lead-out trace 42 and the first inorganic layer 91. At the same time, by setting the side of the blocking sublayer 82 close to the light extraction layer 81 to contact the light extraction layer 81, and the side of the blocking sublayer 82 close to the first barrier wall 101 to contact the first barrier wall 101, the orthographic projection of the light extraction layer 81 on the substrate 10 covers the orthographic projection of the overlapping portion 421 on the substrate 10, and the orthographic projection of the blocking sublayer 82 on the substrate 10 covers the orthographic projection of the exposed portion 422 on the substrate 10, the high-energy plasma bombardment damage to the lead-out trace 42 is avoided when the first inorganic layer 91 is fabricated by plasma-enhanced chemical vapor deposition in the prior art, thereby avoiding the phenomenon of uneven film thickness of the first inorganic layer 91.

[0060] Example 3

[0061] Please see Figure 4 This is a third cross-sectional schematic diagram of the display panel provided in the embodiments of this application.

[0062] In this embodiment, the structure of the display panel is similar to / the same as the second structure of the display panel provided in the above embodiment. Please refer to the description of the display panel in the above embodiment for details, which will not be repeated here. The only difference between the two is:

[0063] In this embodiment, the blocking layer 80 includes a blocking sub-layer 82, which is located between the light extraction layer 81 and the first inorganic layer 91. The blocking sub-layer 82 extends from the display area 1000 to the first barrier 101, and the orthographic projection of the blocking sub-layer 82 on the substrate 10 covers the orthographic projection of the lead-out trace 42 on the substrate 10.

[0064] Specifically, the light extraction layer 81 extends from the display area 1000 toward the lead-out trace 42 and directly contacts the lead-out trace 42. The orthographic projection of the light extraction layer 81 on the substrate 10 at least covers part of the orthographic projection of the lead-out trace 42 on the substrate 10. The end of the blocking sub-layer 82 near the first barrier 101 is in direct contact with the first barrier 101. The orthographic projection of the blocking sub-layer 82 on the substrate 10 covers the orthographic projection of the light extraction layer 81 on the substrate 10.

[0065] It is understood that, in this embodiment, by setting the barrier sub-layer 82 to extend from the display area 1000 to the first barrier wall 101, and the orthographic projection of the barrier sub-layer 82 on the substrate 10 covering the orthographic projection of the lead-out trace 42 on the substrate 10, the high-energy plasma bombardment damage to the lead-out trace 42 during the fabrication of the first inorganic layer 91 using plasma-enhanced chemical vapor deposition in the prior art is avoided, thereby preventing the phenomenon of uneven film thickness of the first inorganic layer 91. At the same time, by setting the barrier sub-layer 82 between the light extraction layer 81 and the first inorganic layer 91, and the orthographic projection of the barrier sub-layer 82 on the substrate 10 covering the orthographic projection of the light extraction layer 81 on the substrate 10, the barrier sub-layer 82 can protect the light extraction layer 81 and the light-emitting layer 60, preventing damage to the light extraction layer 81 and the light-emitting layer 60 during the formation of the encapsulation layer 90.

[0066] Example 4

[0067] Please see Figure 5 and Figure 6 ;in, Figure 5 This is a fourth cross-sectional schematic diagram of the display panel provided in the embodiments of this application. Figure 6 This is a top view of the exposed portion provided in an embodiment of this application.

[0068] In this embodiment, the structure of the display panel is similar to / the same as the third structure of the display panel provided in the above embodiments. Please refer to the description of the display panel in the above embodiments for details, which will not be repeated here. The only difference between the two is:

[0069] In this embodiment, the lead-out trace 42 includes a plurality of cutout holes 422A, which penetrate the lead-out trace 42 in a direction perpendicular to the substrate 10; wherein the shape of the cutout hole 422A includes, but is not limited to, a rectangle, a circle or a triangle.

[0070] Specifically, in this embodiment, the border area 2000 includes a first border area 2100 and a second border area 2200. The first border area 2100 is located between the second border area 2200 and the display area 1000. The lead-out trace 42 includes an overlapping portion 421 and an exposed portion 422. The overlapping portion 421 is located within the first border area 2100, and the exposed portion 422 is located within the second border area 2200. The overlapping portion 421 extends from one side of the anode 41 into the first border area 2100, and the exposed portion 422 extends from one side of the overlapping portion 421 into the second border area 2200. The overlapping portion 421 and the exposed portion 422 are disposed on the same layer and connected to each other.

[0071] The light extraction layer 81 extends from the display area 1000 into the first frame area 2100. The light extraction layer 81 is in direct contact with the overlapping portion 421. The orthographic projection of the light extraction layer 81 on the substrate 10 covers the orthographic projection of the overlapping portion 421 on the substrate 10. The blocking sub-layer 82 is disposed in the same layer as the light extraction layer 81. The blocking sub-layer 82 is in direct contact with the exposed portion 422. The orthographic projection of the blocking sub-layer 82 on the substrate 10 covers the orthographic projection of the exposed portion 422 on the substrate 10.

[0072] The exposed portion 422 includes a plurality of hollow holes 422A. In a direction perpendicular to the substrate 10, the hollow holes 422A penetrate the exposed portion 422, and the blocking sublayer 82 fills the plurality of hollow holes 422A.

[0073] It is understood that in this embodiment, by setting the exposed portion 422 to include a plurality of hollow holes 422A, the hollow holes 422A penetrate the exposed portion 422 in a direction perpendicular to the substrate 10, and the blocking sub-layer 82 fills the plurality of hollow holes 422A. Compared with the existing display panel 2, the area of ​​the lead-out trace 42 is reduced, thereby reducing the total amount of material bombarded by plasma, and thus weakening the influence of the existing plasma-enhanced chemical vapor deposition method on the thickness of the first inorganic layer 91.

[0074] It should be noted that the exposed portion 422 includes a plurality of hollow holes 422A. In the direction perpendicular to the substrate 10, the hollow holes 422A penetrate the exposed portion 422. The blocking sublayer 82 filling the plurality of hollow holes 422A is only for illustrative purposes. In other embodiments, such as the above-described Embodiment 1, Embodiment 2 or Embodiment 3, the lead-out trace 42 may be provided with a plurality of hollow holes 422A. This embodiment does not impose specific limitations on this.

[0075] This embodiment provides a display device, which includes the display panel described in any of the above embodiments.

[0076] It is understood that the display panel has been described in detail in the above embodiments, and will not be repeated here.

[0077] In specific applications, the display device can be the display screen of devices such as smartphones, tablets, laptops, smart bracelets, smartwatches, smart glasses, smart helmets, desktop computers, smart TVs, or digital cameras, and can even be applied to electronic devices with flexible displays.

[0078] In summary, this application provides a display panel and a display device. The display panel includes a display area and a non-display area adjacent to the display area. The frame area includes a substrate and signal traces, a planarization layer, lead traces, and an encapsulation layer sequentially stacked on the substrate. The encapsulation layer includes a first inorganic layer disposed on the lead traces. The display area includes the substrate, the planarization layer, and an anode located on the side of the planarization layer away from the substrate. The lead traces extend from one side of the anode into the frame area, and the lead traces are connected to the signal traces. A barrier layer is provided between the lead-out trace and the first inorganic layer. The orthographic projection of the barrier layer on the substrate covers the orthographic projection of the lead-out trace on the substrate. This avoids the situation in the prior art where metal ions in the lead-out trace are easily bombarded by plasma and adhere to the edge of the mask when the first inorganic layer is fabricated using plasma-enhanced chemical vapor deposition. The metal ions will change the magnetic field and affect the distribution of plasma gas, resulting in uneven film thickness at the edge of the mask. This makes the film thickness of the first inorganic layer uniform, thereby improving the ability of the encapsulation layer to block water and oxygen.

[0079] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0080] The above provides a detailed description of a display panel and display device provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A display panel, characterized in that, It includes a display area and a border area adjacent to the display area; The border area includes a substrate, and signal traces, a planarization layer, lead-out traces and a packaging layer sequentially stacked on the substrate. The packaging layer includes a first inorganic layer disposed on the lead-out traces. The display area includes the substrate, the planarization layer, and an anode located on the side of the planarization layer away from the substrate. The lead-out trace extends from one side of the anode into the frame area, and the lead-out trace is connected to the signal trace. The display panel further includes a barrier layer located between the lead-out trace and the first inorganic layer, wherein the orthographic projection of the barrier layer on the substrate covers the orthographic projection of the lead-out trace on the substrate.

2. The display panel according to claim 1, characterized in that, The display panel includes a barrier portion disposed between the planarization layer and the encapsulation layer, the barrier portion being located on the side of the lead-out trace away from the display area; Within the frame area, the barrier layer is in direct contact with the side of the retaining wall closest to the lead-out cable.

3. The display panel according to claim 2, characterized in that, The barrier section includes a first barrier and a second barrier that are spaced apart, with the first barrier located on the side of the second barrier closer to the display area; The height of the first retaining wall is greater than the thickness of the lead-out wire. The lead-out wire extends from one side of the anode to the first retaining wall, and the blocking layer is in direct contact with the side of the first retaining wall closest to the lead-out wire.

4. The display panel according to claim 3, characterized in that, The display area includes a pixel definition layer, a light-emitting layer, a common layer and a cathode, which are sequentially stacked on the anode, and the first inorganic layer is located on the side of the cathode away from the common layer; The blocking layer includes a light extraction layer located between the cathode and the first inorganic layer, and the orthogonal projection of the light extraction layer on the substrate covers the orthogonal projection of the light-emitting layer on the substrate.

5. The display panel according to claim 4, characterized in that, The light extraction layer extends from the display area to the first barrier wall, and the light extraction layer is in direct contact with the side of the first barrier wall near the lead-out trace. The orthographic projection of the light extraction layer on the substrate covers the orthographic projection of the lead-out trace on the substrate.

6. The display panel according to claim 4, characterized in that, The lead-out trace includes an overlapping portion and an exposed portion disposed on the side of the overlapping portion away from the display area; The light extraction layer extends from the display area toward the lead-out trace and directly contacts the overlapping portion. The orthogonal projection of the light extraction layer on the substrate covers the orthogonal projection of the overlapping portion on the substrate. The blocking layer includes a blocking sub-layer that extends from one side of the light extraction layer to the first barrier, and the orthographic projection of the blocking sub-layer on the substrate covers a portion of the orthographic projection of the exposed portion on the substrate.

7. The display panel according to claim 4, characterized in that, The blocking layer includes a blocking sub-layer, which is located between the light extraction layer and the first inorganic layer. The blocking sub-layer extends from the display area to the first barrier, and the orthogonal projection of the blocking sub-layer on the substrate covers the orthogonal projection of the lead-out trace on the substrate.

8. The display panel according to any one of claims 6-7, characterized in that, The material of the barrier sublayer is at least one of magnesium fluoride, aluminum fluoride, sodium fluoride, or lithium fluoride.

9. The display panel according to any one of claims 1-7, characterized in that, The lead-out trace includes multiple cutout holes, which penetrate the lead-out trace in a direction perpendicular to the substrate.

10. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 9.

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