Computing circuitry

Abstract

The application relates to a computing circuit. The computing circuit comprises a plurality of computing units arranged in an array, each computing unit comprising a multiplication computing circuit, a pre-charging circuit and a computing result output circuit, the multiplication computing circuit comprising a first ferroelectric transistor and a second ferroelectric transistor connected to each other, the pre-charging circuit and the computing result output circuit being electrically connected to a computing output node between the first ferroelectric transistor and the second ferroelectric transistor; the first ferroelectric transistor and the second ferroelectric transistor are used to enter a target resistance state under the driving of a write voltage, the pre-charging circuit is used to adjust the computing output node to a target voltage after the first ferroelectric transistor and the second ferroelectric transistor enter the target resistance state, and the first ferroelectric transistor and the second ferroelectric transistor are used to receive a signal input voltage after the computing output node is adjusted to the target voltage; the computing result output circuit is used to output the voltage of the computing output node after receiving the signal input voltage. The computing circuit provided by the application can improve the integration level and reduce the power consumption.

Description

Technical Field

[0001] This application relates to the field of circuit technology, and in particular to a computing circuit. Background Technology

[0002] With the rapid development of deep neural network technology, the computational and storage requirements for deep neural networks (DNNs) are becoming increasingly stringent, while the power consumption of devices also needs to be controlled to improve DNN inference efficiency.

[0003] In existing technologies, when improving the inference efficiency of DNNs, the TNN array units are usually designed based on ternary neural networks (TNNs). By using lower precision weights and excitations, the inference accuracy and inference speed of DNNs are balanced. This is done at the cost of slightly reducing inference accuracy, thereby improving the inference speed of DNNs and thus improving the inference efficiency of DNNs.

[0004] However, existing TNN array units use a large number of components and have a large area, resulting in low integration and high power consumption. Summary of the Invention

[0005] Therefore, it is necessary to provide a computing circuit with high integration and low power consumption to address the aforementioned technical problems.

[0006] This application provides a computing circuit comprising multiple computing units arranged in an array. Each computing unit includes a multiplication computing circuit, a pre-charge circuit, and a calculation result output circuit. The multiplication computing circuit includes a first ferroelectric transistor and a second ferroelectric transistor interconnected. The pre-charge circuit and the calculation result output circuit are both electrically connected to a computing output node located between the first ferroelectric transistor and the second ferroelectric transistor. The first ferroelectric transistor and the second ferroelectric transistor are configured to enter a target resistive state under the drive of a write voltage to characterize the weight value of the neural network unit corresponding to the computing unit. The pre-charge circuit is configured to adjust the calculation output node to a target voltage after the first ferroelectric transistor and the second ferroelectric transistor enter the target resistive state. The first ferroelectric transistor and the second ferroelectric transistor are configured to receive a signal input voltage after the calculation output node is adjusted to the target voltage. The calculation result output circuit is configured to output the voltage of the calculation output node after receiving the signal input voltage to obtain the calculation result of the multiplication computing circuit based on the signal input voltage and the weight value.

[0007] In one embodiment, the first terminal of the first ferroelectric transistor and the first terminal of the second ferroelectric transistor are connected, the second terminal of the first ferroelectric transistor is a first signal input node, the second terminal of the second ferroelectric transistor is a second signal input node, the gate of the first ferroelectric transistor is a first write voltage driving node, and the gate of the second ferroelectric transistor is a second write voltage driving node; the first signal input node and the second signal input node are used to input the signal input voltage; the first write voltage driving node and the second write voltage driving node are used to input the write voltage.

[0008] In one embodiment, the computation output node is located between the first pole of the first ferroelectric transistor and the first pole of the second ferroelectric transistor.

[0009] In one embodiment, the pre-charge circuit includes a first transistor, the source of which is connected to a first voltage source for outputting the target voltage, the drain of which is connected to the compute output node, and the gate of which is used to receive a pulse signal to adjust the compute output node to the target voltage based on the pulse signal.

[0010] In one embodiment, the computing circuit further includes a word line WL; the gate of the first transistor in the precharge circuit of each computing unit is connected to the WL; the WL is used to output the pulse signal to the gate of the first transistor in the precharge circuit of each computing unit.

[0011] In one embodiment, the computing circuit further includes a bit line RBL, and the computing result output circuit in each computing unit is connected to the RBL to output the computing result to the RBL.

[0012] In one embodiment, the calculation result output circuit includes a first capacitor for coupling the voltage of the calculation output node to the RBL.

[0013] In one embodiment, a second transistor is provided on the RBL, which is used to discharge and float the RBL before the multiplication calculation circuit performs calculations based on the signal input voltage and the weight value.

[0014] In one embodiment, the calculation result output circuit includes a third transistor and a fourth transistor, the bit line RBL includes a first RBL and a second RBL, the gates of the third transistor and the fourth transistor are both connected to the calculation output node, the source of the third transistor is connected to a second voltage source, the source of the fourth transistor is connected to the second RBL, the drain of the third transistor is connected to the first RBL, and the drain of the fourth transistor is grounded; the third transistor and the fourth transistor are used to perform charging or discharging operations on the first RBL and the second RBL respectively under the control of the voltage of the calculation output node.

[0015] In one embodiment, the first RBL and the second RBL are connected by a calculation result processing circuit, which includes a first switch, a second switch, a third switch, a fourth switch connection, a second capacitor, and a third capacitor. The calculation result processing circuit is used to accumulate the voltages of the first RBL and the second RBL to obtain the calculation results of the plurality of calculation units.

[0016] The aforementioned computing circuit includes multiple computing units arranged in an array. Each computing unit includes a multiplication computing circuit, a pre-charge circuit, and a calculation result output circuit. The multiplication computing circuit includes a first ferroelectric transistor and a second ferroelectric transistor connected to each other. The pre-charge circuit and the calculation result output circuit are both electrically connected to a computing output node located between the first ferroelectric transistor and the second ferroelectric transistor. The first ferroelectric transistor and the second ferroelectric transistor are used to enter a target resistive state under the drive of a write voltage to characterize the weight value of the neural network unit corresponding to the computing unit. The pre-charge circuit is used to adjust the calculation output node to a target voltage after the first ferroelectric transistor and the second ferroelectric transistor enter the target resistive state. The first ferroelectric transistor and the second ferroelectric transistor are used to receive a signal input voltage after the calculation output node is adjusted to the target voltage. The calculation result output circuit is used to output the voltage of the calculation output node after receiving the signal input voltage to obtain the calculation result of the multiplication computing circuit based on the signal input voltage and the weight value. The computing circuit provided in this application can be used for the calculation of ternary neural networks. Compared with the computing circuits in the prior art, the computing circuit of this application uses fewer components and has a smaller area. Therefore, by using the computing circuit provided in this application, the integration level can be effectively improved and the power consumption can be reduced. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the computing circuit in one embodiment;

[0018] Figure 2 This is a schematic diagram of the IV characteristics of the first ferroelectric transistor and the second ferroelectric transistor in one embodiment;

[0019] Figure 3 This is a timing diagram of the process of writing weight values ​​to a computing unit in one embodiment;

[0020] Figure 4 This is a schematic diagram of the computing circuit in another embodiment;

[0021] Figure 5 This is a timing diagram for the case where the computation unit writes a weight value of 0 in one embodiment;

[0022] Figure 6 This is a timing diagram for a computing unit writing a weight value of 1 in one embodiment;

[0023] Figure 7 The timing diagram for the computation unit writing a weight value of -1 in one embodiment is shown. Detailed Implementation

[0024] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application are described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0025] Furthermore, where the terms "first" and "second" appear, these terms are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, where the term "multiple" appears, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0026] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0027] In this application, unless otherwise expressly specified and limited, the use of descriptions such as "above" or "below" the second feature indicates that the first and second features are in direct contact or indirect contact via an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. Similarly, "below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0028] It should be noted that if an element is referred to as being "fixed to" or "set on" another element, it can be directly on the other element or there may be an intervening element. If an element is considered to be "connected to" another element, it can be directly connected to the other element or there may be an intervening element. If so, the terms "vertical," "horizontal," "upper," "lower," "left," "right," and similar expressions used in this application are for illustrative purposes only and do not represent the only possible implementation.

[0029] With the rapid development of deep neural network technology, the computational and storage requirements for deep neural networks (DNNs) are becoming increasingly stringent, while the power consumption of devices also needs to be controlled to improve DNN inference efficiency.

[0030] In existing technologies, in some DNN computing scenarios with high requirements for power consumption and inference efficiency, lower precision is usually used to represent the weights and excitations of the DNN in order to reduce power consumption in computing, memory and data transmission. However, this also reduces the accuracy of inference. Compared with binary neural networks, ternary neural networks (TNNs) have significantly improved accuracy while maintaining a high level of efficiency, achieving a good balance between efficiency and accuracy.

[0031] However, existing TNN array units use a large number of components and have a large area, resulting in low integration and high power consumption.

[0032] In view of this, this application provides a computing circuit with high integration and low power consumption.

[0033] In one embodiment, such as Figure 1As shown, a computing circuit is provided, comprising a plurality of computing units 100 arranged in an array. Each computing unit 100 includes a multiplication computing circuit 101, a pre-charging circuit 102, and a calculation result output circuit 103. The multiplication computing circuit 101 includes a first ferroelectric transistor 201 and a second ferroelectric transistor 202 interconnected. The pre-charging circuit 102 and the calculation result output circuit 103 are both electrically connected to a calculation output node located between the first ferroelectric transistor 201 and the second ferroelectric transistor 202. Figure 1 Connect point A in the diagram (203).

[0034] The first ferroelectric transistor 201 and the second ferroelectric transistor 202 are used to enter the target resistive state under the drive of the write voltage, so as to characterize the weight value of the neural network unit corresponding to the computing unit 100.

[0035] In an optional embodiment of this application, such as Figure 1 As shown, the first terminal of the first ferroelectric transistor 201 and the first terminal of the second ferroelectric transistor 202 are connected, and the second terminal of the first ferroelectric transistor 201 is the first signal input node. Figure 1 Vin1), the second electrode of the second ferroelectric transistor 202 is the second signal input node (in the second polarity). Figure 1 Vin2 in the first ferroelectric transistor 201 has its gate as the first write voltage drive node. Figure 1 In the second ferroelectric transistor 202, the gate of the second ferroelectric transistor 202 is the second write voltage drive node (Vwrite1). Figure 1 Vwrite2 in (the text is incomplete and cannot be translated).

[0036] The first signal input node and the second signal input node are used to input the signal input voltage.

[0037] The first write voltage driving node and the second write voltage driving node are used to input the write voltage.

[0038] In one possible implementation, such as Figure 2 As shown, Figure 2 The diagrams show the IV characteristics of the first ferroelectric transistor and the second ferroelectric transistor. Figure 2 In the figure, -Vc and Vc are the threshold voltages of the first ferroelectric transistor and the second ferroelectric transistor in the positive polarization state and the negative polarization state, respectively. They are also the coercivity voltages of the ferroelectric transistor. For the first ferroelectric transistor and the second ferroelectric transistor, when the applied positive gate-source voltage is greater than Vc, the first ferroelectric transistor and the second ferroelectric transistor will enter the positive polarization state, which is the low resistance state. When the applied negative gate-source voltage is greater than Vc, the first ferroelectric transistor and the second ferroelectric transistor will enter the negative polarization state, which is the high resistance state.

[0039] Optionally, assuming the write voltage is Vwrite, the value range of Vwrite is related to the value of Vc. Specifically, Vwrite > Vc > Vwrite / 2.

[0040] In one possible implementation, assuming a weight value of 1 needs to be written to the computational unit, that is, to make the weight value of the corresponding neural network unit of the computational unit 1, two stages are required. In the first stage, Vwrite is input to the first write voltage driving node, and the second write voltage driving node is grounded. Both the first signal input node and the second signal input node are input with 0. In this first stage, it is equivalent to inputting a positive gate-source voltage greater than Vc to the first ferroelectric transistor, and the first ferroelectric transistor will enter or remain in a low-resistance state. In the second stage, Vwrite is still input to the first write voltage driving node, and the second write voltage driving node... The point is still grounded. Vwrite is input at both the first signal input node and the second signal input node. At this time, it is equivalent to inputting a negative gate-source voltage greater than Vc to the second ferroelectric transistor. The second ferroelectric transistor will enter or remain in a high-resistivity state. The high-resistivity state and the low-resistivity state are the target states mentioned above. The target state is used to characterize the weight value of the neural network unit corresponding to the computing unit 100. That is, the first ferroelectric transistor is in a low-resistivity state and the second ferroelectric transistor is in a high-resistivity state, which can be used to characterize the weight value of the neural network unit corresponding to the computing unit as 1. The above process is the process of writing the weight value 1 to the computing unit.

[0041] In another possible implementation, assuming a weight value of -1 needs to be written to the computation unit, that is, to make the weight value of the corresponding neural network unit of the computation unit -1, two stages are required. In the first stage, Vwrite is input to the second write voltage driving node, and the first write voltage driving node is grounded. Both the first and second signal input nodes are input with 0. In this first stage, it is equivalent to inputting a positive gate-source voltage greater than Vc to the second ferroelectric transistor, and the second ferroelectric transistor will enter or remain in a low-resistance state. In the second stage, Vwrite is still input to the second write voltage driving node, and the first write voltage driving node... The point is still grounded. Vwrite is input at both the first signal input node and the second signal input node. At this time, it is equivalent to inputting a negative gate-source voltage greater than Vc to the first ferroelectric transistor. The first ferroelectric transistor will enter or remain in a high-resistivity state. The high-resistivity state and the low-resistivity state are the target states mentioned above. The target state is used to characterize the weight value of the neural network unit corresponding to the computing unit 100. That is, the second ferroelectric transistor is in a low-resistivity state, and the first ferroelectric transistor is in a high-resistivity state, which can be used to characterize the weight value of the neural network unit corresponding to the computing unit as -1. The above process is the process of writing the weight value -1 to the computing unit.

[0042] In another possible implementation, assuming it's necessary to write a weight value of 0 to the computation unit, that is, to make the weight value of the corresponding neural network unit of the computation unit 0, then two stages are required. In the first stage, both the first write voltage driving node and the second write voltage driving node are grounded, and both the first signal input node and the second signal input node are input with 0. In this first stage, the resistive state of both the first ferroelectric transistor and the second ferroelectric transistor remains unchanged. In the second stage, both the first write voltage driving node and the second write voltage driving node are grounded, and both the first signal input node and the second signal input node are input with 0. When Vwrite is input to all input nodes, it is equivalent to inputting a negative gate-source voltage greater than Vc to both the first and second ferroelectric transistors. The first and second ferroelectric transistors will enter a high-resistivity state, which is the target state mentioned above. This target state represents the weight value of the neural network unit corresponding to the computing unit 100. In other words, the fact that both the first and second ferroelectric transistors are in a high-resistivity state can be used to represent that the weight value of the neural network unit corresponding to the computing unit is 0. The above process is the process of writing the weight value 0 to the computing unit.

[0043] As described above, this is the process of writing weight values ​​into the computing unit, such as... Figure 3The diagram shown is the timing diagram for this process. The specific operation of this process can be found in Table 1. In Table 1, Vin1 (non-write row) and Vin2 (non-write row) refer to Vin1 and Vin2 of other calculation units in the calculation circuit that do not perform the write weight value calculation.

[0044] Table 1

[0045]

[0046] In one possible implementation, the inputs of Vin1 (non-write row) and Vin2 (non-write row) can be kept at Vwrite / 2. This ensures that during the weight writing process, the gate-source voltages of the first and second ferroelectric transistors in the computing units corresponding to Vin1 (non-write row) and Vin2 (non-write row) will not exceed Vwrite / 2, thus ensuring that the polarization reversal of the first and second ferroelectric transistors in the computing units corresponding to Vin1 (non-write row) and Vin2 (non-write row) will not occur.

[0047] The pre-charge circuit 103 is used to adjust the calculation output node 203 to the target voltage after the first ferroelectric transistor 201 and the second ferroelectric transistor 202 enter the target resistive state.

[0048] In an optional embodiment of this application, such as Figure 1 As shown, the calculation output node 203 is located between the first terminal of the first ferroelectric transistor 201 and the first terminal of the second ferroelectric transistor 202. Figure 1 Point A in the calculation is the output node 203.

[0049] In an optional embodiment of this application, such as Figure 1 As shown, the pre-charge circuit 103 includes a first transistor 1011, the source of which is connected to a first voltage source ( Figure 1 The first voltage source is connected to the Vprecharge in the first transistor 1011, which is used to output the target voltage. The drain of the first transistor 1011 is connected to the calculation output node 203. The gate of the first transistor 1011 is used to receive a pulse signal to adjust the calculation output node 203 to the target voltage based on the pulse signal.

[0050] Optionally, the first transistor 1011 can be an NMOS transistor, and the voltage of the first voltage source is constant at V. DD / 2.

[0051] In an optional embodiment of this application, such as Figure 1 As shown, the computing circuit also includes word line WL104.

[0052] In each of the computing units 100, the gate of the first transistor 1011 in the pre-charge circuit 102 is connected to the WL104; the WL104 is used to output the pulse signal to the gate of the first transistor 1011 in the pre-charge circuit 102 of each computing unit 100.

[0053] Optional, such as Figure 5 , Figure 6 as well as Figure 7 As shown, Figure 5 The timing diagram shows the pre-charging process executed by the charging circuit and the input timing diagram after the pre-charging process, when the weight value of the computing unit is 0. Figure 6 This diagram shows the timing of the charging circuit performing a pre-charging process and inputting different input values ​​after the pre-charging process, given a weight value of 1 for the computing unit. Figure 7 When the weight value is written to the calculation unit as -1, the charging circuit executes the pre-charging process and the timing diagram of inputting different input values ​​after executing the pre-charging process. After the first ferroelectric transistor 201 and the second ferroelectric transistor 202 enter the target resistive state, that is, after the operation of writing the weight value to the calculation unit has been completed, it is necessary to perform a multiplication operation based on the calculation unit with the written weight value. Before performing the multiplication operation, it is also necessary to adjust the calculation output node 203 to the target voltage based on the pre-charging circuit 102.

[0054] In one possible implementation, when the weight value written to the computing unit is 0, a positive pulse with a large amplitude can be applied to WL104 so that the computing output node 203 is charged to V by the first voltage source. DD / 2, when the applied pulse ends, the voltage on WL104 will return to 0 and remain at 0, at which point the connection between the first voltage source and the calculation output node 203 will be cut off.

[0055] In another possible implementation, when the weight value written to the computing unit is 1, a positive pulse with a large amplitude is applied to WL104. At this time, under the combined action of the first signal input node and the first voltage source, the voltage of the computing output node is set to V. DD / 2.

[0056] In another possible implementation, when the weight value written to the computing unit is -1, a positive pulse with a large amplitude is applied to WL104. At this time, under the combined action of the second signal input node and the first voltage source, the voltage of the computing output node is set to V. DD / 2.

[0057] The first ferroelectric transistor 201 and the second ferroelectric transistor 203 are used to receive the signal input voltage after the calculation output node 203 is adjusted to the target voltage.

[0058] Optionally, the signal input voltage is used to characterize the input value.

[0059] In one possible implementation, if the voltage input to the first signal input node is V DD If the voltage input to the second signal input node is 0, then the input value can be determined to be 1.

[0060] In another possible implementation, if the voltage input to the first signal input node is V DD / 2, the voltage input to the second signal input node is V DD If we use / 2, then we can determine that the input value is 0.

[0061] In another possible implementation, if the voltage input to the first signal input node is 0, the voltage input to the second signal input node is V. DD Then the input value can be determined to be -1.

[0062] The calculation result output circuit 103 is used to output the voltage of the calculation output node 203 after receiving the signal input voltage, so as to obtain the calculation result of the multiplication calculation circuit 101 based on the signal input voltage and the weight value.

[0063] Optionally, the voltage of the calculation output node 203 can be used to characterize the calculation result of the multiplication calculation circuit 101 based on the signal input voltage and the weight value.

[0064] In one possible implementation, if the voltage of the calculated output node 203 is V DD Then the calculation result can be determined to be 1, if the voltage of the output node 203 is V. DD If the value is 0, the calculation result is 0. If the voltage of the calculation output node 203 is 0, the calculation result is -1. Specifically, as shown in Table 2, which displays the voltage of the calculation output node 203 under different weights and input values. It should be noted that during the multiplication calculation, all nodes except the first and second signal input nodes remain at 0V. When there is no input value, all nodes except the first and second signal input nodes also remain at 0V, while the first and second signal input nodes remain at V. DD / 2.

[0065] Table 2

[0066]

[0067]

[0068] In one embodiment, such as Figure 1 As shown, the calculation circuit also includes a bit line RBL105, and the calculation result output circuit 103 in each calculation unit 100 is connected to the RBL105 to output the calculation result to the RBL105.

[0069] In an optional embodiment of this application, a second transistor 501 is provided on the RBL105. The second transistor 501 is used to discharge and float the RBL105 before the multiplication calculation circuit 101 performs calculations based on the signal input voltage and the weight value.

[0070] In one possible implementation, the gate of the second transistor 501 is connected to a voltage source Vs. A positive pulse can be applied to the second transistor 501 based on Vs to ground the RBL105. This process is the discharge process. After the pulse ends, the RBL is in a floating state, and the voltage at Vs remains 0. This process is the floating process.

[0071] In an optional embodiment of this application, such as Figure 1 As shown, the calculation result output circuit 103 includes a first capacitor 301, which is used to couple the voltage of the calculation output node 203 to the RBL105.

[0072] In one possible implementation, the voltage of the calculation output node 203 of each computing unit can be used to characterize the calculation result of each computing unit 100. The voltage of the calculation output node 203 of each computing unit can be coupled to the RBL105 by the first capacitor 301 in each computing unit 100. Based on the voltage of the RBL105, the cumulative result of the multiplication calculation of the plurality of computing units 100 can be determined.

[0073] In an optional embodiment of this application, such as Figure 4 As shown, the calculation result output circuit 103 includes a third transistor 302 and a fourth transistor 303. The bit line RBL includes a first RBL 502 and a second RBL 503. The gates of the third transistor 302 and the fourth transistor 303 are both connected to the calculation output node 203. The source of the third transistor 302 is connected to a second voltage source. The source of the fourth transistor 303 is connected to the second RBL 503. The drain of the third transistor 302 is connected to the first RBL 502. The drain of the fourth transistor 303 is grounded.

[0074] The third transistor and the fourth transistor are used to perform charging or discharging operations on the first RBL and the second RBL respectively, under the control of the calculated output node voltage.

[0075] Optionally, the third transistor can be a PMOS transistor, and the fourth transistor can be an NMOS transistor.

[0076] In one optional embodiment of this application, such as Figure 4 As shown, a fifth transistor 504 is provided on the first RBL502, and a sixth transistor 505 is provided on the second RBL503. The fifth transistor 504 and the sixth transistor 505 are used to discharge and float the first RBL502 and the second RBL503 before the multiplication calculation circuit 101 performs calculations based on the signal input voltage and the weight value.

[0077] Both the fifth and sixth transistors are NMOS transistors.

[0078] In one possible implementation, the gate of the fifth transistor 504 is connected to a voltage source Vs. A positive pulse can be applied to the fifth transistor 504 based on Vs to ground RBL502. This process is a discharge process. After the pulse ends, RBL502 is left floating, and the voltage at Vs remains 0. This process is a floating process.

[0079] In one possible implementation, the gate of the sixth transistor 505 is connected to a voltage source Vs. A positive pulse can be applied to the sixth transistor 505 based on Vs to make RBL503 connected to VDD. This process is the charging process. After the pulse ends, RBL503 is left floating, and the voltage at Vs remains 0. This process is the floating process.

[0080] In an optional embodiment of this application, such as Figure 4 As shown, the first RBL502 and the second RBL503 are connected to the calculation result processing circuit 106. The calculation result processing circuit 106 includes a first switch 601, a second switch 602, a third switch 603, a fourth switch connection 604, a second capacitor 605, and a third capacitor 606.

[0081] The calculation result processing circuit 106 is used to average the voltages of the first RBL502 and the second RBL503 to obtain the calculation results of the plurality of calculation units 100.

[0082] In one possible implementation, during the multiplication calculation circuit 101's calculation based on the signal input voltage and the weight value, the first switch 601 and the second switch 602 remain closed, while the third switch 603 and the fourth switch 604 remain open.

[0083] As described above, the first RBL502 and the second RBL503 are discharged and left floating before the multiplication calculation circuit 101 performs calculations based on the signal input voltage and the weight value.

[0084] In one possible implementation, the first switch 601 and the second switch 602 can be closed first, the third switch 603 and the fourth switch 604 can be opened, and a large positive pulse can be applied based on the voltage source Vs to make the first RBL502 pre-discharge to 0 and the first RBL502 pre-charge to V. DD This process is a discharge process. Then, the voltage source Vs is reduced to 0 so that the first RBL502 and the first RBL502 are left floating. This process is a floating process.

[0085] As described above, the third transistor and the fourth transistor are used to perform charging or discharging operations on the first RBL and the second RBL respectively under the control of the calculated output node voltage.

[0086] In one possible implementation, when the voltage at point A is V DD When the value is 2, meaning the calculation result is 0, neither the third transistor 302 nor the fourth transistor 303 is conducting. Therefore, the voltage across the first RBL502 is 0, and the voltage across the second RBL503 is V. DD .

[0087] In another possible implementation, when the voltage at point A is V DD When the calculated result is 1, the third transistor 302 is not turned on, the fourth transistor 303 is turned on, the voltage across the first RBL502 is 0, and the voltage across the second RBL503 is V. DD -ΔV, where ΔV is the voltage change on the second RBL503 due to the change in stored charge when the fourth transistor 303 performs a discharge operation.

[0088] In another possible implementation, when the voltage at point A is 0, i.e., the calculated result is -1, the third transistor 302 is turned on, and the fourth transistor 303 is not turned on. Then, the voltage across the first RBL502 is ΔV, and the voltage across the second RBL503 is V. DD ΔV is the voltage change on the first RBL502 caused by the change in stored charge when the third transistor 302 performs a charging operation.

[0089] As described above, the calculation result processing circuit 106 is used to average the voltages of the first RBL502 and the second RBL503 to obtain the calculation results of the plurality of calculation units 100.

[0090] In one possible implementation, after the multiplication calculation circuit 101 performs calculations based on the signal input voltage and the weight value, the third transistor 302 and the fourth transistor 303 couple the voltages of the calculation output node 203 to the first RBL502 and the second RBL503, respectively. At this time, the voltages on the first RBL502 and the second RBL503 are nΔV and V, respectively. DD -mΔV, where n is the number of calculation units in the calculation circuit whose calculation result is -1, and m is the number of calculation units in the calculation circuit whose calculation result is 1. The second capacitor 605 connected to the first RBL502 and the third capacitor 606 connected to the second RBL503 have the same value, C. Therefore, the charge on the second capacitor 605 is C(nΔV), and the charge on the third capacitor 606 is C(V). DD -mΔV), at this time, the first switch 601 and the second switch 602 are opened, and the charge on the second capacitor 605 and the third capacitor 606 is still retained. Then the third switch 603 and the fourth switch 604 are closed, and the charge on the second capacitor 605 and the third capacitor 606 is... Figure 4 Charge sharing occurs at point B, and the final total charge is C(V). DD Given -mΔV+nΔV), the total capacitance is 2C, so the total voltage is (V). DD -mΔV+nΔV) / 2, and then the calculation result can be obtained through ADC. For details, please refer to Table 3.

[0091] Table 3

[0092]

[0093] The aforementioned computing circuit includes multiple computing units arranged in an array. Each computing unit includes a multiplication computing circuit, a pre-charge circuit, and a calculation result output circuit. The multiplication computing circuit includes a first ferroelectric transistor and a second ferroelectric transistor connected to each other. The pre-charge circuit and the calculation result output circuit are both electrically connected to a computing output node located between the first ferroelectric transistor and the second ferroelectric transistor. The first ferroelectric transistor and the second ferroelectric transistor are used to enter a target resistive state under the drive of a write voltage to characterize the weight value of the neural network unit corresponding to the computing unit. The pre-charge circuit is used to adjust the calculation output node to a target voltage after the first ferroelectric transistor and the second ferroelectric transistor enter the target resistive state. The first ferroelectric transistor and the second ferroelectric transistor are used to receive a signal input voltage after the calculation output node is adjusted to the target voltage. The calculation result output circuit is used to output the voltage of the calculation output node after receiving the signal input voltage to obtain the calculation result of the multiplication computing circuit based on the signal input voltage and the weight value. The computing circuit provided in this application can be used for the calculation of ternary neural networks. Compared with the computing circuits in the prior art, the computing circuit of this application uses fewer components and has a smaller area. Therefore, by using the computing circuit provided in this application, the integration level can be effectively improved and the power consumption can be reduced.

[0094] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0095] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A computing circuit, characterized in that, The computing circuit includes multiple computing units arranged in an array. Each computing unit includes a multiplication computing circuit, a pre-charging circuit, and a computing result output circuit. The multiplication computing circuit includes a first ferroelectric transistor and a second ferroelectric transistor connected to each other. The pre-charging circuit and the computing result output circuit are both electrically connected to a computing output node located between the first ferroelectric transistor and the second ferroelectric transistor. The first ferroelectric transistor and the second ferroelectric transistor are used to enter the target resistive state under the drive of the write voltage, so as to characterize the weight value of the neural network unit corresponding to the computing unit; The pre-charge circuit is used to adjust the calculation output node to the target voltage after the first ferroelectric transistor and the second ferroelectric transistor enter the target resistive state. The first ferroelectric transistor and the second ferroelectric transistor are used to receive the signal input voltage after the calculation output node is adjusted to the target voltage; The calculation result output circuit is used to output the voltage of the calculation output node after receiving the signal input voltage, so as to obtain the calculation result of the multiplication calculation circuit based on the signal input voltage and the weight value; The first ferroelectric transistor is in a low-resistance state, and the second ferroelectric transistor is in a high-resistance state, which is used to characterize that the weight value of the neural network unit corresponding to the computing unit is 1; The first ferroelectric transistor is in a high-resistivity state, and the second ferroelectric transistor is in a low-resistivity state, which is used to characterize that the weight value of the neural network unit corresponding to the computing unit is -1; Both the first ferroelectric transistor and the second ferroelectric transistor are in a high-resistivity state, which indicates that the weight value of the neural network unit corresponding to the computing unit is 0.

2. The computing circuit according to claim 1, characterized in that, The first terminal of the first ferroelectric transistor and the first terminal of the second ferroelectric transistor are connected. The second terminal of the first ferroelectric transistor is a first signal input node, and the second terminal of the second ferroelectric transistor is a second signal input node. The gate of the first ferroelectric transistor is a first write voltage driving node, and the gate of the second ferroelectric transistor is a second write voltage driving node. The first signal input node and the second signal input node are used to input the signal input voltage; The first write voltage driving node and the second write voltage driving node are used to input the write voltage.

3. The computing circuit according to claim 2, characterized in that, The computational output node is located between the first electrode of the first ferroelectric transistor and the first electrode of the second ferroelectric transistor.

4. The computing circuit according to any one of claims 1 to 3, characterized in that, The pre-charge circuit includes a first transistor, the source of which is connected to a first voltage source for outputting the target voltage, the drain of which is connected to the compute output node, and the gate of which is used to receive a pulse signal to adjust the compute output node to the target voltage based on the pulse signal.

5. The computing circuit according to claim 4, characterized in that, The computing circuit also includes a word line WL; The gate of the first transistor in the pre-charge circuit of each computing unit is connected to the WL; the WL is used to output the pulse signal to the gate of the first transistor in the pre-charge circuit of each computing unit.

6. The computing circuit according to any one of claims 1 to 3, characterized in that, The computing circuit also includes a bit line RBL, and the computing result output circuit in each computing unit is connected to the RBL to output the computing result to the RBL.

7. The computing circuit according to claim 6, characterized in that, The calculation result output circuit includes a first capacitor, which is used to couple the voltage of the calculation output node to the RBL.

8. The computing circuit according to claim 7, characterized in that, A second transistor is provided on the RBL. The second transistor is used to discharge and float the RBL before the multiplication calculation circuit performs calculations based on the signal input voltage and the weight value.

9. The computing circuit according to claim 6, characterized in that, The calculation result output circuit includes a third transistor and a fourth transistor. The bit line RBL includes a first RBL and a second RBL. The gates of the third transistor and the fourth transistor are both connected to the calculation output node. The source of the third transistor is connected to a second voltage source. The source of the fourth transistor is connected to the second RBL. The drain of the third transistor is connected to the first RBL. The drain of the fourth transistor is grounded. The third transistor and the fourth transistor are used to perform charging or discharging operations on the first RBL and the second RBL, respectively, under the control of the calculated output node voltage.

10. The computing circuit according to claim 9, characterized in that, The first RBL and the second RBL are connected by a calculation result processing circuit, which includes a first switch, a second switch, a third switch, a fourth switch, a second capacitor, and a third capacitor. The calculation result processing circuit is used to accumulate the voltages of the first RBL and the second RBL to obtain the calculation results of multiple calculation units.

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