Computing circuitry

By designing an array-arranged computing circuit, utilizing ferroelectric transistors to enter a resistive state under write voltage drive, and adjusting the voltage through pre-charging and output circuits, the problems of low integration and high power consumption of TNN array units are solved, realizing a computing circuit with high integration and low power consumption, and improving the inference efficiency of deep neural networks.

CN117474058BActive Publication Date: 2026-05-12TSINGHUA UNIVERSITY
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Patent Information

Application Number
CN202311262056.X
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2023-09-27
Publication Date
2026-05-12
Estimated Expiration
2043-09-27

AI Technical Summary

Technical Problem

Existing ternary neural network (TNN) array units have a large number of components and a large area, resulting in low integration and high power consumption, which cannot effectively improve the inference efficiency of deep neural networks.

Method used

The computational circuit, which employs an array arrangement, includes a multiplication computation circuit, a pre-charge circuit, and a computation result output circuit. It utilizes the first and second ferroelectric transistors to enter the target resistive state under the drive of the write voltage, adjusts the computation output node to the target voltage through the pre-charge circuit, and outputs the voltage through the computation result output circuit to obtain the computation result.

Benefits of technology

It improves the integration of computing circuits, reduces power consumption, is suitable for ternary neural network calculations, reduces the use of components, and thus improves computing efficiency.

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Abstract

The application relates to a computing circuit. The computing circuit comprises a plurality of computing units arranged in an array, each computing unit comprising a multiplication computing circuit, a pre-charging circuit and a computing result output circuit, the multiplication computing circuit comprising a first ferroelectric transistor and a second ferroelectric transistor connected to each other, the pre-charging circuit and the computing result output circuit being electrically connected to a computing output node between the first ferroelectric transistor and the second ferroelectric transistor; the first ferroelectric transistor and the second ferroelectric transistor are used to enter a target resistance state under the driving of a write voltage, the pre-charging circuit is used to adjust the computing output node to a target voltage after the first ferroelectric transistor and the second ferroelectric transistor enter the target resistance state, and the first ferroelectric transistor and the second ferroelectric transistor are used to receive a signal input voltage after the computing output node is adjusted to the target voltage; the computing result output circuit is used to output the voltage of the computing output node after receiving the signal input voltage. The computing circuit provided by the application can improve the integration level and reduce the power consumption.
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