GOA circuit, display panel and display device

Abstract

Embodiments of the present invention provide a GOA circuit, a display panel, and a display device. The GOA circuit includes a connected pull-up control module and a pull-up module, the pull-up control module includes a first pull-up control unit and at least one second pull-up control unit, and the pull-up module includes a first pull-up unit and at least one second pull-up unit. The first pull-up control unit is connected to the first pull-up unit and the second pull-up unit, and the at least one second pull-up control unit is connected to the first pull-up unit and at least one third pull-up unit. In this way, a first-level GOA circuit can be used to simultaneously generate scan signals corresponding to two rows of different pixels, enabling the first-level GOA circuit to drive two rows of pixels, reducing the number of GOA circuits and, in turn, reducing the space occupied by the GOA circuits to achieve a narrow-frame design.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a GOA circuit, a display panel, and a display device. Background Art

[0002] With the continuous advancement of the information age, people's dependence on electronic products and their performance requirements have increased. As a medium for human-computer communication, the continuous development of display technology has a significant impact on improving people's visual enjoyment, simplifying operation, and facilitating portability. Currently, liquid crystal displays (LCDs) and organic light-emitting diodes (OLEDs) are the main display devices on the market. These display devices consist of a display panel and a driver that drives the display panel. The driver includes a gate driver for driving the pixels in the display panel to turn on row by row, a data driver for providing the display screen voltage, and a timing controller for providing image data and various control signals to the gate and data drivers. To enhance visual enjoyment and maximize display area, gate drivers have evolved from integrated circuits (ICs) to gate-on-array (GOA) drivers. GOA driver circuits are formed outside the display area at the same time as the array substrate is formed. The GOA circuits correspond to the number of pixel rows, enabling row-by-row gate switching. However, the continuous development of high-end displays towards higher resolutions and narrower bezels poses significant challenges to the driving capability and layout space of the GOA circuits. Summary of the Invention

[0003] Embodiments of the present invention provide a GOA circuit, a display panel, and a display device, which solve the problem in the prior art that the GOA circuit occupies a large space and affects spatial arrangement.

[0004] To solve the above problems, in a first aspect, the present application provides a GOA circuit, wherein the GOA circuit includes a plurality of cascaded GOA units, wherein the n-th stage GOA unit is used to drive the n-th row of pixel units; the circuit of the n-th stage GOA unit includes a pull-up control module and a pull-up module, wherein the pull-up control module is electrically connected to the pull-up module to control the pull-up module;

[0005] The pull-up control module includes: a first pull-up control unit connected to the first clock signal of the n-1th row and the first stage transmission signal of the n-1th row;

[0006] At least one second pull-up control unit, the at least one second pull-up control unit connected to the first stage transmission signal and the first clock signal of the (n-1+m)th row, where m and n are both not less than 1;

[0007] The pull-up module includes: a first pull-up unit, the first pull-up unit being configured to generate a second-stage transmission signal for the nth row according to a second clock signal for the nth row;

[0008] a second pull-up unit, configured to generate a first scan signal for the nth row according to the first clock signal for the nth row;

[0009] at least one third pull-up unit, configured to generate a second scan signal for the n+mth row according to the first clock signal for the n+mth row;

[0010] The first pull-up control unit is electrically connected to the first pull-up unit and the second pull-up unit, and the at least one second pull-up control unit is electrically connected to the first pull-up unit and the at least one third pull-up unit.

[0011] In some possible embodiments, the first pull-up control unit includes a first thin film transistor and a second thin film transistor connected in series, the first thin film transistor is connected to the first clock signal of the (n-1)th row, and the second thin film transistor is connected to the first stage transmission signal.

[0012] In some possible embodiments, the at least one second pull-up control unit includes a third thin film transistor and a fourth thin film transistor connected in series, the third thin film transistor is connected to the first-stage transmission signal, and the fourth thin film transistor is connected to the first clock signal of the (n-1+m)th row.

[0013] In some possible embodiments, there are multiple second pull-up control units, there are multiple third pull-up units, each of the multiple second pull-up control units is connected to the second pull-up unit, each of the multiple second pull-up control units is connected to one of the multiple third pull-up units, and the multiple third pull-up units are respectively used to generate multiple scanning signals to drive multiple rows of pixel units.

[0014] In some possible embodiments, the first pull-up control unit includes a first thin film transistor and a second thin film transistor connected in series, the second pull-up control unit is one and includes a third thin film transistor and a fourth thin film transistor connected in series, one end of the source and drain of the first thin film transistor, one end of the source and drain of the second thin film transistor, one end of the source and drain of the third thin film transistor, and one end of the source and drain of the fourth thin film transistor are connected to the same node.

[0015] In some possible embodiments, the first pull-up unit includes a fifth thin film transistor, and the fifth thin film transistor is configured to generate a second-stage transmission signal for the nth row according to the second clock signal for the nth row;

[0016] The second pull-up unit includes a sixth thin film transistor, and the sixth thin film transistor is configured to generate a first scan signal for the nth row according to the first clock signal for the nth row.

[0017] In some possible embodiments, the at least one third pull-up unit includes a seventh thin film transistor, and the seventh thin film transistor is configured to generate the second scan signal of the (n+m)th row according to the first clock signal of the (n+m)th row.

[0018] In some possible embodiments, the GOA circuit further includes a pull-down module, which is electrically connected to the pull-up module and is configured to pull down the potential of the pull-up module.

[0019] In a second aspect, the present application further provides a display panel, comprising the GOA circuit as described in any one of the above items.

[0020] In a third aspect, the present application further provides a display device, which includes the display panel as described above.

[0021] Beneficial Effects: Embodiments of the present invention provide a GOA circuit, a display panel, and a display device. The GOA circuit includes a connected pull-up control module and a pull-up module, the pull-up control module includes a first pull-up control unit and at least one second pull-up control unit, and the pull-up module includes a first pull-up unit and at least one second pull-up unit. The first pull-up control unit is connected to the first pull-up unit and the second pull-up unit, and the at least one second pull-up control unit is connected to the first pull-up unit and at least one third pull-up unit. In this way, a first-level GOA circuit can be used to simultaneously generate scan signals corresponding to two rows of different pixels, enabling the first-level GOA circuit to drive two rows of pixels, reducing the number of GOA circuits and, in turn, reducing the space occupied by the GOA circuits to achieve a narrow-frame design. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0023] Figure 1 A schematic diagram of the circuit structure of the n-th level GOA unit provided in an embodiment of the present application;

[0024] Figure 2 This is a circuit timing diagram provided for an embodiment of the present application. DETAILED DESCRIPTION

[0025] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0026] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0027] In this application, the word "exemplary" is used to mean "serving as an example, illustration, or illustration." Any embodiment described in this application as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. The following description is given to enable any person skilled in the art to make and use the invention. In the following description, details are listed for the purpose of explanation. It should be understood that one of ordinary skill in the art will recognize that the invention can be practiced without these specific details. In other instances, well-known structures and processes are not described in detail to avoid obscuring the description of the invention with unnecessary detail. Therefore, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.

[0028] The embodiments of the present invention provide a GOA circuit, a display panel, and a display device, which are described in detail below.

[0029] Display panels typically include pixel cells arranged in multiple rows and columns, and a GOA circuit is typically used to control each row of pixel cells separately. However, a GOA circuit typically includes multiple cascaded GOA cells, with each stage of GOA cells controlling a row of pixel cells. This results in an excessive number of GOA cells, which occupies a large space for the entire GOA circuit and prevents the implementation of a narrow bezel design.

[0030] This application provides a new GOA circuit that uses a first-level GOA unit to control multiple rows of pixel units, thereby reducing the number of GOA units and achieving a narrow frame design. Figure 1 , which is a circuit diagram of the GOA unit provided in an embodiment of the present application. Figure 1 Schematic diagram of the circuit structure of the n-th level GOA unit provided in the embodiment of the present application; the complete GOA circuit in the present application can be composed of Figure 1 The circuit shown is obtained by cascading multiple GOA units.

[0031] exist Figure 1 In the illustrated embodiment, the circuit of the n-th stage GOA unit includes a pull-up control module 10 and a pull-up module 20 ; the pull-up control module 10 is electrically connected to the pull-up module 20 to control the pull-up module.

[0032] The pull-up control module 10 may include a first pull-up control unit 101 and at least one second pull-up control unit 102; the pull-up module 20 may include a first pull-up unit 201, a second pull-up unit 202, and at least one third pull-up unit 203. The pull-up control module 10 and the pull-up module 20 are electrically connected, and in fact, the first pull-up control unit 101 is connected to the first pull-up unit 201 and the second pull-up unit 202; and the at least one second pull-up control unit 102 is connected to the first pull-up unit 201 and the at least one third pull-up unit 203. The first pull-up unit 201 and each pull-up control unit in the pull-up control module 10 remain connected. Different pull-up units can generate scanning signals corresponding to different rows of pixel units under the control of different pull-up control units.

[0033] Specifically, the first pull-up control unit 101 is connected to the first clock signal CKB(n-1) of the n-1th row and the first-level transmission signal cout(n-1) of the n-1th row; the first pull-up control unit 101 is turned on under the control of the first clock signal CKB(n-1) and the first-level transmission signal cout(n-1) of the n-1th row, and further controls the first pull-up unit 201 and the second pull-up unit 202 to generate the first scan signal of the nth row. As for the at least one third pull-up unit 203, under the premise that the first pull-up unit 201 and the at least one second pull-up control unit 102 remain connected, the at least one third pull-up unit 203 can generate the second scan signal of the n+mth row. Thus, the circuit of the first-level GOA unit can simultaneously generate the scan signals corresponding to the two rows of pixel units, and the circuit of the first-level GOA unit can drive multiple rows of pixel units.

[0034] It should be noted that in the embodiment of the present application, when there are multiple second pull-up control units 102, there are also multiple third pull-up units 203, and the number of the multiple second pull-up control units 102 is the same as the number of the multiple third pull-up units 203; and the multiple second pull-up control units 102 and the multiple third pull-up units 203 are connected separately. The multiple pull-up units in the present application can output multiple scanning signals for driving different rows of pixel units.

[0035] by Figure 1 Taking the embodiment shown as an example, Figure 1 The system includes only one second pull-up control unit 102 and one third pull-up unit 203. The first pull-up control unit 101 may include a first thin-film transistor T11A and a second thin-film transistor T12A connected in series, while the second pull-up control unit 102 may include a third thin-film transistor T12A and a fourth thin-film transistor T12B connected in series. In the first pull-up control unit 101, the gates of the first thin-film transistor T11A and the second thin-film transistor T11B are both connected to the first clock signal CKB(n-1) of the n-1th row, and one end of the source and drain of the first thin-film transistor T11A is connected to the first-stage transmission signal cout(n-1) of the n-1th row. In the second pull-up control unit 102, the gates of the third thin-film transistor T12A and the fourth thin-film transistor T12B are both connected to the first clock signal CKB(n-1+m) of the n-1+mth row, and one end of the source and drain of the third thin-film transistor T12A is also connected to the first-stage transmission signal cout(n-1) of the n-1th row.

[0036] It should be noted that although one end of the source and drain of the first thin-film transistor T11A and one end of the source and drain of the third thin-film transistor T12A are both connected to the first-stage signal transmission line of the (n-1)th row, in this application, two first-stage signal transmission lines are provided and connected to two pull-up control units, respectively. In other embodiments, the specific lines can also be changed according to actual needs and are not limited here.

[0037] Please refer to Figure 1 ,for Figure 1 In the illustrated embodiment, one end of the source and drain of the first thin-film transistor T11A is connected to the first-stage transmission signal of the (n-1)th row, and the other end is connected to the source and drain of the second thin-film transistor T11B. One end of the source and drain of the third thin-film transistor T12A is connected to the first-stage transmission signal of the (n-1+m)th row, and the other end is connected to the source and drain of the fourth thin-film transistor T12B. Furthermore, the first thin-film transistor T11A, the second thin-film transistor T11B, the third thin-film transistor T12A, and the fourth thin-film transistor T12B are all connected to the first node N(n).

[0038] exist Figure 1In the embodiment, the first pull-up unit 201 may include a fifth thin-film transistor T21, the second pull-up unit 202 may include a sixth thin-film transistor T22, and the third pull-up unit 203 may include a seventh thin-film transistor T23. For the first pull-up unit, the fifth thin-film transistor T21 is mainly used to generate the second-stage transmission signal cout(n) of the nth row based on the second clock signal CKA(n) of the nth row. One end of the source and drain of the sixth thin-film transistor T22 is connected to the first clock signal CKB(n) of the nth row, and generates the first scan signal out(n) of the nth row under the control of the first clock signal CKB(n) of the nth row. One end of the source and drain of the seventh thin-film transistor T23 is connected to the first clock signal CKB(n+m) of the n+mth row, and generates the second scan signal out(n+m) of the n+mth row under the control of the first clock signal CKB(n+m) of the n+mth row.

[0039] exist Figure 1 In the embodiment, the plurality of thin film transistors in the pull-up control module 10 and the plurality of transistors in the pull-up module 20 are connected to the same node; Figure 1 The second node Q is shown in FIG. The source and drain of the thin film transistor in the pull-up control module 10 are connected to the Q point, while the gates of the thin film transistors in the pull-up module 20 are both connected to the Q point. The potential at the Q point will continuously change, and the specific process will be described in subsequent embodiments.

[0040] It should be noted that the pixel units in the display panel are driven row by row from top to bottom during the actual driving process, so it is necessary to control multiple cascaded GOA units to generate scanning signals corresponding to each row of pixel units. The scanning signal in this application is mainly used to turn on the pixel circuit, while the level transmission signal is mainly used to turn on each level of GOA units to control each level of GOA units to generate scanning signals.

[0041] Please refer to Figure 1 , Figure 1 In the illustrated embodiment, the circuit of the n-th level GOA unit further includes a pull-down module 30, which is electrically connected to the pull-up module 20; the pull-down module 30 is mainly used to lower the potential of the pull-up module, that is, to pull down the potential of the pull-up module when the pull-up module is at a high potential.

[0042] for Figure 1In the illustrated embodiment, since the first-level GOA circuit generates a first scan signal out(n) and a second scan signal out(n+m) to drive two row drive circuits, respectively, the pull-up module 20 performs two potential increases, and subsequently requires two circuit pull-down operations. Therefore, the pull-down module 30 in this application includes two pull-down units, namely a first pull-down unit 301 and a second pull-down unit 302; these two pull-down units perform two pull-down operations; the specific process is described in subsequent embodiments.

[0043] exist Figure 1 In the embodiment, the first pull-down unit 301 may include an eighth thin-film transistor T31A and a ninth thin-film transistor T31B connected in series; one end of the source and drain of the eighth thin-film transistor T31A is also connected to the second node Q, and one end of the source and drain of the ninth thin-film transistor T31B is connected to a fixed low potential VGL1. Furthermore, the gates of the eighth thin-film transistor T31A and the ninth thin-film transistor T31B are both connected to the first-stage transmission signal cout(n+1) of the n+1th row. The second pull-down unit 302 may also include a tenth thin-film transistor T32A and an eleventh thin-film transistor T32B connected in series; one end of the source and drain of the tenth thin-film transistor T32A is connected to the second node Q, and one end of the source and drain of the eleventh thin-film transistor T32B is connected to the fixed low potential VGL1.

[0044] After the pull-down unit pulls down the potential, it is also necessary to maintain the pull-down state, so the present application also includes a pull-down maintaining module 40. Figure 1 As shown, the pull-down maintenance module 40 may include a twelfth thin-film transistor T41, a thirteenth thin-film transistor T42, and a fourteenth thin-film transistor T43. The twelfth thin-film transistor T41 is electrically connected to the fifth thin-film transistor T21 to pull down the potential of the fifth thin-film transistor T21. Similarly, the thirteenth thin-film transistor T42 is electrically connected to the sixth thin-film transistor T22 to pull down the potential of the sixth thin-film transistor T22. The fourteenth thin-film transistor T43 is electrically connected to the seventh thin-film transistor T23 to pull down the potential of the seventh thin-film transistor T23. Generally speaking, the number of thin-film transistors in the pull-down maintenance module 40 is the same as the number of thin-film transistors in the pull-up module 20, and they are connected in a one-to-one correspondence.

[0045] Figure 1 The circuit of the GOA unit further includes an inverting module 50, which may include a fifteenth thin film transistor T51 and a sixteenth thin film transistor T52 connected in series. One end of the source and drain of the sixteenth thin film transistor T52 is connected to a fixed low potential VGL1, and the gate of the sixteenth thin film transistor T52 is connected to the second node Q. The gate and one end of the source and drain of the fifteenth thin film transistor T51 are both connected to a fixed high potential VGH.

[0046] The GOA unit circuit provided herein also includes an anti-leakage module 60, which primarily prevents leakage at the GOA circuit's intermediate nodes (primarily the Q point) due to Vth voltage drift, potentially leading to circuit inefficiency. By adding the anti-leakage module 60 and utilizing multiple fixed low-voltage VGL signals to generate a voltage differential, the reliability of the GOA circuit is improved.

[0047] Please refer to Figure 1 , Figure 1 The anti-leakage module 60 may include: a seventeenth thin film transistor T61 and an eighteenth thin film transistor T62 connected in series; the gates of the two thin film transistors are both connected to the second node Q, one end of the source and drain of the seventeenth thin film transistor T61 is connected to the N(n) node, and one end of the source and drain of the eighteenth thin film transistor T62 is connected to a fixed high potential VGH.

[0048] like Figure 2 As shown, this is a circuit timing diagram provided by an embodiment of the present application. Figure 1 and Figure 2 The present application describes how to use the circuit of a first-level GOA unit to drive multiple rows of pixel units at the same time. In the P1 stage, the first pull-up module 101 in the pull-up control module 10 receives: the level transmission signal cout(n-1) of the n-1 row and the first clock signal CKB(n) of the n-1 row, and at this time the level transmission signal cout(n-1) of the n-1 row and the first clock signal CKB(n) of the n-1 row are both high-voltage signals. The thin-film transistor in the first pull-up module 101 is turned on, and the Q point is pre-charged, so that the potential of the Q point is raised for the first time. And the charged charge is stored in the capacitor C1. The potential of the N(n) node will also rise, thereby avoiding the loss of charge in the capacitor C1, that is, avoiding leakage in the GOA circuit.

[0049] It should be noted here that, Figure 1 The multiple N(n) nodes in the diagram represent that these traces are actually connected together, or have the same potential, and are all N(n) node points.

[0050] During phase P1, after the potential at point Q rises, the gate of the sixteenth thin-film transistor T52 reaches a high potential, turning on the sixteenth thin-film transistor T52. The third node Qb between the sixteenth thin-film transistor T52 and the fifteenth thin-film transistor T51 changes from a high potential to a low potential. The gates of the tenth thin-film transistor T32A and the eleventh thin-film transistor T32B are both connected to the third node Qb. When the third node Qb drops from a high potential to a low potential, the tenth thin-film transistor T32A and the eleventh thin-film transistor T32B turn off. The gates of the twelfth thin-film transistor T41, the thirteenth thin-film transistor T42, and the fourteenth thin-film transistor T43 are also connected to the third node Qb. At this point, the twelfth thin-film transistor T41, the thirteenth thin-film transistor T42, and the fourteenth thin-film transistor T43 are also turned off.

[0051] During phase P2, due to the increased potential at point Q, the gates of the fifth, sixth, and seventh thin-film transistors T21, T22, and T23 are at a high potential, turning on all three thin-film transistors in the pull-up module. At this point, the first clock signal CKB(n) and the second clock signal CKA(n) for row n each output high-potential pulse signals, raising the potential of the stage transfer signal cout(n) for row n and the potential of the first scan signal for row n; thus, generating the stage transfer signal and scan signal corresponding to row n.

[0052] At this time, the Q-point potential rises again due to the coupling effect of capacitor C1, thereby improving the driving capability of the thin-film transistors in the pull-up module. During phase P2, although the gate of the seventh thin-film transistor T23 is at a high potential, the second clock signal CKB(n+m) for the n+mth row input to the seventh thin-film transistor T23 remains at a low potential; therefore, the second scan signal out(n+m) for the n+mth row input to the seventh thin-film transistor T23 remains at a low potential.

[0053] During phase P3, the first clock signal CKB(n) and the second clock signal CKA(n) of row n also transition from high to low, causing the corresponding output signals cout(n) and out(n) of the two transistors to also transition to low. Simultaneously, due to the coupling effect of capacitor C1, the potential at point Q decreases.

[0054] In the P2 stage, the level transmission signal cout(n) corresponding to the nth row is generated, and the level transmission signal will be transmitted to the circuit corresponding to the GOA unit in the n+1th row. The circuit corresponding to the GOA unit in the n+1th row repeats the above potential change process to generate the level transmission signal cout(n+1) corresponding to the n+1th row; the level transmission signal in the n+1th row will be fed back to the circuit corresponding to the GOA unit in the nth stage. In the P4 stage, Figure 1The thin-film transistor in the first pull-down unit 301 in the pull-down module 30 receives the level transfer signal cout(n+1) corresponding to the n+1th row, and cout(n+1) changes from a low potential to a high potential. At this point, the thin-film transistor in the first pull-down unit 301 turns on, releasing the charge stored in capacitor C1. The gates of the fifth thin-film transistor T21, the sixth thin-film transistor T22, and the seventh thin-film transistor T23 in the pull-up module 20 are at a low potential, and all three thin-film transistors are turned off. This completes the output of the first scan signal for row n, generating the first scan signal for row n.

[0055] In the P5 stage, the potential of the level transfer signal of the n-1th row and the first clock signal CKB(n-1+m) of the n-1+mth row input in the second pull-up control unit 102 increases at the same time, and the Q point potential is raised again. The process of raising the Q point potential can refer to the aforementioned P1 stage and will not be repeated here. In the P6 stage, due to the increase in the Q point potential, the gates of the fifth thin film transistor T21, the sixth thin film transistor T22, and the seventh thin film transistor T23 are at a high potential, and the three thin film transistors in the pull-up module 20 are all turned on. At this time, the first clock signal CKB(n+m) of the n+mth row and the second clock signal CKA(n) of the nth row simultaneously output high-potential pulse signals, causing the level transfer signal cout(n) of the nth row to rise in potential, and the second scan signal of the n+mth row to rise in potential; that is, the level transfer signal corresponding to the nth row and the second scan signal corresponding to the n+mth row are generated.

[0056] At the same time, the potential at point Q is also raised a second time due to the coupling effect of capacitor C1, thereby improving the driving capability of the thin-film transistors in the pull-up module. At this time, the first clock signal CKB(n) of the nth row in the pull-up module is at a low level, so out(n) maintains a low signal output.

[0057] During phase P7, the potentials of the first clock signal CKB(n+m) for row (n+m) and the second clock signal CKA(n) for row (n) change from high to low. Consequently, the potential of the stage transfer signal cout(n) for row (n+m) decreases, as does the potential of the second scan signal for row (n+m). Simultaneously, due to the coupling effect of capacitor C1, the potential at point Q decreases again.

[0058] When the level transmission signal cout(n) of the nth row is generated for the second time, the level transmission signal will also be transmitted to the circuit of the GOA unit of the n+1th row, and the GOA unit of the n+1th row will regenerate the level transmission signal cout(n+1) of the n+1th row. Similarly, the level transmission signal cout(n+1) will be fed back to the circuit of the GOA unit of the nth stage; therefore, in the T8 stage, Figure 1The first pull-down unit 301 receives the second high-voltage pulse output of the cout(n+1) signal. At this point, the thin-film transistor in the first pull-down unit 301 is turned on again, the charge at point Q is released again, and the potential at point Q decreases again. This completes the waveform output of the second scan signal for row (n+m).

[0059] like Figure 2 As shown in , since the first scan signal out(n) of the nth stage is generated under the common control of the first clock signal CKB(n) and the second clock signal CKA(n) of the nth stage, the waveform of the first scan signal out(n) is similar to the waveform of the first clock signal CKB(n) of the nth stage. The second scan signal out(n+m) of the n+mth stage is generated under the common control of the first clock signal CKB(n) of the n+mth stage and the second clock signal CKA(n) of the nth stage. Therefore, the waveform of the second scan signal out(n+m) is similar to the waveform of the clock signal CKB(n+m) of the n+mth stage.

[0060] Since two scanning signals are generated, the signal is pulled down twice and the n-th level transmission signal cout(n) is generated twice; and the n-th level transmission signal is generated by the first pull-up unit, so the signal input by the first pull-up unit has two high potential inputs. Figure 2 As shown in the second clock signal CKA(n) in FIG, the CKA(n) signal of the nth stage has two high potentials. However, the first clock signal has only one high potential output. Moreover, both the first clock signal CKB(n) of the nth stage and the first clock signal (n+m) of the n+mth stage have only one high potential output.

[0061] It should be noted that two types of clock signals are provided in this application, namely a first clock signal CKB and a second clock signal CKA; the first clock signal CKB mainly controls the generation of the scan signal, and the second clock signal is mainly used to generate the stage transfer signal.

[0062] In a specific embodiment, Figure 1 The GOA unit shown can drive the pixel units in the first and ninth rows simultaneously, where n is 1 and m is 8. Because the CKA(n) signal needs to drive the thin-film transistor to generate two secondary transmission signals, the phase of CKA needs to change twice within the same cycle; that is, the phase change period of the CKB signal is twice that of CKA.

[0063] In the circuit of the GOA unit at the same level, if the same level of GOA unit is used to generate scan signals corresponding to two rows of pixel units, then in the pull-up module, the number of traces corresponding to the first clock signal CKB is twice the number of traces corresponding to the second clock signal CKA. In other embodiments, if the same level of GOA unit is used to generate scan signals corresponding to more than two rows of pixel units, then in the pull-up module, the number of traces corresponding to the first clock signal CKB is w times the number of traces corresponding to the second clock signal CKA; where w is the number of scan signals that can be generated by the circuit of the first-level GOA unit, or the number of rows of pixel units that can be controlled by the first-level GOA unit at the same time. Accordingly, the phase change period of the first clock signal CKB and the second clock signal CKA will also change accordingly.

[0064] It should be noted that n and m in this application are both positive integers greater than or equal to 1; further, m is generally a positive integer greater than or equal to 2. This is to avoid the coupling effect of the Q points of the output signals of the two rows, thereby avoiding the use of the same level of GOA units to drive two adjacent rows of pixel units. In addition, in this application, the pulse width of the scanning signal is set to be greater than the charging time of the pixel circuit, so that the Q point can be pre-charged, thereby solving the problem of uneven brightness caused by the first level of GOA units driving multiple rows of pixel units.

[0065] Figure 1 In the illustrated embodiment, the pull-up control unit includes only one second pull-up control unit, and the pull-up unit includes only one third pull-up unit. In other embodiments, there may be multiple second pull-up control units, corresponding to multiple third pull-up units, and the multiple second pull-up control units are connected to the multiple third pull-up units in a one-to-one correspondence. The multiple third pull-up units can respectively generate scan signals corresponding to multiple rows of pixel units (except for the scan signal for the current row, which is generated by the second pull-up unit).

[0066] The present application also provides a display panel, the display panel comprising the circuit structure of the GOA unit as described above. The present application also provides a display device, the display device comprising the display panel as described above.

[0067] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, please refer to the detailed description of other embodiments above and will not be repeated here.

[0068] In specific implementation, the above units or structures can be implemented as independent entities, or can be arbitrarily combined to implement as the same or several entities. The specific implementation of the above units or structures can refer to the previous method embodiments and will not be repeated here.

[0069] The specific implementation of the above operations can be found in the previous embodiments and will not be repeated here.

[0070] The above is a detailed introduction to a GOA circuit, a display panel, and a display device provided in an embodiment of the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there may be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A GOA circuit, characterized in that: The GOA circuit includes a plurality of cascaded GOA units, wherein the n-th stage GOA unit is used to drive the n-th row of pixel units; the circuit of the n-th stage GOA unit includes a pull-up control module and a pull-up module, and the pull-up control module is electrically connected to the pull-up module to control the pull-up module; The pull-up control module includes: a first pull-up control unit connected to the first clock signal of the n-1th row and the first stage transmission signal of the n-1th row; At least one second pull-up control unit, the at least one second pull-up control unit connected to the first stage transmission signal and the first clock signal of the (n-1+m)th row, where m and n are both not less than 1; The pull-up module includes: a first pull-up unit, the first pull-up unit being configured to generate a second-stage transmission signal for the nth row according to a second clock signal for the nth row; a second pull-up unit, configured to generate a first scan signal for the nth row according to the first clock signal for the nth row; at least one third pull-up unit, configured to generate a second scan signal for the n+mth row according to the first clock signal for the n+mth row; Wherein, under the control of the first pull-up control unit, the first pull-up unit and the second pull-up unit respectively generate the second-level transmission signal of the nth row and the first scanning signal of the nth row; under the control of the second pull-up control unit, the first pull-up unit and the at least one third pull-up unit respectively generate the second-level transmission signal of the nth row and the second scanning signal of the (n+m)th row.

2. The GOA circuit according to claim 1, wherein: The first pull-up control unit includes a first thin film transistor and a second thin film transistor connected in series, the first thin film transistor is connected to the first clock signal of the (n-1)th row, and the second thin film transistor is connected to the first stage transmission signal.

3. The GOA circuit according to claim 1, wherein: The at least one second pull-up control unit includes a third thin film transistor and a fourth thin film transistor connected in series, the third thin film transistor is connected to the first stage transmission signal, and the fourth thin film transistor is connected to the first clock signal of the (n-1+m)th row.

4. The GOA circuit according to claim 1, wherein: There are multiple second pull-up control units, and there are multiple third pull-up units. Each of the multiple second pull-up control units is connected to the second pull-up unit, and each of the multiple second pull-up control units is connected to one of the multiple third pull-up units. The multiple third pull-up units are respectively used to generate multiple scanning signals to drive multiple rows of pixel units.

5. The GOA circuit according to claim 1, wherein: The first pull-up control unit includes a first thin film transistor and a second thin film transistor connected in series, the second pull-up control unit is one and includes a third thin film transistor and a fourth thin film transistor connected in series, one end of the source and drain of the first thin film transistor, one end of the source and drain of the second thin film transistor, one end of the source and drain of the third thin film transistor, and one end of the source and drain of the fourth thin film transistor are connected to the same node.

6. The GOA circuit according to claim 1, wherein: The first pull-up unit includes a fifth thin film transistor, and the fifth thin film transistor is used to generate a second-stage transmission signal of the nth row according to the second clock signal of the nth row; The second pull-up unit includes a sixth thin film transistor, and the sixth thin film transistor is configured to generate a first scan signal for the nth row according to the first clock signal for the nth row.

7. The GOA circuit according to claim 1, wherein: The at least one third pull-up unit includes a seventh thin film transistor, and the seventh thin film transistor is configured to generate a second scan signal for the (n+m)th row according to the first clock signal for the (n+m)th row.

8. The GOA circuit according to claim 1, wherein: The GOA circuit further includes a pull-down module, which is electrically connected to the pull-up module and is used to pull down the potential of the pull-up module.

9. A display panel, characterized in that: The display panel includes the GOA circuit according to any one of claims 1 to 8.

10. A display device, characterized in that: The display device includes the display panel according to claim 9.

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