A timing debugging method, display device and storage medium

Abstract

The application discloses a timing debugging method, a display device and a storage medium. The method comprises the following steps: acquiring an optimal common voltage of a display panel at a preset gray scale; determining the number of measuring points on the display panel according to the number of chip-on-film (COF) chips, wherein the number of measuring points is positively correlated with the number of COF chips; acquiring the optimal charging time corresponding to each measuring point according to the optimal common voltage; and adjusting the timing of a scanning signal and a data signal input to the display panel according to the optimal charging time. The application improves the debugging accuracy of signal timing and improves the display effect of image quality.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of driving of display panels, and in particular to a timing debugging method, a display device, and a storage medium. BACKGROUND

[0002] Currently, the picture quality of display products is increasingly attracting the attention of users, and the display product charges each sub-pixel in each frame of picture under the joint action of a scanning signal and a data signal.

[0003] Since there are various resistors, capacitors and other components in the internal circuit of the display panel of the display product, if the charging time is not the actual best charging time of the display panel, the brightness and chroma of each sub-pixel will be directly affected, and therefore the timing of the signals is crucial to the effect of picture quality display.

[0004] Since there are various resistors, capacitors and other components in the internal circuit of the display panel of the display product, the waveforms of the scanning signal and the data signal will change and be delayed when passing through these resistors and capacitors. If the delay steps of the scanning signal and the data signal are inconsistent, the theoretically set charging time will not be the actual best charging time of the display panel, and thus the brightness and chroma of each sub-pixel will be directly affected, and therefore it is crucial to evaluate the best charging timing of the display product for the effect of picture quality display. SUMMARY

[0005] The embodiments of the present application provide a timing debugging method, a display device, and a storage medium, which improve the debugging accuracy of the timing of signals and improve the effect of picture quality display.

[0006] In a first aspect, the embodiments of the present application provide a timing debugging method applied to a display device, the display device including a display panel, N chip-on-film (COF) chips attached to the display panel, and a control board connected with the COF chips, the number of the COF chips being positively correlated with the area of the display panel, and the method including:

[0007] obtaining a best common voltage of the display panel at a preset gray scale;

[0008] determining the number of measuring points on the display panel according to the number of the COF chips, the number of the measuring points being positively correlated with the number of the COF chips;

[0009] obtaining a best charging time corresponding to each of all the measuring points according to the best common voltage;

[0010] adjusting the timing of a scanning signal and a data signal input to the display panel according to the best charging time.

[0011] In some embodiments, the acquiring the optimal common voltage of the display panel at the preset gray scale includes:

[0012] driving the display panel to display a flickering picture at the preset gray scale, and determining a common voltage corresponding to a minimum flickering value as the optimal common voltage.

[0013] In some embodiments, after the acquiring the optimal common voltage of the display panel at the preset gray scale, the determining the number of measuring points on the display panel according to the number of the COF chips includes:

[0014] determining whether the optimal common voltage is the same as an output common voltage provided by the control board to the display panel;

[0015] if the optimal common voltage is different from the output common voltage, adjusting the output common voltage until it is equal to the optimal common voltage.

[0016] In some embodiments, the display panel includes a display area extending along a first direction and a second direction, the second direction being perpendicular to the first direction, the display area being divided into a plurality of sub-display areas along the second direction, the sub-display areas including a plurality of control areas, one COF chip corresponding to one control area, the control area including a plurality of pixels; and the determining the number of measuring points on the display panel according to the number of the COF chips includes:

[0017] setting a first number;

[0018] calculating the number of measuring points in the display panel according to the number of the sub-display areas and the first number.

[0019] In some embodiments, the first number is equal to a sum of a number of center measuring points, a number of boundary measuring points, and a number of intermediate measuring points, wherein a line segment formed by the center measuring points, the boundary measuring points, and the intermediate measuring points is parallel to the first direction, and the center measuring points are located at the center points of the control areas.

[0020] In some embodiments, the acquiring the optimal charging time corresponding to each of the measuring points according to the optimal common voltage includes:

[0021] acquiring a brightness curve corresponding to each of the measuring points at the optimal common voltage and different panel charging times; each of the brightness curves includes brightness values corresponding to the measuring point at different panel charging times;

[0022] determining a panel charging time corresponding to a maximum brightness value in the brightness curve as the optimal charging time corresponding to the measuring point.

[0023] In some embodiments, the adjustment of the timing of the scan signal comprises:

[0024] A first difference value is calculated by subtracting the optimal charging time of the measurement point in a first sub-display area close to the control plate along the second direction from the optimal charging time of the measurement point in a second sub-display area away from the control plate along the second direction, the delay time of the scan signal is set according to the minimum value of the first difference value, and the first sub-display area and the second sub-display area are symmetric to each other along the center point of the display panel in the second direction.

[0025] In some embodiments, the adjustment of the timing of the data signal comprises:

[0026] The delay time of the data signal of the chip on film corresponding to the control area is set according to the optimal charging time of the measurement point in the control area along the first direction;

[0027] A second difference value is calculated by subtracting the optimal charging time of the measurement point in the adjacent control area along the first direction, and the delay time of the data signal between the adjacent chip on films is set according to the second difference value.

[0028] In a second aspect, the embodiments of the present application further provide a display device, which comprises a display panel, a memory and a processor; the memory stores a computer program, and the processor is used to run the computer program in the memory to execute the steps in the timing debugging method according to the first aspect.

[0029] In a third aspect, the embodiments of the present application further provide a storage medium, which stores a plurality of instructions, and the instructions are suitable for being loaded by a processor to execute the steps in the timing debugging method according to the first aspect.

[0030] The embodiments of the present application provide a timing debugging method, a display device and a storage medium. The present application obtains the optimal common voltage of the display panel under a preset gray scale, determines the number of measurement points on the display panel according to the number of chip on films, the number of measurement points is positively correlated with the number of chip on films, obtains the optimal charging time of each measurement point according to the optimal common voltage, and adjusts the timing of the scan signal and the data signal input to the display panel according to the optimal charging time. Since the number of measurement points is positively correlated with the number of chip on films, the number of measurement points increases with the increase of the number of chip on films. The present application improves the debugging effect by increasing the number of measurement points, can obtain more accurate delay time, eliminates visual flicker, further improves the display quality and enhances the use experience. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a schematic diagram of a scenario for setting the measuring points on the display panel in an embodiment of this application;

[0033] Figure 2 This is a schematic diagram of the structure of a display device provided in an embodiment of this application;

[0034] Figure 3 A flowchart illustrating a timing debugging method provided in this application embodiment;

[0035] Figure 4 A schematic diagram of a scenario providing a sub-display area and a control area of ​​a display panel for embodiments of this application;

[0036] Figure 5 This is another schematic diagram illustrating the measurement point settings of the display panel in this application embodiment. Detailed Implementation

[0037] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0038] In the description of this application, it should be understood that the terms "one end," "the other end," etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, the meaning of "" is two or more, unless otherwise explicitly specified.

[0039] In the description of the present application, it is necessary to point out that, unless otherwise explicitly specified and limited, the terms "connected" and "connection" should be understood in a broad sense, for example, it can be fixed connection, or detachable connection, or integrally connected; it can be mechanical connection, or connection, or can communicate with each other; it can be directly connected, or indirectly connected through intermediate medium, it can be the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0040] The following disclosure provides many different embodiments or examples for implementing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, reference numerals and / or reference letters can be repeated in different examples in the present application. Such repetition is for the purpose of simplification and clarity, and in itself does not indicate the relationship between the various embodiments and / or settings discussed. In the above embodiments, the description of each embodiment is focused on, and the part not described in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0041] The liquid crystal display device comprises a liquid crystal display panel and a drive circuit, wherein the liquid crystal display panel comprises a plurality of scan lines and a plurality of data lines, and two adjacent scan lines and two adjacent data lines cross to form a pixel unit. The drive circuit comprises a gate drive circuit and a source drive circuit. Taking a thin film transistor (TFT) liquid crystal display device as an example, each pixel unit comprises at least one TFT. The basic working principle of the liquid crystal display panel and the drive circuit is that the gate drive circuit sends out a gate drive signal to the scan line through the pull-up transistor electrically connected with the scan line, sequentially opens the TFT of each row, and then the source drive circuit sends out a data signal to the data line, and simultaneously charges a whole row of pixel units to the required voltage of each pixel unit to display different gray scales. That is, the first row of thin film transistors is opened by the pull-up transistor of the first row of gate drive circuits, and then the first row of pixel units is charged by the source drive circuit. When the first row of pixel units is fully charged, the gate drive circuit closes the thin film transistor of the row, and then the second row of gate drive circuits opens the thin film transistor of the second row through the pull-up transistor, and then the source drive circuit charges and discharges the pixel units of the second row. In this way, when the pixel units of the last row are fully charged, the charging starts from the first row again. In this way, when the display panel is controlled to refresh the picture at a corresponding refresh frequency, the picture is displayed at a preset brightness.

[0042] Typically, the luminance of each pixel can be defined by "grayscale". Grayscale refers to dividing the luminance of a pixel from its brightest to its darkest point into several levels, with each grayscale representing a brightness level. Generally, each pixel in a display panel has a total of 256 grayscale levels, from 0 to 255.

[0043] One method for adjusting the charging timing of a display panel mainly consists of five parts: S1, confirming that the CFcom voltage (i.e., common voltage) of the display panel is consistent with the CFcom voltage on the control board; S2, measuring the optimal charging time at each point on the display panel; S3, adjusting the delay of the scan signal; S4, adjusting the delay of the data signal inside the COF (Chip On Film); S5, adjusting the delay of the data signal between COFs on the display panel. If the CFcom voltage of the display panel is inconsistent with the CFcom voltage on the control board, it will cause noticeable flickering on the screen, which will affect the accuracy of measuring the optimal charging time in the next step. Measuring the optimal charging time at each point on the display panel provides data support for subsequent adjustments to the delays of the scan and data signals. Adjusting the delay of the scan signal can make the brightness of the display panel more uniform in the vertical direction. Adjusting the delay of the data signal inside the COF can make the brightness of the corresponding display panel area in the horizontal direction more uniform. After making the brightness of the corresponding display panel area in the horizontal direction uniform, adjusting the delay of the data signal between COFs can make the brightness of the entire display panel more uniform in the horizontal direction. In detail, the above five parts are implemented as follows:

[0044] The first step in debugging the display panel charging timing, namely step S1, is as follows: Under a flickering screen at grayscale 127, measure the optimal CF com voltage on the panel and confirm whether the optimal CF com voltage on the panel is consistent with the CF com voltage on the control board. If they are inconsistent, the CF com voltage on the control board needs to be changed.

[0045] The second step, S2, in debugging the display panel charging timing is to measure the optimal charging time of the display panel. For example... Figure 1 As shown, the optimal charging time is measured at 9 points on the display panel. However, for display panels with a larger area of ​​55 inches or more, measuring only 9 points is not sufficient to meet the requirements for adjusting the charging sequence of the display panel. If the debugging personnel need to measure the optimal charging time at more than 9 points, it will affect the efficiency of the display panel debugging.

[0046] The third step, S3, in debugging the display panel charging timing is to adjust the delay of the scan signal. Based on the optimal charging time data, such as... Figure 1As shown, the display area 11 of the display panel 1 is divided into two areas: the upper half and the lower half. The minimum value of the difference between the optimal charging time of the measuring point 1 and the measuring point 4, the optimal charging time of the measuring point 2 and the measuring point 5, and the optimal charging time of the measuring point 3 and the measuring point 6 is taken to adjust the delay of the scanning signal. The minimum value of the difference between the optimal charging time of the measuring point 4 and the measuring point 7, the optimal charging time of the measuring point 5 and the measuring point 8, and the optimal charging time of the measuring point 6 and the measuring point 9 is taken to adjust the delay time of the scanning signal.

[0047] The fourth step S4 of adjusting the charging time sequence of the display panel 1 is to adjust the delay of the internal data signal of the COF. According to the data of the optimal charging time, the delay of the internal data signal of the COF is set.

[0048] The fifth step S5 of adjusting the charging time sequence of the display panel 1 is to adjust the delay of the data signal between the COFs. According to the data of the optimal charging time and the split-screen phenomenon under the G48 picture and the Y48 picture, the delay of the data signal between the COFs is set. After the adjustment, the CCT (Color Cross-talk) of the 19 points of the display panel 1 is measured to evaluate the charging level of the display panel 1.

[0049]

[0050] wherein L W255 is the luminance of the white picture of the gray scale 255, L R255 is the luminance of the red picture of the gray scale 255, L G255 is the luminance of the green picture of the gray scale 255, L B255 is the luminance of the blue picture of the gray scale 255, and L K255 is the luminance of the black picture.

[0051] Since there are various components such as resistors and capacitors in the internal circuit of the display panel 1 of the display product, the waveforms of the scanning signal and the data signal will change and delay when passing through these components. If the delay steps of the scanning signal and the data signal are inconsistent, the theoretically set charging time will not be the actual optimal charging time of the display panel 1, which will directly affect the brightness and chroma of each sub-pixel, and therefore it is crucial to evaluate the charging time sequence of the display product (including the delay time of the scanning signal, the delay time of the data signal of each measuring point in the control area 121 connected by the COF, and the delay time of the data signal of the control area 121 connected by the adjacent COF in the horizontal direction) for the effect of the display quality. Since the size of the display panel 1 is different, it is necessary to use a small number of measuring points to measure the optimal charging time of the display panel 1 for a larger size display panel 1. If the measuring points are not enough, the optimal charging time of the display panel 1 cannot be accurately measured, which will directly affect the brightness and chroma of each sub-pixel, and therefore it is crucial to evaluate the charging time sequence of the display product (including the delay time of the scanning signal, the delay time of the data signal of each measuring point in the control area 121 connected by the COF, and the delay time of the data signal of the control area 121 connected by the adjacent COF in the horizontal direction) for the effect of the display quality. Figure 1As shown in FIG. 1, the whole display panel 1 still uses 9 measuring points, which may not meet the charging timing requirement of adjusting the large-size display panel 1, thereby leading to inaccurate optimal charging time measured for the large-size display panel 1.

[0052] The present application provides a timing debugging method, a display device 100 and a storage medium. The display panel 1 in the embodiment of the present application can be used in a mobile phone, a tablet computer, a desktop computer, a laptop computer, an electronic reader, a handheld computer, an electronic display screen, a notebook computer, an ultra-mobile personal computer (UMPC), a netbook, a cellular phone, a personal digital assistant (PDA), an augmented reality (AR) \ virtual reality (VR) device, a media player, a wearable device, a digital camera, a car navigation device, etc.

[0053] The display panel 1 can be a liquid crystal display panel. The present application does not limit the type of the liquid crystal display panel. The liquid crystal display panel provided by the present application can be a horizontal electric field type liquid crystal display panel, such as a fringe field switching (FFS) type liquid crystal display panel or an in-plane switching (IPS) type liquid crystal display panel, or a vertical electric field type liquid crystal display panel, such as a twisted nematic (TN) type liquid crystal display panel or a multi-domain vertical alignment (MVA) type liquid crystal display panel.

[0054] The timing debugging method, the display device 100 and the storage medium of the present application are described below in conjunction with the accompanying drawings of the specification to solve the above problems.

[0055] Please refer to Figure 2 and Figure 3 , Figure 2 FIG. 1 is a structural schematic diagram of a display device 100 provided by an embodiment of the present application, Figure 3 FIG. 2 is a flowchart of a timing debugging method provided by an embodiment of the present application. The timing debugging method is applied to a display device 100. The display device 100 includes a display panel 1, N chip-on-film (COF) chips 3 attached to the display panel 1, and a control board 2 connected with the COF chips 3. The number of the COF chips 3 is positively correlated with the area of the display panel 1. As shown in FIG. 1, the timing debugging method includes the following steps. Figure 3

[0056] ​S100, acquire the optimal common voltage of the display panel 1 under a preset gray scale.

[0057] Specifically, the optimal common voltage of the display panel 1 under multiple preset gray scales can be acquired. Assuming that the multiple preset gray scales are at least two gray scales or at least three gray scales, the at least three gray scales are respectively taken from low gray scales, middle gray scales and high gray scales, the charging time of 0-255 full gray scales can be better considered, so that the optimal charging time can have better display brightness under each gray scale.

[0058] The value range of the gray scale number of the low gray scale can be 0-48; the value range of the gray scale number of the middle gray scale can be 49-128; and the value range of the gray scale number of the high gray scale can be 129-255.

[0059] In one of the embodiments, the gray scale number of the low gray scale is 48, the gray scale number of the middle gray scale is 127 (or 128), and the gray scale number of the high gray scale is 255. The optimal charging time obtained by taking the three gray scales as 48, 127 (or 128) and 255 respectively can minimize the risk of charging error.

[0060] The acquiring of the optimal common voltage of the display panel 1 under the preset gray scale includes:

[0061] S101, drive the display panel 1 to display a flicker picture under the preset gray scale, and determine the common voltage corresponding to the minimum flicker value as the optimal common voltage.

[0062] Specifically, in the use process of the liquid crystal panel, the polarity switching of the common electrode signal (VCOM) will produce horizontal stripe flicker phenomenon, which is generally called Flicker phenomenon. The numerical value of the Flicker flicker value directly reflects the quality reliability of the liquid crystal panel. The common voltage of the display panel 1 can be adjusted so that the numerical value of the Flicker flicker value is the smallest, and the VCOM value corresponding to the minimum flicker value is the optimal common voltage.

[0063] Since the display panel 1 can be composed of red sub-pixels, green sub-pixels and blue sub-pixels, the red optimal common voltage, the green optimal common voltage and the blue optimal common voltage can be obtained respectively. Of course, the display panel 1 can also be composed of red sub-pixels, green sub-pixels, blue sub-pixels, white sub-pixels and black sub-pixels, so the red optimal common voltage, the green optimal common voltage, the blue optimal common voltage, the white optimal common voltage and the black optimal common voltage can also be obtained respectively. Among them, the red optimal common voltage is the optimal common voltage obtained by testing the red pure color picture at a preset gray scale, the green optimal common voltage is the optimal common voltage obtained by testing the green pure color picture at a preset gray scale, the blue optimal common voltage is the optimal common voltage obtained by testing the blue pure color picture at a preset gray scale, the white optimal common voltage is the optimal common voltage obtained by testing the white pure color picture at a preset gray scale, and the black optimal common voltage is the optimal common voltage obtained by testing the black pure color picture at a preset gray scale. The display panel 1 displays the red pure color picture, the green pure color picture, the blue pure color picture and the white pure color picture in turn at a preset gray scale. The luminance of the red pure color picture, the green pure color picture, the blue pure color picture, the white pure color picture and the black pure color picture displayed by the display panel 1 can be tested in turn by using a luminance meter or a photosensitive diode, so as to obtain red luminance information, green luminance information, blue luminance information, white luminance information and black luminance information. After obtaining the red luminance information, the green luminance information, the blue luminance information, the white luminance information and the black luminance information respectively, the red weight coefficient, the green weight coefficient, the blue weight coefficient, the white weight coefficient and the black weight coefficient are calculated according to the red luminance information, the green luminance information, the blue luminance information, the white luminance information and the black luminance information respectively.

[0064] Among them, the red weight coefficient is equal to the red luminance information divided by the luminance sum value, and the luminance sum value is equal to the sum of the red luminance information, the green luminance information, the blue luminance information, the white luminance information and the black luminance information. Similarly, the green weight coefficient, the blue weight coefficient, the white weight coefficient and the black weight coefficient can be calculated. The red optimal common voltage, the green optimal common voltage, the blue optimal common voltage, the white optimal common voltage, the black optimal common voltage, the red weight coefficient, the green weight coefficient, the blue weight coefficient, the white weight coefficient and the black weight coefficient are taken as the input of the convergence algorithm, and formula (1) is substituted to obtain the optimal common voltage, wherein formula (1) is:

[0065] VCOM=V R *ΔR+V G *ΔG+V B *ΔB+V W *ΔW+VK AK (1)

[0066] wherein, V R is the optimal common voltage for red, V G is the optimal common voltage for green, V B is the optimal common voltage for blue, V W is the optimal common voltage for white, V K is the optimal common voltage for black, AR is the weight coefficient for red, AG is the weight coefficient for green, AB is the weight coefficient for blue, AW is the weight coefficient for white, and AK is the weight coefficient for black.

[0067] The optimal common voltage of the display panel 1 calculated by comprehensively considering the optimal common voltages corresponding to different color sub-pixels is more accurate, and the Flicker phenomenon can be effectively adjusted. The preset gray scale can be 127 gray scale or 128 gray scale. In the case that the optimal common voltages corresponding to different color pictures of the liquid crystal panel are inconsistent, the application can allocate the deviation between the optimal common voltages of different colors through the weight coefficients corresponding to different colors to ensure the display effect of the display panel 1.

[0068] The above flicker value refers to the flicker value of the display picture corresponding to the preset gray scale calculated according to the difference in brightness between the display pictures before and after the polarity of the electric field of the display panel 1 is reversed. For example, in the case of the polarity reversal mode of frame reversal, the brightness value of the display picture before the polarity of the electric field of the display panel 1 is reversed (corresponding to the positive polarity preset gray scale) is L1, and the brightness value of the display picture after the polarity of the electric field of the display panel 1 is reversed (corresponding to the negative polarity preset gray scale) is L2. In this case, the picture flicker value F can be obtained according to the ratio of the absolute value of the difference between the brightness value L1 of the display picture before reversal and the brightness value L2 of the display picture after reversal to the brightness value L1 of the display picture before reversal, that is, F = —L1-L2— / L1. Here, only frame reversal is taken as an example for description, and of course, it can also be point reversal, line reversal or column reversal, which is not limited in the application.

[0069] S200, according to the number of the chip-on-film chips 3, the number of measuring points on the display panel 1 is determined, and the number of measuring points is positively correlated with the number of the chip-on-film chips 3.

[0070] Specifically, the number of the chip-on-film chips 3 is positively correlated with the area of the display panel 1, and the number of measuring points on the display panel 1 is positively correlated with the number of the chip-on-film chips 3, that is, the larger the area of the display panel 1, the greater the number of the chip-on-film chips 3 attached to the display panel 1, and the greater the number of measuring points provided in the display panel 1. In the application, the measuring point is actually a test point on the display panel 1 that is prone to mischarging.

[0071] In some embodiments, as shown in Figure 4 and Figure 5 The display panel 1 includes a display area extending along a first direction and a second direction, respectively, the second direction being perpendicular to the first direction, the display area being divided into a plurality of sub-display areas 12 along the second direction, the sub-display areas 12 including a plurality of control areas 121, one of the COF chips 3 corresponding to one of the control areas 121, the control areas 121 including a plurality of pixels; the number of measurement points on the display panel 1 is determined according to the number of COF chips 3, the number of measurement points being positively correlated with the number of COF chips 3, comprising:

[0072] Setting a first number;

[0073] According to the number of sub-display areas 12 and the first number, the number of measurement points in the display panel 1 is calculated.

[0074] Specifically, in the embodiments of the present application, the first direction is set as the X-axis direction, and the second direction is set as the Y-axis direction. Along the second direction, the display area can be divided into M sub-display areas 12, each of the sub-display areas 12 including N control areas 121, and the display device 100 being provided with the same number of COF chips 3 as the number of control areas 121. The number of control areas 121 in each sub-display area 12 is the same, and the number of measurement points along the first direction in each control area 121 is the same. The first number can be set according to the area of the display panel 1, wherein the first number is equal to an integer multiple of the number of control areas 121, i.e., the first number W of measurement points along the first direction in the control area 121 is k*N, k is a positive integer greater than 2, N is a positive integer greater than 2, and M is a positive integer greater than 2. Then, the number M of sub-display areas 12 and the first number W are substituted into the following formula (2) to calculate the number Q of measurement points in the display panel 1: Q = M*W = k*M*N.

[0075] Wherein, Q is the number of measurement points in the display panel 1, M is the number of sub-display areas 12 in the display area 11 of the display panel 1, W is the first number of measurement points along the first direction in the control area 121, k is a constant, and N is the number of control areas 121 in the sub-display area 12.

[0076] In some embodiments, the first number is equal to the sum of the number of center measurement points, the number of boundary measurement points, and the number of intermediate measurement points, wherein the line segment formed by connecting the center measurement points, the boundary measurement points, and the intermediate measurement points is parallel to the first direction, and the center measurement points are located at the center points of the control areas 121.

[0077] Specifically, assuming that the number of COFs of the display panel 1, i.e., the number of the COF chips 3, is N, and the area governed or managed by one COF is taken as a control area 121, the display panel 1 is divided into N control areas 121 along a first direction, i.e., the X-axis direction. As shown in FIG. 1, five measuring points are arranged in each control area 121 corresponding to a COF in the first direction, i.e., the horizontal direction. Figure 5

[0078] As shown in FIG. 2, the five measuring points corresponding to each control area 121 are respectively: one measuring point is arranged at the boundary of the control area 121 corresponding to the COF (including the boundary of the control area 121 corresponding to the COF at the boundary of the display panel 1), which is two boundary measuring points n1 and n5; one measuring point is arranged at the center point of the control area 121 corresponding to the COF, which is one center measuring point n3; and one measuring point is arranged at the center position between the center point and the boundary point of the control area 121 corresponding to the COF, which is two intermediate measuring points n2 and n4. Therefore, as shown in FIG. 2, the first number of measuring points in each control area 121 along the first direction is five. Figure 5 Figure 5 As shown in FIG. 3, the display panel 1 is divided into nine sub-display areas 12 in the second direction, i.e., the vertical direction, so that a total of 9(4N+1) measuring points are marked in the display panel 1. For example, the display panel 1 with four COFs needs to mark 153 measuring points; the display panel 1 with three COFs needs to mark 117 measuring points; the display panel 1 with five COFs needs to mark 189 measuring points; and the display panel 1 with six COFs needs to mark 225 measuring points.

[0079] Of course, in other embodiments, the number of intermediate measuring points can also be zero, four, six, eight or more, so that the first number of measuring points in each control area 121 along the first direction can be three, seven, nine, eleven or more. In summary, the number Q of measuring points arranged in the display panel 1 in the present application is Q=M*W=k*M*N=k*M*(3+P).

[0080] Wherein, Q is the number of measuring points in the display panel 1, M is the number of sub-display areas 12 in the display area 11 of the display panel 1, W is the first number of measuring points in the control area 121 along the first direction, k is a constant, N is the number of control areas 121 in the sub-display area 12, and P is the number of intermediate measuring points between the center point and the boundary point.

[0081] After the optimal common voltage of the display panel 1 at a preset gray scale is obtained, the number of measuring points on the display panel 1 is determined according to the number of the COF chips 3 before the display panel 1 is divided into control areas 121.

[0082] ​​S110, judging whether the optimal common voltage is same as an output common voltage provided by the control board 2 to the display panel 1;

[0083] S120, adjusting the output common voltage until it is equal to the optimal common voltage if the optimal common voltage is different from the output common voltage.

[0084] Specifically, after obtaining the optimal common voltage of the display panel 1 under the preset gray scale through the above embodiment, the output common voltage provided by the control board 2 to the display panel 1 can be obtained from the output port of the control board 2 or directly obtained from the control board 2, and then whether the optimal common voltage is same as the output common voltage provided by the control board 2 to the display panel 1 is compared. If the optimal common voltage is same as the output common voltage, the brightness values of all the measuring points in the display panel 1 can be measured by the luminance meter or the photo diode. If the optimal common voltage is different from the output common voltage, the output common voltage provided by the control board 2 to the display panel 1 is adjusted according to the size relationship between the optimal common voltage and the output common voltage, that is, if the optimal common voltage is greater than the output common voltage, the output common voltage is adjusted to be lower, if the optimal common voltage is less than the output common voltage, the output common voltage is adjusted to be higher, until the adjusted output common voltage is equal to the optimal common voltage of the display panel 1 under the preset gray scale.

[0085] S300, obtaining the optimal charging time corresponding to each of the measuring points according to the optimal common voltage.

[0086] Specifically, the brightness values corresponding to each of the measuring points in the display panel 1 can be measured by the luminance meter or the photo diode, and then the optimal charging time corresponding to each of the measuring points can be calculated.

[0087] In some embodiments, the obtaining the optimal charging time corresponding to each of the measuring points according to the optimal common voltage comprises:

[0088] S310, obtaining the brightness curve corresponding to each of the measuring points in the display panel 1 under the optimal common voltage and different panel charging times, wherein each of the brightness curves comprises the brightness values corresponding to the measuring points under different panel charging times;

[0089] S320, determining the panel charging time corresponding to the maximum brightness value in the brightness curve as the optimal charging time corresponding to the measuring point.

[0090] Specifically, the display panel 1 is provided with different initial charging times or default charging times under different gray scales. After the optimal common voltage of the display panel 1 under a preset gray scale is obtained through the above embodiment, the display panel 1 is controlled to display a picture under the corresponding optimal common voltage, and the initial charging time of the display panel 1 is adjusted, and then the initial charging time of any measuring point n r corresponding to the initial charging time, so that the brightness value corresponding to the initial charging time of the measuring point n r corresponding to the initial charging time is drawn to obtain a corresponding brightness curve Ln r , so as to obtain the panel charging time corresponding to the maximum brightness value of the measuring point n r corresponding to the initial charging time. r corresponding to the initial charging time. r corresponding to the initial charging time. r corresponding to the initial charging time. Similarly, the brightness curve corresponding to each measuring point of the display panel 1 and the optimal charging time corresponding thereto can be obtained.

[0091] S400, adjust the timing of the scan signal and the data signal input to the display panel 1 according to the optimal charging time.

[0092] Specifically, the architecture of each sub-pixel in the display panel 1 is 2TXC, T represents a TFT (Thin Film Transistor), and C represents a storage capacitor. Among them, one TFT is used as a switch tube to control the path of the data line charging the storage capacitor; another TFT is used as a driving tube to receive a driving power (Vdd) and provide a driving current for the display panel 1; the storage capacitor is mainly used to maintain the driving voltage applied to the gate of the driving tube during the light-emitting stage of the display panel 1. The scan signal is a signal input to the switch tube, and the data signal is a signal input to the driving tube.

[0093] The display panel 1 comprises a plurality of sub-pixels, a plurality of scan lines, a plurality of data lines, a plurality of power lines and a plurality of chip-on-film chips 3, each chip-on-film chip 3 comprising a scan signal output unit, a data signal output unit and a PMIC (Power Management IC). The plurality of sub-pixels are arranged in an array along a first direction and a second direction, each row of sub-pixels is provided with a scan line electrically connected to the row of sub-pixels, each row of sub-pixels is provided with a power line electrically connected to the row of sub-pixels, and each column of sub-pixels is provided with a data line electrically connected to the column of sub-pixels. The scan signal output unit is electrically connected to the plurality of scan lines, and the data signal output unit is electrically connected to the plurality of data lines. For each sub-pixel, the data signal Data is provided by the data line, the scan signal Gate is provided by the scan line, and the optimal common voltage Vcom is provided by the power line.

[0094] In some embodiments, the adjustment of the timing of the scan signal comprises:

[0095] S410, the optimal charging time of the measurement point in the first sub-display area 12 close to the control plate 2 along the second direction is subtracted from the optimal charging time of the measurement point in the second sub-display area 12 away from the control plate 2 along the second direction to obtain a first difference value, and the delay time of the scan signal is set according to the minimum value of the first difference value. The first sub-display area 12 and the second sub-display area 12 are symmetric to each other along the center point of the display panel 1 along the second direction.

[0096] Specifically, the two sub-display areas 12 participating in the subtraction calculation of the first difference value according to the optimal charging time of the measurement point in the two sub-display areas 12 along the second direction are symmetric to each other along the center point of the display panel 1 along the second direction, i.e. the two sub-display areas 12 comprise a first sub-display area 1212a close to the control plate 2 along the second direction and a second sub-display area 1212b away from the control plate 2 along the second direction, and the distance between the first sub-display area 1212a and the center point of the display panel 1 is equal to the distance between the second sub-display area 1212b and the center point of the display panel 1. Therefore, the optimal charging time corresponding to all measurement points in the first sub-display area 1212a of the display panel 1 can be obtained, and the optimal charging time corresponding to all measurement points in the second sub-display area 1212b of the display panel 1 can be obtained. The sum of the optimal charging time corresponding to all measurement points in the first sub-display area 1212a is calculated to obtain a first optimal charging time, and the sum of the optimal charging time corresponding to all measurement points in the second sub-display area 1212b is calculated to obtain a second optimal charging time. The first optimal charging time is subtracted from the second optimal charging time to obtain a first difference value, and the delay time of the scan signal is set according to the minimum value of the first difference value.

[0097] The above illustrates an example of dividing the display area 11 into two sub-display areas 12 in the second direction. In a scenario of dividing the display area 11 into at least three sub-display areas 12 in the second direction, for example, as shown in FIG. 2B, the display area 11 of the display panel 1 is equally divided into three sub-display areas 12: an upper half screen (the sub-display area 12 located at the upper end of the display area 11, i.e., the sub-display area 12 away from the control board 2 in the vertical direction), a lower half screen (the sub-display area 12 located at the lower end of the display area 11, i.e., the sub-display area 12 close to the control board 2 in the vertical direction), and a middle screen (the sub-display area 12 located between the upper half screen and the lower half screen). Figure 1 The above illustrates an example of dividing the display area 11 into two sub-display areas 12 in the second direction. In a scenario of dividing the display area 11 into at least three sub-display areas 12 in the second direction, for example, as shown in FIG. 2B, the display area 11 of the display panel 1 is equally divided into three sub-display areas 12: an upper half screen (the sub-display area 12 located at the upper end of the display area 11, i.e., the sub-display area 12 away from the control board 2 in the vertical direction), a lower half screen (the sub-display area 12 located at the lower end of the display area 11, i.e., the sub-display area 12 close to the control board 2 in the vertical direction), and a middle screen (the sub-display area 12 located between the upper half screen and the lower half screen).

[0098] The above illustrates an example of dividing the display area 11 into two sub-display areas 12 in the second direction. In a scenario of dividing the display area 11 into at least three sub-display areas 12 in the second direction, for example, as shown in FIG. 2B, the display area 11 of the display panel 1 is equally divided into three sub-display areas 12: an upper half screen (the sub-display area 12 located at the upper end of the display area 11, i.e., the sub-display area 12 away from the control board 2 in the vertical direction), a lower half screen (the sub-display area 12 located at the lower end of the display area 11, i.e., the sub-display area 12 close to the control board 2 in the vertical direction), and a middle screen (the sub-display area 12 located between the upper half screen and the lower half screen). Figure 1 The above illustrates an example of dividing the display area 11 into two sub-display areas 12 in the second direction. In a scenario of dividing the display area 11 into at least three sub-display areas 12 in the second direction, for example, as shown in FIG. 2B, the display area 11 of the display panel 1 is equally divided into three sub-display areas 12: an upper half screen (the sub-display area 12 located at the upper end of the display area 11, i.e., the sub-display area 12 away from the control board 2 in the vertical direction), a lower half screen (the sub-display area 12 located at the lower end of the display area 11, i.e., the sub-display area 12 close to the control board 2 in the vertical direction), and a middle screen (the sub-display area 12 located between the upper half screen and the lower half screen). Figure 4 The above illustrates an example of dividing the display area 11 into two sub-display areas 12 in the second direction. In a scenario of dividing the display area 11 into at least three sub-display areas 12 in the second direction, for example, as shown in FIG. 2B, the display area 11 of the display panel 1 is equally divided into three sub-display areas 12: an upper half screen (the sub-display area 12 located at the upper end of the display area 11, i.e., the sub-display area 12 away from the control board 2 in the vertical direction), a lower half screen (the sub-display area 12 located at the lower end of the display area 11, i.e., the sub-display area 12 close to the control board 2 in the vertical direction), and a middle screen (the sub-display area 12 located between the upper half screen and the lower half screen). Figure 1 The above illustrates an example of dividing the display area 11 into two sub-display areas 12 in the second direction. In a scenario of dividing the display area 11 into at least three sub-display areas 12 in the second direction, for example, as shown in FIG. 2B, the display area 11 of the display panel 1 is equally divided into three sub-display areas 12: an upper half screen (the sub-display area 12 located at the upper end of the display area 11, i.e., the sub-display area 12 away from the control board 2 in the vertical direction), a lower half screen (the sub-display area 12 located at the lower end of the display area 11, i.e., the sub-display area 12 close to the control board 2 in the vertical direction), and a middle screen (the sub-display area 12 located between the upper half screen and the lower half screen).

[0099] The above illustrates an example of dividing the display area 11 into two sub-display areas 12 in the second direction. In a scenario of dividing the display area 11 into at least three sub-display areas 12 in the second direction, for example, as shown in FIG. 2B, the display area 11 of the display panel 1 is equally divided into three sub-display areas 12: an upper half screen (the sub-display area 12 located at the upper end of the display area 11, i.e., the sub-display area 12 away from the control board 2 in the vertical direction), a lower half screen (the sub-display area 12 located at the lower end of the display area 11, i.e., the sub-display area 12 close to the control board 2 in the vertical direction), and a middle screen (the sub-display area 12 located between the upper half screen and the lower half screen). Figure 1 The above illustrates an example of dividing the display area 11 into two sub-display areas 12 in the second direction. In a scenario of dividing the display area 11 into at least three sub-display areas 12 in the second direction, for example, as shown in FIG. 2B, the display area 11 of the display panel 1 is equally divided into three sub-display areas 12: an upper half screen (the sub-display area 12 located at the upper end of the display area 11, i.e., the sub-display area 12 away from the control board 2 in the vertical direction), a lower half screen (the sub-display area 12 located at the lower end of the display area 11, i.e., the sub-display area 12 close to the control board 2 in the vertical direction), and a middle screen (the sub-display area 12 located between the upper half screen and the lower half screen).

[0100] In some embodiments, the adjustment of the timing of the data signal comprises:

[0101] According to the optimal charging time corresponding to each measuring point in the control area 121 along the first direction, the delay time of the data signal of the corresponding connected COF 3 in the control area 121 is set;

[0102] A second difference value is obtained by subtracting the optimal charging time corresponding to the measuring points in the adjacent control areas 121 along the first direction, and the delay time of the data signal between the adjacent COFs 3 is set according to the second difference value.

[0103] Specifically, the delay of the data signal inside the COF is set as follows: for each row of measuring points, that is, for each control area 121 in each sub-display area 12, the delay time of the data signal inside the same COF control area 121 in the same row of sub-display areas 12 is set according to the optimal charging time of the five measuring points inside and at the boundary of the same COF control area 121. The delay of the data signal between COFs is set as follows: for each row of measuring points, that is, for multiple control areas 121 in each sub-display area 12, the delay time of the data signal between the adjacent COF control areas 121 in the same row of sub-display areas 12 is set according to the second difference value obtained by subtracting the optimal charging time corresponding to all measuring points in the multiple COF control areas 121 in the same row of sub-display areas 12, thereby obtaining the delay time of the data signal between the multiple COF control areas 121 in the same row of sub-display areas 12.

[0104] The present application improves the debugging effect by increasing the number of measuring points, improves the debugging efficiency by simultaneously measuring the brightness of all measuring points at the same charging time by using a brightness meter and integrating the debugging process. Since the number of measuring points is positively correlated with the number of COFs 3, the number of measuring points increases with the increase of the number of COFs 3. The present application can obtain more accurate optimal common voltage, more accurate delay time of the scan signal and the data signal, overcome the phenomenon of partial pixel charging error caused by the timing of the scan signal and the data signal, thereby eliminating visual flicker, further improving the display quality and enhancing the user experience.

[0105] The embodiment of the present application also provides a display device 100, which comprises a display panel 1, a processor and a memory, the processor is connected with the memory through a communication bus, the memory is used for storing computer execution instructions, when the driving mode of the display panel 1 is debugged, the processor executes the computer execution instructions stored in the memory, so that the display device 100 executes the steps in the timing debugging method.

[0106] The memory is an internal storage unit of the display device 100, such as a hard disk or a memory of the display device 100, or the memory is an external storage device of the display device 100, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, or the like. Further, the memory can include both the internal storage unit and the external storage device. The memory is used to store application software and various data installed in the display device 100, or to temporarily store data that has been output or is to be output. The memory stores computer execution instructions that can be executed by the processor, thereby implementing the steps in the timing debugging method.

[0107] The embodiment of the present application further provides a storage medium, which includes computer execution instructions. When the computer execution instructions run on the display device 100, the display device 100 executes the steps in the timing debugging method.

[0108] The storage medium can include a non-volatile and / or volatile memory. The non-volatile memory can include a read-only memory (ROM), a programmable memory (PROM), an electrically programmable memory (EPROM), an electrically erasable programmable memory (EEPROM), or a flash memory, or the like. The volatile memory can include a random access memory (RAM) or an external cache memory, or the like. As an illustration but not limitation, the RAM is available in various forms, such as a static RAM (SRAM), a dynamic RAM (DRAM), a synchronous DRAM (SDRAM), a double data rate SDRAM (DDR SDRAM), an enhanced SDRAM (ESDRAM), a synchronous link DRAM (SLDRAM), a memory bus direct RAM (RDRAM), a direct memory bus dynamic RAM (DRDRAM), and a memory bus dynamic RAM (RDRAM), or the like.

[0109] It should be noted that the storage medium stores one or more computer programs, which are loaded by one or more processors to execute the steps in any timing debugging method provided by the embodiment of the present application.

[0110] Since the computer program stored in the storage medium can execute the steps in any timing debugging method provided by the embodiment of the present application, the beneficial effects of any timing debugging method provided by the embodiment of the present application can be achieved. Details are described in the foregoing embodiments, which will not be repeated here.

[0111] In the above embodiments, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0112] The timing debugging method, the display device 100, and the storage medium provided by the embodiments of the present application are described in detail above, and the principles and implementation manners of the present application are described by applying specific examples. The above description of the embodiments is only used to help understand the technical solutions of the present application and the core ideas thereof; those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can be modified, or some technical features thereof can be replaced equivalently; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A timing debugging method, characterized in that, The method is applied to a display device, the display device including a display panel, N flip-chips attached to the display panel, and a control board connected to the flip-chips, wherein the number of flip-chips is positively correlated with the area of ​​the display panel. Obtain the optimal common voltage of the display panel at a preset grayscale level; The number of measurement points on the display panel is determined based on the number of flip-chip chips, and the number of measurement points is positively correlated with the number of flip-chip chips. The optimal charging time for each of the measurement points is obtained based on the optimal common voltage. The timing of the scan signal and data signal input to the display panel is adjusted according to the optimal charging time; The display panel includes display areas extending along a first direction and a second direction, respectively, the second direction being perpendicular to the first direction, and the display areas being divided into multiple sub-display areas along the second direction; determining the number of measuring points on the display panel based on the number of flip-chip chips includes: Set the first quantity; The number of measuring points in the display panel is calculated based on the number of sub-display areas and the first number. The timing adjustment of the scanning signal includes: The optimal charging time of the measuring point in the first sub-display area near the control board along the second direction is subtracted from the optimal charging time of the measuring point in the second sub-display area away from the control board along the second direction to obtain a first difference. The delay time of the scanning signal is set according to the minimum value of the first difference. The first sub-display area and the second sub-display area are symmetrical to each other along the center point of the display panel in the second direction.

2. The timing debugging method as described in claim 1, characterized in that, The step of obtaining the optimal common voltage of the display panel at a preset grayscale includes: The display panel is driven to display a flickering image under the preset grayscale, and the common voltage corresponding to the minimum flicker value is determined as the optimal common voltage.

3. The timing debugging method as described in claim 1, characterized in that, After obtaining the optimal common voltage of the display panel at a preset grayscale, and before determining the number of measurement points on the display panel based on the number of flip-chip chips, the following steps are included: Determine whether the optimal common voltage is the same as the output common voltage provided by the control board to the display panel; If the optimal common voltage is different from the output common voltage, adjust the output common voltage until it equals the optimal common voltage.

4. The timing debugging method as described in claim 1, characterized in that, The sub-display area includes multiple control areas, and one flip-chip chip controls one control area. The control area includes multiple pixels.

5. The timing debugging method as described in claim 4, characterized in that, The first quantity is equal to the sum of the number of central measuring points, the number of boundary measuring points, and the number of intermediate measuring points, wherein the line segment formed by connecting the central measuring points, the boundary measuring points, and the intermediate measuring points is parallel to the first direction, and the central measuring point is located at the center point of the control area.

6. The timing debugging method according to any one of claims 1 to 4, characterized in that, The step of obtaining the optimal charging time for each of the measuring points based on the optimal common voltage includes: Obtain the brightness curves of each measuring point in the display panel under the optimal common voltage and different panel charging times; each brightness curve includes the brightness value of the measuring point at different panel charging times. The panel charging time corresponding to the maximum brightness value in the brightness curve is determined as the optimal charging time for the measuring point.

7. The timing debugging method as described in claim 4, characterized in that, The timing adjustment of the data signal includes: Based on the optimal charging time corresponding to each measurement point along the first direction within the control area, the delay time of the data signal of the flip-chip connected to the control area is set. The second difference is calculated by subtracting the optimal charging time corresponding to the measurement point in the adjacent control area along the first direction, and the delay time of the data signal between adjacent flip-chip chips is set according to the second difference.

8. A display device, characterized in that, The display device includes a display panel, a memory, and a processor; the memory stores a computer program, and the processor runs the computer program in the memory to perform the steps of the timing debugging method according to any one of claims 1 to 7.

9. A storage medium, characterized in that, The storage medium stores a plurality of instructions adapted for loading by a processor to execute the steps of the timing debugging method according to any one of claims 1 to 7.

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