Managed nvm adaptive cache management

Abstract

This application relates to managed NVM adaptive cache management. In some examples, customizable single level cell (SLC) and multi-level cell (MLC) configurations of memory devices are provided. The configuration (e.g., size and location) of the SLC cache can affect the power consumption, speed, and other performance of the memory device. An operating system of an electronic device to which the memory device is installed can wish to achieve different performance of the device based on certain conditions that the operating system can detect. In this way, the operating system can customize the performance of the memory device by adjusting the performance characteristics of the SLC cache.

Description

[0001] Information related to divisional application

[0002] This application is a divisional application of the invention patent application filed on August 21, 2018, with application number 201880062659.6 and invention title "Managed NVM Adaptive Cache Management".

[0003] Priority application

[0004] This application claims priority to U.S. Application Serial No. 15 / 691,147, filed August 30, 2017, which is incorporated herein by reference in its entirety. Background Technology

[0005] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices. Many different types of memory exist, including volatile and non-volatile memory.

[0006] Volatile memory requires power to maintain its data and includes random access memory (RAM), dynamic random access memory (DRAM), or synchronous dynamic random access memory (SDRAM), etc.

[0007] Non-volatile memory can retain stored data when not powered, and includes flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), static RAM (SRAM), erasable programmable ROM (EPROM), and resistive variable memory, such as phase-change random access memory (PCRAM), resistive random access memory (RRAM), magnetoresistive random access memory (MRAM), or 3D XPoint. TM Memory, etc.

[0008] Flash memory is used as a non-volatile memory for a wide range of electronic applications. Flash memory devices typically contain one or more groups of single-transistor floating-gate or charge-trapping memory cells that allow for high memory density, high reliability, and low power consumption.

[0009] Two common types of flash memory array architectures include NAND and NOR architectures, named after the logical arrangement of their basic memory cell configurations. The memory cells of a memory array are typically arranged in a matrix. In one example, the gate of each floating-gate memory cell in a row of the array is coupled to an access line (e.g., a word line). In a NOR architecture, the drain of each memory cell in a column of the array is coupled to a data line (e.g., a bit line). In a NAND architecture, the drains of each memory cell in a string of the array are coupled together in series, source-to-drain, between the source line and the bit line.

[0010] Both NOR and NAND architecture semiconductor memory arrays are accessed via a decoder that activates a specific memory cell by selecting a word line coupled to the gate of that specific memory cell. In a NOR architecture semiconductor memory array, once activated, the selected memory cell places its data value on the bit line, thereby allowing different currents to flow depending on the programmed state of that particular cell. In a NAND architecture semiconductor memory array, a high bias voltage is applied to the drain-side selected gate (SGD) line. A word line coupled to the gate of each group of non-selected memory cells is driven with a specified pass voltage (e.g., Vpass) to cause each group of non-selected memory cells to operate as pass transistors (e.g., to pass current regardless of the data value they store). Current then flows from the source line through each series-coupled group to the bit line, limited only by the selected memory cell in each group, thereby placing the currently encoded data value of the selected memory cell on the bit line.

[0011] Each flash memory cell in a NOR or NAND architecture semiconductor memory array can be programmed individually or collectively into one or more programmed states. For example, a single-level cell (SLC) can represent one of two programmed states (e.g., 1 or 0), thus representing a data bit.

[0012] However, flash memory cells can also represent one of more than two programmed states, allowing for the manufacture of higher-density memory without increasing the number of memory cells, because each cell can represent more than one binary digit (e.g., more than one bit). Such cells may be referred to as multi-state memory cells, multi-digit cells, or multi-level cells (MLCs). In some instances, MLC can refer to a memory cell that can store two data bits per cell (e.g., one of four programmed states), TLC can refer to a memory cell that can store three data bits per cell (e.g., one of eight programmed states), and QLC can store four data bits per cell. MLC is used in its broader sense herein to refer to any memory cell that can store more than one data bit per cell (i.e., can represent more than two programmed states).

[0013] Traditional memory arrays are two-dimensional (2D) structures arranged on the surface of a semiconductor substrate. To increase memory capacity and reduce cost for a given area, the size of individual memory cells has been reduced. However, there are technological limitations to reducing the size of individual memory cells, and therefore, the memory density of 2D memory arrays is also limited. In response, three-dimensional (3D) memory structures, such as 3D NAND architecture semiconductor memory devices, are being developed to further increase memory density and reduce memory costs.

[0014] Such 3D NAND devices typically comprise strings of memory cells coupled in series (e.g., drain-to-source) between one or more source-side selected gates (SGS) near the source and one or more drain-side selected gates (SGD) near the bit lines. In examples, the SGS or SGD may comprise one or more field-effect transistor (FET) or metal-oxide-semiconductor (MOS) structures. In some examples, the strings extend vertically through multiple vertically spaced layers containing corresponding word lines. Semiconductor structures (e.g., polysilicon structures) may extend adjacent to the memory cell strings to form channels for the memory cells of the strings. In examples of vertical strings, the polysilicon structure may take the form of vertically extending pillars. In some examples, the strings may be “folded” and thus arranged relative to U-shaped pillars. In other examples, multiple vertical structures may be stacked one on top of the other to form a stacked array of memory cell strings.

[0015] Memory arrays or devices can be combined to form the storage of a memory system, such as solid-state drives (SSDs) and universal flash memory (UFS). TM Multimedia Card (MMC) solid-state storage device, embedded MMC device (eMMC) TMSSDs are particularly useful as primary storage devices for computers, offering advantages over traditional hard drives with moving parts in terms of performance, size, weight, strength, operating temperature range, and power consumption. For example, SSDs can have reduced seek time, latency, or other latency associated with disk drives (e.g., electromechanical). SSDs use non-volatile memory cells, such as flash memory cells, to avoid internal battery power requirements, thus allowing for more versatile and compact drives.

[0016] An SSD may include several memory devices, including several dies or logic units (e.g., logic unit numbers or LUNs), and may include one or more processors or other controllers that perform the logic functions required to operate the memory devices or interface with external systems. Such SSDs may include one or more flash memory dies on which several memory arrays and peripheral circuitry are contained. Flash memory arrays may include several blocks of memory cells organized into several physical pages. In many instances, SSDs may also include DRAM or SRAM (or other forms of memory dies or other memory structures). An SSD may receive commands from a host in conjunction with memory operations, such as read or write operations transferring data (e.g., user data and associated integrity data, such as error data and address data) between the memory devices and the host, or erase operations erasing data from the memory devices. Summary of the Invention

[0017] An embodiment of the present invention provides a memory device. The memory device includes: a memory cell array, wherein the memory cells in the array are configurable as a multi-level cell (MLC) configuration or a single-level cell (SLC) configuration; and a controller configured to: receive an instruction to use at least a portion of the memory cell array in the SLC configuration; reconfigure the at least portion of the memory cell array from the MLC configuration to the SLC configuration based at least partially on the instruction; receive incoming data and write the incoming data to the at least portion of the memory cell array in the SLC configuration; and reconfigure the at least portion of the memory cell array from the SLC configuration back to the MLC configuration.

[0018] Another embodiment of the present invention provides a method for operating a memory device. The method includes: receiving an instruction to use at least a portion of a memory cell array of the memory device in a single-level cell (SLC) configuration, wherein the memory cells in the array of the memory device are configurable as either a multi-level cell (MLC) configuration or the single-level cell (SLC) configuration; reconfiguring the at least portion of the memory cell array from the MLC configuration to the SLC configuration, at least partially based on the instruction; receiving incoming data and writing the incoming data to the at least portion of the memory cell array in the SLC configuration; and reconfiguring the at least portion of the memory cell array from the SLC configuration back to the MLC configuration. Attached Figure Description

[0019] In the accompanying drawings, which are not necessarily drawn to scale, similar reference numerals may describe similar components in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar components. The drawings are intended to illustrate, rather than limit, the various embodiments discussed in this document.

[0020] Figure 1 Examples of environments including memory devices according to some embodiments of the present invention are described.

[0021] Figure 2-3 A schematic diagram illustrating an example of a 3D NAND architecture semiconductor memory array according to some embodiments of the present invention.

[0022] Figure 4 Example block diagrams illustrating memory modules according to some embodiments of the present invention.

[0023] Figure 5 A flowchart illustrating the method for controlling the performance of an operating system control device according to some embodiments of the present invention.

[0024] Figure 6 A flowchart illustrating a method for handling write requests at a memory device according to some embodiments of the present invention.

[0025] Figure 7 A flowchart illustrating a method for an operating system to monitor an electronic device and send status indications of the electronic device according to some embodiments of the present invention.

[0026] Figure 8 The memory controller 815 according to some embodiments of the present invention is described.

[0027] Figure 9 This is a block diagram illustrating examples of machines that may implement one or more embodiments according to some examples of the present invention. Detailed Implementation

[0028] Memory devices may include multiple memory cells that can be reconfigured between single-level cell (SLC) and multi-level cell (MLC) configurations. In some instances, the memory device configures some SLC cells to act as a high-speed cache for write requests. Data is first written to the higher-performance SLC cells and then later rewritten to cells configured as MLC cells. The number of cells configured as the SLC cache portion can change during operation of the memory device. For example, when the memory device is full, it can reconfigure SLC cells as MLC cells to increase storage capacity. These techniques provide the storage capacity of a memory device with MLC memory cells to SLC-level performance.

[0029] The configuration (e.g., size and location) of SLC cache memory can affect the power consumption, speed, and other performance characteristics of the memory device. The operating system of an electronic device in which the memory device is installed may wish to achieve different performance characteristics of the device based on certain conditions that the operating system can detect. For example, to achieve lower power consumption in response to low battery conditions, the operating system may instruct the memory device to adjust the behavior of the SLC cache memory to achieve lower power consumption. In other instances, the operating system may infer memory device degradation or other conditions and may send instructions to the device to reconfigure the device to have more SLC storage (more reliable) or to compress or delete external files (which may have the effect of reducing LBA utilization and thus migrating MLC to SLC cache memory). In this way, the operating system can customize the performance of the memory device by adjusting the performance characteristics of the SLC cache memory, either explicitly by sending messages or implicitly by changing the storage on the memory device to cause a shift in the performance of the SLC cache memory.

[0030] For example, electronic devices such as mobile electronic devices (e.g., smartphones, tablets, etc.), electronic devices for automotive applications (e.g., automotive sensors, control units, driver assistance systems, passenger safety or comfort systems, etc.), and Internet-connected electrical appliances or devices (e.g., Internet of Things (IoT) devices, etc.) have varying storage needs, depending on the type of electronic device, the environment in which it is used, and performance expectations.

[0031] Electronic devices can be broken down into several main components: a processor (e.g., a central processing unit (CPU) or other main processor); memory (e.g., one or more volatile or non-volatile random access memory (RAM) devices, such as dynamic RAM (DRAM), mobile or low-power dual data rate synchronous DRAM (DDR SDRAM), etc.); and storage devices (e.g., non-volatile memory (NVM) devices, such as flash memory, read-only memory (ROM), SSD, MMC, or other memory card structures or assemblies, etc.). In some instances, electronic devices may include a user interface (e.g., a display, touchscreen, keyboard, one or more buttons, etc.), a graphics processing unit (GPU), a power management circuitry, a baseband processor, or one or more transceiver circuits, etc.

[0032] Figure 1 The description includes an example of an environment 100 configured to communicate via a communication interface, comprising a host 105 and a memory device 110. The host 105 or memory device 110 may be included in a variety of products 150, such as Internet of Things (IoT) devices (e.g., refrigerators or other appliances, sensors, motors or actuators, mobile communication devices, automobiles, drones, etc.) to support the processing, communication, or control of the product 150.

[0033] Memory device 110 includes a memory controller 115 and a memory array 120 comprising, for example, several individual memory devices (e.g., a stack of three-dimensional (3D) NAND dies). In 3D architecture semiconductor memory technology, vertical structures are stacked, thereby increasing the number of layers, physical pages, and thus the density of memory devices (e.g., storage devices). In one example, memory device 110 may be a discrete memory or storage device component of host 105. In other examples, memory device 110 may be part of an integrated circuit (e.g., a system-on-a-chip (SoC), etc.) that is stacked or otherwise incorporated with one or more other components of host 105.

[0034] Data can be transferred between the memory device 110 and one or more other components of the host 105 using one or more communication interfaces, such as Serial Advanced Technology Attachment (SATA) interface, Peripheral Component Interconnect High Speed ​​(PCIe) interface, Universal Serial Bus (USB) interface, Universal Flash Memory (UFS) interface, and eMMC. TM An interface or one or more other connectors or interfaces. Host 105 may include a host system, electronic devices, a processor, a memory card reader, or one or more other electronic devices external to memory device 110. In some instances, host 105 may be a device with a reference... Figure 9 The machine 900 is a component of the machine, or all of the components discussed.

[0035] The memory controller 115 may receive instructions from the host 105 and may communicate with the memory array to transfer data to or from one or more memory cells, planes, sub-blocks, blocks, or pages of the memory array (e.g., write or erase). The memory controller 115 may, in particular, include circuitry or firmware comprising one or more components or integrated circuits. For example, the memory controller 115 may include one or more memory control units, circuitry, or components configured to control access across the memory array 120 and provide a translation layer between the host 105 and the memory device 110. The memory controller 115 may include one or more input / output (I / O) circuitry, lines, or interfaces to transfer data to or from the memory array 120. The memory controller 115 may include a memory manager 125 and an array controller 135.

[0036] The memory manager 125 may include, in particular, circuitry or firmware, such as components or integrated circuits associated with various memory management functions. For the purposes of this description, example memory operation and management functions will be described in the context of NAND memory. Those skilled in the art will recognize that other forms of non-volatile memory may have similar memory operation or management functions. Such NAND management functions include wear leveling (e.g., garbage collection or recycling), error detection or correction, block termination, or one or more other memory management functions. The memory manager 125 may parse or format host commands (e.g., commands received from the host) into device commands (e.g., commands associated with the operation of the memory array, etc.), or generate device commands for the array controller 135 or one or more other components of the memory device 110 (e.g., to implement various memory management functions).

[0037] Memory manager 125 may include a set of management tables 130 configured to maintain various information associated with one or more components of memory device 110 (e.g., various information associated with a memory array or one or more memory cells coupled to memory controller 115). For example, management table 130 may contain information about block age, block erase count, error history, or one or more error counts (e.g., write operation error count, read bit error count, read operation error count, erase error count, etc.) of one or more memory cell blocks coupled to memory controller 115. In some instances, a bit error may be termed an uncorrectable bit error if the number of detected errors for one or more of the error counts exceeds a threshold. Management table 130 may specifically maintain counts of correctable or uncorrectable bit errors.

[0038] The array controller 135 may in particular include circuitry or components configured to control memory operations associated with writing data to, reading data from, or erasing memory cells of the memory device 110 coupled to the memory controller 115. Memory operations may be based on host commands (e.g., associated with wear leveling, error detection, or correction) received, for example, from the host 105 or generated internally by the memory manager 125.

[0039] Array controller 135 may include an error correction code (ECC) component 140, which may in particular include an ECC engine or other circuitry configured to detect or correct errors associated with writing or reading data from one or more memory cells of memory device 110 coupled to memory controller 115. Memory controller 115 may be configured to effectively detect and recover from errors associated with various operations or data storage (e.g., bit errors, operational errors, etc.), while maintaining the integrity of data transferred between host 105 and memory device 110, or maintaining the integrity of stored data (e.g., using redundant RAID storage, etc.), and may remove (e.g., retire) faulty memory resources (e.g., memory cells, memory arrays, pages, blocks, etc.) to prevent future errors.

[0040] Memory array 120 may contain a number of memory cells arranged, for example, in devices, planes, sub-blocks, blocks, or pages. As an example, a 48GB TLC NAND memory device may contain 18,592 bytes (B) of data per page (16,384 + 2208 bytes), 1536 pages per block, 548 blocks per plane, and four or more planes per device. As another example, a 32GB MLC memory device (each cell storing two data bits (i.e., four programmable states)) may contain 18,592 bytes (B) of data per page (16,384 + 2208 bytes), 1024 pages per block, 548 blocks per plane, and four planes per device, but requires half the write time and twice the program / erase (P / E) cycles compared to a corresponding TLC memory device. Other examples may contain other numbers or arrangements. In some examples, the memory device or portions thereof may operate selectively in SLC mode or in a desired MLC mode (e.g., TLC, QLC, etc.).

[0041] During operation, data is typically written to or read from NAND memory device 110 in pages and erased in blocks. However, one or more memory operations (e.g., read, write, erase, etc.) may be performed on larger or smaller groups of memory cells as needed. The data transfer size of NAND memory device 110 is typically referred to as a page, while the data transfer size of the host is typically referred to as a sector.

[0042] While a data page may contain several bytes of user data (e.g., a data payload consisting of several data sectors) and its corresponding metadata, the page size often refers only to the number of bytes used to store the user data. As an example, a data page with a page size of 4KB may contain 4KB of user data (e.g., eight sectors of a sector size assuming 512B) and several bytes of metadata corresponding to the user data (e.g., 32B, 54B, 224B, etc.), such as integrity data (e.g., error detection or correction code data), address data (e.g., logical address data, etc.), or other metadata associated with the user data.

[0043] Different types of memory cells or memory arrays 120 may offer different page sizes, or may require different amounts of metadata associated with them. For example, different memory device types may have different bit error rates, which may result in different amounts of metadata being required to ensure the integrity of data pages (e.g., a memory device with a higher bit error rate may require more bytes of error correction code data than a memory device with a lower bit error rate). As an example, a multi-level cell (MLC) NAND flash device may have a higher bit error rate than its corresponding single-level cell (SLC) NAND flash device. Therefore, an MLC device may require more bytes of metadata for error data than its corresponding SLC device.

[0044] Figure 2 The description includes several memory cell strings (e.g., the first to third A0 memory strings 205A0-207A0 ... n Memory String 205A n -207A n The first to third B0 memory strings are 205B0-207B0, the first to third B0 n Memory String 205B n -207B n A schematic diagram of an example of a 3D NAND architecture semiconductor memory array 200, wherein the memory cell strings are organized into blocks (e.g., block A 201A, block B 201B, etc.) and sub-blocks (e.g., sub-block A0 201A0, sub-block A0 201A0, etc.). n 201A n Sub-block B0201B0, Sub-block B n201B n (etc.). Memory array 200 represents a portion of a large number of similar structures that are typically found in blocks, devices, or other cells of a memory device.

[0045] Each memory cell string contains several layers of charge storage transistors (e.g., floating gate transistors, charge-structures, etc.), which are stacked in the Z direction in a source-to-drain manner on the source line (SRC) 235 or the source-side selected gate (SGS) (e.g., first to third A0 SGS231A0-233A0, first to third A...). n SGS 231A n -233A n First to third B0 SGS231B0-233B0, first to third B n SGS231B n -233B n (etc.) and drain-side selected gate (SGD) (e.g., first to third A0 SGD 226A0-228A0, first to third A n SGD 226A n -228A n First to third B0 SGD 226B0-228B0, first to third B n SGD 226B n -228B n Between (etc.). Each string of memory cells in a 3D memory array can be arranged as data lines (e.g., bit lines (BL) BL0-BL2 220-222) along the X direction and as physical pages along the Y direction.

[0046] Within a physical page, each level represents a row of memory cells, and each string of memory cells represents a column. A sub-block may contain one or more physical pages. A block may contain several sub-blocks (or physical pages) (e.g., 128, 256, 384, etc.). Although described herein as having two blocks, each block having two sub-blocks, each sub-block having a single physical page, each physical page having three strings of memory cells, and each string having eight levels of memory cells, in other instances, the memory array 200 may contain more or fewer blocks, sub-blocks, physical pages, strings of memory cells, memory cells, or levels. For example, each string of memory cells may contain more or fewer levels as needed (e.g., 16, 32, 64, 128, etc.), and one or more additional layers of semiconductor material above or below charge storage transistors (e.g., select gates, data lines, etc.). As an example, a 48GB TLC NAND memory device may contain 18,592 bytes (B) of data per page (16,384+2208 bytes), 1536 pages per block, 548 blocks per plane, and 4 or more planes per device.

[0047] Each memory cell in the memory array 200 includes a control gate (CG) coupled to (e.g., electrically connected or otherwise operably connected to) access lines (e.g., word lines (WL) WL00-WL70 210A-217A, WL01-WL71 210B-217B, etc.), which, as needed, cross a specific layer or a portion of a layer and jointly couple the control gate (CG). A specific memory cell in a specific layer and therefore a string within the 3D memory array can be accessed or controlled using the corresponding access lines. Various select lines can be used to access select gate groups. For example, the first to third A0 SGD 226A0-228A0 can be accessed using the A0 SGD line SGDA0 225A0, and A... n SGD line SGDA n 225A n Accessing the first to third A n SGD226A n -228A n You can use B0 SGD line SGDB0 225B0 to access the first to third B0 SGD 226B0-228B0, and you can use B n SGD line SGDB n 225B n Accessing the first to third B n SGD 226B n -228B n The first to third A0 gates (SGS231A0-233A0) and the first to third A0 gates (SGS231A0-233A0) can be accessed using the gate select lines SGS0 230A. nSGS231A n -233A n Furthermore, the gate select lines SGS1 230B can be used to access the first to third B0 SGS231B0-233B0 and the first to third B0. n SGS231B n -233B n .

[0048] In an example, memory array 200 may comprise several layers of semiconductor material (e.g., polysilicon, etc.) configured to couple a control gate (CG) or select gate (or a portion of a CG or select gate) to each memory cell in a corresponding layer of the array. A particular string of memory cells in the array can be accessed, selected, or controlled using a combination of bit lines (BLs) and select gates, and a particular memory cell at one or more layers within a particular string can be accessed, selected, or controlled using one or more access lines (e.g., word lines).

[0049] Figure 3 This is an example schematic diagram illustrating a portion of a NAND architecture semiconductor memory array 300, which includes a plurality of memory cells 302 arranged in a two-dimensional array of strings (e.g., first to third strings 305-307) and layers (e.g., shown as corresponding word lines (WL) WL0-WL7310-317, drain-side selected gate (SGD) line 325, source-side selected gate (SGS) line 330, etc.), and a sense amplifier or device 360. For example, the memory array 300 may illustrate, for instance... Figure 2 This is a schematic diagram illustrating an example of a portion of a physical page of a memory cell in a 3D NAND architecture semiconductor memory device.

[0050] Each memory cell string is coupled to a source line (SRC) using a corresponding source-side selected gate (SGS) (e.g., first to third SGS 331-333) and to a corresponding data line (e.g., first to third bit lines (BL) BL0-BL2 320-322) using a corresponding drain-side selected gate (SGD) (e.g., first to third SGD 326-328). Although in Figure 3 The example is described as having 8 levels (e.g., using word lines (WL) WL0-WL7 310-317) and three data lines (BL0-BL2 326-328), but other examples may contain strings of memory cells with more or fewer levels or data lines as needed.

[0051] In a NAND architecture semiconductor memory array such as example memory array 300, the state of a selected memory cell 302 can be accessed by sensing current or voltage changes associated with a specific data line containing the selected memory cell. Memory array 300 can be accessed using one or more drivers (e.g., via control circuitry, one or more processors, digital logic, etc.). In this example, depending on the type of desired operation to be performed on a particular memory cell or group of memory cells, one or more drivers can activate a particular memory cell or group of memory cells by driving a specific potential to one or more data lines (e.g., bit lines BL0-BL2), access lines (e.g., word lines WL0-WL7), or a select gate.

[0052] To program or write data to a memory cell, a programming voltage (Vpgm) (e.g., one or more programming pulses, etc.) may be applied to a selected word line (e.g., WL4), and thus to the control gate of each memory cell coupled to the selected word line (e.g., the first to third control gates (CG) 341-343 of the memory cell coupled to WL4). The programming pulse may begin, for example, at or near 15V, and in some instances, the amplitude may be increased during each programming pulse application. While the programming voltage is applied to the selected word line, a potential, for example, ground potential (e.g., Vss), may be applied to the data line (e.g., bit line) and substrate (and thus the channel between the source and drain) of the target memory cell, resulting in charge transfer from the channel to the floating gate of the target memory cell (e.g., direct injection or Fowler-Nordheim (FN) tunneling, etc.).

[0053] In contrast, a pass voltage (Vpass) can be applied to one or more word lines having memory cells not intended for programming, or a disable voltage (e.g., Vcc) can be applied to data lines (e.g., bit lines) having memory cells not intended for programming, such that charge transfer from the channel to the floating gate of such non-target memory cells is disabled, for example. The pass voltage can vary, for example, depending on the proximity of the applied pass voltage to the word line intended for programming. The disable voltage can include a supply voltage (Vcc), such as a voltage from an external source or power supply (e.g., a battery, AC-DC converter, etc.) relative to a ground potential (e.g., Vss).

[0054] As an example, if a programming voltage (e.g., 15V or higher) is applied to a specific word line, such as WL4, then a 10V pass-through voltage can be applied to one or more other word lines, such as WL3, WL5, etc., to prevent programming of non-target memory cells or to preserve the values ​​stored on such memory cells that are not intended for programming. As the distance between the applied programming voltage and the non-target memory cell increases, the pass-through voltage required to prevent programming of the non-target memory cell can decrease. For example, when a 15V programming voltage is applied to WL4, a 10V pass-through voltage can be applied to WL3 and WL5, an 8V pass-through voltage to WL2 and WL6, and a 7V pass-through voltage to WL1 and WL7, etc. In other examples, the pass-through voltage or the number of word lines can be higher or lower, or larger or smaller.

[0055] One or more sense amplifiers 360 coupled to data lines (e.g., first, second, third, or fourth bit lines (BL0-BL2) 320-322) can detect the state of each memory cell in the corresponding data line by sensing the voltage or current on the specific data line.

[0056] Between the application of one or more programming pulses (e.g., Vpgm), a verification operation can be performed to determine whether the selected memory cell has reached its intended programmed state. If the selected memory cell has reached its intended programmed state, further programming can be prevented. If the selected memory cell has not yet reached its intended programmed state, additional programming pulses can be applied. If the selected memory cell has not reached its intended programmed state after a certain number of programming pulses (e.g., a maximum number), the selected memory cell, or the string, block, or page associated with such selected memory cell, can be marked as defective.

[0057] To erase a memory cell or group of memory cells (e.g., erasure is typically performed in blocks or sub-blocks), an erase voltage (Vers) (e.g., typically Vpgm) can be applied (e.g., using one or more bit lines, select gates, etc.) to the substrate of the memory cell to be erased (and thus the channel between the source and drain), while the word line of the target memory cell is held at a potential, such as ground (e.g., Vss), resulting in charge transfer from the floating gate of the target memory cell to the channel (e.g., direct injection or Wohl-Nordheim (FN) tunneling, etc.).

[0058] Figure 4The illustrated block diagram of a memory device 400 includes a memory array 402 having a plurality of memory cells 404, and one or more circuits or components for providing communication with the memory array 402 or performing one or more memory operations on the memory array 402. The memory device 400 may include a row decoder 412, a column decoder 414, a sense amplifier 420, a page buffer 422, a selector 424, input / output (I / O) circuitry 426, and a memory control unit 430.

[0059] The memory cells 404 of the memory array 402 can be arranged in blocks, such as a first block 402A and a second block 402B. Each block can contain sub-blocks. For example, the first block 402A can contain a first sub-block 402A0 and a second sub-block 402A0. n Furthermore, the second sub-block 402B may include the first sub-block 402B0 and the second sub-block 402B. n Each subblock may contain several physical pages, and each page contains several memory cells 404. Although described herein as having two blocks, each block having two subblocks, and each subblock having several memory cells 404, in other embodiments, the memory array 402 may contain more or fewer blocks, subblocks, memory cells, etc. In other embodiments, the memory cells 404 may be arranged in multiple rows, columns, pages, subblocks, blocks, etc., and accessed using, for example, access lines 406, first data lines 410, or one or more select gates, source lines, etc.

[0060] The memory control unit 430 can control the memory operation of the memory device 400 according to one or more signals or instructions received on the control line 432. The one or more signals or instructions include, for example, one or more clock signals or control signals indicating the desired operation (e.g., write, read, erase, etc.), or address signals (A0-AX) received on one or more address lines 416. One or more devices external to the memory device 400 can control the values ​​of the control signals on the control line 432 or the address signals on the address lines 416. Examples of devices external to the memory device 400 may include, but are not limited to, a host, a memory controller, a processor, or... Figure 4 One or more circuits or components not specified in the text.

[0061] The memory device 400 may use access lines 406 and first data lines 410 to transfer data to (e.g., write to or erase) or from (e.g., read from) one or more memory cells 404. Row decoder 412 and column decoder 414 may receive and decode address signals (A0-AX) from address lines 416 to determine which memory cells 404 will be accessed, and may provide signals to, for example, one or more of the access lines 406 (e.g., one or more of a plurality of word lines (WL0-WLm)) or the first data lines 410 (e.g., one or more of a plurality of bit lines (BL0-BLn)) as described above.

[0062] The memory device 400 may include a sensing circuitry system, such as a sensing amplifier 420, configured to determine (e.g., read) the value of data on the memory cell 404, or to determine the value of data to be written to the memory cell 404, using a first data line 410. For example, in a selected string of memory cells 404, one or more of the sensing amplifiers 420 may read logic levels in selected memory cells 404 in response to a read current flowing through the selected string to the data line 410 in the memory array 402.

[0063] One or more devices external to memory device 400 may communicate with memory device 400 using I / O lines (DQ0-DQN) 408, address lines 416 (A0-AX) or control lines 432. Input / output (I / O) circuitry 426 may, for example, use I / O lines 408 to transfer data values ​​in and out of memory device 400, such as in and out of page buffer 422 or memory array 402, according to control lines 432 and address lines 416. Page buffer 422 may store data received from one or more devices external to memory device 400 and then program the data into a relevant portion of memory array 402, or it may store data read from memory array 402 and then transmit the data to one or more devices external to memory device 400.

[0064] Column decoder 414 can receive address signals (A0-AX) and decode them into one or more column address signals (CSEL1-CSELn). Selector 424 (e.g., selection circuitry) can receive column selection signals (CSEL1-CSELn) and select data in page buffer 422 representing values ​​of data to be read from or programmed into memory cell 404. The selected data can be transferred between page buffer 422 and I / O circuitry 426 using a second data line 418.

[0065] The memory control unit 430 may receive positive and negative power signals from an external source or power supply (e.g., an internal or external battery, an AC-DC converter, etc.), such as a power supply voltage (Vcc) 434 and a negative power supply (Vss) 436 (e.g., ground potential). In some instances, the memory control unit 430 may include a regulator 428 to provide positive or negative power signals internally.

[0066] In typical memory devices, the operating system of an electronic device and the firmware of the memory device installed within it will benefit from more complete synchronization of the memory device's performance with respect to the performance needs and demands of the electronic device. For example, it is advantageous to reduce the power consumption of the memory device when the battery power of the electronic device is low. As another example, it is advantageous to increase the speed of the memory device before transferring large files. Current operating systems and memory devices are not synchronized in this way.

[0067] The disclosure discloses methods, systems, and machine-readable media that allow the operating system of an electronic device to control the performance characteristics of the memory device by modifying the behavior characteristics of the SLC cache. These mechanisms provide the operating system with a way to change the performance characteristics of the running memory device in response to changing operating conditions. Instance memory device performance characteristics include speed, power usage, temperature output, data integrity, and free space. Modifiable instance SLC cache behavior characteristics include the configuration of the SLC cache, the behavior of the SLC cache, and, in some instances, triggering cache operations (e.g., garbage collection).

[0068] In some instances, the operating system can modify the performance characteristics of a memory device by sending messages to the firmware of the memory device via a communication interface (e.g., UFS). The operating system can send one or more electronic device status indicators to the memory device, which can cause changes to the configuration and / or behavior of the SLC cache. The electronic device status indicators can be the operating system informing the memory device of the status of the electronic devices in which the memory device is installed. In other instances, instead of explicitly changing the performance characteristics of the memory device, the operating system can write or erase data to change the configuration (e.g., size) of the SLC cache and thus alter the performance characteristics of the memory device.

[0069] An example electronic device status indicator is a low power indicator, which indicates that the operating system detects a potentially low battery level. In response, the memory device can reconfigure the memory cells to have less SLC cache (and more MLC cache), and / or bypass the newly written SLC cache to conserve power. Another example electronic device status indicator could be an impending large transfer. In this indicator, the operating system can determine or predict that a large amount of data can be written within a predetermined timeframe. For example, the operating system may be preparing to receive, send, or record streaming audio or video. In response, the memory device can increase the size of the SLC cache when a large data transfer is anticipated to provide optimal performance.

[0070] Another example of an electronic device status indicator includes a high ambient temperature indication. This indication can be triggered in response to an operating system detecting that the ambient air temperature of the electronic device exceeds a threshold (e.g., detected by a temperature sensor that is part of the electronic device but not the memory device). The memory device can take actions, such as limiting the use of SLC cache memory, to reduce heat generation and prevent heat dissipation in an effort to maintain a cool temperature for the memory device.

[0071] Another example of an electronic device status indicator is the indication that it is about to enter sleep or hibernation mode. This indication allows the memory device to perform various garbage collection operations and / or move data from the SLC cache to the MLC memory.

[0072] As mentioned, in some instances, instead of sending device status indications, the operating system can erase, move, or write data to the memory device to influence the reconfiguration of the SLC cache without explicit guidance. This leverages the fact that in some memory devices, the amount of SLC cache is determined by Logical Block Addressing (LBA) allocation. Allocating more LBAs reduces the free memory blocks on the drive. The memory device providing the advertised capacity shrinks the size of the SLC cache and converts SLC to MLC. Once free space is created, the MLC can then be converted back to SLC.

[0073] Therefore, for example, if the operating system detects a failure in a memory cell of a memory device (e.g., through metrics reported by the Self-Monitoring, Analysis, and Reporting Technology (SMART) based on monitoring drives, bit errors, or other criteria), the operating system can delete data from the memory device. This causes the memory device to reallocate MLC memory cells to SLC memory cells, moving the data from less reliable storage to more reliable storage. To delete data, the operating system can compress operating system or user data, delete temporary files (e.g., cache, internet browsing history, cookies, recycle bins, etc.), reduce page or swap file size, prompt the user to delete user data, etc.

[0074] Now refer to Figure 5 This is a flowchart of a method 500 for controlling device performance using an operating system according to some embodiments of the present invention. At operation 510, the memory device may receive an electronic device status condition indication from the operating system. For example, it may receive a low battery indication, an impending large transfer indication, a high ambient temperature indication, etc., via an interface such as a Universal Flash Memory (UFS) interface.

[0075] At operation 514, in some instances, the memory device may determine one or more rules for handling the received electronic device status indication. The memory device may be configured with a set of rules specifying how to modify the SLC cache in the event of a given device condition indication. The memory device may receive the electronic device status indication, confirm the appropriate rules, and perform actions according to the rules. Rules may be executed at operation 515 and may specify the memory device to modify the cache configuration at operation 516, modify the cache behavior indicator at operation 518, and / or execute one or more SLC cache routines at operation 520. The rule set may be programmed into the memory device via firmware objects, external programmers, communication interfaces from the operating system, etc.

[0076] At operation 516, the SLC cache configuration can be changed based on the instructions received at operation 510 and the rules identified at operation 514. Instance configuration changes include modifying the size of the SLC cache (increasing or decreasing it), modifying which memory cells include the SLC cache (e.g., the physical arrangement of the SLC cache), and so on.

[0077] As an example, an electronic device status indicator can instruct the operating system to prepare for the transfer of large files. For instance, a user might request a video or music stream, or begin saving a high-definition video. Rules stored in the memory device can instruct that one or more available MLC memory cells be reconfigured into SLC cache memory immediately upon receiving this instruction. The size increase of the SLC cache memory can be specified through rules, and in some instances, it can be a fixed increase. In other instances, the rules can specify a formula that depends on several factors, such as available MLCs (e.g., LBA utilization), the expected transfer size (which can be provided by the operating system in the instruction), and so on.

[0078] At operation 518, a behavior modification indicator for the SLC cache can be set to signal to the memory device to modify the cache's behavior. In some instances, this indication may involve setting a flag or utilizing other data structures (such as rule-based indications) to signal to the memory device that certain behaviors have been changed. For example, upon receiving a low power indication, the memory device can set a flag to bypass the SLC cache to conserve power when a write request is received. Subsequent write requests can bypass the SLC cache and be written directly to the MLC if the flags are set.

[0079] In other instances, various cache routines may be invoked at operation 520 (as specified by a rule) in response to receiving certain electronic device status indications. For example, if the operating system indicates that an electronic device containing a memory device is about to enter sleep or hibernation, the rule may specify that the memory device may begin garbage collection and / or move data from the SLC cache to the MLC storage and / or reduce the size of the SLC cache.

[0080] In some instances, the indication can be that the device's power is no longer low and it has resumed full-power operation. For example, this could be used to write new data to the SLC cache. In these instances, if a flag is set in the SLC cache preset file to pause writes to the SLC cache, then that flag can be cleared.

[0081] Because the behavior of SLC cache memory can be modified, the memory device can perform some operations, such as processing requests, in different ways. Now refer to... Figure 6The diagram illustrates a flowchart of a method 600 for processing write requests at a memory device according to some embodiments of the present invention. At operation 610, the memory device may receive a write operation from a host, for example, via a UFS or other communication interface. At operation 616, the memory device may identify the presence of any behavior modification indicators (e.g., any set of flags). At operation 618, the memory device may determine, based on the behavior modification indicators, whether to write the data from the request to the SLC cache. For example, if the memory device receives an indication that the electronic device is currently in a low battery condition, then the behavior modification indicators may be set to instruct the memory device not to store the write request to the SLC cache.

[0082] If at operation 618 the memory device determines not to write to the SLC cache, then at operation 620 the system can write the data directly to the MLC storage. If at operation 618 the memory device determines to write data to the SLC cache, then at operation 622 the system can write the data to the SLC cache, and subsequently (e.g., during idle time), the block can be moved from the SLC to the MLC.

[0083] Now refer to Figure 7 A flowchart of a method 700 for an operating system to monitor an electronic device and send electronic device status indications according to some embodiments of the present invention is shown. At operation 710, the operating system may monitor one or more device conditions. Examples include an imminent need to write a large amount of data to a memory device, high ambient temperature, low power conditions, a return to normal power conditions after a low power condition, an imminent entry into sleep or hibernation, etc. At operation 714, the device may detect one of these conditions. At operation 716, the operating system may determine that the device condition indicates a change in the behavior of the memory device. For example, the operating system may use a series of rules to specify which electronic device status indications to send and in response to which device conditions. At operation 720, given that the device has determined that it will send a device status condition, the operating system sends the electronic device status indication to the memory device via a communication interface (e.g., UFS).

[0084] Although as already mentioned, Figure 7 Method 700 utilizes electronic device status indication messages, but the operating system can write, delete, move, or otherwise manipulate data via normal read / write commands sent to the memory device, thereby altering the SLC cache configuration and thus the behavior characteristics of the memory device.

[0085] Figure 8 This describes a memory controller 815 according to some embodiments of the present invention. The memory controller 815 may be... Figure 1One embodiment of the memory controller 115. Memory manager 825 may be an instance of memory manager 125, table 530 may be an instance of table 130, controller 835 may be an instance of controller 135, and ECC 840 may be an instance of ECC 140. In some instances, memory manager 825 may include SLC cache memory manager 832. SLC cache memory manager 832 may load an SLC cache behavior preset file, such as SLC cache behavior preset file 834, and configure the SLC cache using the preset file. SLC cache behavior preset file 834 may include SLC cache configuration information, behavior modification indicators, and a set of rules for processing electronic device status indications. SLC cache memory manager may read the SLC cache behavior preset file to initialize the memory cells as SLC or MLC. SLC cache memory manager 832 may also receive electronic device status indications and, in response, update the SLC cache configuration and behavior indicators. The SLC cache behavior preset file 834 can be hard-decoded into the memory device, can be in the working memory of the memory manager 825 (or controller 835), can be located in the storage of the memory device, can be sent from the host device via an interface (e.g., a UFS interface), etc.

[0086] The write controller 837 may also utilize the SLC cache behavior preset file 834. For example, the SLC cache behavior preset file 834 may contain behavior modification indicators added to the configuration information to specify modifications to the SLC cache behavior. For instance, when writing to a memory cell of a memory device, the behavior modification indicator may specify that the memory device should be written to MLC storage instead of utilizing the SLC cache. Upon receiving a write request, the write controller 837 can check the SLC cache behavior preset file 834 and determine if any behavior modification indicators fulfill the write request, and if so, take appropriate action.

[0087] Figure 9This diagram illustrates an instance machine 900 capable of performing one or more of the techniques (e.g., methods) discussed herein. In alternative embodiments, machine 900 may operate as a standalone device or be connected (e.g., networked) to other machines. In a networked deployment, machine 900 may operate as a server machine, a client machine, or both in a server-client network environment. In instances, machine 900 may act as a peer-to-peer (P2P) (or other distributed) network environment. Machine 900 may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), mobile phone, network appliance, IoT device, automotive system, or any machine capable of (sequentially or otherwise) executing instructions specifying actions to be taken by said machine. Furthermore, while only a single machine is described, the term "machine" will also be considered as encompassing any collection of machines that individually or collectively execute a set (or more) of instructions to perform one or more of the methods discussed herein (e.g., cloud computing, Software as a Service (SaaS), other computer cluster configurations).

[0088] As described herein, an instance may comprise logic, components, devices, packages, or mechanisms, or may be operable through logic, components, devices, packages, or mechanisms. A circuit is an assembly (e.g., a collection) of circuits implemented in a tangible entity containing hardware (e.g., simple circuits, gates, logic, etc.). Circuit members can be flexible over time and as the underlying hardware changes. A circuit contains components that can perform a specific task individually or in combination when operating. In an instance, the hardware of a circuit system can be designed in an immutable manner to perform a specific operation (e.g., hardwired). In an instance, the hardware of a circuit system may contain physically connected components (e.g., execution units, transistors, simple circuits, etc.) and computer-readable media that are physically modified (e.g., magnetically, electrically, with movable placement of constantly aggregated particles, etc.) to encode instructions for a specific operation. When connecting the physical components, the underlying electrical characteristics of the hardware configuration change, for example, from an insulator to a conductor or vice versa. Instructions enable participating hardware (e.g., execution units or loading mechanisms) to generate portions of the circuit system within the hardware via variable connections to perform a specific task when operating. Therefore, when the device is operating, the computer-readable medium is communicatively coupled to other components of the circuit system. In one example, any one of the physical components can be used in more than one part of more than one circuit system. For instance, under operation, an execution unit can be used at one point in time in a first circuit of a first circuit system and reused by a second circuit in the first circuit system, or reused at a different time by a third circuit in the second circuit system.

[0089] Machine (e.g., computer system) 900 (e.g., host 105, managed memory device 110, etc.) may include a hardware processor 902 (e.g., a central processing unit (CPU), graphics processing unit (GPU), hardware processor core, or any combination thereof, such as memory controller 115, etc.), main memory 904, and static memory 906, some or all of which may communicate with each other via interconnects (e.g., bus) 908. Machine 900 may additionally include a display unit 910, an alphanumeric input device 912 (e.g., keyboard), and a user interface (UI) navigation device 914 (e.g., mouse). In one example, the display unit 910, input device 912, and UI navigation device 914 may be a touchscreen display. Machine 900 may additionally include a storage device (e.g., drive unit), a signal generation device 918 (e.g., speaker), a network interface device 920, and one or more sensors 916, such as a global positioning system (GPS) sensor, compass, accelerometer, or other sensors. Machine 900 may include an output controller 928, for example, serial (e.g., Universal Serial Bus (USB), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection, to communicate with or control one or more peripheral devices (e.g., printer, card reader, etc.).

[0090] The storage device may include a machine-readable medium 922 on which one or more data structures or instruction sets 924 (e.g., software) embody or are utilized by any one or more of the techniques or functions described herein. The instructions 924 may also reside wholly or at least partially within main memory 904, static memory 906, or hardware processor 902 during execution by machine 900. In an example, one or any combination of hardware processor 902, main memory 904, static memory 906, or the storage device may constitute the machine-readable medium 922.

[0091] Although machine-readable media 922 is described as a single medium, the term "machine-readable media" may include a single medium or multiple media (e.g., a centralized or distributed database, or associated cache and server) configured to store one or more instructions 924.

[0092] The term "machine-readable media" can include any medium capable of storing, encoding, or transmitting instructions for execution by machine 900 and causing machine 900 to perform any one or more of the technologies disclosed herein, or any medium capable of storing, encoding, or transmitting data structures used by or associated with such instructions. Non-limiting examples of machine-readable media can include solid-state memory as well as optical and magnetic media. In examples, mass-capacity machine-readable media includes machine-readable media having a plurality of particles with invariant mass (e.g., stationary). Therefore, mass-capacity machine-readable media are non-transitory propagating signals. Specific examples of mass-capacity machine-readable media can include: non-volatile memory, such as semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)) and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

[0093] Instructions 924 (e.g., software, programs, operating system (OS), etc.) or other data are stored on storage device 921 and are accessible by memory 904 for use by processor 902. Memory 904 (e.g., DRAM) is typically fast but volatile and is therefore a different type of storage device from storage device 921 (e.g., SSD) suitable for long-term storage (including storage when in a "shutdown" state). Instructions 924 or data for use by the user or machine 900 are typically loaded into main memory 904 for use by processor 902. When memory 904 is full, virtual space from storage device 921 can be allocated to supplement memory 904; however, because storage device 921 is typically slower than memory 904 and write speeds are typically at least twice as slow as read speeds, the use of virtual memory can significantly degrade the user experience due to storage device latency (compared to memory 904, such as DRAM). Furthermore, the use of storage device 921 for virtual memory can significantly reduce the available lifespan of storage device 921.

[0094] Compared to virtual memory, virtual memory compression (e.g., The kernel feature “ZRAM” uses portions of memory as compressed blocks to avoid paging of storage device 921. Paging occurs within the compressed blocks until such data must be written to storage device 921. Virtual memory compression increases the available size of memory 904 while reducing wear on storage device 921.

[0095] Storage devices or mobile storage devices optimized for mobile electronic devices traditionally include MMC solid-state storage devices (e.g., microSD cards). TM(e.g., cards, etc.) MMC devices contain several interfaces that run in parallel with the host device (e.g., 8-bit parallel interfaces) and are typically components that can be detached and separated from the host device. In contrast, eMMC... TM The device is attached to the circuit board and is considered a component of the host device; its read speed is comparable to that based on Serial ATA. TM SSD devices using Serial Advanced Technology (AT) Attached, or SATA, were previously used. However, the demand for mobile device performance continued to increase to fully enable virtual or augmented reality devices, take advantage of increased network speeds, and so on. In response to this demand, storage devices have transitioned from parallel communication interfaces to serial communication interfaces. Universal Flash Storage (UFS) devices, which include controllers and firmware, communicate with host devices using a Low Voltage Differential Signaling (LVDS) serial interface with dedicated read / write paths, further advancing read / write speeds.

[0096] Instruction 924 can further utilize any of a plurality of transport protocols (e.g., Frame Relay, Internet Protocol (IP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), Hypertext Transfer Protocol (HTTP), etc.) to transmit or receive on communication network 926 via network interface device 920 using a transmission medium. Example communication networks may include local area networks (LANs), wide area networks (WANs), packet data networks (e.g., the Internet), mobile phone networks (e.g., cellular networks), simple old-fashioned telephone (POTS) networks, and wireless data networks (e.g., referred to as…). The Institute of Electrical and Electronics Engineers (IEEE) 802.11 series of standards, known as The network interface device 920 may include one or more physical jacks (e.g., Ethernet, coaxial, or telephone jacks) or one or more antennas for connection to the communication network 926. In an example, the network interface device 920 may include multiple antennas for wireless communication using at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) technologies. The term "transmitting medium" should be considered as including any intangible medium capable of storing, encoding, or transmitting instructions for execution by the machine 900, and including digital or analog communication signals or other intangible media used to facilitate communication of this software.

[0097] The above detailed description includes reference to the accompanying drawings, which form part of the detailed description. The drawings illustrate, by means of illustration, specific embodiments in which the invention may be practiced. These embodiments are also referred to herein as “examples.” Such examples may include elements other than those shown or described. However, the inventors also contemplate that only examples of those elements shown or described are provided herein. Furthermore, the inventors of the invention also contemplate examples (or aspects thereof) of any combination or arrangement of those elements shown or described relative to a particular example (or one or more aspects thereof) or relative to other examples (or one or more aspects thereof) shown or described herein.

[0098] In this document, the term “a” is used as commonly found in patent documents to include one or more, independent of any other example or use of “at least one” or “one or more”. In this document, the term “or” is used to refer to a non-exclusive “or”, such that “A or B” may include “A but not B,” “B but not A,” and “A and B” unless otherwise indicated. In the appended claims, the terms “comprising” and “in which” are used as concise equivalents to the corresponding terms “including” and “wherein.” Furthermore, in the appended claims, the terms “comprising” and “including” are open-ended, meaning that a system, apparatus, article, or process that includes elements other than those listed after this term in the claims is still considered to be within the scope of the claims. Additionally, in the appended claims, the terms “first,” “second,” and “third,” etc., are used merely as designations and are not intended to impose numerical requirements on their objects.

[0099] In various instances, the components, controllers, processors, units, engines, or tables described herein may particularly include physical circuitry systems or firmware stored on a physical device. As used herein, "processor" means any type of computing circuitry, such as, but not limited to, microprocessors, microcontrollers, graphics processors, digital signal processors (DSPs), or any other type of processor or processing circuitry, including groups of processors or multi-core devices.

[0100] As used in this document, the term "horizontal" is defined as a plane parallel to a conventional plane or surface of the substrate, such as a plane or surface beneath a wafer or die, regardless of the actual orientation of the substrate at any given time. The term "vertical" refers to a direction perpendicular to the horizontal as defined above. Prepositions such as "above," "above," and "below" are defined relative to a conventional plane or surface on top of or on an exposed surface of the substrate, regardless of the orientation of the substrate; and "above" explicitly indicates direct contact between a structure and another structure located "above" it (unless otherwise indicated); the terms "above" and "below" explicitly identify the relative placement of structures (or layers, features, etc.), and unless specifically indicated as such, explicitly include, but are not limited to, direct contact between the identified structures. Similarly, the terms "on" and "below" are not limited to horizontal orientation, because if a structure is the outermost part of the construction under discussion at a given time, then this structure may be "on" the reference structure even if it extends vertically relative to the reference structure rather than in a horizontal orientation.

[0101] The terms “wafer” and “substrate” are used herein to generally refer to any structure on which an integrated circuit is formed, and also to such structures during the various stages of integrated circuit manufacturing. Therefore, the following detailed description should not be construed in a limiting sense, and the scope of the various embodiments is defined only by the full scope of the appended claims together with their equivalents.

[0102] Various embodiments of the present invention, and described herein, include memories that utilize vertical structures of memory cells (e.g., NAND strings of memory cells). As used herein, directional adjectives relative to the surface of the substrate on which the memory cells are formed will be used (i.e., the vertical structure will be considered as extending away from the substrate surface, the bottom end of the vertical structure will be considered as the end closest to the substrate surface, and the top end of the vertical structure will be considered as the end furthest from the substrate surface).

[0103] As used herein, directional adjectives (e.g., horizontal, vertical, orthogonal, parallel, perpendicular, etc.) may refer to relative orientation and, unless otherwise indicated, are not intended to require strict adherence to specific geometric properties. For example, as used herein, a vertical structure need not be precisely perpendicular to the surface of the substrate, but may instead be substantially perpendicular to the surface of the substrate, and may form an acute angle with the surface of the substrate (e.g., between 60 and 120 degrees, etc.).

[0104] In some embodiments described herein, different doping configurations can be applied to the source-side selected gate (SGS), control gate (CG), and drain-side selected gate (SGD), each of which in this example may be formed of or at least comprise polysilicon, resulting in these layers (e.g., polysilicon, etc.) having different etch rates when exposed to an etch solution. For example, during the formation of a monolithic pillar in a 3D semiconductor device, SGS and CG may form recesses, while SGD may retain less or no recess. These doping configurations can therefore enable selective etching of different layers (e.g., SGS, CG, and SGD) in a 3D semiconductor device using an etch solution (e.g., tetramethylammonium hydroxide (TMCH)).

[0105] As used herein, operating a memory cell includes reading from, writing to, or erasing the memory cell. The operation of placing a memory cell in a predetermined state is referred to herein as “programming” and may include writing to or erasing the memory cell (e.g., the memory cell may be programmed into an erased state).

[0106] According to one or more embodiments of this disclosure, a memory controller (e.g., processor, controller, firmware, etc.) located inside or outside the memory device can determine (e.g., select, set, adjust, calculate, change, clear, communicate, adapt, derive, limit, utilize, modify, apply, etc.) a certain number of wear cycles or wear states (e.g., record wear cycles, count operations on the memory device when they occur, track the memory device operations that started them, evaluate memory device characteristics corresponding to wear states, etc.).

[0107] According to one or more embodiments of this disclosure, a memory access device may be configured to provide wear cycle information to the memory device for each memory operation. Memory device control circuitry (e.g., control logic) may be programmed to compensate for changes in memory device performance corresponding to the wear cycle information. The memory device may receive the wear cycle information and determine one or more operating parameters (e.g., values, characteristics) in response to the wear cycle information.

[0108] It will be understood that when an element is referred to as "on another element," "connected to another element," or "coupled to another element," it may be directly on, directly connected to, or directly coupled to the other element, or there may be intermediate elements. In contrast, when an element is referred to as "directly on another element," "directly connected to another element," or "directly coupled to another element," there are no intermediate elements or layers. If two elements are shown in the diagram as being connected by a line, then unless otherwise specified, the two elements may be coupled or directly coupled.

[0109] The methods described herein can be implemented, at least in part, by a machine or computer. Some examples may include computer-readable or machine-readable media encoded with instructions that can be used to configure electronic devices to perform the methods as described in the examples above. Implementations of such methods may include code, such as microcode, assembly language code, high-level language code, etc. This code may include computer-readable instructions for performing various methods. The code may form part of a computer program product. Furthermore, the code may be tangibly stored, for example, during execution or at other times, on one or more volatile or non-volatile tangible computer-readable media. Examples of such tangible computer-readable media may include, but are not limited to: hard disks, removable disks, removable optical discs (e.g., compressed optical discs and digital video optical discs), magnetic tape cartridges, memory cards or sticks, random access memory (RAM), read-only memory (ROM), solid-state drives (SSDs), universal flash memory (UFS) devices, embedded MMC (eMMC) devices, etc.

[0110] The foregoing description is intended to be illustrative, not limiting. For example, the above examples (or one or more aspects thereof) can be used in combination with each other. Other embodiments may be used by those skilled in the art upon review of the above description. It should be understood that the summary is not intended to interpret or limit the scope or meaning of the claims. Furthermore, in the above detailed description, various features may be grouped together to simplify the invention. This should not be construed as an expectation that unclaimed disclosed features are necessary for any claim. Rather, the subject matter of the invention may consist of fewer features than all of the particular disclosed embodiments. Therefore, the appended claims are hereby incorporated into the detailed description, wherein each claim exists independently as a separate embodiment, and these embodiments are contemplated to be combined or arranged in various ways. The scope of the invention should be determined by reference to the appended claims and the full scope of the equivalents granted by those claims.

[0111] Notes and Examples

[0112] Example 1 is a memory device comprising: an array of memory cells configured in a multi-level cell (MLC) configuration or a single-level cell (SLC) configuration, wherein memory cells configured as SLC in the array include an SLC cache memory; and a controller that executes firmware instructions to cause the controller to perform operations including: receiving from a host an indication that the battery level measured by the host is below a predetermined threshold; and, in response, placing data for a write request into a memory cell of the array configured as MLC without writing the cell into the SLC cache memory.

[0113] In Example 2, the object according to Example 1 optionally includes the operation further comprising: after receiving the instruction from the host, receiving a second instruction from the host, the second instruction indicating that the battery power is higher than the predetermined threshold, and in response, placing the second data of the second request in the SLC cache memory; and after placing the second data of the second request in the SLC cache memory, moving the second data of the second request to a memory cell of the array configured as MLC.

[0114] In Example 3, the object described in any or more of Examples 1-2 optionally includes the operation of receiving the instruction from the host, which includes receiving a message via a communication interface.

[0115] In Example 4, the object described in Example 3 optionally includes the communication interface being an interface based on a Universal Flash Storage (UFS) device.

[0116] In Example 5, the subject matter according to any one or more of Examples 1-4 optionally includes the operation of further including delaying the reconfiguration of the MLC memory cell to the SLC memory cell in response to the instruction.

[0117] In Example 6, the subject matter according to any one or more of Examples 1-5 optionally includes the host associated with an operating system, and the battery is a battery of a mobile computing device.

[0118] In Example 7, the subject matter according to any one or more of Examples 1-6 optionally includes the operation further comprising: receiving an incoming big data transmission instruction before receiving the incoming big data; reconfiguring one or more memory cells of the array configured as MLC as SLC; receiving the incoming big data transmission and writing the incoming big data transmission to the SLC; and reconfiguring the one or more memory cells of the array configured as SLC back to MLC.

[0119] Example 8 is a machine-readable medium including instructions that, when executed by a processor, cause the processor to perform operations including: at a memory device comprising an array of memory cells configured as a multi-level cell (MLC) configuration or a single-level cell (SLC) configuration, wherein the SLC-configured memory cells in the array include SLC cache memory; receiving from a host an indication that the battery level measured by the host is below a predetermined threshold; and, in response, placing data for a write request into the MLC-configured memory cells of the array without writing the cells into the SLC cache memory.

[0120] In Example 9, the object according to Example 8 optionally includes the operation further comprising: after receiving the instruction from the host, receiving a second instruction from the host, the second instruction indicating that the battery power is higher than the predetermined threshold, and in response, placing the second data of the second request in the SLC cache memory; and after placing the second data of the second request in the SLC cache memory, moving the second data of the second request to a memory cell of the array configured as MLC.

[0121] In Example 10, the object described in any or more of Examples 8-9 optionally includes the operation of receiving the instruction from the host, which includes receiving a message via a communication interface.

[0122] In Example 11, the object described in Example 10 optionally includes the communication interface being an interface based on a Universal Flash Storage (UFS) device.

[0123] In Example 12, the subject matter according to any one or more of Examples 8-11 optionally includes the operation of further including delaying the reconfiguration of the MLC memory cell to the SLC memory cell in response to the instruction.

[0124] In Example 13, the subject matter according to any one or more of Examples 8-12 optionally includes the host associated with an operating system, and the battery is a battery of a mobile computing device.

[0125] In Example 14, the subject matter according to any one or more of Examples 8-13 optionally includes the operation further comprising: receiving an incoming big data transmission instruction before receiving the incoming big data; reconfiguring one or more memory cells of the array configured as MLC as SLC; receiving the incoming big data transmission and writing the incoming big data transmission to the SLC; and reconfiguring the one or more memory cells of the array configured as SLC back to MLC.

[0126] Example 15 is a method comprising: at a memory device comprising an array of memory cells, the memory cells in the array being configurable as a multi-level cell (MLC) configuration or a single-level cell (SLC) configuration, the memory cells in the array configured as SLC including an SLC cache memory; receiving from a host an indication that a battery charge measured by the host is below a predetermined threshold; and, in response, placing data for a write request into a memory cell in the array configured as an MLC without writing the cell into the SLC cache memory.

[0127] In Example 16, the object according to Example 15 optionally includes receiving a second instruction from the host after receiving the instruction from the host, the second instruction indicating that the battery power is higher than the predetermined threshold, and in response, placing the second data of the second request in the SLC cache memory; and after placing the second data of the second request in the SLC cache memory, moving the second data of the second request to a memory cell of the array configured as MLC.

[0128] In Example 17, the object described in any or more of Examples 15-16 optionally includes receiving the instruction from the host, which includes receiving a message via a communication interface.

[0129] In Example 18, the object described in Example 17 optionally includes the communication interface being an interface according to a Universal Flash Storage (UFS) device.

[0130] In Example 19, the subject matter according to any one or more of Examples 15-18 optionally includes a delayed reconfiguration of MLC memory cells to SLC memory cells in response to the instruction.

[0131] In Example 20, the subject matter according to any one or more of Examples 15-19 optionally includes the host associated with an operating system, and the battery is a battery of a mobile computing device.

[0132] In Example 21, the subject matter according to any one or more of Examples 15-20 optionally includes, before receiving the incoming big data transmission instruction; reconfiguring one or more memory cells of the array configured as MLC as SLC; receiving the incoming big data transmission and writing the incoming big data transmission to the SLC; and reconfiguring the one or more memory cells of the array configured as SLC back to MLC.

[0133] Example 22 is an apparatus comprising: an array of memory cells configured in a multi-level cell (MLC) configuration or a single-level cell (SLC) configuration, wherein memory cells configured as SLC in the array include an SLC cache memory; means for receiving from a host an indication that a battery charge measured by the host is below a predetermined threshold; and means for, in response, placing data of a write request into a memory cell of the array configured as MLC without writing the cell into the SLC cache memory.

[0134] In Example 23, the object according to Example 22 optionally includes means for receiving a second instruction from the host after receiving the instruction from the host, the second instruction indicating that the battery power is higher than the predetermined threshold, and in response, means for placing second data of a second request in the SLC cache memory; and means for moving the second data of the second request to a memory cell of the array configured as MLC after placing the second data of the second request in the SLC cache memory.

[0135] In Example 24, the object according to any one or more of Examples 22-23 optionally includes the means for receiving the instruction from the host, including means for receiving messages via a communication interface.

[0136] In Example 25, the object described in Example 24 optionally includes the communication interface being an interface according to a Universal Flash Storage (UFS) device.

[0137] In Example 26, the object according to any one or more of Examples 22-25 optionally includes means for delaying the reconfiguration of an MLC memory cell as an SLC memory cell in response to the instruction.

[0138] In Example 27, the subject matter according to any one or more of Examples 22-26 optionally includes the host associated with an operating system, and the battery is a battery of a mobile computing device.

[0139] In Example 28, the object according to any one or more of Examples 22-27 optionally includes: means for receiving an incoming big data transmission instruction before receiving the incoming big data; means for reconfiguring one or more memory cells of the array configured as MLC to SLC; means for receiving the incoming big data transmission and writing the incoming big data transmission to the SLC; and means for reconfiguring the one or more memory cells of the array configured as SLC back to MLC.

[0140] Example 29 is a memory device comprising: an array of memory cells configured in a multi-level cell (MLC) configuration or a single-level cell (SLC) configuration, wherein memory cells configured as SLC in the array include SLC cache memory; and a controller that executes firmware instructions to cause the controller to perform operations including: receiving an electronic device status indication via a communication interface, the electronic device status indication providing a status of a device in which the memory device is installed; identifying rules for handling the electronic device status indication; and executing the rules by one of: modifying the SLC cache memory configuration; setting a behavior modification indicator; or executing an SLC cache memory routine.

[0141] In Example 30, the object according to Example 29 optionally includes the operation of executing the rule, wherein the operation includes setting the behavior modification indicator, and wherein the operation further includes: receiving a write request via the communication interface; identifying the behavior modification indicator; and satisfying the write request by writing data to a memory cell configured as MLC in response to the behavior modification indicator.

[0142] In Example 31, the subject matter according to any one or more of Examples 29-30 optionally includes the electronic device status indicator being a low power indicator, and the operation of executing the rule includes setting a behavior indicator to bypass the SLC cache memory.

[0143] In Example 32, the subject matter according to any one or more of Examples 29-31 optionally includes the electronic device status indication that a large transfer is imminent, and the operation of executing the rule includes modifying the SLC cache memory configuration by increasing the amount of memory cells configured as SLC.

[0144] In Example 33, the subject matter according to any one or more of Examples 29-32 optionally includes the electronic device status indicator being an ambient temperature indicator, and the operation of executing the rule includes setting a behavior indicator to bypass the SLC cache memory.

[0145] In Example 34, the subject matter according to any one or more of Examples 29-33 optionally includes the electronic device status indication being provided by an operating system.

[0146] In Example 35, the subject matter according to any one or more of Examples 29-34 optionally includes the electronic device state indicator being a sleep or hibernation indicator, and the operation of executing the rule includes executing an SLC cache routine to initiate garbage collection.

[0147] Example 36 is a machine-readable medium including instructions that, when executed by a machine, cause the machine to perform operations including: at a memory device comprising an array of memory cells configured as a multi-level cell (MLC) configuration or a single-level cell (SLC) configuration, wherein memory cells configured as SLC in the array include SLC cache memory; receiving an electronic device status indication via a communication interface, the electronic device status indication providing a status of a device in which the machine-readable medium is installed; identifying a rule for disposing of the electronic device status indication; and executing the rule by one of the following operations: modifying the SLC cache memory configuration; setting a behavior modification indicator; or executing an SLC cache memory routine.

[0148] In Example 37, the object according to Example 36 optionally includes the operation of performing the rule, which includes setting the behavior modification indicator, and wherein the operation further includes: receiving a write request via the communication interface; identifying the behavior modification indicator; and satisfying the write request by writing data to a memory cell configured as MLC in response to the behavior modification indicator.

[0149] In Example 38, the subject matter according to any one or more of Examples 36-37 optionally includes the electronic device status indicator being a low power indicator, and the operation of executing the rule includes setting a behavior indicator to bypass the SLC cache memory.

[0150] In Example 39, the subject matter according to any one or more of Examples 36-38 optionally includes the electronic device status indication that a large transfer is imminent, and the operation of executing the rule includes modifying the SLC cache memory configuration by increasing the amount of memory cells configured as SLC.

[0151] In Example 40, the subject matter according to any one or more of Examples 36-39 optionally includes the electronic device status indicator being an ambient temperature indicator, and the operation of executing the rule includes setting a behavior indicator to bypass the SLC cache memory.

[0152] In Example 41, the subject matter according to any one or more of Examples 36-40 optionally includes the electronic device status indication being provided by an operating system.

[0153] In Example 42, the subject matter according to any one or more of Examples 36-41 optionally includes the electronic device state indication being a sleep or hibernation indication, and the operation of executing the rule includes executing an SLC cache routine to initiate garbage collection.

[0154] Example 43 A method comprising: at a memory device comprising an array of memory cells, the memory cells in the array being configurable as a multi-level cell (MLC) configuration or a single-level cell (SLC) configuration, the memory cells configured as SLC in the array including an SLC cache memory; receiving an electronic device status indication via a communication interface, the electronic device status indication providing a status of a device in which the method is installed; identifying a rule for disposing of the electronic device status indication; and executing the rule by one of the following operations: modifying the SLC cache memory configuration; setting a behavior modification indicator; or executing an SLC cache memory routine.

[0155] In Example 44, the object according to Example 43 optionally includes an execution of the rule comprising setting the behavior modification indicator, and wherein the method further comprises: receiving a write request via the communication interface; identifying the behavior modification indicator; and, in response to the behavior modification indicator, satisfying the write request by writing data to a memory cell configured as MLC.

[0156] In Example 45, the subject matter according to any one or more of Examples 43-44 optionally includes the electronic device status indicator being a low power indicator, and wherein executing the rule includes setting a behavior indicator to bypass the SLC cache memory.

[0157] In Example 46, the subject matter according to any one or more of Examples 43-45 optionally includes the electronic device status indication that a large transfer is imminent, and wherein executing the rule includes modifying the SLC cache configuration by increasing the amount of memory cells configured as SLC.

[0158] In Example 47, the subject matter according to any one or more of Examples 43-46 optionally includes the electronic device status indicator being an ambient temperature indicator, and wherein executing the rule includes setting a behavior indicator to bypass the SLC cache memory.

[0159] In Example 48, the subject matter according to any one or more of Examples 43-47 optionally includes the electronic device status indication being provided by an operating system.

[0160] In Example 49, the subject matter according to any one or more of Examples 43-48 optionally includes the electronic device state indicator being a sleep or hibernation indicator, and wherein executing the rule includes executing an SLC cache routine to initiate garbage collection.

[0161] Example 50 is an apparatus comprising: at a memory device comprising an array of memory cells, the memory cells in the array being configurable as a multi-level cell (MLC) configuration or a single-level cell (SLC) configuration, the memory cells configured as SLC in the array including an SLC cache memory; means for receiving an electronic device status indication via a communication interface, the electronic device status indication providing a status of a device in which the device is installed; means for identifying a rule for disposing of the electronic device status indication; and means for executing the rule by one of: means for modifying an SLC cache memory configuration; means for setting a behavior modification indicator; or means for executing an SLC cache memory routine.

[0162] In Example 51, the object according to Example 50 optionally includes an embodiment in which executing the rule includes setting the behavior modification indicator, and wherein the means further includes: means for receiving a write request via the communication interface; means for identifying the behavior modification indicator; and means for satisfying the write request by writing data to a memory cell configured as MLC in response to the behavior modification indicator.

[0163] In Example 52, the subject matter according to any one or more of Examples 50-51 optionally includes the electronic device status indicator being a low power indicator, and the means for enforcing the rule includes means for setting a behavior indicator to bypass the SLC cache memory.

[0164] In Example 53, the subject matter according to any one or more of Examples 50-52 optionally includes the electronic device state indication that a large transfer is imminent, and the means for enforcing the rule includes means for modifying the SLC cache memory configuration by increasing the amount of memory cells configured as SLC.

[0165] In Example 54, the subject matter according to any one or more of Examples 50-53 optionally includes the electronic device status indicator being an ambient temperature indicator, and the means for enforcing the rule includes means for setting a behavior indicator to bypass the SLC cache memory.

[0166] In Example 55, the subject matter according to any one or more of Examples 50-54 optionally includes the electronic device status indication being provided by an operating system.

[0167] In Example 56, the subject matter according to any one or more of Examples 50-55 optionally includes the electronic device state indicator being a sleep or hibernation indicator, and the means for executing the rule includes means for executing an SLC cache routine to initiate garbage collection.

Claims

1. A memory device comprising: A memory cell array, wherein the memory cells in the array can be configured as a multi-level cell (MLC) configuration or a single-level cell (SLC) configuration. The controller is configured to: Receive an instruction to use at least a portion of the memory cell array in the SLC configuration; At least a portion of the memory cell array is reconfigured from the MLC configuration to the SLC configuration, at least in part, based on the instruction. Receive incoming data and write the incoming data into at least a portion of the memory cell array in the SLC configuration; as well as At least a portion of the memory cell array is reconfigured from the SLC configuration back to the MLC configuration.

2. The memory device of claim 1, wherein the indication includes a status indication signal configured such that the memory device configures at least some of the memory cells from the MLC configuration to the SLC configuration.

3. The memory device of claim 1, wherein the indication includes a status indication signal configured such that the memory device configures at least some of the memory cells from the SLC configuration to the MLC configuration.

4. The memory device of claim 1, wherein reconfiguring at least a portion of the memory cell array from the MLC configuration to the SLC configuration reduces a certain amount of available space in the memory cell array for memory operations.

5. The memory device of claim 1, wherein receiving the indication includes receiving a size indication specifying the size of at least a portion of the memory cell array configured in the SLC configuration.

6. The memory device of claim 1, wherein receiving the indication includes receiving a maximum size indication, the maximum size indication specifying a maximum memory size that can be allocated to the at least portion of the memory cell array configured in the SLC configuration.

7. The memory device of claim 1, wherein the controller is configured to refresh the incoming data from at least a portion of the memory cell array in the SLC configuration to other memory cells of the memory cell array in the MLC configuration.

8. The memory device of claim 1, wherein the controller is configured to refresh the incoming data from at least a portion of the memory cell array in the SLC configuration to other memory cells of the memory cell array in the MLC configuration, based at least in part on a received indication that the memory device will enter a sleep mode.

9. The memory device of claim 1, wherein the controller is configured to facilitate memory transfer when the temperature of the memory device is above a threshold.

10. The memory device of claim 9, wherein facilitating the memory transfer includes restricting the use of at least a portion of the memory cell array in the SLC configuration.

11. The memory device of claim 1, wherein if the available power level of the device comprising the memory device is below a threshold, then the controller is configured to facilitate memory transfer.

12. The memory device of claim 11, wherein facilitating the memory transfer includes restricting the use of at least a portion of the memory cell array in the SLC configuration.

13. The memory device of claim 1, comprising an interface conforming to the Universal Flash Storage (UFS) standard.

14. The memory device of claim 1, wherein the controller is configured to use at least a portion of the memory cell array in the SLC configuration as a memory buffer for temporarily storing the incoming data before it is moved to a memory cell in the MLC configuration.

15. A method for operating a memory device, the method comprising: Receive an instruction to use at least a portion of the memory cell array of the memory device in a single-level cell (SLC) configuration, wherein the memory cells in the array of the memory device can be configured as either a multi-level cell (MLC) configuration or the single-level cell (SLC) configuration; At least a portion of the memory cell array is reconfigured from the MLC configuration to the SLC configuration, at least in part, based on the instruction. Receive incoming data and write the incoming data into at least a portion of the memory cell array in the SLC configuration; as well as At least a portion of the memory cell array is reconfigured from the SLC configuration back to the MLC configuration.

16. The method of claim 15, wherein the indication includes a status indication signal configured such that the memory device configures at least some of the memory cells from the MLC configuration to the SLC configuration.

17. The method of claim 15, wherein the indication includes a status indication signal configured such that the memory device configures at least some of the memory cells from the SLC configuration to the MLC configuration.

18. The method of claim 15, wherein reconfiguring at least a portion of the memory cell array from the MLC configuration to the SLC configuration reduces a certain amount of available space in the memory cell array for memory operations.

19. The method of claim 15, wherein receiving the indication includes receiving a size indication specifying the size of at least a portion of the memory cell array configured in the SLC configuration.

20. The method of claim 15, further comprising refreshing the incoming data from at least a portion of the memory cell array in the SLC configuration to other memory cells of the memory cell array in the MLC configuration.

21. The method of claim 15, further comprising refreshing the incoming data from at least a portion of the memory cell array in the SLC configuration to other memory cells in the memory cell array in the MLC configuration based at least in part on a received indication that the memory device will enter a sleep mode.

22. The method of claim 15, further comprising receiving the incoming data via an interface of the memory device conforming to the Universal Flash Storage (UFS) standard.

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