Sensitivity amplifier control method and electronic device

Abstract

This disclosure provides a sensitive amplifier control method and an electronic device using the amplification. The sensitive amplifier control method includes, in sequence, an idle phase, an offset cancellation phase, a charge sharing phase, and an inductive amplification phase. In the charge sharing phase, the first node is controlled to connect to the complementary bit line for a first preset duration. After the second node is connected to the bit line for the first preset duration, the connection between the bit line and the second node, and the connection between the first node and the complementary bit line, are disconnected. In the inductive amplification phase, when a voltage is detected on the first node or the voltage on the second node reaches a preset voltage, the first node is controlled to connect to the complementary bit line, and the second node is controlled to connect to the bit line, so as to transmit the amplified voltage to the bit line and the complementary bit line. Embodiments of this disclosure can reduce the noise of the sensitive amplifier.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and more specifically, to a sensitive amplifier control method and an electronic device using the control method. Background Technology

[0002] A sense amplifier (SA, also known as an inductive amplifier) ​​is an important circuit in memory for realizing data transmission. It is used to amplify tiny voltage differences on bit lines to enable writing and reading from memory cells.

[0003] A sensitive amplifier primarily consists of two inverters connected in series with their input and output loops. The input of one inverter is connected to the bit line, and the input of the other inverter is connected to the complementary bit line. Internally, the sensitive amplifier amplifies the voltage difference between the bit line and the complementary bit line by controlling the switching of the transistors in the two inverters. During this inductive amplification process, a mismatch can occur between the transistors in the two inverters, generating noise. This noise can be transmitted to other circuits in the memory through the bit line and the complementary bit line, affecting the memory's performance.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this disclosure is to provide a sensitive amplifier control method and an electronic device using the control method, so as to overcome, at least to some extent, the problem of noise generated by the sensitive amplifier during inductive amplification due to the limitations and defects of related technologies.

[0006] According to a first aspect of this disclosure, a sensitive amplifier control method is provided. The sensitive amplifier includes a first N-type transistor, a second N-type transistor, a first P-type transistor, and a second P-type transistor. The drains of the first N-type transistor and the first P-type transistor, and the gate of the second P-type transistor are connected to a first node. The drains of the second N-type transistor and the second P-type transistor, and the gate of the first P-type transistor are connected to a second node. The gate of the first N-type transistor is connected to a bit line, and the gate of the second N-type transistor is connected to a complementary bit line. The sources of the first P-type transistor and the second P-type transistor are both used to connect to a power supply voltage. The source of the first N-type transistor and the second N-type transistor are connected to a complementary bit line. The sources of all transistors are grounded. The sensitive amplifier control method includes, in sequence, an idle phase, an offset elimination phase, a charge sharing phase, and an inductive amplification phase. Specifically: In the charge sharing phase, the first node is connected to the complementary bit line for a first preset duration; after the second node is connected to the bit line for the first preset duration, the connection between the bit line and the second node, and the connection between the first node and the complementary bit line, are disconnected. In the inductive amplification phase, when a voltage is detected on the first node or the voltage on the second node reaches a preset voltage, the first node is connected to the complementary bit line, and the second node is connected to the bit line, so that the amplified voltage is transmitted to the bit line and the complementary bit line.

[0007] In an exemplary embodiment of this disclosure, the method further includes: during the idle phase, controlling the first node, the second node, the bit line, and the complementary bit line to be interconnected and connected to a preset equalization voltage; during the offset elimination phase, disconnecting the connection between the first node and the complementary bit line, and the connection between the second node and the bit line, while simultaneously disconnecting the connection between the first node, the second node, the bit line, the complementary bit line, and the preset equalization voltage; during the charge sharing phase, after inputting an activation signal to the word line corresponding to the memory cell connected to the sensitive amplifier, controlling the first node to connect only to the complementary bit line for a first preset duration, and controlling the second node to connect only to the bit line for the first preset duration.

[0008] In an exemplary embodiment of this disclosure, the charge sharing phase includes: controlling the first node to connect to the second node for a second preset duration, and then disconnecting the connection between the first node and the second node; after disconnecting the first node and the second node, controlling the first node to connect to the complementary bit line for a first preset duration, and the second node to connect to the bit line for a first preset duration, and then disconnecting the connection between the bit line and the second node, and the connection between the first node and the complementary bit line.

[0009] In an exemplary embodiment of this disclosure, the charge sharing phase includes: controlling the first node to connect to the second node while controlling both the first node and the second node to connect to the preset equalization voltage; and disconnecting the first node and the second node from the preset equalization voltage while disconnecting the connection between the first node and the second node.

[0010] In an exemplary embodiment of this disclosure, the method further includes: in both the idle phase and the charge sharing phase, controlling the source of the first P-type transistor and the source of the second P-type transistor to disconnect from the power supply voltage, and controlling the source of the first N-type transistor and the source of the second N-type transistor to disconnect from ground; in both the offset elimination phase and the inductive amplification phase, controlling the source of the first P-type transistor and the source of the second P-type transistor to connect to the power supply voltage, and controlling the source of the first N-type transistor and the source of the second N-type transistor to connect to the power supply voltage.

[0011] In an exemplary embodiment of this disclosure, the sensitive amplifier includes a first switch, a second switch, a third switch, and a fourth switch, wherein a first end of the first switch is connected to the first node, and a second end is connected to the complementary bit line; a first end of the second switch is connected to the second node, and a second end is connected to the bit line; a first end of the third switch is connected to the first node, and a second end is connected to the bit line; and a first end of the fourth switch is connected to the second node, and a second end is connected to the complementary bit line.

[0012] In an exemplary embodiment of this disclosure, the first switch and the second switch have the same process parameters. During the charge sharing stage, the first switch and the second switch are turned on by a first voltage. During the inductive amplification stage, the turn-on voltage of the first switch and the second switch is gradually increased from the first voltage to a second voltage to control the first switch and the second switch to turn on. The first voltage is greater than or equal to the turn-on voltage of the first switch and the second switch.

[0013] In an exemplary embodiment of this disclosure, the sensitive amplifier includes a pre-charge switch, a first terminal of which is connected to the preset equalization voltage, a second terminal of which is used to provide the preset equalization voltage, and the pre-charge switch is used to control at least one of the first node, the second node, the bit line, and the complementary bit line to connect to or disconnect from the preset equalization voltage.

[0014] In one exemplary embodiment of this disclosure, the second end of the precharge switch is connected to the first node, or the second end of the precharge switch is connected to the second node.

[0015] In one exemplary embodiment of this disclosure, the second end of the precharge switch is connected to the bit line, or the second end of the precharge switch is connected to the complementary bit line.

[0016] In one exemplary embodiment of this disclosure, the sensitive amplifier includes an equalization switch, a first end of which is connected to the first node, and a second end of which is connected to the second node. The equalization switch is used to control the connection between the first node and the second node.

[0017] According to a second aspect of this disclosure, an electronic device is provided, comprising: a memory, having a sensitive amplifier and a sensitive amplifier control circuit, the sensitive amplifier control circuit being configured to perform the method as described in any of the preceding claims to control the sensitive amplifier to amplify the voltage difference between its connected bit lines and complementary bit lines.

[0018] This embodiment of the present disclosure avoids the transmission of noise generated during inductive amplification to the bit lines and complementary bit lines by disconnecting the bit lines and complementary bit lines from the nodes in the sensitive amplifier after the charge sharing phase, and only reconnecting the bit lines and complementary bit lines when the voltage on the node is detected to have reached a preset voltage. This reduces the noise impact of the inductive amplification process on the circuit.

[0019] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0020] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0021] Figure 1 This is a schematic diagram of the structure of a sensitive amplifier.

[0022] Figure 2 This is a flowchart of the sensitive amplifier control method in an embodiment of this disclosure.

[0023] Figure 3 This is a schematic diagram of a sensitive amplifier in one embodiment of the present disclosure.

[0024] Figure 4 Based on Figure 3 The sensitive amplifier circuit shown is implemented Figure 2 The timing diagram of the control method shown is shown.

[0025] Figure 5 This is a schematic diagram of a sensitive amplifier control method in another embodiment of this disclosure.

[0026] Figure 6 Is with Figure 5 A schematic diagram of the sensitive amplifier corresponding to the embodiment shown.

[0027] Figure 7 Based on Figure 6 The sensitive amplifier circuit shown is implemented Figure 5 The timing diagram of the control method shown is shown.

[0028] Figure 8 This is a schematic diagram of a sensitive amplifier control method in another embodiment of the present disclosure.

[0029] Figure 9 Based on Figure 6 The sensitive amplifier circuit shown is implemented Figure 8 The timing diagram of the control method shown is shown.

[0030] Figure 10 This is a schematic diagram of a sensitive amplifier control method in another embodiment of the present disclosure.

[0031] Figure 11 yes Figure 10 The timing diagram of the isolation control signal ISO in the sensitive amplifier control method shown is illustrated. Detailed Implementation

[0032] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this disclosure more comprehensive and complete, and to fully convey the concept of the example embodiments to those skilled in the art. The described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a full understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced with one or more of the specific details omitted, or other methods, components, apparatus, steps, etc., can be employed. In other instances, well-known technical solutions are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0033] Furthermore, the accompanying drawings are merely illustrative of this disclosure, and the same reference numerals in the drawings denote the same or similar parts, thus repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0034] The exemplary embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0035] Figure 1 This is a schematic diagram of the structure of a sensitive amplifier.

[0036] refer to Figure 1 The sensitive amplifier 100 may include:

[0037] A first N-type transistor MN1, a second N-type transistor MN2, a first P-type transistor MP1, and a second P-type transistor MP2 are connected. The drains of the first N-type transistor MN1 and MP1, and the gate of the second P-type transistor MP2 are connected to a first node N1. The drains of the second N-type transistor MN2 and MP2, and the gate of MP1 are connected to a second node N2. The gate of the first N-type transistor MN1 is connected to bit line BLA, and the gate of the second N-type transistor MN2 is connected to complementary bit line BLB. The sources of both MP1 and MP2 are connected to the power supply voltage PCS, and the sources of both MN1 and MN2 are grounded (connected to NCS). The second node N2 is connected to bit line BLA, and the first node N1 is connected to complementary bit line BLB.

[0038] It is understood that other circuits, such as memory cells and input / output conversion circuits, are also connected to the bit line BLA and the complementary bit line BLB, but the embodiments of this disclosure do not involve modifications to this part, so they are not shown.

[0039] Depend on Figure 1 As can be seen from the sensitive amplifier circuit shown, the first P-type transistor MP1 and the first N-type transistor MN1 form an inverter, and the second P-type transistor MP2 and the second N-type transistor MN2 form another inverter. The inputs and outputs of these two inverters are connected to form a latch.

[0040] When the potential of bit line BLA and complementary bit line BLB changes, causing potential changes in the first node N1 and the second node N2, during the potential amplification process achieved by the conduction difference of the first P-type transistor MP1, the second P-type transistor MP2, the first N-type transistor MN1, and the second N-type transistor MN2, the mismatch of the first P-type transistor MP1, the second P-type transistor MP2, the first N-type transistor MN1, and the second N-type transistor MN2 cannot be eliminated. The noise of the first node N1 and the second node N2 will be transmitted to bit line BLA and complementary bit line BLB in real time.

[0041] Figure 2 This is a flowchart of the sensitive amplifier control method in an embodiment of this disclosure.

[0042] refer to Figure 2 The sensitive amplifier control method 200 may, in a timing sequence, include an idle phase, an offset cancellation phase, a charge sharing phase, and a sensing phase, which occur sequentially. The sensitive amplifier control method 200 may also include:

[0043] Step S21: During the idle phase, control the first node, the second node, the bit line, and the complementary bit line to connect to each other and connect to a preset equalization voltage;

[0044] Step S22: During the offset elimination stage, disconnect the connection between the first node and the complementary bit line, and the connection between the second node and the bit line. At the same time, disconnect the connection between the first node, the second node, the bit line, the complementary bit line and the preset equalization voltage.

[0045] Step S23: During the charge sharing phase, control the first node to connect to the complementary bit line for a first preset time, and after the second node connects to the bit line for a first preset time, disconnect the bit line and the second node, and disconnect the first node from the complementary bit line.

[0046] Step S24: In the inductive amplification stage, when the voltage on the first node or the voltage on the second node reaches a preset voltage, control the first node to connect to the complementary bit line and the second node to connect to the bit line, so as to transmit the amplified voltage to the bit line and the complementary bit line.

[0047] In order to achieve Figure 2 The method 200 shown in this disclosure embodiment is for... Figure 1 The sensitive amplifier 100 shown is equipped with multiple controllable switching elements.

[0048] Figure 3 This is a schematic diagram of a sensitive amplifier in one embodiment of the present disclosure.

[0049] refer to Figure 3In one embodiment, the sensitive amplifier 300 includes a first switch M1, a second switch M2, a third switch M3, and a fourth switch M4, wherein the first terminal of the first switch M1 is connected to a first node N1, and the second terminal is connected to a complementary bit line BLB; the first terminal of the second switch M2 is connected to a second node N2, and the second terminal is connected to a bit line BLA; the first terminal of the third switch M3 is connected to the first node N1, and the second terminal is connected to the bit line BLA; and the first terminal of the fourth switch M4 is connected to the second node N2, and the second terminal is connected to the complementary bit line BLB.

[0050] Specifically, the third switch M3 and the fourth switch M4 are turned on and off by the offset cancellation signal NC, and the first switch M1 and the second switch M2 are turned on and off by the isolation control signal ISO.

[0051] In addition, the sensitive amplifier 300 also includes a pre-charge switch PREEQ. The first terminal of the pre-charge switch PREEQ is connected to a preset equalization voltage VBLP, and the second terminal is used to provide the preset equalization voltage VBLP. The pre-charge switch PREEQ is used to control at least one of the first node N1, the second node N2, the bit line BLA, and the complementary bit line BLB to connect to or disconnect from the preset equalization voltage VBLP. Figure 3 In the illustrated embodiment, the second terminal of the precharge switch PREEQ is connected to the second node N2. However, in other embodiments of this disclosure, the second terminal of the precharge switch PREEQ can also be connected to the first node N1, or to bit line BLA, or to complementary bit line BLB. Regardless of which node it is connected to, the precharge switch PREEQ is used to provide a preset equalization voltage VBLP to these four nodes when the first node N1, the second node N2, bit line BLA, and complementary bit line BLB are interconnected during the idle phase.

[0052] exist Figure 3 In the illustrated embodiment, the sources of the first P-type transistor and the second P-type transistor are connected to the power supply voltage PCS through the first power control switch Q1, and the control signal of the first power control switch Q1 is SAP; the sources of the first N-type transistor and the second N-type transistor are connected to the ground voltage NCS through the second power control switch Q2, and the control signal of the second power control switch Q2 is SAN.

[0053] Figure 4 Based on Figure 3 The sensitive amplifier circuit shown is implemented Figure 2 The timing diagram of the control method shown is shown.

[0054] refer to Figure 2 , Figure 3 , Figure 4During the idle phase, the first switch M1, the second switch M2, the third switch M3, the fourth switch M4, and the pre-charge switch PREEQ are all turned on, connecting the first node N1, the second node N2, the bit line BLA, and the complementary bit line BLB to a preset equalization voltage VBLP. This process is also called the pre-charge phase, which pre-charges each node of the sensitive amplifier 300. Figure 3 In the illustrated embodiment, the pre-charge switch PREEQ is configured as an N-type switch, and the control signal of the pre-charge switch PREEQ is marked by the signal PreEQ, with an enable level of high. In other embodiments, the pre-charge switch PREEQ can also be a P-type switch, with a corresponding enable level of low. Therefore, to summarize the control logic in each embodiment, Figure 4 In the timing diagram shown, PREEQ is used to mark the switching state of the precharge switch PREEQ. A high level PREEQ indicates that the precharge switch PREEQ is in the on state, and a low level PREEQ indicates that the precharge switch PREEQ is in the off state. The same applies to other transistors, and will not be repeated here.

[0055] During the offset elimination phase, the first switch M1 and the second switch M2 are turned off by the isolation control signal ISO to disconnect the connection between the first node N1 and the complementary bit line BLB and the connection between the second node N2 and the bit line BLA. At the same time, the precharge switch PREEQ is turned off to disconnect the connection between the first node N1, the second node N2, the bit line BLA, the complementary bit line BLB and the preset equalization voltage VBLP.

[0056] During the charge sharing phase, the isolation control signal ISO controls the first switch M1 and the second switch M2 to be turned on for a first preset duration T1 and then turned off. This achieves the following: after the first node N1 is connected to the complementary bit line BLB for a first preset duration T1 and the second node N2 is connected to the bit line BLA for a first preset duration T1, the connection between bit line BLA and the second node N2, and the connection between the first node N1 and the complementary bit line BLB are disconnected. Specifically, during the charge sharing phase, after inputting an activation signal (WL ON) to the word line corresponding to the memory cell connected to the sensitive amplifier 300, the first node N1 can be controlled to connect only to the complementary bit line BLB for a first preset duration T1, and the second node N2 can be controlled to connect only to the bit line BLA for a first preset duration T1. It is important to note that the first switch M1 and the second switch M2 must be turned off after being turned on for the first preset duration T1 and before the sensitive amplifier is enabled to prevent noise from the enabled sensitive amplifier from being transmitted to the bit line BLA and the complementary bit line BLB.

[0057] During the inductive amplification stage, when the voltage on the first node N1 or the second node N2 is detected to reach a preset voltage VT, the first switch M1 and the second switch M2 are turned on via the isolation control signal ISO. This controls the first node N1 to connect to the complementary bit line BLB and the second node N2 to connect to the bit line BLA, transmitting the amplified voltage to bit lines BLA and BLB. The preset voltage VT can be the power supply voltage, indicating that the inductive amplification process has amplified the small voltage difference between bit lines BLA and BLB to a more easily detectable value, allowing bit lines BLA and BLB to acquire the voltage difference amplification result.

[0058] During the offset elimination phase, the first node N1, the second node N2, the bit line BLA, and the complementary bit line BLB are disconnected from the preset equalization voltage VBLP. The connection between the first node N1 and the complementary bit line BLB, and the connection between the second node N2 and the bit line BLA are both disconnected. The bit line BLA will be affected by the storage cell that has stored data or the local signal line that transmits data to the storage cell, resulting in a small voltage change, which in turn creates a voltage difference with the complementary bit line BLB.

[0059] After the offset cancellation phase, the voltage information stored on the internal nodes SABLA (second node N2) and SABLB (first node N1) of the sensitive amplifier 300 is opposite to the voltage information on the bit line BLA and the complementary bit line BLB. During the charge sharing phase, before the inductive amplification process begins, after the first switch M1 and the second switch M2 are turned on, significant noise will occur between the connected internal nodes SABLA and BLA, and between the internal nodes SABLB and the complementary bit line BLB, due to the voltage difference. This noise may reach 20mV to 30mV, while the input voltage difference between the bit line BLA and the complementary bit line BLB in advanced DRAM processes is only 60mV to 90mV. Therefore, this noise greatly affects the effective sense margin. This noise will persist until the voltage between the internal nodes SABLA and BLA, and between the internal nodes SABLB and the complementary bit line BLB, are equal.

[0060] pass Figure 2 and Figure 4As shown in the embodiment, in the latter half of the charge sharing stage and before the end of the inductive amplification stage, because the connection between bit line BLA and the second node N2, and between the first node N1 and the complementary bit line BLB, is broken, the noise generated by the sensitive amplifier 300 during the inductive amplification process can only be stored on the internal nodes SABLA and SABLB of the sensitive amplifier 300 and cannot be transmitted to the bit line BLA and the complementary bit line BLB. After the inductive amplification process has progressed to a certain stage, the voltage difference between the internal node SABLA and the bit line BLA, and the voltage difference between the internal node SABLB and the complementary bit line BLB, are eliminated, and the noise generated during the inductive amplification process disappears (or is reduced to an acceptable level). At this time, the first switch M1 and the second switch M2 are turned on to transmit the amplified voltage to the bit line BLA and the complementary bit line BLB, which can effectively reduce the noise influence on the bit line BLA and the complementary bit line BLB.

[0061] The reason for setting the first node N1 to be connected to the complementary bit line BLB for a first preset time T1 and the second node N2 to be connected to the bit line BLA for a first preset time T1 before disconnecting during the charge sharing phase is to transmit the small signals on the bit line BLA and the complementary bit line BLB to the internal nodes SABLA and SABLB. Otherwise, the internal nodes would always store signals that are opposite to those on the bit line BLA and the complementary bit line BLB, which are invalid and have a counterproductive effect, and would damage the performance of the sensitive amplifier.

[0062] It should be noted that the reference Figure 4 In one embodiment of this disclosure, during the idle phase and the charge sharing phase, the sources of the first P-type transistor and the second P-type transistor are disconnected from the power supply voltage PCS, and the sources of the first N-type transistor and the second N-type transistor are disconnected from the ground terminal NCS; during the offset elimination phase and the inductive amplification phase, the sources of the first P-type transistor and the second P-type transistor are connected to the power supply voltage PCS, and the sources of the first N-type transistor and the second N-type transistor are grounded to NCS.

[0063] The above power control can be achieved by connecting a switching transistor to the power supply voltage PCS and the ground voltage NCS, such as... Figure 3 The first power control switch Q1 and the second power control switch Q2 are configured in the circuit. Correspondingly, the control signal for the first power control switch Q1 is SAP, and the control signal for the second power control switch Q2 is SAN. The timing sequences for SAP and SAN are as follows: Figure 4 As shown in the diagram. The schematic diagrams of the source nodes of the first P-type transistor and the second P-type transistor (PCS), and the source nodes of the first N-type transistor and the second N-type transistor (NCS) are also shown in the diagram. Figure 4 As shown.

[0064] Figure 5 This is a schematic diagram of a sensitive amplifier control method in another embodiment of this disclosure.

[0065] refer to Figure 5 In one exemplary embodiment of this disclosure, step S23 may further include:

[0066] Step S131: After controlling the first node to connect to the second node for a second preset time during the charge sharing phase, disconnect the connection between the first node and the second node.

[0067] Step S132: After disconnecting the first node and the second node, control the first node to connect to the complementary bit line for a first preset time, control the second node to connect to the bit line for a first preset time, and disconnect the bit line and the second node, as well as the first node and the complementary bit line.

[0068] In order to achieve Figure 5 In the illustrated embodiment, a controllable switching element can be provided between the first node N1 and the second node N2.

[0069] Figure 6 Is with Figure 5 A schematic diagram of the sensitive amplifier corresponding to the embodiment shown.

[0070] refer to Figure 6 An equalization switch EQ is also provided between the first node N1 and the second node N2. The first end of the equalization switch EQ is connected to the first node N1, and the second end is connected to the second node N2. The equalization switch EQ is used to control the connection between the first node N1 and the second node N2.

[0071] Although this disclosure Figure 4 , Figure 6 In this embodiment, the switching elements (precharge switch PREEQ and equalization switch EQ) are both set as N-type transistors. Correspondingly, in the control timing, a high level indicates that the switching element is turned on and a low level indicates that the switching element is turned off. However, in some embodiments of this disclosure, the switching elements can also be P-type transistors or other controlled switching elements. Correspondingly, in the control timing, the levels of the on-control signal and the off-control signal of the switching element can also be changed accordingly. This disclosure does not impose any special restrictions on this.

[0072] Figure 7 Based on Figure 6 The sensitive amplifier circuit shown is implemented Figure 5 The timing diagram of the control method shown is shown.

[0073] refer to Figure 5 , Figure 6 , Figure 7By setting a second preset duration T2 for the conduction between internal nodes SABLA and SABLA (i.e., the first node N1 and the second node N2) before transmitting the information of bit line BLA and complementary bit line BLB to internal nodes SABLA and SABLA, the invalid voltage difference on the internal nodes can be eliminated in advance, thereby further reducing the noise generated when small signals on bit line BLA and complementary bit line BLB are transmitted to the internal nodes, and reducing the noise impact on bit line BLA and complementary bit line BLB during the signal transmission process of the first preset duration T1.

[0074] exist Figure 7 In the timing diagram shown, since the equalization switch EQ is turned on during the idle phase, it controls the connection of the first node N1 to the second node N2 (i.e., the internal node SABLB is connected to the internal node SABLA). The offset cancellation signal NC is enabled during the idle phase, connecting the bit line BLA to the first node N1 / internal node SABLB and the complementary bit line BLB to the second node N2 / internal node SABLA. Therefore, it is not necessary to enable the isolation control signal ISO during the idle phase to connect the bit line BLA and the internal node SABLA, or the complementary bit line BLB and the internal node SABLB. The isolation control signal ISO can be set to the disabled state during the idle phase to reduce circuit power consumption.

[0075] from Figure 7 Looking at the signal change process of SABLA and SABLB, the change in signal voltage difference in the dashed box area is compared to Figure 4 The change process of the dashed box part is gradual, which is more conducive to reducing noise.

[0076] Figure 8 This is a schematic diagram of a sensitive amplifier control method in another embodiment of the present disclosure.

[0077] refer to Figure 5 In one exemplary embodiment of this disclosure, step S23 may further include:

[0078] Step S233: During the charge sharing phase, while controlling the first node to connect to the second node, control both the first node and the second node to connect to a preset equalization voltage.

[0079] Step S234: While disconnecting the connection between the first node and the second node, disconnect the connection between the first node, the second node and the preset equalization voltage.

[0080] Figure 8 The illustrated embodiment can also be achieved through Figure 6 The circuit shown is implemented.

[0081] Figure 9 Based on Figure 6 The sensitive amplifier circuit shown is implemented Figure 8 The timing diagram of the control method shown is shown.

[0082] refer to Figure 9 By setting the voltages of the first node N1 and the second node N2 to be equal, and controlling the voltages of both the first node N1 and the second node N2 to be equal to the preset equalization voltage VBLP, the voltage difference between the internal nodes SABLB and SABLA, as well as the voltage difference between the internal node SABLB and the complementary bit line BLB (the complementary bit line BLB usually maintains the previous preset equalization voltage VBLP during this stage), can be further reduced, thereby further reducing the noise impact on the bit line BLA and the complementary bit line BLB during the signal transmission process of the first preset duration T1. Figure 9 Looking at the signal change process of SABLA and SABLB, the signal change in the dashed box area is compared to... Figure 7 The dashed box shown is flatter, which is more conducive to reducing noise.

[0083] Figure 10 This is a schematic diagram of a sensitive amplifier control method in another embodiment of the present disclosure.

[0084] refer to Figure 10 The process parameters of the first switching transistor M1 and the second switching transistor M2 can be set to be the same, thus... Figure 2 , Figure 5 , Figure 8 The sensitive amplifier control methods shown can all include:

[0085] Step S101: During the charge sharing phase, the first and second switching transistors are turned on by controlling the first voltage.

[0086] In step S102, during the inductive amplification stage, the turn-on voltage of the first and second switching transistors is gradually increased from a first voltage to a second voltage to control the first and second switching transistors to turn on. The first voltage is greater than or equal to the turn-on voltage of the first and second switching transistors.

[0087] Figure 10 The method shown can be used Figure 3 or Figure 6 Implemented using any sensitive amplifier circuit.

[0088] Figure 11 yes Figure 10 The timing diagram of the isolation control signal ISO in the sensitive amplifier control method shown is illustrated.

[0089] refer to Figure 11 During the charge sharing phase, when the isolation control signal ISO is enabled, the enable voltage of the isolation control signal ISO can be set to be equal to the first voltage V1, which is greater than or equal to the turn-on voltage of the first switch M1 and the second switch M2.

[0090] During the inductive amplification stage, as the isolation control signal ISO enters and remains enabled, the enable voltage of the isolation control signal ISO can be gradually increased, from the first voltage V1 to the second voltage V2. The second voltage V2 can be equal to the power supply voltage, or the gate control voltage of the N-type transistor commonly used in current circuits.

[0091] Since the amplitude of the small signal transmitted during the charge sharing phase is not large, signal transmission can be achieved even with relatively low control voltages applied to the first switch M1 and the second switch M2. Figure 10 The illustrated embodiment can use different switching voltages according to the needs of different control stages, thereby reducing the power consumption and noise of the sensitive amplifier and reducing power consumption during signal transmission.

[0092] In summary, the sensitive amplifier circuit provided in this disclosure adds an extra toggle timing sequence to the control timing. When the sensitive amplifier starts working, the internal nodes of the sensitive amplifier simultaneously begin to effectively sense and amplify data, and the sensed amplification result is first stored on the internal nodes without being transmitted to the external bit lines and complementary bit lines. After the data is amplified to a certain amplitude at the internal nodes, it is then transmitted to the external nodes. This effectively avoids noise caused by mismatch during the sensed amplification process from being transmitted to the external nodes. It also solves the problems of sensitive amplifier adaptation and noise cancellation, reducing the impact of various mismatches and system errors on the memory. Furthermore, it can be adapted to various structural variations and timing combinations of sensitive amplifiers.

[0093] According to a second aspect of this disclosure, an electronic device is provided, comprising: a memory, having a sensitive amplifier and a sensitive amplifier control circuit, the sensitive amplifier control circuit being configured to perform the method of any of the above embodiments to control the sensitive amplifier to amplify the voltage difference between its connected bit lines and complementary bit lines.

[0094] It should be noted that although several modules or units for the device used to perform actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0095] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and concept of this disclosure are indicated by the claims.

Claims

1. A method of controlling a sensitive amplifier, characterized by, The sensitive amplifier includes a first N-type transistor, a second N-type transistor, a first P-type transistor, and a second P-type transistor. The drains of the first N-type transistor and the first P-type transistor, and the gate of the second P-type transistor are connected to a first node. The drains of the second N-type transistor and the second P-type transistor, and the gate of the first P-type transistor are connected to a second node. The gate of the first N-type transistor is connected to a bit line, and the gate of the second N-type transistor is connected to a complementary bit line. The sources of the first P-type transistor and the second P-type transistor are both connected to a power supply voltage. The sources of the first N-type transistor and the second N-type transistor are both grounded. The sensitive amplifier control method includes, in sequence, an idle phase, an offset cancellation phase, a charge sharing phase, and an inductive amplification phase, wherein: During the charge sharing phase, the first node is connected to the complementary bit line for a first preset duration, and after the second node is connected to the bit line for a first preset duration, the connection between the bit line and the second node, and the connection between the first node and the complementary bit line are disconnected. During the inductive amplification stage, when the voltage on the first node or the voltage on the second node reaches a preset voltage, the first node is controlled to connect to the complementary bit line, and the second node is controlled to connect to the bit line, so as to transmit the amplified voltage to the bit line and the complementary bit line.

2. The sensitive amplifier control method of claim 1, wherein, Also includes: During the idle phase, the first node, the second node, the bit line, and the complementary bit line are controlled to be interconnected and connected to a preset equalization voltage; During the offset elimination phase, the connection between the first node and the complementary bit line, the connection between the second node and the bit line are disconnected, and the connection between the first node, the second node, the bit line, the complementary bit line and the preset equalization voltage is also disconnected. During the charge sharing phase, after an activation signal is input to the word line corresponding to the memory cell connected to the sensitive amplifier, the first node is controlled to connect only to the complementary bit line for the first preset duration, and the second node is controlled to connect only to the bit line for the first preset duration.

3. The sensitive amplifier control method of claim 1, wherein, The charge sharing phase includes: After controlling the first node to connect to the second node for a second preset time, disconnect the connection between the first node and the second node; After disconnecting the first node and the second node, the first node is connected to the complementary bit line for a first preset duration. After the second node is connected to the bit line for a first preset duration, the connection between the bit line and the second node, and the connection between the first node and the complementary bit line are disconnected.

4. The sensitive amplifier control method of claim 3, wherein, The charge sharing phase includes: While controlling the first node to connect to the second node, control both the first node and the second node to connect to a preset equalization voltage; While disconnecting the first node and the second node, disconnect the first node, the second node and the preset equalization voltage.

5. The sensitive amplifier control method of claim 1, wherein, Also includes: During the idle phase and the charge sharing phase, the source of the first P-type transistor and the source of the second P-type transistor are disconnected from the power supply voltage, and the source of the first N-type transistor and the source of the second N-type transistor are disconnected from ground. In both the offset elimination stage and the inductive amplification stage, the sources of the first P-type transistor and the second P-type transistor are connected to the power supply voltage, and the sources of the first N-type transistor and the second N-type transistor are also connected to the power supply voltage.

6. The sensitive amplifier control method according to any one of claims 1 to 5, characterized by, The sensitive amplifier includes a first switch, a second switch, a third switch, and a fourth switch. The first switch has a first end connected to the first node and a second end connected to the complementary bit line. The second switch has a first end connected to the second node and a second end connected to the bit line. The third switch has a first end connected to the first node and a second end connected to the bit line. The fourth switch has a first end connected to the second node and a second end connected to the complementary bit line.

7. The sensitive amplifier control method of claim 6, wherein, The first and second switching transistors have the same process parameters. In the charge sharing stage, the first and second switching transistors are turned on by a first voltage. In the inductive amplification stage, the turn-on voltage of the first and second switching transistors is gradually increased from the first voltage to a second voltage to control the first and second switching transistors to turn on. The first voltage is greater than or equal to the turn-on voltage of the first and second switching transistors.

8. The sensitive amplifier control method of claim 1, wherein, The sensitive amplifier includes a pre-charge switch, the first terminal of which is connected to a preset equalization voltage, and the second terminal of which is used to provide the preset equalization voltage. The pre-charge switch is used to control at least one of the first node, the second node, the bit line, and the complementary bit line to connect to or disconnect from the preset equalization voltage.

9. The sensitive amplifier control method of claim 8, wherein, The second end of the pre-charge switch is connected to the first node, or the second end of the pre-charge switch is connected to the second node.

10. The sensitive amplifier control method of claim 8, wherein, The second end of the precharge switch is connected to the bit line, or the second end of the precharge switch is connected to the complementary bit line.

11. The sensitive amplifier control method according to any one of claims 8 to 10, characterized by, The sensitive amplifier includes an equalization switch, with a first end connected to the first node and a second end connected to the second node. The equalization switch is used to control the connection between the first node and the second node.

12. An electronic device, comprising: include: The memory includes a sensitive amplifier and a sensitive amplifier control circuit, the sensitive amplifier control circuit being configured to perform the method as described in any one of claims 1 to 11, to control the sensitive amplifier to amplify the voltage difference between its connected bit lines and complementary bit lines.

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