Driving method of display panel and display device

Abstract

A driving method and display device for a display panel (100) are disclosed. The driving method includes: acquiring display data corresponding to the current display frame and the current refresh rate (S10); determining a target frequency level corresponding to the current refresh rate based on the current refresh rate and pre-stored frequency levels corresponding to different refresh rate intervals (S20); and controlling the sub-pixels in the display panel (100) to receive data voltage based on the target frequency level and the display data (S30). The driving method for the display panel (100) can improve the problem of different brightness of the displayed image at different refresh rates, reduce flickering, and improve display quality and viewing experience.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a driving method and display device for a display panel. Background Technology

[0002] Displays such as Liquid Crystal Displays (LCDs) and Organic Light-Emitting Diodes (OLEDs) typically include multiple pixel units. Each pixel unit may include a red subpixel, a green subpixel, and a blue subpixel. By controlling the brightness of each subpixel, the desired colors are mixed to display a color image. Summary of the Invention

[0003] The display panel driving method provided in this disclosure includes:

[0004] Get the display data and current refresh rate corresponding to the current display frame;

[0005] Based on the current refresh frequency and the pre-stored frequency levels corresponding to different refresh frequency ranges, determine the target frequency level corresponding to the current refresh frequency.

[0006] Based on the target frequency level and the display data, control the charging voltage of the sub-pixels in the display panel.

[0007] In some examples, controlling the sub-pixel input data voltage in the display panel according to the target frequency level and the display data includes:

[0008] Based on the target frequency level, a target voltage for generating the gate scan signal is determined; wherein: different frequency levels correspond to different target voltages for generating the gate scan signal.

[0009] Based on the target voltage, the display panel is controlled to apply a gate scan signal to the gate, and based on the display data, a data voltage is applied to the data line, so that the sub-pixels in the display panel input data voltage.

[0010] In some examples, the target level includes an active level; determining the target voltage for generating the gate scan signal based on the target frequency level includes:

[0011] Based on the target frequency level, the first reference voltage for generating the effective level of the gate scan signal is adjusted to obtain the target voltage of the effective level; wherein, the target voltage of the effective level is different for different frequency levels;

[0012] The step of controlling the display panel to apply a gate scan signal to the gate according to the target voltage includes:

[0013] Based on the target voltage of the obtained effective level, the display panel is controlled to apply a gate scan signal to the gate.

[0014] In some examples, the first reference voltage is a first reference voltage corresponding to a set frequency level; the effective level is a high level;

[0015] The step of adjusting the first reference voltage for generating the effective level of the gate scan signal according to the target frequency level to obtain the target voltage of the effective level includes:

[0016] When the set frequency level is the minimum frequency level and the target frequency level is greater than the minimum frequency level, the first reference voltage is reduced by a first effective adjustment voltage to obtain the target voltage of the effective level; wherein, as the frequency level increases, the corresponding first effective adjustment voltage increases;

[0017] When the set frequency level is the maximum frequency level, and the target frequency level is less than the maximum frequency level, the first reference voltage is increased by a second effective adjustment voltage to obtain the target voltage of the effective level; wherein, as the frequency level increases, the corresponding second effective adjustment voltage decreases;

[0018] When the set frequency level is greater than the minimum frequency level and less than the maximum frequency level, and the target frequency level is less than the set frequency level, the first reference voltage is increased by a third effective adjustment voltage to obtain the target voltage of the effective level; wherein, as the frequency level increases, the corresponding third effective adjustment voltage decreases;

[0019] When the set frequency level is greater than the minimum frequency level and less than the maximum frequency level, and the target frequency level is greater than the set frequency level, the first reference voltage is reduced by a fourth effective adjustment voltage to obtain the target voltage of the effective level; wherein, as the frequency level increases, the corresponding fourth effective adjustment voltage increases.

[0020] In some examples, the first reference voltage is a first reference voltage corresponding to a set frequency level; the effective level is a low level;

[0021] The step of adjusting the first reference voltage for generating the effective level of the gate scan signal according to the target frequency level to obtain the target voltage of the effective level includes:

[0022] When the set frequency level is the minimum frequency level and the target frequency level is greater than the minimum frequency level, the first reference voltage is increased by a fifth effective adjustment voltage to obtain the target voltage of the effective level; wherein, as the frequency level increases, the corresponding fifth effective adjustment voltage increases;

[0023] When the set frequency level is the maximum frequency level, and the target frequency level is less than the maximum frequency level, the first reference voltage is reduced by a sixth effective adjustment voltage to obtain the target voltage of the effective level; wherein, as the frequency level increases, the corresponding sixth effective adjustment voltage decreases;

[0024] When the set frequency level is greater than the minimum frequency level and less than the maximum frequency level, and the target frequency level is less than the set frequency level, the first reference voltage is reduced by a seventh effective adjustment voltage to obtain the target voltage of the effective level; wherein, as the frequency level increases, the corresponding seventh effective adjustment voltage decreases;

[0025] When the set frequency level is greater than the minimum frequency level and less than the maximum frequency level, and the target frequency level is greater than the set frequency level, the first reference voltage is increased by an eighth effective adjustment voltage to obtain the target voltage of the effective level; wherein, as the frequency level increases, the corresponding eighth effective adjustment voltage increases.

[0026] In some examples, the target level includes an invalid level; determining the target voltage for generating the gate scan signal based on the target frequency level includes:

[0027] Based on the target frequency level, the second reference voltage that generates the invalid level of the gate scan signal is adjusted to obtain the target voltage of the invalid level; wherein, the target voltage of the invalid level is different for different frequency levels.

[0028] The step of controlling the display panel to apply a gate scan signal to the gate according to the target voltage includes:

[0029] Based on the target voltage of the obtained invalid level, the display panel is controlled to apply a gate scan signal to the gate.

[0030] In some examples, the second reference voltage is a second reference voltage corresponding to a set frequency level; the invalid level is a low level;

[0031] The step of adjusting the second reference voltage that generates the invalid level of the gate scan signal according to the target frequency level to obtain the target voltage of the invalid level includes:

[0032] When the set frequency level is the minimum frequency level and the target frequency level is greater than the minimum frequency level, the second reference voltage is increased by a first invalid adjustment voltage to obtain the target voltage of the invalid level; wherein, as the frequency level increases, the corresponding first invalid adjustment voltage increases;

[0033] When the set frequency level is the maximum frequency level, and the target frequency level is less than the maximum frequency level, the second reference voltage is reduced by a second invalid adjustment voltage to obtain the target voltage of the invalid level; wherein, as the frequency level increases, the corresponding second invalid adjustment voltage decreases;

[0034] When the set frequency level is greater than the minimum frequency level and less than the maximum frequency level, and the target frequency level is less than the set frequency level, the second reference voltage is reduced by a third invalid adjustment voltage to obtain the target voltage of the invalid level; wherein, as the frequency level increases, the corresponding third invalid adjustment voltage decreases;

[0035] When the set frequency level is greater than the minimum frequency level and less than the maximum frequency level, and the target frequency level is greater than the set frequency level, the second reference voltage is increased by a fourth invalid adjustment voltage to obtain the target voltage of the invalid level; wherein, as the frequency level increases, the corresponding fourth invalid adjustment voltage increases.

[0036] In some examples, the second reference voltage is a second reference voltage corresponding to a set frequency level; the invalid level is a high level;

[0037] The step of adjusting the second reference voltage that generates the invalid level of the gate scan signal according to the target frequency level to obtain the target voltage of the invalid level includes:

[0038] When the set frequency level is the minimum frequency level and the target frequency level is greater than the minimum frequency level, the second reference voltage is reduced by a fifth invalid adjustment voltage to obtain the target voltage of the invalid level; wherein, as the frequency level increases, the corresponding fifth invalid adjustment voltage increases;

[0039] When the set frequency level is the maximum frequency level, and the target frequency level is less than the maximum frequency level, the second reference voltage is increased by a sixth invalid adjustment voltage to obtain the target voltage of the invalid level; wherein, as the frequency level increases, the corresponding sixth valid adjustment voltage decreases;

[0040] When the set frequency level is greater than the minimum frequency level and less than the maximum frequency level, and the target frequency level is less than the set frequency level, the second reference voltage is increased by a seventh invalid adjustment voltage to obtain the target voltage of the invalid level; wherein, as the frequency level increases, the corresponding seventh invalid adjustment voltage decreases;

[0041] When the set frequency level is greater than the minimum frequency level and less than the maximum frequency level, and the target frequency level is greater than the set frequency level, the second reference voltage is reduced by an eighth invalid adjustment voltage to obtain the target voltage of the invalid level; wherein, as the frequency level increases, the corresponding eighth invalid adjustment voltage increases.

[0042] In some examples, controlling the sub-pixel input data voltage in the display panel according to the target frequency level and the display data includes:

[0043] Based on the target frequency level and the display data, the display panel is controlled to apply a gate scan signal to the gate and apply a data voltage to the data lines in the display panel, such that the interval between the end time of the voltage conversion edge when the data line starts to apply the data voltage and the start time of the data charging phase corresponding to the sub-pixel that is charged with the data voltage is the interval corresponding to the target frequency level.

[0044] In this context, increasing the refresh frequency within the refresh frequency range corresponds to increasing the frequency level and the corresponding interval duration.

[0045] In some examples, applying a data voltage to the data lines in the display panel includes:

[0046] Based on the voltage conversion rate of the voltage conversion edge corresponding to the target frequency level, a data voltage is applied to the data lines in the display panel to adjust the interval duration; wherein, as the frequency level increases, the corresponding voltage conversion rate decreases.

[0047] In some examples, applying a data voltage to the data lines in the display panel according to the voltage slewing rate of the voltage slewing edge corresponding to the target frequency level includes:

[0048] Based on the target frequency level, the output impedance corresponding to the target frequency level is selected so that the data voltage is applied to the data line after passing through the output impedance; wherein, as the frequency level increases, the output impedance increases, and the corresponding voltage conversion rate decreases.

[0049] In some examples, the start time of the voltage transition edge when the data line starts loading the data voltage is after the start time of the data charging phase corresponding to the sub-pixel that is charging the data voltage, and there is a transition time between the start time of the voltage transition edge when the data line starts loading the data voltage and the start time of the data charging phase corresponding to the sub-pixel that is charging the data voltage.

[0050] The control of the display panel to apply a gate scan signal to the gate includes:

[0051] Based on the conversion time corresponding to the target frequency level, the display panel is controlled to apply a gate scan signal to the gate to adjust the interval time; wherein, as the frequency level increases, the corresponding conversion time increases.

[0052] In some examples, controlling the display panel to apply a gate scan signal to the gate based on the conversion time corresponding to the target frequency level includes:

[0053] Based on the target frequency level, the first reference output time is obtained by adjusting the set level of the reference clock control signal to obtain the first target output time; wherein, as the frequency level increases, the corresponding first target output time is earlier.

[0054] Based on the first target output time, the set level of the reference clock control signal is output to control the display panel to apply a gate scan signal to the gate.

[0055] In some examples, the first reference output time is the output time corresponding to a set frequency level;

[0056] The step of adjusting the output time of the set level of the reference clock control signal according to the target frequency level to obtain the first target output time includes:

[0057] When the set frequency level is the minimum frequency level, and the target frequency level is greater than the minimum frequency level, the first reference output time is advanced by the first clock adjustment period to obtain the first target output time; wherein, as the frequency level increases, the corresponding first clock adjustment period increases;

[0058] When the set frequency level is the maximum frequency level, and the target frequency level is less than the maximum frequency level, the first reference output time is delayed by the second clock adjustment duration to obtain the first target output time; wherein, as the frequency level increases, the corresponding second clock adjustment duration decreases;

[0059] When the set frequency level is greater than the minimum frequency level and less than the maximum frequency level, and the target frequency level is less than the set frequency level, the first reference output time is delayed by a third clock adjustment duration to obtain the first target output time; wherein, as the frequency level increases, the corresponding third clock adjustment duration decreases;

[0060] When the set frequency level is greater than the minimum frequency level and less than the maximum frequency level, and the target frequency level is greater than the set frequency level, the first reference output time is advanced by the fourth clock adjustment period to obtain the first target output time; wherein, as the frequency level increases, the corresponding fourth clock adjustment period increases.

[0061] In some examples, applying a data voltage to the data line includes:

[0062] Based on the target frequency level, the second reference output time of the data voltage is adjusted to obtain the second target output time; wherein, the second target output time is different for different frequency levels; as the frequency level increases, the corresponding second target output time is later.

[0063] Based on the second target output time, a data voltage is applied to the data line to adjust the interval duration.

[0064] In some examples, the second reference output time is the output time corresponding to a set frequency level;

[0065] The step of adjusting the second reference output time of the data voltage according to the target frequency level to obtain the second target output time includes:

[0066] When the set frequency level is the minimum frequency level, and the target frequency level is greater than the minimum frequency level, the second reference output time is delayed by the first data adjustment duration to obtain the second target output time; wherein, as the frequency level increases, the corresponding first data adjustment duration increases;

[0067] When the set frequency level is the maximum frequency level, and the target frequency level is less than the maximum frequency level, the second reference output time is advanced by the second data adjustment time to obtain the second target output time; wherein, as the frequency level increases, the corresponding second data adjustment time decreases;

[0068] When the set frequency level is greater than the minimum frequency level and less than the maximum frequency level, and the target frequency level is less than the set frequency level, the second reference output time is advanced by the third data adjustment duration to obtain the second target output time; wherein, as the frequency level increases, the corresponding third clock adjustment duration decreases;

[0069] When the set frequency level is greater than the minimum frequency level and less than the maximum frequency level, and the target frequency level is greater than the set frequency level, the second reference output time is delayed by the fourth data adjustment duration to obtain the second target output time; wherein, as the frequency level increases, the corresponding fourth clock adjustment duration increases.

[0070] In some examples, controlling the sub-pixel input data voltage in the display panel according to the target frequency level and the display data includes:

[0071] Based on the target frequency level, a target grayscale lookup table corresponding to the target frequency level is determined from a pre-stored grayscale lookup table that corresponds one-to-one with multiple different frequency levels. The grayscale lookup table includes: multiple different first grayscale values, multiple different second grayscale values, and a target grayscale value corresponding to any first grayscale value and any second grayscale value. Furthermore, for the same first grayscale value and the same second grayscale value corresponding to the same target grayscale value in different grayscale lookup tables, the target grayscale value corresponding to different frequency levels is different.

[0072] Based on the target grayscale lookup table and the display data, a data voltage is applied to the data line, so that the sub-pixels in the display panel receive the data voltage.

[0073] In some examples, applying a data voltage to the data line based on the target grayscale lookup table and the display data includes:

[0074] Based on the original grayscale value of the display data corresponding to the sub-pixel of the previous row in the same column and the original grayscale value of the display data corresponding to the sub-pixel of the current row in the same column, the target grayscale value corresponding to the sub-pixel of the current row is determined from the target grayscale lookup table; wherein, the target grayscale value corresponding to the sub-pixel of the current row is greater than the original grayscale value corresponding to the sub-pixel of the current row.

[0075] Based on the determined target grayscale value, a data voltage is applied to the data line.

[0076] In some examples, for the same first gray level value and the same second gray level value in different gray level lookup tables, the corresponding target gray level value decreases as the frequency level increases.

[0077] The driving device for the display panel provided in this embodiment includes:

[0078] The acquisition circuit is configured to acquire the display data corresponding to the current display frame and the current refresh rate;

[0079] The frequency level determination circuit is configured to determine the target frequency level corresponding to the current refresh frequency based on the current refresh frequency and the frequency levels corresponding to different refresh frequency ranges that are pre-stored one-to-one.

[0080] The control circuit is configured to control the charging data voltage of the sub-pixels in the display panel according to the target frequency level and the display data.

[0081] In some examples, the control circuitry includes:

[0082] A voltage determination circuit is configured to determine a target voltage for generating the gate scan signal based on the target frequency level; wherein: different frequency levels correspond to different target voltages for generating the gate scan signal.

[0083] A level shifting circuit is configured to control the display panel to apply a gate scan signal to the gate according to the target voltage;

[0084] The source drive circuit is configured to apply a data voltage to the data line according to the display data, so that the sub-pixels in the display panel receive the data voltage.

[0085] In some examples, the control circuitry includes:

[0086] The first driving circuit is configured to control the display panel to apply a gate scan signal to the gate according to the target frequency level;

[0087] The second driving circuit is configured to apply a data voltage to the data lines in the display panel according to the target frequency level and the display data, such that the interval between the end time of the voltage conversion edge when the data line starts to apply the data voltage and the start time of the data charging phase corresponding to the sub-pixel that is charged with the data voltage is the interval corresponding to the target frequency level.

[0088] In this context, increasing the refresh frequency within the refresh frequency range corresponds to increasing the frequency level and decreasing the interval duration.

[0089] In some examples, the control circuitry includes:

[0090] The lookup table determination circuit is configured to determine a target grayscale lookup table corresponding to the target frequency level from a pre-stored set of grayscale lookup tables that correspond one-to-one with different frequency levels; wherein the grayscale lookup table includes: multiple different first grayscale values, multiple different second grayscale values, and a target grayscale value corresponding to any first grayscale value and any second grayscale value; and, for the same first grayscale value and the same second grayscale value in different grayscale lookup tables, the target grayscale value corresponding to different frequency levels is different.

[0091] The source drive circuit is configured to apply a data voltage to the data line according to the target grayscale lookup table and the display data, so that the sub-pixels in the display panel input the data voltage. Attached Figure Description

[0092] Figure 1 These are some structural schematic diagrams of the display panel in the embodiments of this disclosure;

[0093] Figure 2a These are some other structural schematic diagrams of the display panel in the embodiments of this disclosure;

[0094] Figure 2b These are some signal timing diagrams from embodiments of this disclosure;

[0095] Figure 3 These are further structural schematic diagrams of the display panel in the embodiments of this disclosure;

[0096] Figure 4 Here are some other signal timing diagrams in the embodiments of this disclosure;

[0097] Figure 5 These are some more signal timing diagrams in the embodiments of this disclosure;

[0098] Figure 6 Here are some flowcharts of the driving method in the embodiments of this disclosure;

[0099] Figure 7 These are some more signal timing diagrams in the embodiments of this disclosure;

[0100] Figure 8 These are some structural schematic diagrams of the driving device in the embodiments of this disclosure;

[0101] Figure 9 These are some structural schematic diagrams of the data output circuit in the embodiments of this disclosure;

[0102] Figure 10 These are some more signal timing diagrams in the embodiments of this disclosure;

[0103] Figure 11These are some more signal timing diagrams in the embodiments of this disclosure;

[0104] Figure 12 These are some more signal timing diagrams in the embodiments of this disclosure;

[0105] Figure 13 These are some other structural schematic diagrams of the driving device in the embodiments of this disclosure;

[0106] Figure 14 These are further structural schematic diagrams of the driving device in the embodiments of this disclosure;

[0107] Figure 15 These are some more signal timing diagrams in the embodiments of this disclosure;

[0108] Figure 16 These are some more signal timing diagrams in the embodiments of this disclosure;

[0109] Figure 17 These are some more signal timing diagrams in the embodiments of this disclosure;

[0110] Figure 18 These are some more signal timing diagrams in the embodiments of this disclosure;

[0111] Figure 19a These are further structural schematic diagrams of the driving device in the embodiments of this disclosure;

[0112] Figure 19b These are some structural schematic diagrams of the first reference circuit in the embodiments of this disclosure;

[0113] Figure 19c These are some structural schematic diagrams of the second reference circuit in the embodiments of this disclosure;

[0114] Figure 19d These are some structural schematic diagrams of the third reference circuit in the embodiments of this disclosure;

[0115] Figure 19e These are some structural schematic diagrams of the fourth reference circuit in the embodiments of this disclosure;

[0116] Figure 20 These are some more signal timing diagrams in the embodiments of this disclosure;

[0117] Figure 21 These are some more signal timing diagrams in the embodiments of this disclosure;

[0118] Figure 22 These are some more signal timing diagrams in the embodiments of this disclosure;

[0119] Figure 23 These are some more signal timing diagrams in the embodiments of this disclosure;

[0120] Figure 24 These are some more signal timing diagrams in the embodiments of this disclosure;

[0121] Figure 25 These are some more signal timing diagrams in the embodiments of this disclosure;

[0122] Figure 26 These are some more signal timing diagrams in the embodiments of this disclosure;

[0123] Figure 27 These are some more signal timing diagrams in the embodiments of this disclosure;

[0124] Figure 28 These are some more signal timing diagrams in the embodiments of this disclosure;

[0125] Figure 29 These are some more signal timing diagrams in the embodiments of this disclosure;

[0126] Figure 30 These are some more signal timing diagrams in the embodiments of this disclosure;

[0127] Figure 31 These are some more signal timing diagrams in the embodiments of this disclosure;

[0128] Figure 32 These are further structural schematic diagrams of the driving device in the embodiments of this disclosure;

[0129] Figure 33 This is a schematic diagram of some grayscale lookup tables in the embodiments of this disclosure;

[0130] Figure 34 This is a schematic diagram of some grayscale lookup tables in the embodiments of this disclosure;

[0131] Figure 35 This is a schematic diagram of some grayscale lookup tables in the embodiments of this disclosure. Detailed Implementation

[0132] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0133] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0134] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0135] See Figure 1 The display device may include a display panel 100 and a source driving circuit 120. The display panel 100 may include multiple pixel units arranged in an array, multiple gate lines GA (e.g., GA1, GA2, GA3, GA4), multiple data lines DA (e.g., DA1, DA2, DA3), and a gate driving circuit 110. The gate driving circuit 110 is coupled to the gate lines GA1, GA2, GA3, and GA4, respectively, and the source driving circuit 120 is coupled to the data lines DA1, DA2, and DA3, respectively. Exemplarily, each pixel unit includes multiple sub-pixels SPX. For example, a pixel unit may include red sub-pixels, green sub-pixels, and blue sub-pixels, allowing for color mixing to achieve color display. Alternatively, a pixel unit may also include red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels, allowing for color mixing to achieve color display. Of course, in practical applications, the emission color of the sub-pixels in a pixel unit can be designed and determined according to the actual application environment, and is not limited here.

[0136] For example, there can be two source drive circuits 120, with one source drive circuit 120 connected to half of the data lines and the other source drive circuit 120 connected to the other half of the data lines. Of course, there can also be three, four, or more source drive circuits 120, which can be designed and determined according to the actual application requirements, and are not limited here.

[0137] See Figure 1As shown, each sub-pixel SPX includes a transistor 01 and a pixel electrode 02. One row of sub-pixels SPX corresponds to one gate line, and one column of sub-pixels SPX corresponds to one data line. The gate of transistor 01 is electrically connected to the corresponding gate line, the source of transistor 01 is electrically connected to the corresponding data line, and the drain of transistor 01 is electrically connected to the pixel electrode 02. It should be noted that the pixel array structure of this disclosure can also be a dual-gate structure, that is, two gate lines are set between two adjacent rows of sub-pixels. This arrangement can reduce the number of data lines by half; that is, some adjacent columns of sub-pixels contain data lines, while others do not. The specific sub-pixel arrangement structure and the arrangement of data lines and scan lines are not limited.

[0138] In some embodiments of this disclosure, the display panel 100 may further include multiple clock signal lines, and these multiple clock signal lines are coupled to the gate driving circuit 110. This allows a corresponding clock signal to be input to the gate driving circuit 110 via the clock signal lines, thereby loading a signal onto the gate line. For example, as... Figure 2a As shown, the display panel 100 may include clock signal lines CK1 to CK12, which are coupled to the gate driving circuit 110. For example, if the display panel 100 uses a single gate driving circuit 110, then the gate driving circuit 110 can couple to 12 clock signal lines CK1 to CK12. If the display panel 100 uses a dual gate driving circuit 110 design, then each gate driving circuit 110 can couple to 12 clock signal lines CK1 to CK12. It should be noted that... Figure 2a This example uses 12 clock signal lines. In practical applications, the specific number of clock signal lines can be determined according to the actual application requirements and is not limited here. For example, it can also be other numbers of clock signal lines that are multiples of 2, such as 2, 4, 6, 8, 10, etc.

[0139] Figure 2a The signal timing diagram corresponding to the gate drive circuit 110 shown is as follows: Figure 2bAs shown in the diagram. Here, ck1 represents the clock signal input to clock signal line CK1, ck2 represents the clock signal on clock signal line CK2, ck3 represents the clock signal on clock signal line CK3, ck4 represents the clock signal on clock signal line CK4, ck5 represents the clock signal on clock signal line CK5, ck6 represents the clock signal on clock signal line CK6, ck7 represents the clock signal on clock signal line CK7, ck8 represents the clock signal on clock signal line CK8, ck9 represents the clock signal on clock signal line CK9, ck10 represents the clock signal on clock signal line CK10, ck11 represents the clock signal on clock signal line CK11, and ck12 represents the clock signal on clock signal line CK12.

[0140] Furthermore, signal ga1 represents the gate scan signal output by the gate drive circuit 110 to the gate line GA1, signal ga2 represents the gate scan signal output by the gate drive circuit 110 to the gate line GA2, ... signal ga10 represents the gate scan signal output by the gate drive circuit 110 to the gate line GA10, signal ga11 represents the gate scan signal output by the gate drive circuit 110 to the gate line GA11, and signal ga12 represents the gate scan signal output by the gate drive circuit 110 to the gate line GA12.

[0141] Furthermore, the gate drive circuit 110 outputs the first high level of the clock signal ck1 to the gate line GA1 to generate a high level in signal ga1. The gate drive circuit 110 outputs the first high level of the clock signal ck2 to the gate line GA2 to generate a high level in signal ga2. ... The gate drive circuit 110 outputs the first high level of the clock signal ck10 to the gate line GA10 to generate a high level in signal ga10. The gate drive circuit 110 outputs the first high level of the clock signal ck11 to the gate line GA11 to generate a high level in signal ga11. The gate drive circuit 110 outputs the first high level of the clock signal ck12 to the gate line GA12 to generate a high level in signal ga12. That is, a high level of the clock signal can be its valid level, and a low level can be its invalid level. Of course, when the shift register outputs a low level of the clock signal to generate a low-level signal that controls the transistor to turn on, the low level of the clock signal can be taken as its valid level, and the high level as its invalid level.

[0142] It should be noted that the display panel 100 in this embodiment can be a liquid crystal display panel 100, an OLED display panel 100, etc., and is not limited thereto. It should also be noted that when the display panel in this embodiment is a liquid crystal display panel, the liquid crystal display panel generally includes an upper substrate and a lower substrate of a cell, and liquid crystal molecules encapsulated between the upper substrate and the lower substrate. When displaying an image, since there is a voltage difference between the data voltage applied to the pixel electrode of each sub-pixel SPX and the common electrode voltage on the common electrode, this voltage difference can form an electric field, causing the liquid crystal molecules to deflect under the action of this electric field. Because different intensities of electric fields cause different degrees of deflection of the liquid crystal molecules, the transmittance of the sub-pixel SPX is different, enabling the sub-pixel SPX to achieve different grayscale brightness levels, thereby realizing image display.

[0143] Different display application scenarios require different display effects. For example, in static image display, low power consumption is preferred over a high refresh rate. In game mode, a higher refresh rate is needed for smoother display. The display panel 100 provided in this embodiment can be applied to a variety of different refresh rates. For example, in conjunction with... Figure 1 A clock signal is input to the gate driving circuit 110 in the display panel 100, causing the gate driving circuit 110 to input gate scan signals to the gate lines GA (e.g., GA1, GA2, GA3, GA4) in the display panel 100, thereby driving the gate lines GA (e.g., GA1, GA2, GA3, GA4) in the display panel 100 and controlling the transistors in the sub-pixels to turn on. Simultaneously, display data is input to the source driving circuit 120, which loads data voltage onto the data lines DA (e.g., DA1, DA2, DA3) in the display panel 100 according to the received display data. When the transistors in the sub-pixels are turned on, the sub-pixels are charged, thus charging each sub-pixel with data voltage and realizing the image display function.

[0144] Grayscale, in general, divides the brightness variation between the darkest and brightest points into several parts to facilitate screen brightness control. For example, a displayed image may consist of three colors: red, green, and blue. Each color can be displayed at different brightness levels, and combinations of different brightness levels of red, green, and blue can form different colors. For instance, if an LCD panel has a grayscale bit depth of 6 bits, then red, green, and blue each have 64 (i.e., 2^34) grayscale values. 6 There are 64 gray levels, with gray values ​​ranging from 0 to 63. If the LCD panel has an 8-bit grayscale bit depth, then red, green, and blue each have 256 (i.e., 2^6) gray levels. 8 There are 256 gray levels, with gray values ​​ranging from 0 to 255. If the LCD panel has a 10-bit grayscale, then red, green, and blue each have 1024 (i.e., 2^35) grayscale values. 10There are 1024 gray levels, with gray values ​​ranging from 0 to 1023. If the LCD panel has a 12-bit grayscale, then red, green, and blue each have 4096 (i.e., 2^3) gray levels. 12 There are 4096 gray levels, with gray values ​​ranging from 0 to 4093.

[0145] The following explanation uses an example where a pixel unit includes red, green, and blue sub-pixels. For example, as... Figure 3 As shown, red sub-pixels R11, green sub-pixels G11, and blue sub-pixels B11 form a pixel unit; red sub-pixels R12, green sub-pixels G12, and blue sub-pixels B12 form a pixel unit; red sub-pixels R21, green sub-pixels G21, and blue sub-pixels B21 form a pixel unit; red sub-pixels R22, green sub-pixels G22, and blue sub-pixels B22 form a pixel unit; red sub-pixels R31, green sub-pixels G31, and blue sub-pixels B31 form a pixel unit; red sub-pixels R32, green sub-pixels G32, and blue sub-pixels B32 form a pixel unit; red sub-pixels R41, green sub-pixels G41, and blue sub-pixels B41 form a pixel unit; red sub-pixels R42, green sub-pixels G42, and blue sub-pixels B42 form a pixel unit.

[0146] Combination Figure 4 As shown, taking a sub-pixel SPX as an example, Vcom represents the common electrode voltage. When the data voltage input to the pixel electrode of the sub-pixel SPX is greater than the common electrode voltage Vcom, the liquid crystal molecules at that sub-pixel SPX will be positively polarized, and the polarity corresponding to the data voltage in the sub-pixel SPX will be positive. When the data voltage input to the pixel electrode of the sub-pixel SPX is less than the common electrode voltage Vcom, the liquid crystal molecules at that sub-pixel SPX will be negatively polarized, and the polarity corresponding to the data voltage in the sub-pixel SPX will be negative. For example, the common electrode voltage can be 8.3V. If a data voltage of 8.3V to 16V is input to the pixel electrode of the sub-pixel SPX, the liquid crystal molecules at that sub-pixel SPX will be positively polarized, and the data voltage of 8.3V to 16V will be the corresponding positive polarity data voltage. If a data voltage of 0.6V to 8.3V is input to the pixel electrode of a sub-pixel SPX, the liquid crystal molecules at that sub-pixel SPX can be made negatively polarized. Therefore, the 0.6V to 8.3V data voltage corresponds to the negative polarity. For example, taking an 8-bit grayscale of 0 to 255 as an example, if a data voltage of 16V is input to the pixel electrode of a sub-pixel SPX, the sub-pixel SPX can correspond to the maximum grayscale value of the positive polarity. If a data voltage of 0.6V is input to the pixel electrode of a sub-pixel SPX, the sub-pixel SPX can correspond to the maximum grayscale value of the negative polarity.

[0147] Combination Figure 3 and Figure 4 As shown, taking frame flipping (also known as dot flipping, column flipping, row flipping, etc.) as an example, a display frame F0 of the display panel can include a data refresh phase TS and a blanking time phase TB. During the data refresh phase TS, the input data voltage of the sub-pixels in the display panel can be controlled, thereby causing the display panel to display the image of display frame F0. Specifically, as... Figure 4 As shown, a gate scan signal ga1 is applied to gate line GA1, a gate scan signal ga2 is applied to gate line GA2, a gate scan signal ga3 is applied to gate line GA3, and a gate scan signal ga4 is applied to gate line GA4. When a valid level (e.g., a high level) appears in any of the gate scan signals ga1 to ga4, the corresponding transistor 01 can be turned on. When an invalid level (e.g., a low level) appears in any of the gate scan signals ga1 to ga4, the corresponding transistor 01 can be turned off.

[0148] Furthermore, when the gate scan signal ga1 is active, all transistors 01 in the first row of sub-pixels can be turned on, applying a corresponding data voltage da1 to data line DA1, a corresponding data voltage da2 to data line DA2, and a corresponding data voltage da3 to data line DA3. This causes the pixel electrodes 02 in the first row of sub-pixels to input the target data voltage corresponding to the grayscale value, thereby ensuring that each sub-pixel in the first row receives the target data voltage. Similarly, when the gate scan signal ga2 is active, all transistors 01 in the second row of sub-pixels can be turned on, applying a corresponding data voltage da1 to data line DA1, a corresponding data voltage da2 to data line DA2, and a corresponding data voltage da3 to data line DA3. This causes the pixel electrodes 02 in the second row of sub-pixels to input the target data voltage corresponding to the grayscale value, thereby ensuring that each sub-pixel in the second row receives the target data voltage. Furthermore, when the gate scan signal ga3 is active, transistors 01 in the third row of sub-pixels can be turned on, applying a corresponding data voltage da1 to data line DA1, a corresponding data voltage da2 to data line DA2, and a corresponding data voltage da3 to data line DA3. This causes the pixel electrodes 02 in the third row of sub-pixels to input the target data voltage corresponding to the grayscale value, thereby inputting the panel data voltage to each sub-pixel in the third row. Similarly, when the gate scan signal ga4 is active, transistors 01 in the fourth row of sub-pixels can be turned on, applying a corresponding data voltage da1 to data line DA1, a corresponding data voltage da2 to data line DA2, and a corresponding data voltage da3 to data line DA3. This causes the pixel electrodes 02 in the fourth row of sub-pixels to input the target data voltage corresponding to the grayscale value, thereby inputting the panel data voltage to each sub-pixel in the fourth row. The remaining rows follow the same principle and will not be elaborated upon here.

[0149] like Figure 4 As shown, during the Blanking Time (TB) phase, the gate scan signals ga1 to ga4 are all at a low level, and the transistor 01 in each sub-pixel is in the off state, controlling the pixel electrode 02 in each sub-pixel to maintain the data voltage, thereby controlling the sub-pixels in the display panel to maintain the data voltage, so that the display panel continues to display the image of the display frame F0.

[0150] To accommodate different application scenarios, display panels can be configured with multiple refresh rates. For example, in some applications, to save power, the display panel needs to reduce its refresh rate, such as from 60Hz to 30Hz or 1Hz. In other scenarios, such as when playing high-frequency games, the display panel's frequency needs to be increased, such as from 60Hz to 120Hz or 240Hz, to achieve smoother visuals. Therefore, to suit different scenarios, the display panel can change its refresh rate, i.e., use Variable Refresh Rate (VRR) display. Typically, when the display panel's refresh rate changes from a high refresh rate to a low refresh rate, the duration of the data refresh phase (TS) in each display frame remains unchanged; only the idle time phase (TB) is extended. For example, combined with... Figure 5 As shown, the refresh rate corresponding to display frame F1 is greater than that corresponding to display frame F2, and the refresh rate corresponding to display frame F2 is greater than that corresponding to display frame F3. The duration of the data refresh phase TS in display frames F1, F2, and F3 is the same. The duration of the blank time phase TB in display frame F1 is greater than that in display frame F2, and the duration of the blank time phase TB in display frame F2 is greater than that in display frame F3. It should be noted that... Figure 5 In this context, LS represents the brightness of the display panel, and da1 represents the data voltage on data line DA1.

[0151] Therefore, the display panel displays one frame of the image until it receives the display data for the next frame and refreshes. The duration of displaying one frame can be divided into two phases: a data refresh phase (TS) and a blank time phase (TB). At different refresh rates, the duration of the data refresh phase within a display frame is the same, while the duration of the blank time phase (TB) varies. One data refresh phase (TS) and one blank time phase (TB) constitute the total time of one display frame. During the data refresh phase (TS), the brightness of the displayed image first decreases and then increases. During the blank time phase (TB), the transistors are off, and the display panel maintains the displayed image. However, as the refresh rate increases, the duration of the blank time phase (TB) decreases, leakage current decreases, and the average brightness of the display panel increases. Conversely, as the refresh rate decreases, the duration of the blank time phase (TB) increases, leakage current increases, and the average brightness of the display panel decreases. Thus, when the refresh rate changes, the brightness of the display panel changes abruptly, causing flickering. For example, combined with… Figure 5As shown, the average brightness L01 corresponding to display frame F1 is less than the average brightness L02 corresponding to display frame F2, and the average brightness L02 corresponding to display frame F2 is less than the average brightness L03 corresponding to display frame F3. Thus, in practical applications, due to the continuous change in refresh rate, the brightness of the display panel also continuously changes, easily perceptible to the human eye as flicker, affecting the viewing experience. This disclosure provides a driving method for a display panel that can improve the problem of inconsistent brightness of the displayed image at different refresh rates, reduce flicker, and improve display quality and viewing experience.

[0152] like Figure 6 As shown, the display panel driving method provided in this embodiment may include the following steps:

[0153] S10. Obtain the display data corresponding to the current display frame and the current refresh rate. For example, as shown... Figure 8 As shown, the display device also includes system circuitry 210 and acquisition circuitry 220, which is configured to acquire display data and the current refresh rate corresponding to the current display frame. In some examples, system circuitry 210 (e.g., a system-on-a-chip (SOC)) acquires the display data and current refresh rate corresponding to the current display frame from a network or local source. System circuitry 210 can send the display data and current refresh rate corresponding to the current display frame to acquisition circuitry 220 so that acquisition circuitry 220 can acquire the display data and current refresh rate corresponding to the current display frame.

[0154] In some embodiments of this disclosure, the acquired display data may include: a digital signal form of a data voltage carrying the original grayscale value corresponding to at least one sub-pixel SPX. This allows the original grayscale value corresponding to each sub-pixel to be determined based on the display data corresponding to each sub-pixel.

[0155] S20. Determine the target frequency level corresponding to the current refresh frequency based on the current refresh frequency and the pre-stored frequency levels corresponding to different refresh frequency ranges. For example, the display device further includes a frequency level determination circuit 230, which is configured to determine the target frequency level corresponding to the current refresh frequency based on the current refresh frequency and the pre-stored frequency levels corresponding to different refresh frequency ranges.

[0156] In some embodiments of this disclosure, the frequency levels corresponding to different refresh frequency ranges in advance can be: refresh frequency range [H1, H2) corresponds to frequency level Lev1, refresh frequency range [H2, H3) corresponds to frequency level Lev2, refresh frequency range [H3, H4) corresponds to frequency level Lev3, refresh frequency range [H4, H5) corresponds to frequency level Lev4, refresh frequency range [H5, H6) corresponds to frequency level Lev5, refresh frequency range [H6, H7) corresponds to frequency level Lev6, refresh frequency range [H7, H8) corresponds to frequency level Lev7, and so on. If the refresh frequency of the refresh frequency range [H1, H2) is less than the refresh frequency of the refresh frequency range [H2, H3), the refresh frequency of the refresh frequency range [H2, H3) is less than the refresh frequency of the refresh frequency range [H3, H4), the refresh frequency of the refresh frequency range [H3, H4) is less than the refresh frequency of the refresh frequency range [H4, H5), the refresh frequency of the refresh frequency range [H4, H5) is less than the refresh frequency of the refresh frequency range [H5, H6), the refresh frequency of the refresh frequency range [H5, H6) is less than the refresh frequency of the refresh frequency range [H6, H7), and the refresh frequency of the refresh frequency range [H6, H7) is less than the refresh frequency of the refresh frequency range [H7, H8), then frequency level Lev1 is less than frequency level Lev2, frequency level Lev2 is less than frequency level Lev3, frequency level Lev3 is less than frequency level Lev4, frequency level Lev4 is less than frequency level Lev5, frequency level Lev5 is less than frequency level Lev6, and frequency level Lev6 is less than frequency level Lev7.

[0157] For example, H1 to H8 represent refresh rates, such as H1 being set to 1Hz, H2 to 30Hz, H3 to 60Hz, H4 to 90Hz, H5 to 120Hz, H6 to 150Hz, H7 to 240Hz, and H8 to 300Hz. Of course, in practical applications, the refresh rate range can be determined according to the specific needs of the application, and is not limited here.

[0158] For example, the display panel 100 can support refresh rates including 1Hz, 30Hz, 60Hz, 90Hz, 120Hz, 150Hz, and 240Hz. If the current refresh rate is 1Hz, the corresponding refresh rate range is [H1, H2), and the corresponding target frequency level is frequency level Lev1. If the current refresh rate is 60Hz, the corresponding refresh rate range is [H3, H4), and the corresponding target frequency level is frequency level Lev3. If the current refresh rate is 240Hz, the corresponding refresh rate range is [H7, H8), and the corresponding target frequency level is frequency level Lev7.

[0159] S30. Control the data voltage supplied to the sub-pixels in the display panel according to the target frequency level and display data.

[0160] In some examples, step S30 includes: according to the target frequency level and display data, controlling the display panel to apply a gate scan signal to the gate and apply a data voltage to the data lines in the display panel, such that the interval between the end time of the voltage transition edge when the data line begins to apply the data voltage and the start time of the data charging phase corresponding to the sub-pixel receiving the data voltage is the interval duration corresponding to the target frequency level. As the refresh rate of the refresh frequency range increases, the corresponding frequency level increases, and the corresponding interval duration increases. For example, the interval duration corresponding to frequency level Lev1 is less than the interval duration corresponding to frequency level Lev2, the interval duration corresponding to frequency level Lev2 is less than the interval duration corresponding to frequency level Lev3, the interval duration corresponding to frequency level Lev3 is less than the interval duration corresponding to frequency level Lev4, ..., the interval duration corresponding to frequency level Lev6 is less than the interval duration corresponding to frequency level Lev7. This ensures that the time when the target data voltage for the corresponding grayscale value is maximized in the sub-pixels of the display frame corresponding to the higher frequency level is later than the time when the target data voltage for the corresponding grayscale value is maximized in the sub-pixels of the display frame corresponding to the lower frequency level. This is equivalent to reducing the charging rate of the sub-pixels in the display frame corresponding to the higher frequency level and increasing the charging rate of the sub-pixels in the display frame corresponding to the lower frequency level. Furthermore, since the leakage current during the blank time phase in the display frame corresponding to the lower frequency level is greater than that during the blank time phase in the display frame corresponding to the higher frequency level, and by reducing the charging rate of the sub-pixels in the display frame corresponding to the higher frequency level and increasing the charging rate of the sub-pixels in the display frame corresponding to the lower frequency level, the difference in the charging rate of sub-pixels in display frames with different refresh rates is minimized, thereby improving the display panel's display defects.

[0161] For example, combined Figure 3 and Figure 7As shown, taking the red sub-pixel R12, data line DA1, and gate line GA2 as examples, V12_Lev1 represents the data voltage charged into data line DA1 in the display frame corresponding to frequency level Lev1, and V12_Lev7 represents the data voltage charged into data line DA1 in the display frame corresponding to frequency level Lev7. SB1 represents the voltage transition edge when data voltages V12_Lev1 and V12_Lev7 are applied to data line DA1. Furthermore, when the data voltage is applied to data line DA2, there is a charging and discharging process, which forms the voltage transition edge SB1 (e.g., the voltage transition edge when transitioning from low voltage to high voltage). The end time of the voltage transition edge SB1 when the data voltage V12_Lev1 is applied to data line DA1 is separated from the start time of the data charging phase T12 corresponding to the red sub-pixel R12, which is to be charged with the data voltage V12_Lev1 as the target data voltage, by an interval of time t1. There is an interval t2 between the end of the voltage transition edge SB1 when the control data line DA1 starts loading the data voltage V12_Lev7 and the start of the data charging phase T12 corresponding to the red sub-pixel R12, which is to be charged with the data voltage V12_Lev7 as the target data voltage. By making t2>t1, the time when the red sub-pixel R12 in the display frame corresponding to frequency level Lev7 is charged with the maximum value V0 of the data voltage V12_Lev7 is later than the time when the red sub-pixel R12 in the display frame corresponding to frequency level Lev1 is charged with the maximum value V0 of the data voltage V12_Lev1. This is equivalent to reducing the charging rate of the red sub-pixel R12 in the display frame corresponding to frequency level Lev7 and increasing the charging rate of the red sub-pixel R12 in the display frame corresponding to frequency level Lev1. Furthermore, since the leakage current during the blank time phase of the display frame corresponding to frequency level Lve1 is greater than that during the blank time phase of the display frame corresponding to frequency level Lve7, the difference in the charging rate of sub-pixels in the display frames of refresh rate levels Lve1 and Lve7 can be minimized, thereby improving the display panel's display defects.

[0162] In some embodiments of this disclosure, different refresh rate levels have a one-to-one corresponding voltage conversion rate of the voltage conversion edge, and the corresponding voltage conversion rate decreases as the frequency level increases. Applying data voltage to the data lines in the display panel includes: applying data voltage to the data lines in the display panel according to the voltage conversion rate of the voltage conversion edge corresponding to the target frequency level to adjust the interval duration. This allows the data voltage to be applied to the data lines according to the voltage conversion rate of the corresponding target frequency level, thereby changing the interval duration. For example, the voltage conversion rate corresponding to frequency level Lve7 is less than the voltage conversion rate corresponding to frequency level Lve6, the voltage conversion rate corresponding to frequency level Lve6 is less than the voltage conversion rate corresponding to frequency level Lve5, the voltage conversion rate corresponding to frequency level Lve5 is less than the voltage conversion rate corresponding to frequency level Lve4, ..., the voltage conversion rate corresponding to frequency level Lve2 is less than the voltage conversion rate corresponding to frequency level Lve1. For example, combined with... Figure 7 As shown, the voltage conversion rate corresponding to frequency level Lve7 is less than the voltage conversion rate corresponding to frequency level Lve1. Therefore, the time when the data line DA1 is charged with the maximum value V0 of data voltage V12_Lev7 at frequency level Lve7 is later than the time when the data line DA1 is charged with the maximum value V0 of data voltage V12_Lev1 at frequency level Lev1. This ensures that the time when the red sub-pixel R12 is charged with the maximum value V0 of data voltage V12_Lev7 at frequency level Lve7 is later than the time when the red sub-pixel R12 is charged with the maximum value V0 of data voltage V12_Lev1 at frequency level Lev1.

[0163] For example, applying data voltage to the data lines in the display panel according to the voltage slewing rate of the voltage slewing edge corresponding to the target frequency level includes: selecting the output impedance corresponding to the target frequency level, so that the data voltage is applied to the data lines after passing through the output impedance; wherein, as the frequency level increases, the output impedance increases, and the corresponding voltage slewing rate decreases. For example, each frequency level Lev1 to Lev7 corresponds to an output impedance, and the output impedance corresponding to frequency level Lev7 is greater than the output impedance corresponding to frequency level Lev6, the output impedance corresponding to frequency level Lev6 is greater than the output impedance corresponding to frequency level Lev5, the output impedance corresponding to frequency level Lev5 is greater than the output impedance corresponding to frequency level Lev4, ... the output impedance corresponding to frequency level Lev2 is greater than the output impedance corresponding to frequency level Lev1.

[0164] Exemplarily, the display device may further include a control circuit configured to control the charging of data voltage to sub-pixels in the display panel according to a target frequency level and display data. Exemplarily, the control circuit may include a first driving circuit 243 and a second driving circuit 244. The first driving circuit 243 is configured to control the display panel to apply a gate scan signal to the gate according to the target frequency level and display data. The second driving circuit 244 is configured to apply data voltage to the data lines in the display panel according to the target frequency level and display data, such that the interval between the end time of the voltage transition edge when the data line begins to apply data voltage and the start time of the data charging phase corresponding to the sub-pixel receiving the data voltage is the interval duration corresponding to the target frequency level. Wherein, as the refresh frequency in the refresh frequency range increases, the corresponding frequency level increases, and the corresponding interval duration decreases.

[0165] For example, the first driving circuit 243 is configured to input a clock signal to the gate driving circuit in the display panel according to the target frequency level, and control the gate driving circuit to load a gate scan signal onto the gate.

[0166] For example, such as Figure 8 As shown, the second driving circuit 244 may include a first signal generation circuit 2441 and a source driving circuit 120. The first signal generation circuit 2441 generates a first data output control signal in digital signal form corresponding to the target frequency level, and sends the displayed data and the generated first data output control signal to the source driving circuit 120. The source driving circuit 120 selects the output impedance corresponding to the target frequency level according to the first data output control signal, so that the data voltage corresponding to the grayscale value of each displayed data is applied to the data line after passing through the output impedance, thereby achieving the application of the data voltage to the data line using the corresponding voltage conversion rate.

[0167] For example, the source drive circuit 120 includes a voltage conversion circuit and multiple data output circuits. Each data line is coupled to one data output circuit. The voltage conversion circuit outputs a target data voltage according to the displayed data. The data output circuit receives the target data voltage and a first data output control signal. According to the first data output control signal, it selects the output impedance corresponding to the target frequency level and applies the target data voltage to the data line through the selected output impedance. For example, as... Figure 9As shown, the data output circuit 121 includes multiple transistors M1 to M8, voltage divider resistors RZ1 to RZ3, and a primary resistor RS. The primary resistor RS is the output impedance of each data output circuit. The gates of transistors M1 and M5 receive the target data voltage VDA1, the gates of transistors M3 and M7 receive signal DO2, the gates of transistors M2 and M4 receive signal DO3, and the gates of transistors M6 and M8 receive signal DO4. The sources of transistors M1, M3, M5, and M7 all receive the target voltage corresponding to the grayscale value. The drain of transistor M1 is coupled to the source of transistor M2, and the drain of transistor M2 is coupled to the first terminal of voltage divider resistor RZ3. The drain of transistor M3 is coupled to the source of transistor M4, and the drain of transistor M4 is coupled to the second terminal of voltage divider resistor RZ3 and the first terminal of voltage divider voltage RZ2. The drain of transistor M5 is coupled to the source of transistor M6. The drain of transistor M6 is coupled to the second terminal of voltage divider resistor RZ2 and the first terminal of voltage divider voltage RZ1. The drain of transistor M7 is coupled to the source of transistor M8. The drain of transistor M8 is coupled to the second terminal of voltage divider resistor RZ1 and the first terminal of the original voltage RS. The second terminal of the original voltage RS is coupled to the corresponding data line. For example, taking data line DA1 as an example, the second terminal of the original voltage RS is coupled to data line DA1. Signals DO1 and DO2 have opposite levels, and signals DO3 and DO4 have opposite levels. By using transistors M1 to M8 as resistors, different output impedances can be selected according to the first data output control signals corresponding to different frequency levels. For example, each first data output control signal includes DO1, DO2, DO3, and DO4. By setting at least one of DO1, DO2, DO3 and DO4 to be different, different first data output control signals corresponding to different frequency levels can be implemented, thereby selecting different output impedances. The target data voltage VDA1 can be applied to the data line DA1 through the selected output impedance.

[0168] For example, referring to Table 1, when DO1 is 0, DO2 is 1, DO3 is 0, and DO4 is 1, the selectable output impedance is the original resistance RS, which is used as the output impedance corresponding to frequency level Lev1. When DO1 is 1, DO2 is 0, DO3 is 0, and DO4 is 1, the selectable output impedance is the sum of the original resistance RS and the voltage divider RZ1, which is used as the output impedance corresponding to frequency level Lev2. When DO1 is 0, DO2 is 1, DO3 is 1, and DO4 is 0, the selectable output impedance is the sum of the original resistance RS, the voltage divider RZ1, and the voltage divider RZ2, which is used as the output impedance corresponding to frequency level Lev3. When DO1 is 1, DO2 is 0, DO3 is 1, and DO4 is 0, the selectable output impedance is the sum of the original resistance RS, the voltage divider RZ1, the voltage divider RZ2, and the voltage divider RZ3, which is used as the output impedance corresponding to frequency level Lev4. It should be noted that the specific structure of the data output circuit and the implementation method of the output impedance are only illustrative examples. In practical applications, the specific details can be determined according to the actual application requirements, and no limitations are imposed here.

[0169] Output impedance RS RS+RZ1 RS+RZ2+RZ1 RS+RZ3+RZ2+RZ1 DO1 0 1 0 1 DO2 1 0 1 0 DO3 0 0 1 1 DO4 1 1 0 0

[0170] Table 1

[0171] In other embodiments of this disclosure, applying a data voltage to the data line includes: adjusting a second reference output time of the data voltage according to a target frequency level to obtain a second target output time. Applying the data voltage to the data line according to the second target output time adjusts the interval duration. The second target output time is the time when the data voltage begins to be applied to the data line. Different frequency levels correspond to different second target output times, and the second target output time becomes later as the frequency level increases. This allows the data voltage to be applied to the data line according to the second target output time of the corresponding target frequency level, thereby changing the interval duration. For example, the second target output time corresponding to frequency level Lve7 is later than the second target output time corresponding to frequency level Lve6, the second target output time corresponding to frequency level Lve6 is later than the second target output time corresponding to frequency level Lve5, the second target output time corresponding to frequency level Lve5 is later than the second target output time corresponding to frequency level Lve4, and so on, until the second target output time corresponding to frequency level Lve2 is later than the second target output time corresponding to frequency level Lve1. For example, in combination with... Figure 10As shown, V12_Lev1 represents the data voltage charged into data line DA1 in the display frame corresponding to frequency level Lev1, V12_Lev3 represents the data voltage charged into data line DA1 in the display frame corresponding to frequency level Lev3, and V12_Lev7 represents the data voltage charged into data line DA1 in the display frame corresponding to frequency level Lev7. Since the second target output time corresponding to frequency level Lev7 is later than the second target output time corresponding to frequency level Lev3, the maximum value V0 of the data voltage V12_Lev7 charged into data line DA1 at frequency level Lev7 is later than the maximum value V0 of the data voltage V12_Lev3 charged into data line DA1 at frequency level Lev3. This ensures that the maximum value V0 of the data voltage V12_Lev7 charged into red sub-pixel R12 at frequency level Lev7 is later than the maximum value V0 of the data voltage V12_Lev3 charged into red sub-pixel R12 at frequency level Lev3. Furthermore, since the second target output time corresponding to frequency level Lve3 is later than the second target output time corresponding to frequency level Lve1, the time when the data line DA1 is charged with the maximum value V0 of data voltage V12_Lev3 at frequency level Lve3 is later than the time when the data line DA1 is charged with the maximum value V0 of data voltage V12_Lev1 at frequency level Lev1, so that the time when the red sub-pixel R12 is charged with the maximum value V0 of data voltage V12_Lev3 at frequency level Lve3 is later than the time when the red sub-pixel R12 is charged with the maximum value V0 of data voltage V12_Lev1 at frequency level Lev1.

[0172] In some examples, the second reference output time is the output time corresponding to a set frequency level. Based on the target frequency level, the second reference output time of the data voltage is adjusted to obtain the second target output time, including: when the set frequency level is the minimum frequency level and the target frequency level is greater than the minimum frequency level, delaying the second reference output time by a first data adjustment duration to obtain the second target output time; wherein, as the frequency level increases, the corresponding first data adjustment duration increases. For example, combined with... Figure 10As shown, the second reference output time is the output time DSOUT1 of the data voltage V12_Lev1 corresponding to frequency level Lve1. This output time DSOUT1 has an output waiting time DS11 between it and the start of the data charging phase T12. When the target frequency level is Lve1, there is no need to adjust the output time DSOUT1; the data voltage V12_Lev1 can be directly output based on the output time DSOUT1, thus making the output time of the data voltage V12_Lev1 DSOUT1 and the output waiting time DS11. When the target frequency level is Lve3, the output time DSOUT1 is delayed by the first data adjustment duration TD11 to obtain the second target output time corresponding to frequency level Lve3. This allows the output time of the data voltage V12_Lev3 to be delayed by TD11 on DSOUT1, and the output waiting time to be DS12. When the target frequency level is Lve7, the output time DSOUT1 is delayed by the first data adjustment time TD12 to obtain the second target output time corresponding to frequency level Lve7. This allows the output time of the data voltage V12_Lev7 to be delayed by TD12 on DSOUT1, with an output waiting time of DS13. Furthermore, TD12 > TD11.

[0173] In other examples, the second reference output time is the output time corresponding to a set frequency level. Based on the target frequency level, the second reference output time of the data voltage is adjusted to obtain the second target output time, including: when the set frequency level is the maximum frequency level, and the target frequency level is less than the maximum frequency level, the second reference output time is advanced by a second data adjustment duration to obtain the second target output time; wherein, as the frequency level increases, the corresponding second data adjustment duration decreases. For example, combined with... Figure 11As shown, the second reference output time is the output time DSOUT2 of the data voltage V12_Lev7 corresponding to frequency level Lve7. This output time DSOUT2 has an output waiting time DS13 between it and the start of the data charging phase T12. When the target frequency level is Lve7, there is no need to adjust the output time DSOUT2; the data voltage V12_Lev7 can be directly output based on the output time DSOUT2, thus making the output time of the data voltage V12_Lev7 DSOUT2 and the output waiting time DS13. When the target frequency level is Lve3, the output time DSOUT2 is advanced by the second data adjustment duration TD22 to obtain the second target output time corresponding to frequency level Lve3. This allows the output time of the data voltage V12_Lev3 to be advanced by TD22 on DSOUT2, and the output waiting time to be DS12. When the target frequency level is frequency level Lve1, the output time DSOUT2 is advanced by the second data adjustment duration TD21 to obtain the second target output time corresponding to frequency level Lve1. This allows the output time of data voltage V12_Lev1 to be advanced by TD21 on DSOUT2, with an output waiting time of DS11. Furthermore, TD21 > TD22.

[0174] In some other examples, the second reference output time is the output time corresponding to a set frequency level. Based on the target frequency level, the second reference output time of the data voltage is adjusted to obtain the second target output time, including: when the set frequency level is greater than the minimum frequency level and less than the maximum frequency level, and the target frequency level is less than the set frequency level, advancing the second reference output time by a third data adjustment duration to obtain the second target output time. And, when the set frequency level is greater than the minimum frequency level and less than the maximum frequency level, and the target frequency level is greater than the set frequency level, delaying the second reference output time by a fourth data adjustment duration to obtain the second target output time. Wherein, as the frequency level increases, the corresponding third clock adjustment duration decreases, and the corresponding fourth clock adjustment duration increases. For example, combined with... Figure 12As shown, the frequency level can be set to frequency level Lve3 (of course, it can also be other frequency levels, which are not limited here). The second reference output time is the output time DSOUT3 of the data voltage V12_Lev3 corresponding to frequency level Lve3. There is an output waiting time DS12 between the output time DSOUT3 and the start time of the data charging phase T12. When the target frequency level is frequency level Lve3, there is no need to adjust the output time DSOUT3. The data voltage V12_Lev3 can be directly output according to the output time DSOUT3, so that the output time of the data voltage V12_Lev3 is DSOUT3 and the output waiting time is DS12. When the target frequency level is frequency level Lve7, the output time DSOUT3 is delayed by the fourth data adjustment duration TD41 to obtain the second target output time corresponding to frequency level Lve7. This allows the output time of the data voltage V12_Lev7 to be delayed by TD41 on DSOUT3, and the output waiting time to be DS13. When the target frequency level is frequency level Lve1, the output time DSOUT3 is advanced by the third data adjustment duration TD31 to obtain the second target output time corresponding to frequency level Lve1. This allows the output time of data voltage V12_Lev1 to be advanced by TD31 on DSOUT3, and the output waiting time is DS11.

[0175] For example, such as Figure 13 As shown, the second driving circuit 244 may include a data output adjustment circuit 2442 and a source driving circuit 120. The data output adjustment circuit 2442 adjusts the second reference output time of the data voltage according to the target frequency level to obtain a second target output time, and sends the displayed data and the obtained second target output time to the source driving circuit 120. The source driving circuit 120 loads the data voltage corresponding to the grayscale value of each displayed data onto the data lines according to the second target output time, thereby achieving the loading of data voltage onto the data lines using the second target output time.

[0176] In some embodiments of this disclosure, such as Figure 14As shown, the first driving circuit 243 may include a reference clock generation circuit 2431 and a level shifting circuit 2432. The reference clock generation circuit 2431 is configured to generate a reference clock control signal according to a target frequency level and send the generated reference clock control signal to the level shifting circuit 2432. The level shifting circuit 2432 is configured to receive a first reference voltage VREF1 and a second reference voltage VREF2 (the second reference voltage VREF2 is less than the first reference voltage VREF1), generate a clock signal based on the received reference clock control signal and the first and second reference voltages VREF1 and VREF2, and send the generated clock signal to the gate driving circuit 110. The gate driving circuit 110 outputs a gate scan signal based on the received clock signal. Each clock signal input to the gate driving circuit 110 corresponds one-to-one with a reference clock control signal, and the timing of the clock signals input to the gate driving circuit 110 is the same as the corresponding reference clock control signal. The first reference voltage VREF1 is used to generate the high-level voltage of the clock signal; that is, the high-level voltage of the clock signal is the first reference voltage VREF1. The second reference voltage VREF2 is used to generate the low-level voltage of the clock signal; that is, the low-level voltage of the clock signal is the second reference voltage VREF2. This makes the high-level voltage of the gate scan signal also the first reference voltage VREF1, and the low-level voltage also the second reference voltage VREF2. For example, combined with... Figure 15 As shown, level conversion circuit 2432 generates clock signal ck1 according to the timing of reference clock control signal cks1, and the first reference voltage VREF1 and the second reference voltage VREF2. Level conversion circuit 2432 generates clock signal ck2 according to the timing of reference clock control signal cks2, and the first reference voltage VREF1 and the second reference voltage VREF2. Level conversion circuit 2432 generates clock signal ck3 according to the timing of reference clock control signal cks3, and the first reference voltage VREF1 and the second reference voltage VREF2. ... Level conversion circuit 2432 generates clock signal ck12 according to the timing of reference clock control signal cks12, and the first reference voltage VREF1 and the second reference voltage VREF2.

[0177] In some embodiments of this disclosure, the start time of the voltage transition edge when the data line begins to load the data voltage is located after the start time of the data charging phase corresponding to the sub-pixel receiving the data voltage, and there is a transition time between the start time of the voltage transition edge when the data line begins to load the data voltage and the start time of the data charging phase corresponding to the sub-pixel receiving the data voltage. Furthermore, controlling the display panel to load a gate scan signal onto the gate includes: controlling the display panel to load a gate scan signal onto the gate according to the transition time corresponding to the target frequency level, so as to adjust the interval time. Moreover, as the frequency level increases, the corresponding transition time increases. For example, the transition time corresponding to frequency level Lev7 is greater than the transition time corresponding to frequency level Lev6, the transition time corresponding to frequency level Lev6 is greater than the transition time corresponding to frequency level Lev5, the transition time corresponding to frequency level Lev5 is greater than the transition time corresponding to frequency level Lev4, ..., the transition time corresponding to frequency level Lev2 is greater than the transition time corresponding to frequency level Lev1. This ensures that the time when the target data voltage of the corresponding grayscale value is maximized in the sub-pixels of the display frame corresponding to the higher frequency level is later than the time when the target data voltage is maximized in the sub-pixels of the display frame corresponding to the lower frequency level. This is equivalent to reducing the charging rate of the sub-pixels in the higher frequency level display frame and increasing the charging rate of the sub-pixels in the lower frequency level display frame. Furthermore, since the leakage current during the blank time phase in the lower frequency level display frame is greater than that in the higher frequency level display frame, reducing the charging rate of the sub-pixels in the higher frequency level display frame and increasing the charging rate of the sub-pixels in the lower frequency level display frame minimizes the difference in the charging rate of sub-pixels in display frames with different refresh rates, thereby improving the display panel's display defects.

[0178] For example, combined Figure 3 and Figure 16As shown, taking the red sub-pixel R12, data line DA1, and gate line GA2 as examples, V12_Lev1 represents the data voltage charged to data line DA1 in the display frame corresponding to frequency level Lev1, V12_Lev3 represents the data voltage charged to data line DA1 in the display frame corresponding to frequency level Lev3, and V12_Lev7 represents the data voltage charged to data line DA1 in the display frame corresponding to frequency level Lev7. ga2_Lev1 represents the gate scan signal loaded onto gate line GA2 in the display frame corresponding to frequency level Lev1, ga2_Lev3 represents the gate scan signal loaded onto gate line GA2 in the display frame corresponding to frequency level Lev3, and ga2_Lev7 represents the gate scan signal loaded onto gate line GA2 in the display frame corresponding to frequency level Lev7. T12_Lev1 represents the data charging stage in the display frame corresponding to frequency level Lev1, T12_Lev3 represents the data charging stage in the display frame corresponding to frequency level Lev3, and T12_Lev7 represents the data charging stage in the display frame corresponding to frequency level Lev7. Taking the reference clock control signal cks2 as an example, cks2_Lve1 represents the reference clock control signal at frequency level Lev1, cks2_Lve3 represents the reference clock control signal at frequency level Lev3, and cks2_Lve7 represents the reference clock control signal at frequency level Lev7. Specifically, when the target frequency level is Lev1, the conversion time is GOE1. When the target frequency level is Lev3, the conversion time is GOE2. When the target frequency level is Lev7, the conversion time is GOE3. Furthermore, GOE3 > GOE2 > GOE1.

[0179] In some embodiments of this disclosure, controlling the display panel to apply a gate scan signal to the gate according to the conversion time of the corresponding target frequency level includes: adjusting the first reference output time of the set level of the reference clock control signal according to the target frequency level to obtain a first target output time. Then, based on the first target output time, controlling the display panel to apply a gate scan signal to the gate when the set level of the output reference clock control signal is reached. The first target output time varies for different frequency levels, and the first target output time becomes earlier as the frequency level increases. For example, the first target output time corresponding to frequency level Lev7 is earlier than the first target output time corresponding to frequency level Lev6, the first target output time corresponding to frequency level Lev6 is earlier than the first target output time corresponding to frequency level Lev5, the first target output time corresponding to frequency level Lev5 is earlier than the first target output time corresponding to frequency level Lev4, and so on, until the first target output time corresponding to frequency level Lev2 is earlier than the first target output time corresponding to frequency level Lev1. This allows adjustment of the output time of the reference clock control signal, which in turn adjusts the output time of the clock signal input to the gate drive signal, thereby adjusting the output time of the effective level of the gate scan signal. This ensures that the time when the sub-pixel in the display frame corresponding to the higher frequency level is charged with the maximum value of the target data voltage corresponding to the gray level is later than the time when the sub-pixel in the display frame corresponding to the lower frequency level is charged with the maximum value of the panel data voltage corresponding to the gray level.

[0180] In some examples, the first reference output time is the output time corresponding to a set frequency level. Based on the target frequency level, the output time of the set level of the reference clock control signal is adjusted to obtain the first target output time. This includes: when the set frequency level is the minimum frequency level and the target frequency level is greater than the minimum frequency level, advancing the first reference output time by a first clock adjustment duration to obtain the first target output time; wherein, as the frequency level increases, the corresponding first clock adjustment duration increases. Exemplarily, the set level can be an active level or an inactive level. The following explanation uses an active level, specifically a high level, as an example. Figure 16As shown, taking the reference clock control signal cks2 as an example, cks2_Lve1 represents the reference clock control signal at frequency level Lev1, cks2_Lve3 represents the reference clock control signal at frequency level Lev3, and cks2_Lve7 represents the reference clock control signal at frequency level Lev7. The first reference output time is the high-level output time TSOUT1 of the reference clock control signal cks2_Lve1 at frequency level Lev1. When the target frequency level is Lev1, there is no need to adjust the output time TSOUT1; the reference clock control signal cks2_Lve1 can be directly output based on the output time TSOUT1, thus making the output time of signal ga2_Lev1 TSOUT1. When the target frequency level is Lev3, the output time TSOUT1 is advanced by the first clock adjustment duration TS11 to obtain the first target output time corresponding to frequency level Lev3, thus making the output time of signal ga2_Lev3 advance TSOUT1 by TS11. When the target frequency level is Lve7, the output time TSOUT1 is advanced by the first clock adjustment period TS12 to obtain the first target output time corresponding to frequency level Lve7. This allows the output time of signal ga2_Lev7 to be advanced by TS12 on TSOUT1. Furthermore, TS12 > TS11.

[0181] In other examples, the first reference output time is the output time corresponding to a set frequency level. Based on the target frequency level, the output time of the set level of the reference clock control signal is adjusted to obtain the first target output time. This includes: when the set frequency level is the maximum frequency level and the target frequency level is less than the maximum frequency level, delaying the first reference output time by a second clock adjustment duration to obtain the first target output time; wherein, as the frequency level increases, the corresponding second clock adjustment duration decreases. Exemplarily, the set level can be an active level or an inactive level. The following explanation uses an active level, specifically a high level, as an example. Figure 17As shown, taking the reference clock control signal cks2 as an example, cks2_Lve1 represents the reference clock control signal at frequency level Lev1, cks2_Lve3 represents the reference clock control signal at frequency level Lev3, and cks2_Lve7 represents the reference clock control signal at frequency level Lev7. ga2_Lve1 represents the gate scan signal transmitted at frequency level Lev1 corresponding to gate line GA2, ga2_Lve3 represents the gate scan signal transmitted at frequency level Lev3 corresponding to gate line GA2, and ga2_Lve7 represents the gate scan signal transmitted at frequency level Lev7 corresponding to gate line GA2. V12_Lev1 represents the data voltage charged into data line DA1 in the display frame corresponding to frequency level Lev1, V12_Lev3 represents the data voltage charged into data line DA1 in the display frame corresponding to frequency level Lev3, and V12_Lev7 represents the data voltage charged into data line DA1 in the display frame corresponding to frequency level Lev7. The first reference output time is the high-level output time TSOUT2 of the reference clock control signal cks2_Lve7 corresponding to frequency level Lve7. When the target frequency level is Lve7, there is no need to adjust the output time TSOUT2; the reference clock control signal cks2_Lve7 can be directly output based on the output time TSOUT2, thus making the output time of signal ga2_Lev7 TSOUT2. When the target frequency level is Lve3, the output time TSOUT2 is delayed by the second clock adjustment duration TS21 to obtain the first target output time corresponding to frequency level Lve3, thus making the output time of signal ga2_Lev3 delayed by TS21 on TSOUT2. When the target frequency level is Lve1, the output time TSOUT2 is delayed by the second clock adjustment duration TS22 to obtain the first target output time corresponding to frequency level Lve1, thus making the output time of signal ga2_Lev1 delayed by TS22 on TSOUT2. Furthermore, TS22 > TS21.

[0182] In some other examples, the first target output time is obtained by adjusting the output time of the set level of the reference clock control signal according to the target frequency level. This includes: when the set frequency level is greater than the minimum frequency level and less than the maximum frequency level, and the target frequency level is less than the set frequency level, delaying the first reference output time by a third clock adjustment period to obtain the first target output time; and when the set frequency level is greater than the minimum frequency level and less than the maximum frequency level, and the target frequency level is greater than the set frequency level, advancing the first reference output time by a fourth clock adjustment period to obtain the first target output time. As the frequency level increases, the corresponding third clock adjustment period decreases, and the corresponding fourth clock adjustment period increases. Exemplarily, the set level can be an active level or an inactive level. The following explanation uses an active level, specifically a high level, as an example. Figure 18 As shown, taking the reference clock control signal cks2 as an example, cks2_Lve1 represents the reference clock control signal at frequency level Lev1, cks2_Lve3 represents the reference clock control signal at frequency level Lev3, and cks2_Lve7 represents the reference clock control signal at frequency level Lev7. The frequency level can be set to frequency level Lev3 (or other frequency levels, which are not limited here). The first reference output time is the high-level output time TSOUT3 of the reference clock control signal cks2_Lve3 at frequency level Lev3. When the target frequency level is Lev3, there is no need to adjust the output time TSOUT3; the reference clock control signal cks2_Lve3 can be directly output based on the output time TSOUT3, thus making the output time of signal ga2_Lev3 TSOUT3. When the target frequency level is Lve7, advancing the output time TSOUT3 by the fourth clock adjustment period TS41 yields the first target output time corresponding to frequency level Lve7, thus advancing the output time of signal ga2_Lev7 by TS41 on TSOUT3. When the target frequency level is Lve1, delaying the output time TSOUT3 by the third clock adjustment period TS31 yields the first target output time corresponding to frequency level Lve1, thus delaying the output time of signal ga2_Lev1 by TS31 on TSOUT3.

[0183] This disclosure provides other driving methods for display panels, which are variations of the implementation methods described in the above embodiments. The differences between this embodiment and the above embodiments will be described below, while the similarities will not be repeated.

[0184] In some embodiments of this disclosure, such as Figure 19a As shown, the control circuit may include a voltage determination circuit 241, a level conversion circuit 2432, and a source drive circuit 120. The voltage determination circuit 241 is configured to determine a target voltage for generating a gate scan signal based on a target frequency level. The level conversion circuit 2432 is configured to control the display panel 100 to apply a gate scan signal to the gate based on the target voltage. The source drive circuit 120 is configured to apply a data voltage to the data lines based on the displayed data, causing the sub-pixels in the display panel 100 to input data voltage. Exemplarily, the level conversion circuit 2432 is configured to receive a valid target voltage and an invalid target voltage, generate a clock signal based on the received reference clock control signal and the valid and invalid target voltages, and send the generated clock signal to the gate drive circuit 110. The gate drive circuit 110 outputs a gate scan signal based on the received clock signal. Each clock signal input to the gate drive circuit 110 corresponds one-to-one with a reference clock control signal, and the timing of the clock signals input to the gate drive circuit 110 is the same as the corresponding reference clock control signal. The set level can include an active level and an inactive level. The target voltage for the active level is used to generate the active level voltage of the clock signal. The target voltage for the inactive level is used to generate the inactive level voltage of the clock signal. This ensures that the active level voltage of the gate scan signal is also the target voltage for the active level, and the voltage with no level is also the target voltage for the inactive level. For example, combined with... Figure 15 As shown, clock signal ck1 corresponds to reference clock control signal cks1, clock signal ck2 corresponds to reference clock control signal cks2, clock signal ck3 corresponds to reference clock control signal cks3, ... clock signal ck12 corresponds to reference clock control signal cks12. Furthermore, the level conversion circuit 2432 can output clock signal ck1 based on reference clock control signal cks1, clock signal ck2 based on reference clock control signal cks2, clock signal ck3 based on reference clock control signal cks3, ... clock signal ck12 based on reference clock control signal cks12.

[0185] In some embodiments of this disclosure, step S30, controlling the sub-pixel input data voltage in the display panel according to the target frequency level and display data, may include: determining a target voltage for generating a gate scan signal based on the target frequency level; controlling the display panel to apply a gate scan signal to the gate based on the target voltage; and applying a data voltage to the data lines based on the display data, thereby causing the sub-pixel input data voltage in the display panel to be different. Specifically, the target voltage for generating the gate scan signal differs for different frequency levels. By controlling the target voltage for the gate scan signal to be different for different frequency levels, the degree to which transistors are turned on and off in display frames of different frequency levels can be different, thereby minimizing the difference in charging rate of sub-pixels in display frames with different refresh rates and improving the display panel's display defects.

[0186] In some examples, the target level may include an effective level. Determining the target voltage for generating the gate scan signal based on the target frequency level includes: adjusting a first reference voltage for the effective level of the gate scan signal based on the target frequency level to obtain the target voltage for the effective level. And, controlling the display panel to apply the gate scan signal to the gate based on the target voltage includes: controlling the display panel to apply the gate scan signal to the gate based on the obtained target voltage for the effective level. The target voltage for the effective level differs for different frequency levels. For example, if the effective level is high, the target voltage for the high level decreases as the frequency level increases. And if the effective level is low, the target voltage for the low level increases as the frequency level increases. Thus, as the frequency level increases, the degree of transistor activation in the sub-pixels decreases, thereby reducing the charging rate of sub-pixels in display frames corresponding to higher frequency levels and increasing the charging rate of sub-pixels in display frames corresponding to lower frequency levels. This minimizes the difference in charging rate between sub-pixels in display frames with different refresh rates, improving the display panel's display performance.

[0187] For example, such as Figure 19b As shown, the voltage determination circuit 241 may include a second signal generation circuit 2411 and a first reference circuit 2412. The second signal generation circuit 2411 can generate a first reference control signal in digital signal form according to the target frequency level, and send the generated first reference control signal to the first reference circuit 2412. The first reference circuit 2412 is configured to output a target voltage of a high level for generating a gate scan signal based on the first reference control signal when the effective level is high. For example, as... Figure 19bAs shown, the first reference circuit 2412 includes multiple transistors M11 to M18 (taking a circuit with 7 refresh frequency levels as an example). The gate of M11 receives signal DEF11, the gate of M12 receives signal DEF12, ..., the gate of M18 receives signal DEF18. The source of M11 receives the first reference voltage VREF1, and the drain of M18 receives the ground voltage VGND (the first reference voltage VREF1 is greater than the ground voltage VGND). The remaining transistors are connected in series. Each first reference control signal includes DEF11 to DEF18. By setting at least one of DEF11 to DEF18 differently, different first reference control signals can be implemented for different frequency levels, thereby turning on different transistors to output different target voltages. For example, the first reference control signal corresponding to refresh frequency level Lev1 can control transistor M11 to be turned on, while the other transistors are turned off. Then, the first reference circuit 2412 outputs a high-level target voltage VGHS1 corresponding to refresh frequency level Lev1. The first reference control signal corresponding to refresh frequency level Lev2 controls transistors M11 and M12 to turn on, while the remaining transistors are turned off. The first reference circuit 2412 then outputs a high-level target voltage VGHS2 corresponding to refresh frequency level Lev2. The first reference control signal corresponding to refresh frequency level Lev3 controls transistors M11 to M13 to turn on, while the remaining transistors are turned off. The first reference circuit 2412 then outputs a high-level target voltage VGHS3 corresponding to refresh frequency level Lev3. ... The first reference control signal corresponding to refresh frequency level Lev7 controls transistors M11 to M17 to turn on, while the remaining transistors are turned off. The first reference circuit 2412 then outputs a high-level target voltage VGHS7 corresponding to refresh frequency level Lev7. Furthermore, VGHS1 > VGHS2 > VGHS3 > VGHS4 > VGHS5 > VGHS6 > VGHS7. It should be noted that transistors M11 to M18 act as resistors to divide the voltage between the first reference voltage VREF1 and the ground voltage VGND, thereby obtaining different target voltages.

[0188] For example, the first reference voltage is the first reference voltage corresponding to the set frequency level. When the effective level is high, the first reference voltage VREF1 is adjusted to the target voltage so that the high level of the clock signal output by the level conversion circuit 2432 is the target voltage, thereby making the high level voltage of the gate drive signal the target voltage. According to the target frequency level, the first reference voltage for generating the effective level of the gate scan signal is adjusted to obtain the target voltage of the effective level, including: when the set frequency level is the minimum frequency level and the target frequency level is greater than the minimum frequency level, the first reference voltage is reduced by a first effective adjustment voltage to obtain the target voltage of the effective level; wherein, as the frequency level increases, the corresponding first effective adjustment voltage increases. For example, combined with... Figure 20As shown, taking clock signal ck2 as an example, ck2_Lve1 represents the signal at frequency level Lev1 corresponding to clock signal ck2, ck2_Lve3 represents the signal at frequency level Lev3 corresponding to clock signal ck2, and ck2_Lve7 represents the clock signal at frequency level Lev7 corresponding to clock signal ck2. ga2_Lve1 represents the gate scan signal transmitted at frequency level Lev1 corresponding to gate line GA2, ga2_Lve3 represents the gate scan signal transmitted at frequency level Lev3 corresponding to gate line GA2, and ga2_Lve7 represents the gate scan signal transmitted at frequency level Lev7 corresponding to gate line GA2. The first reference voltage is the first reference voltage VREF1, i.e., voltage VGH01 (this voltage VGH01 is the aforementioned target voltage VGHS1), which is the high level of the generated clock signal cks2_Lve1 corresponding to frequency level Lev1. When the target frequency level is Lve1, there is no need to adjust the first reference voltage (i.e., voltage VGH01). The first reference voltage (i.e., voltage VGH01) can be directly used as the target voltage corresponding to frequency level Lve1, and the clock signal ck2_Lve1 is output, so that the high level voltage of the signal ga2_Lev1 is VGH01. When the target frequency level is Lve3, the first reference voltage (i.e., voltage VGH01) is reduced by the first effective adjustment voltage VSZ11 to obtain the target voltage VGH11 corresponding to frequency level Lve3 (this target voltage VGH11 is the aforementioned target voltage VGHS3). The clock signal ck2_Lve3 is output, so that the high level voltage of the signal ga2_Lev3 is VGH11, that is, VSZ11 is reduced on VGH01. When the target frequency level is Lve7, the first reference voltage (i.e., voltage VGH01) is reduced by the first effective adjustment voltage VSZ12 to obtain the target voltage VGH12 corresponding to frequency level Lve7 (this target voltage VGH12 is the aforementioned target voltage VGHS7). A clock signal ck2_Lve7 is then output, making the high-level voltage of the signal ga2_Lev7 VGH12, i.e., reducing VSZ12 from VGH01. Furthermore, VSZ12 > VSZ11.

[0189] For example, the first reference voltage is the first reference voltage corresponding to the set frequency level. When the effective level is high, the first reference voltage VREF1 is adjusted to the target voltage so that the high level of the clock signal output by the level conversion circuit 2432 is the target voltage, thereby making the high level voltage of the gate drive signal the target voltage. According to the target frequency level, the first reference voltage for generating the effective level of the gate scan signal is adjusted to obtain the target voltage of the effective level, including: when the set frequency level is the maximum frequency level and the target frequency level is less than the maximum frequency level, the first reference voltage is increased by a second effective adjustment voltage to obtain the target voltage of the effective level; wherein, as the frequency level increases, the corresponding second effective adjustment voltage decreases. For example, in conjunction with... Figure 21As shown, taking clock signal ck2 as an example, ck2_Lve1 represents the signal at frequency level Lev1 corresponding to clock signal ck2, ck2_Lve3 represents the signal at frequency level Lev3 corresponding to clock signal ck2, and ck2_Lve7 represents the clock signal at frequency level Lev7 corresponding to clock signal ck2. ga2_Lve1 represents the gate scan signal transmitted at frequency level Lev1 corresponding to gate line GA2, ga2_Lve3 represents the gate scan signal transmitted at frequency level Lev3 corresponding to gate line GA2, and ga2_Lve7 represents the gate scan signal transmitted at frequency level Lev7 corresponding to gate line GA2. The first reference voltage is the first reference voltage VREF1, i.e., voltage VGH02 (this voltage VGH02 is the aforementioned target voltage VGHS7), which is the high level of the generated clock signal cks2_Lve7 corresponding to frequency level Lev7. When the target frequency level is Lve7, there is no need to adjust the first reference voltage (i.e., voltage VGH02). The first reference voltage (i.e., voltage VGH02) can be directly used as the target voltage corresponding to frequency level Lve7, and the clock signal ck2_Lve7 is output, so that the high level voltage of the signal ga2_Lev7 is VGH02. When the target frequency level is Lve3, the first reference voltage (i.e., voltage VGH02) is increased by the second effective adjustment voltage VSZ21 to obtain the target voltage VGH21 corresponding to frequency level Lve3 (this target voltage VGH21 is the aforementioned target voltage VGHS3), and the clock signal ck2_Lve3 is output, so that the high level voltage of the signal ga2_Lev3 is VGH21, that is, VSZ21 is increased on VGH02. When the target frequency level is Lve1, the first reference voltage (i.e., voltage VGH02) is increased by the second effective adjustment voltage VSZ22 to obtain the target voltage VGH22 corresponding to frequency level Lve1 (this target voltage VGH22 is the aforementioned target voltage VGHS1). The clock signal ck2_Lve1 is then output, making the high-level voltage of the signal ga2_Lev1 VGH22, i.e., increasing VSZ22 on VGH02. Furthermore, VSZ22 > VSZ21.

[0190] For example, the first reference voltage is the first reference voltage corresponding to the set frequency level. When the effective level is high, the first reference voltage VREF1 is adjusted to the target voltage so that the high level of the clock signal output by the level conversion circuit 2432 is the target voltage, thereby making the high level voltage of the gate drive signal the target voltage. According to the target frequency level, the first reference voltage for generating the effective level of the gate scan signal is adjusted to obtain the target voltage of the effective level, including: when the set frequency level is greater than the minimum frequency level and less than the maximum frequency level, and the target frequency level is less than the set frequency level, the first reference voltage is increased by a third effective adjustment voltage to obtain the target voltage of the effective level. And, when the set frequency level is greater than the minimum frequency level and less than the maximum frequency level, and the target frequency level is greater than the set frequency level, the first reference voltage is decreased by a fourth effective adjustment voltage to obtain the target voltage of the effective level; wherein, as the frequency level increases, the corresponding third effective adjustment voltage decreases, and the corresponding fourth effective adjustment voltage increases. For example, in conjunction with... Figure 22As shown, taking clock signal ck2 as an example, ck2_Lve1 represents the signal at frequency level Lev1 corresponding to clock signal ck2, ck2_Lve3 represents the signal at frequency level Lev3 corresponding to clock signal ck2, and ck2_Lve7 represents the clock signal at frequency level Lev7 corresponding to clock signal ck2. ga2_Lve1 represents the gate scan signal transmitted at frequency level Lev1 corresponding to gate line GA2, ga2_Lve3 represents the gate scan signal transmitted at frequency level Lev3 corresponding to gate line GA2, and ga2_Lve7 represents the gate scan signal transmitted at frequency level Lev7 corresponding to gate line GA2. The frequency level can be set to frequency level Lev3 (of course, it can also be other frequency levels, which are not limited here). The first reference voltage is the first reference voltage VREF1 of the high level of the generated clock signal cks2_Lve3 corresponding to frequency level Lev3, i.e., voltage VGH03 (this voltage VGH03 is the target voltage VGHS3 mentioned above). When the target frequency level is Lve3, there is no need to adjust the first reference voltage (i.e., voltage VGH03). The first reference voltage (i.e., voltage VGH03) can be directly used as the target voltage corresponding to frequency level Lve3, and the clock signal ck2_Lve3 is output, so that the high level voltage of the signal ga2_Lev3 is VGH03. When the target frequency level is Lve1, the first reference voltage (i.e., voltage VGH03) is increased by the third effective adjustment voltage VSZ31 to obtain the target voltage VGH31 corresponding to frequency level Lve1 (this target voltage VGH31 is the aforementioned target voltage VGHS1). The clock signal ck2_Lve1 is output, so that the high level voltage of the signal ga2_Lev1 is VGH31, that is, VSZ31 is increased on VGH03. When the target frequency level is frequency level Lve7, the first reference voltage (i.e., voltage VGH03) is reduced by the fourth effective adjustment voltage VSZ41 to obtain the target voltage VGH41 corresponding to frequency level Lve7 (this target voltage VGH41 is the target voltage VGHS7 mentioned above). The clock signal ck2_Lve7 is output, so that the high level voltage of the signal ga2_Lev7 can be VGH41, that is, VSZ41 is reduced on VGH03.

[0191] For example, such as Figure 19cAs shown, the voltage determination circuit 241 may include a third signal generation circuit 2413 and a second reference circuit 2414. Among them, the third signal generation circuit 2413 may generate a second reference control signal in the form of a digital signal according to the target frequency level, and send the generated second reference control signal to the second reference circuit 2414. The second reference circuit 2414 is configured to output a target voltage of the low level for generating the gate scan signal according to the second reference control signal when the effective level is low. For example, as Figure 19c shown, the second reference circuit 2414 includes multiple transistors M21 to M28 (taking 7 refresh frequency levels as an example). The gate of M21 receives the signal DEF21, the gate of M22 receives the signal DEF22,... the gate of M28 receives the signal DEF28. The source of M21 receives the ground voltage, the drain of M28 receives the second reference voltage VREF2 (the second reference voltage VREF2 is less than the ground voltage VGND), and the remaining transistors are connected in series in turn. Each second reference control signal includes DEF21 to DEF28. By setting at least one of DEF21 to DEF28 to be different, different second reference control signals corresponding to different frequency levels can be realized, so as to turn on different transistors and output different target voltages. For example, for the second reference control signal corresponding to the refresh frequency level Lev1, it can control transistors M21 to M27 to conduct, and the remaining transistors to cut off. Then the second reference circuit 2414 outputs the target voltage VGLS1 corresponding to the refresh frequency level Lev1. For the second reference control signal corresponding to the refresh frequency level Lev2, it can control transistors M21 to M26 to conduct, and the remaining transistors to cut off. Then the second reference circuit 2414 outputs the target voltage VGLS2 corresponding to the refresh frequency level Lev2. For the second reference control signal corresponding to the refresh frequency level Lev3, it can control transistors M21 to M25 to conduct, and the remaining transistors to cut off. Then the second reference circuit 2414 outputs the target voltage VGLS3 corresponding to the refresh frequency level Lev3.... For the second reference control signal corresponding to the refresh frequency level Lev7, it can control transistor M21 to conduct, and the remaining transistors to cut off. Then the second reference circuit 2414 outputs the target voltage VGLS7 corresponding to the refresh frequency level Lev7. And, VGLS1 < VGLS2 < VGLS3 < VGLS4 < VGLS5 < VGLS6 < VGLS7. It should be noted that the transistors M21 to M28 are equivalent to resistors, which divide the voltage between the second reference voltage VREF2 and the ground voltage VGND to obtain different target voltages.

[0192] For example, the first reference voltage is the first reference voltage corresponding to the set frequency level. The effective level can also be a low level, that is, the second reference voltage VREF2 is adjusted to the target voltage so that the low level of the clock signal output by the level conversion circuit 2432 is the target voltage, thereby making the low level voltage of the gate drive signal the target voltage. According to the target frequency level, the first reference voltage for generating the effective level of the gate scan signal is adjusted to obtain the target voltage of the effective level, including: when the set frequency level is the minimum frequency level and the target frequency level is greater than the minimum frequency level, the first reference voltage is increased by a fifth effective adjustment voltage to obtain the target voltage of the effective level; wherein, as the frequency level increases, the corresponding fifth effective adjustment voltage increases. For example, combined with Figure 23As shown, taking clock signal ck2 as an example, ck2_Lve1 represents the signal at frequency level Lev1 corresponding to clock signal ck2, ck2_Lve3 represents the signal at frequency level Lev3 corresponding to clock signal ck2, and ck2_Lve7 represents the clock signal at frequency level Lev7 corresponding to clock signal ck2. ga2_Lve1 represents the gate scan signal transmitted at frequency level Lev1 corresponding to gate line GA2, ga2_Lve3 represents the gate scan signal transmitted at frequency level Lev3 corresponding to gate line GA2, and ga2_Lve7 represents the gate scan signal transmitted at frequency level Lev7 corresponding to gate line GA2. The first reference voltage is the second reference voltage VREF2, i.e., voltage VGL01, which is the low level of the generated clock signal cks2_Lve1 corresponding to frequency level Lev1 (this voltage VGL01 is the aforementioned target voltage VGLS1). When the target frequency level is Lve1, there is no need to adjust the first reference voltage (i.e., voltage VGL01). The first reference voltage (i.e., voltage VGL01) can be directly used as the target voltage corresponding to frequency level Lve1, and the clock signal ck2_Lve1 is output, so that the low level voltage of the signal ga2_Lev1 is VGL01. When the target frequency level is Lve3, the first reference voltage (i.e., voltage VGL01) is increased by the fifth effective adjustment voltage VSZ51 to obtain the target voltage VGL11 corresponding to frequency level Lve3 (this target voltage VGL11 is the aforementioned target voltage VGLS3), and the clock signal ck2_Lve3 is output, so that the low level voltage of the signal ga2_Lev3 is VGL11, that is, VSZ51 is increased on VGL01. When the target frequency level is Lve7, the first reference voltage (i.e., voltage VGL01) is increased by the fifth effective adjustment voltage VSZ52 to obtain the target voltage VGL12 corresponding to frequency level Lve7 (this target voltage VGL12 is the aforementioned target voltage VGLS7). The clock signal ck2_Lve7 is then output, making the low-level voltage of the signal ga2_Lev7 VGL12, i.e., increasing VSZ52 on VGL01. Furthermore, VSZ52 > VSZ51.

[0193] For example, the first reference voltage is the first reference voltage corresponding to the set frequency level. The effective level can also be a low level, that is, the second reference voltage VREF2 is adjusted to the target voltage so that the low level of the clock signal output by the level conversion circuit 2432 is the target voltage, thereby making the low level voltage of the gate drive signal the target voltage. According to the target frequency level, the first reference voltage for generating the effective level of the gate scan signal is adjusted to obtain the target voltage of the effective level, including: when the set frequency level is the maximum frequency level and the target frequency level is less than the maximum frequency level, the first reference voltage is reduced by a sixth effective adjustment voltage to obtain the target voltage of the effective level; wherein, as the frequency level increases, the corresponding sixth effective adjustment voltage decreases. For example, combined with Figure 24As shown, taking clock signal ck2 as an example, ck2_Lve1 represents the signal at frequency level Lev1 corresponding to clock signal ck2, ck2_Lve3 represents the signal at frequency level Lev3 corresponding to clock signal ck2, and ck2_Lve7 represents the clock signal at frequency level Lev7 corresponding to clock signal ck2. ga2_Lve1 represents the gate scan signal transmitted at frequency level Lev1 corresponding to gate line GA2, ga2_Lve3 represents the gate scan signal transmitted at frequency level Lev3 corresponding to gate line GA2, and ga2_Lve7 represents the gate scan signal transmitted at frequency level Lev7 corresponding to gate line GA2. The first reference voltage is the second reference voltage VREF2, i.e., voltage VGL02 (this voltage VGL02 is the aforementioned target voltage VGLS7), which is the low level of the generated clock signal cks2_Lve7 corresponding to frequency level Lev7. When the target frequency level is Lve7, there is no need to adjust the first reference voltage (i.e., voltage VGL02). The first reference voltage (i.e., voltage VGL02) can be directly used as the target voltage corresponding to frequency level Lve7, and the clock signal ck2_Lve7 is output, so that the low level voltage of the signal ga2_Lev7 is VGL02. When the target frequency level is Lve3, the first reference voltage (i.e., voltage VGL02) is reduced by the sixth effective adjustment voltage VSZ61 to obtain the target voltage VGL21 corresponding to frequency level Lve3 (this target voltage VGL21 is the aforementioned target voltage VGLS3), and the clock signal ck2_Lve3 is output, so that the low level voltage of the signal ga2_Lev3 is VGL21, that is, VSZ61 is reduced on VGL02. When the target frequency level is Lve1, the first reference voltage (i.e., voltage VGL02) is reduced by the sixth effective adjustment voltage VSZ62 to obtain the target voltage VGL22 corresponding to frequency level Lve1 (this target voltage VGL22 is the aforementioned target voltage VGLS1). The clock signal ck2_Lve1 is then output, making the low-level voltage of the signal ga2_Lev1 VGL22, i.e., reducing VSZ62 on VGL02. Furthermore, VSZ62 > VSZ61.

[0194] For example, the first reference voltage is the first reference voltage corresponding to the set frequency level. The effective level can also be a low level, that is, the second reference voltage VREF2 is adjusted to the target voltage so that the low level of the clock signal output by the level conversion circuit 2432 is the target voltage, thereby making the low level voltage of the gate drive signal the target voltage. According to the target frequency level, the first reference voltage for generating the effective level of the gate scan signal is adjusted to obtain the target voltage of the effective level, including: when the set frequency level is greater than the minimum frequency level and less than the maximum frequency level, and the target frequency level is less than the set frequency level, the first reference voltage is reduced by a seventh effective adjustment voltage to obtain the target voltage of the effective level. And, when the set frequency level is greater than the minimum frequency level and less than the maximum frequency level, and the target frequency level is greater than the set frequency level, the first reference voltage is increased by an eighth effective adjustment voltage to obtain the target voltage of the effective level; wherein, as the frequency level increases, the corresponding eighth effective adjustment voltage increases, and the corresponding seventh effective adjustment voltage decreases. For example, in combination with... Figure 25As shown, taking clock signal ck2 as an example, ck2_Lve1 represents the signal at frequency level Lev1 corresponding to clock signal ck2, ck2_Lve3 represents the signal at frequency level Lev3 corresponding to clock signal ck2, and ck2_Lve7 represents the clock signal at frequency level Lev7 corresponding to clock signal ck2. ga2_Lve1 represents the gate scan signal transmitted at frequency level Lev1 corresponding to gate line GA2, ga2_Lve3 represents the gate scan signal transmitted at frequency level Lev3 corresponding to gate line GA2, and ga2_Lve7 represents the gate scan signal transmitted at frequency level Lev7 corresponding to gate line GA2. The frequency level can be set to frequency level Lev3 (of course, it can also be other frequency levels, which are not limited here). The first reference voltage is the second reference voltage VREF2, i.e., voltage VGL03, which is the low level of the generated clock signal cks2_Lve3 corresponding to frequency level Lev3 (this voltage VGL03 is the target voltage VGLS3 mentioned above). When the target frequency level is Lve3, there is no need to adjust the first reference voltage (i.e., voltage VGL03). The first reference voltage (i.e., voltage VGL03) can be directly used as the target voltage corresponding to frequency level Lve3, and the clock signal ck2_Lve3 is output, so that the low level voltage of the signal ga2_Lev3 is VGL03. When the target frequency level is Lve7, the first reference voltage (i.e., voltage VGL03) is increased by the eighth effective adjustment voltage VSZ81 to obtain the target voltage VGL41 corresponding to frequency level Lve7 (this target voltage VGL41 is the aforementioned target voltage VGLS7), and the clock signal ck2_Lve7 is output, so that the low level voltage of the signal ga2_Lev7 is VGL41, that is, VSZ81 is increased on VGL03. When the target frequency level is frequency level Lve1, the first reference voltage (i.e., voltage VGL03) is reduced by the seventh effective adjustment voltage VSZ71 to obtain the target voltage VGL31 corresponding to frequency level Lve1 (this target voltage VGL31 is the target voltage VGLS1 mentioned above). The clock signal ck2_Lve1 is output, so that the low level voltage of the signal ga2_Lev1 can be VGL31, that is, VSZ81 is reduced on VGL03.

[0195] It should be noted that the first to eighth effective adjustment voltages are all voltage values, without a positive or negative sign. That is, the first to eighth effective adjustment voltages can be considered as absolute values ​​of specific voltages.

[0196] This disclosure provides further driving methods for display panels, which are variations of the implementation methods described in the above embodiments. The differences between this embodiment and the above embodiments will be described below, while the similarities will not be repeated.

[0197] In some examples, the target level may include an invalid level. Determining the target voltage for generating the gate scan signal based on the target frequency level includes: adjusting a second reference voltage for the invalid level of the gate scan signal based on the target frequency level to obtain the target voltage for the invalid level. And, controlling the display panel to apply the gate scan signal to the gate based on the target voltage includes: controlling the display panel to apply the gate scan signal to the gate based on the obtained target voltage for the invalid level. The target voltage for the invalid level differs for different frequency levels. For example, if the invalid level is high, the target voltage for the high level decreases as the frequency level increases. And if the invalid level is low, the target voltage for the low level increases as the frequency level increases. Thus, as the frequency level increases, the cutoff degree of the transistors in the sub-pixels decreases, thereby reducing leakage current in sub-pixels in display frames corresponding to lower frequency levels and increasing leakage current in sub-pixels in display frames corresponding to higher frequency levels. This minimizes the brightness difference between sub-pixels in display frames with different refresh rates, improving the display panel's display performance.

[0198] For example, such as Figure 19d As shown, the voltage determination circuit 241 may include a fourth signal generation circuit 2415 and a third reference circuit 2416. The fourth signal generation circuit 2415 generates a third reference control signal in digital signal form according to the target frequency level and sends the generated third reference control signal to the third reference circuit 2416. The third reference circuit 2416 is configured to output a low-level target voltage for generating a gate scan signal based on the third reference control signal when the invalid level is low. For example, as... Figure 19dAs shown, the third reference circuit 2416 includes multiple transistors M31 to M38 (taking 7 refresh frequency levels as an example). The gate of M31 receives the signal DEF31, the gate of M32 receives the signal DEF32,..., the gate of M38 receives the signal DEF38. The source of M31 receives the ground voltage, the drain of M38 receives the second reference voltage VREF2 (the second reference voltage VREF2 is less than the ground voltage VGND), and the remaining transistors are connected in series in turn. Each of the second reference control signals includes DEF31 to DEF38. By setting at least one of DEF31 to DEF38 differently, different third reference control signals corresponding to different frequency levels can be achieved, so as to turn on different transistors and output different target voltages. For example, for the third reference control signal corresponding to the refresh frequency level Lev1, transistors M31 to M37 can be controlled to conduct, and the remaining transistors are cut off. Then, the third reference circuit 2416 outputs the target voltage VGLW1 corresponding to the refresh frequency level Lev1. For the third reference control signal corresponding to the refresh frequency level Lev2, transistors M31 to M36 can be controlled to conduct, and the remaining transistors are cut off. Then, the third reference circuit 2416 outputs the target voltage VGLW2 corresponding to the refresh frequency level Lev2. For the third reference control signal corresponding to the refresh frequency level Lev3, transistors M31 to M35 can be controlled to conduct, and the remaining transistors are cut off. Then, the third reference circuit 2416 outputs the target voltage VGLW3 corresponding to the refresh frequency level Lev3.... For the third reference control signal corresponding to the refresh frequency level Lev7, transistor M31 can be controlled to conduct, and the remaining transistors are cut off. Then, the third reference circuit 2416 outputs the target voltage VGLW7 corresponding to the refresh frequency level Lev7. And, VGLW1 < VGLW2 < VGLW3 < VGLW4 < VGLW5 < VGLW6 < VGLW7. It should be noted that transistors M31 to M38 are equivalent to resistors, dividing the voltage between the second reference voltage VREF2 and the ground voltage VGND to obtain different target voltages.

[0199] Exemplarily, when the second reference voltage is the second reference voltage corresponding to the set frequency level and the invalid level is the low level, that is, the second reference voltage VREF2 is adjusted to the target voltage, so that the low level of the clock signal output by the level conversion circuit 2432 is the target voltage, and thus the voltage of the low level of the gate drive signal is the target voltage. According to the target frequency level, after adjusting the second reference voltage that generates the invalid level of the gate scan signal, the target voltage of the invalid level is obtained, including: when the set frequency level is the minimum frequency level and the target frequency level is greater than the minimum frequency level, the second reference voltage is increased by the first invalid adjustment voltage to obtain the target voltage of the invalid level; wherein, as the frequency level increases, the corresponding first invalid adjustment voltage increases. Exemplarily, in combination with Figure 26As shown, taking clock signal ck2 as an example, ck2_Lve1 represents the signal at frequency level Lev1 corresponding to clock signal ck2, ck2_Lve3 represents the signal at frequency level Lev3 corresponding to clock signal ck2, and ck2_Lve7 represents the clock signal at frequency level Lev7 corresponding to clock signal ck2. ga2_Lve1 represents the gate scan signal transmitted at frequency level Lev1 corresponding to gate line GA2, ga2_Lve3 represents the gate scan signal transmitted at frequency level Lev3 corresponding to gate line GA2, and ga2_Lve7 represents the gate scan signal transmitted at frequency level Lev7 corresponding to gate line GA2. The second reference voltage is the second reference voltage VREF2, i.e., voltage VGL04, which is the low level of the generated clock signal cks2_Lve1 corresponding to frequency level Lev1 (this voltage VGL04 is the aforementioned target voltage VGLW1). When the target frequency level is Lve1, there is no need to adjust the second reference voltage (i.e., voltage VGL04). The second reference voltage (i.e., voltage VGL04) can be directly used as the target voltage corresponding to frequency level Lve1, and the clock signal ck2_Lve1 is output, so that the low level voltage of the signal ga2_Lev1 is VGL04. When the target frequency level is Lve3, the second reference voltage (i.e., voltage VGL04) is increased by the first invalid adjustment voltage VWZ11 to obtain the target voltage VGL51 corresponding to frequency level Lve3 (this target voltage VGL51 is the aforementioned target voltage VGLW3), and the clock signal ck2_Lve3 is output, so that the low level voltage of the signal ga2_Lev3 is VGL51, that is, VWZ11 is increased on VGL04. When the target frequency level is Lve7, the second reference voltage (i.e., voltage VGL04) is increased by the first invalid adjustment voltage VWZ12 to obtain the target voltage VGL52 corresponding to frequency level Lve7 (this target voltage VGL52 is the aforementioned target voltage VGLW7). The clock signal ck2_Lve7 is then output, making the low-level voltage of the signal ga2_Lev7 VGL52, i.e., increasing VWZ12 on VGL04. Furthermore, VWZ12 > VWZ11.

[0200] For example, the second reference voltage is the second reference voltage corresponding to the set frequency level. When the invalid level is low, the second reference voltage VREF2 is adjusted to the target voltage so that the low level of the clock signal output by the level conversion circuit 2432 is the target voltage, thereby making the low level voltage of the gate drive signal the target voltage. According to the target frequency level, the second reference voltage used to generate the invalid level of the gate scan signal is adjusted to obtain the target voltage of the invalid level, including: when the set frequency level is the maximum frequency level and the target frequency level is less than the maximum frequency level, the second reference voltage is reduced by a second invalid adjustment voltage to obtain the target voltage of the invalid level; wherein, as the frequency level increases, the corresponding second invalid adjustment voltage decreases. For example, in conjunction with... Figure 27As shown, taking clock signal ck2 as an example, ck2_Lve1 represents the signal at frequency level Lev1 corresponding to clock signal ck2, ck2_Lve3 represents the signal at frequency level Lev3 corresponding to clock signal ck2, and ck2_Lve7 represents the clock signal at frequency level Lev7 corresponding to clock signal ck2. ga2_Lve1 represents the gate scan signal transmitted at frequency level Lev1 corresponding to gate line GA2, ga2_Lve3 represents the gate scan signal transmitted at frequency level Lev3 corresponding to gate line GA2, and ga2_Lve7 represents the gate scan signal transmitted at frequency level Lev7 corresponding to gate line GA2. The second reference voltage is the second reference voltage VREF2, i.e., voltage VGL05, which is the target voltage VGLW7 mentioned above, corresponding to the low level of the generated clock signal cks2_Lve7 at frequency level Lev7. When the target frequency level is Lve7, there is no need to adjust the second reference voltage (i.e., voltage VGL05). The second reference voltage (i.e., voltage VGL05) can be directly used as the target voltage corresponding to frequency level Lve7, and the clock signal ck2_Lve7 is output, so that the low level voltage of the signal ga2_Lev7 is VGL05. When the target frequency level is Lve3, after reducing the second invalid adjustment voltage VWZ21 of the second reference voltage (i.e., voltage VGL05), the target voltage VGL61 corresponding to frequency level Lve3 is obtained (this target voltage VGL61 is the aforementioned target voltage VGLW3), and the clock signal ck2_Lve3 is output, so that the low level voltage of the signal ga2_Lev3 is VGL61, that is, VWZ21 is reduced from VGL05. When the target frequency level is Lve1, the second reference voltage (i.e., voltage VGL05) is reduced by the second invalid adjustment voltage VWZ22 to obtain the target voltage VGL62 corresponding to frequency level Lve1 (this target voltage VGL62 is the aforementioned target voltage VGLW1). A clock signal ck2_Lve1 is output, thus making the low-level voltage of the signal ga2_Lev1 VGL62, i.e., reducing VWZ22 from VGL05. Furthermore, VSZ22 > VSZ21.

[0201] For example, the second reference voltage is the second reference voltage corresponding to the set frequency level. When the invalid level is low, the second reference voltage VREF2 is adjusted to the target voltage so that the low level of the clock signal output by the level conversion circuit 2432 is the target voltage, thereby making the low level voltage of the gate drive signal the target voltage. According to the target frequency level, after adjusting the second reference voltage that generates the invalid level of the gate scan signal, the target voltage of the invalid level is obtained, including: when the set frequency level is greater than the minimum frequency level and less than the maximum frequency level, and the target frequency level is less than the set frequency level, the second reference voltage is reduced by a third invalid adjustment voltage to obtain the target voltage of the invalid level. And, when the set frequency level is greater than the minimum frequency level and less than the maximum frequency level, and the target frequency level is greater than the set frequency level, the second reference voltage is increased by a fourth invalid adjustment voltage to obtain the target voltage of the invalid level; wherein, as the frequency level increases, the corresponding fourth invalid adjustment voltage increases, and the corresponding third invalid adjustment voltage decreases. For example, in conjunction with... Figure 28As shown, taking clock signal ck2 as an example, ck2_Lve1 represents the signal at frequency level Lev1 corresponding to clock signal ck2, ck2_Lve3 represents the signal at frequency level Lev3 corresponding to clock signal ck2, and ck2_Lve7 represents the clock signal at frequency level Lev7 corresponding to clock signal ck2. ga2_Lve1 represents the gate scan signal transmitted at frequency level Lev1 corresponding to gate line GA2, ga2_Lve3 represents the gate scan signal transmitted at frequency level Lev3 corresponding to gate line GA2, and ga2_Lve7 represents the gate scan signal transmitted at frequency level Lev7 corresponding to gate line GA2. The frequency level can be set to frequency level Lev3 (of course, it can also be other frequency levels, which are not limited here), and the second reference voltage is the second reference voltage VREF2 corresponding to the low level of the generated clock signal cks2_Lve3 at frequency level Lev3, i.e., voltage VGL06 (this voltage VGL06 is the target voltage VGLW3 mentioned above). When the target frequency level is Lve3, there is no need to adjust the second reference voltage (i.e., voltage VGL06). The second reference voltage (i.e., voltage VGL06) can be directly used as the target voltage corresponding to frequency level Lve3, and the clock signal ck2_Lve3 is output, so that the low level voltage of the signal ga2_Lev3 is VGL03. When the target frequency level is Lve7, the second reference voltage (i.e., voltage VGL06) is increased by the fourth invalid adjustment voltage VWZ41 to obtain the target voltage VGL81 corresponding to frequency level Lve7 (this target voltage VGL81 is the aforementioned target voltage VGLW7), and the clock signal ck2_Lve7 is output, so that the low level voltage of the signal ga2_Lev7 is VGL81, that is, VWZ41 is reduced on VGL06. When the target frequency level is frequency level Lve1, the second reference voltage (i.e. voltage VGL06) is reduced by the third invalid adjustment voltage VWZ31 to obtain the target voltage VGL71 corresponding to frequency level Lve1 (this target voltage VGL71 is the target voltage VGLW1 mentioned above). The clock signal ck2_Lve1 is output, so that the low level voltage of the signal ga2_Lev1 can be VGL71, that is, VWZ31 is reduced on VGL06.

[0202] For example, such as Figure 19eAs shown, the voltage determination circuit 241 may include a fifth signal generation circuit 2417 and a fourth reference circuit 2418. The fifth signal generation circuit 2417 generates a fourth reference control signal in digital signal form according to the target frequency level and sends the generated fourth reference control signal to the fourth reference circuit 2418. The fourth reference circuit 2418 is configured to output a target voltage of a high level for generating a gate scan signal based on the fourth reference control signal when the invalid level is high. For example, as... Figure 19e As shown, the fourth reference circuit 2418 includes multiple transistors M41 to M48 (taking a circuit with 7 refresh frequency levels as an example). The gate of M41 receives signal DEF11, the gate of M42 receives signal DEF42, ..., the gate of M48 receives signal DEF48. The source of M41 receives the first reference voltage VREF1, and the drain of M48 receives the ground voltage VGND (the first reference voltage VREF1 is greater than the ground voltage VGND). The remaining transistors are connected in series. Each fourth reference control signal includes DEF41 to DEF48. By setting at least one of DEF41 to DEF48 differently, different fourth reference control signals can be implemented for different frequency levels, thereby turning on different transistors to output different target voltages. For example, the fourth reference control signal corresponding to refresh frequency level Lev1 can control transistor M11 to be turned on, while the other transistors are turned off. Then, the fourth reference circuit 2418 outputs a high-level target voltage VGHW1 corresponding to refresh frequency level Lev1. The fourth reference control signal corresponding to refresh frequency level Lev2 can control transistors M41 and M42 to turn on, while the remaining transistors are turned off. The fourth reference circuit 2418 then outputs a high-level target voltage VGHW2 corresponding to refresh frequency level Lev2. The fourth reference control signal corresponding to refresh frequency level Lev3 can control transistors M41 to M43 to turn on, while the remaining transistors are turned off. The fourth reference circuit 2418 then outputs a high-level target voltage VGHW3 corresponding to refresh frequency level Lev3. ... The fourth reference control signal corresponding to refresh frequency level Lev7 can control transistors M41 to M47 to turn on, while the remaining transistors are turned off. The fourth reference circuit 2418 then outputs a high-level target voltage VGHW7 corresponding to refresh frequency level Lev7. Furthermore, VGHW1 > VGHW2 > VGHW3 > VGHW4 > VGHW5 > VGHW6 > VGHW7. It should be noted that transistors M41 to M48 act as resistors to divide the voltage between the first reference voltage VREF1 and the ground voltage VGND, thereby obtaining different target voltages.

[0203] For example, the second reference voltage is the second reference voltage corresponding to the set frequency level. The invalid level can also be a high level. That is, the first reference voltage VREF1 is adjusted to the target voltage so that the high level of the clock signal output by the level conversion circuit 2432 is the target voltage, thereby making the high level voltage of the gate drive signal the target voltage. According to the target frequency level, after adjusting the second reference voltage that generates the invalid level of the gate scan signal, the target voltage of the invalid level is obtained, including: when the set frequency level is the minimum frequency level and the target frequency level is greater than the minimum frequency level, the second reference voltage is reduced by a fifth invalid adjustment voltage to obtain the target voltage of the invalid level; wherein, as the frequency level increases, the corresponding fifth invalid adjustment voltage increases. For example, combined with Figure 29As shown, taking clock signal ck2 as an example, ck2_Lve1 represents the signal at frequency level Lev1 corresponding to clock signal ck2, ck2_Lve3 represents the signal at frequency level Lev3 corresponding to clock signal ck2, and ck2_Lve7 represents the clock signal at frequency level Lev7 corresponding to clock signal ck2. ga2_Lve1 represents the gate scan signal transmitted at frequency level Lev1 corresponding to gate line GA2, ga2_Lve3 represents the gate scan signal transmitted at frequency level Lev3 corresponding to gate line GA2, and ga2_Lve7 represents the gate scan signal transmitted at frequency level Lev7 corresponding to gate line GA2. The second reference voltage is the first reference voltage VREF1, i.e., voltage VGH04, which is the target voltage VGHW7 mentioned above, for the high level of the generated clock signal cks2_Lve1 corresponding to frequency level Lev1. When the target frequency level is Lve1, there is no need to adjust the second reference voltage (i.e., voltage VGH04). The second reference voltage (i.e., voltage VGH04) can be directly used as the target voltage corresponding to frequency level Lve1, and the clock signal ck2_Lve1 is output, so that the high level voltage of the signal ga2_Lev1 is VGH04. When the target frequency level is Lve3, the second reference voltage (i.e., voltage VGH04) is reduced by the fifth invalid adjustment voltage VWZ51 to obtain the target voltage VGH51 corresponding to frequency level Lve3 (this target voltage VGH51 is the aforementioned target voltage VGHW3). The clock signal ck2_Lve3 is output, so that the high level voltage of the signal ga2_Lev3 is VGH51, that is, VWZ51 is reduced from VGH04. When the target frequency level is Lve7, the second reference voltage (i.e., voltage VGH04) is reduced by the fifth invalid adjustment voltage VWZ52 to obtain the target voltage VGH52 corresponding to frequency level Lve7 (this target voltage VGH52 is the aforementioned target voltage VGHW7). The clock signal ck2_Lve7 is then output, making the high-level voltage of the signal ga2_Lev7 VGH52, i.e., reducing VWZ52 from VGH04. Furthermore, VWZ52 > VWZ51.

[0204] For example, the second reference voltage is the second reference voltage corresponding to the set frequency level. The invalid level can also be a high level. That is, the first reference voltage VREF1 is adjusted to the target voltage so that the high level of the clock signal output by the level conversion circuit 2432 is the target voltage, thereby making the high level voltage of the gate drive signal the target voltage. According to the target frequency level, after adjusting the second reference voltage that generates the invalid level of the gate scan signal, the target voltage of the invalid level is obtained, including: when the set frequency level is the maximum frequency level and the target frequency level is less than the maximum frequency level, the second reference voltage is increased by a sixth invalid adjustment voltage to obtain the target voltage of the invalid level; wherein, as the frequency level increases, the corresponding sixth valid adjustment voltage decreases. For example, combined with Figure 30As shown, taking clock signal ck2 as an example, ck2_Lve1 represents the signal at frequency level Lev1 corresponding to clock signal ck2, ck2_Lve3 represents the signal at frequency level Lev3 corresponding to clock signal ck2, and ck2_Lve7 represents the clock signal at frequency level Lev7 corresponding to clock signal ck2. ga2_Lve1 represents the gate scan signal transmitted at frequency level Lev1 corresponding to gate line GA2, ga2_Lve3 represents the gate scan signal transmitted at frequency level Lev3 corresponding to gate line GA2, and ga2_Lve7 represents the gate scan signal transmitted at frequency level Lev7 corresponding to gate line GA2. The second reference voltage is the first reference voltage VREF1, i.e., voltage VGH05, which is the target voltage VGHW7 mentioned above, for the high level of the generated clock signal cks2_Lve7 corresponding to frequency level Lev7. When the target frequency level is Lve1, there is no need to adjust the second reference voltage (i.e., voltage VGH05). The second reference voltage (i.e., voltage VGH05) can be directly used as the target voltage corresponding to frequency level Lve7, and the clock signal ck2_Lve7 is output, so that the high level voltage of the signal ga2_Lev7 is VGH05. When the target frequency level is Lve3, the second reference voltage (i.e., voltage VGH05) is increased by the sixth invalid adjustment voltage VWZ61 to obtain the target voltage VGH61 corresponding to frequency level Lve3 (this target voltage VGH61 is the aforementioned target voltage VGHW3), and the clock signal ck2_Lve3 is output, so that the high level voltage of the signal ga2_Lev3 is VGH61, that is, VWZ61 is increased on VGH05. When the target frequency level is Lve1, the second reference voltage (i.e., voltage VGH05) is increased by the sixth invalid adjustment voltage VWZ62 to obtain the target voltage VGH62 corresponding to frequency level Lve1 (this target voltage VGH62 is the aforementioned target voltage VGHW1). The clock signal ck2_Lve1 is then output, making the high-level voltage of the signal ga2_Lev1 VGH62, i.e., increasing VWZ62 from VGH05. Furthermore, VWZ62 > VWZ61.

[0205] For example, the second reference voltage is the second reference voltage corresponding to the set frequency level. The invalid level can also be a high level. That is, the first reference voltage VREF1 is adjusted to the target voltage so that the high level of the clock signal output by the level conversion circuit 2432 is the target voltage, thereby making the high level voltage of the gate drive signal the target voltage. According to the target frequency level, the second reference voltage that generates the invalid level of the gate scan signal is adjusted to obtain the target voltage of the invalid level, including: when the set frequency level is greater than the minimum frequency level and less than the maximum frequency level, and the target frequency level is less than the set frequency level, the second reference voltage is increased by a seventh invalid adjustment voltage to obtain the target voltage of the invalid level. And, when the set frequency level is greater than the minimum frequency level and less than the maximum frequency level, and the target frequency level is greater than the set frequency level, the second reference voltage is decreased by an eighth invalid adjustment voltage to obtain the target voltage of the invalid level; wherein, as the frequency level increases, the corresponding eighth invalid adjustment voltage increases, and the corresponding seventh invalid adjustment voltage decreases. For example, combined with Figure 31As shown, taking clock signal ck2 as an example, ck2_Lve1 represents the signal at frequency level Lev1 corresponding to clock signal ck2, ck2_Lve3 represents the signal at frequency level Lev3 corresponding to clock signal ck2, and ck2_Lve7 represents the clock signal at frequency level Lev7 corresponding to clock signal ck2. ga2_Lve1 represents the gate scan signal transmitted at frequency level Lev1 corresponding to gate line GA2, ga2_Lve3 represents the gate scan signal transmitted at frequency level Lev3 corresponding to gate line GA2, and ga2_Lve7 represents the gate scan signal transmitted at frequency level Lev7 corresponding to gate line GA2. The frequency level can be set to frequency level Lev3 (of course, it can also be other frequency levels, which are not limited here), and the second reference voltage is the first reference voltage VREF1, i.e., voltage VGH06, which is the target voltage VGHW3 mentioned above, for the high level of the generated clock signal cks2_Lve3 corresponding to frequency level Lev3. When the target frequency level is Lve3, there is no need to adjust the second reference voltage (i.e., voltage VGH06). The second reference voltage (i.e., voltage VGH06) can be directly used as the target voltage corresponding to frequency level Lve3, and the clock signal ck2_Lve3 is output, so that the high level voltage of the signal ga2_Lev3 is VGH06. When the target frequency level is Lve7, the second reference voltage (i.e., voltage VGH06) is reduced by the eighth invalid adjustment voltage VWZ81 to obtain the target voltage VGH81 corresponding to frequency level Lve7 (this target voltage VGH81 is the aforementioned target voltage VGHW7). The clock signal ck2_Lve7 is output, so that the high level voltage of the signal ga2_Lev7 is VGH81, that is, VWZ81 is reduced from VGH06. When the target frequency level is frequency level Lve1, the second reference voltage (i.e., voltage VGH06) is increased by the seventh invalid adjustment voltage VWZ71 to obtain the target voltage VGH71 corresponding to frequency level Lve1 (this target voltage VGH71 is the target voltage VGHW1 mentioned above). The clock signal ck2_Lve1 is output, so that the high level voltage of the signal ga2_Lev1 can be VGH71, that is, VWZ71 is increased on VGH06.

[0206] It should be noted that the first to the eighth invalid adjustment voltages are all voltage values, without a positive or negative sign. That is, the first to the eighth invalid adjustment voltages can be considered as absolute values ​​of specific voltages.

[0207] This disclosure provides further driving methods for display panels, which are variations of the implementation methods described in the above embodiments. The differences between this embodiment and the above embodiments will be described below, while the similarities will not be repeated.

[0208] In some embodiments of this disclosure, such as Figure 32 As shown, the control circuit may include a lookup table determination circuit 245 and a source drive circuit 120. The lookup table determination circuit 245 is configured to determine a target grayscale lookup table corresponding to the target frequency level from a pre-stored set of grayscale lookup tables corresponding to multiple different frequency levels. The source drive circuit 120 is configured to apply a data voltage to the data lines based on the target grayscale lookup table and display data, causing the sub-pixels in the display panel 100 to input the data voltage. The grayscale lookup table includes multiple different first grayscale values, multiple different second grayscale values, and a target grayscale value corresponding to any first grayscale value and any second grayscale value; furthermore, for the same first grayscale value and the same second grayscale value in different grayscale lookup tables, the target grayscale values ​​corresponding to different frequency levels are different.

[0209] For example, the driving device may further include a memory. The memory 250 pre-stores a grayscale lookup table corresponding to each frequency level. For example, the memory 250 pre-stores a grayscale lookup table LUT1 corresponding to frequency level Lev1, a grayscale lookup table LUT2 corresponding to frequency level Lev2, a grayscale lookup table LUT3 corresponding to frequency level Lev3, a grayscale lookup table LUT4 corresponding to frequency level Lev4, a grayscale lookup table LUT5 corresponding to frequency level Lev5, a grayscale lookup table LUT6 corresponding to frequency level Lev6, and a grayscale lookup table LUT7 corresponding to frequency level Lev7. Furthermore, for the same first grayscale value and the same second grayscale value in the grayscale lookup tables LUT1 to LUT7, these target grayscale values ​​are all different. The memory 250 may include at least one of an electrically erasable programmable read-only memory (EEPROM) and flash memory.

[0210] For example, the lookup table determination circuit 245 is configured to retrieve the target grayscale lookup table corresponding to the target frequency level from a plurality of grayscale lookup tables pre-stored in the memory 250 that correspond one-to-one with different frequency levels. For example, if the target frequency level is frequency level Lve1, the lookup table determination circuit 245 retrieves grayscale lookup table LUT1 from the memory 250 as the target grayscale lookup table. If the target frequency level is frequency level Lve3, the lookup table determination circuit 245 retrieves grayscale lookup table LUT3 from the memory 250 as the target grayscale lookup table. If the target frequency level is frequency level Lve7, the lookup table determination circuit 245 retrieves grayscale lookup table LUT7 from the memory 250 as the target grayscale lookup table.

[0211] In some embodiments of this disclosure, step S30, controlling the sub-pixel input data voltage in the display panel 100 according to the target frequency level and display data, may include: determining a target grayscale lookup table corresponding to the target frequency level from a pre-stored set of grayscale lookup tables corresponding to multiple different frequency levels; applying data voltage to the data lines according to the target grayscale lookup table and display data, thereby causing the sub-pixels in the display panel 100 to input data voltage. The grayscale lookup table includes multiple different first grayscale values, multiple different second grayscale values, and a target grayscale value corresponding to any first grayscale value and any second grayscale value; furthermore, for the same first grayscale value and the same second grayscale value in different grayscale lookup tables, the target grayscale value corresponding to different frequency levels is different. This allows charging of sub-pixels at different refresh rates according to different grayscale lookup tables, driving the display panel at different refresh rates, thereby minimizing the difference in charging rate of sub-pixels in display frames at different refresh rates and improving the display panel's poor display quality.

[0212] For example, for the target gray level values ​​corresponding to the same first gray level value and the same second gray level value in different gray level lookup tables, the corresponding target gray level value decreases as the frequency level increases.

[0213] For example, for the target gray level values ​​corresponding to the same first gray level value and the same second gray level value in different gray level lookup tables, the absolute value of the difference between the target gray level values ​​corresponding to each two adjacent frequency levels is the same.

[0214] For example, for the target gray level values ​​corresponding to the same first gray level value and the same second gray level value in different gray level lookup tables, the absolute value of the difference between the target gray level values ​​corresponding to each two adjacent frequency levels decreases or increases sequentially.

[0215] For example, a grayscale lookup table may include: multiple different first grayscale values, multiple different second grayscale values, and a target grayscale value corresponding to any first grayscale value and any second grayscale value. For example, the grayscale lookup table has a corresponding number of grayscale bits, that is, the first grayscale value, the second grayscale value, and the target grayscale value in the grayscale lookup table have corresponding numbers of grayscale bits. For example, if the grayscale lookup table corresponds to 8 bits, then the number of grayscale bits corresponding to the first grayscale value, the second grayscale value, and the target grayscale value can be 8 bits. For example, the first grayscale value in the grayscale lookup table can be all grayscale values ​​from 0 to 255 in the 8-bit grayscale values, and the second grayscale value can be all grayscale values ​​from 0 to 255 in the 8-bit grayscale values. Alternatively, the first grayscale value in the grayscale lookup table can be a portion of the grayscale values ​​from 0 to 255 in the 8-bit grayscale values, and the second grayscale value can be a portion of the grayscale values ​​from 0 to 255 in the 8-bit grayscale values.

[0216] For example, each grayscale lookup table can be set to a 9*9 format, a 19*19 format, a 30*30 format, or other formats. Specifically, when each grayscale lookup table is set to a 9*9 format, the first grayscale value and the second grayscale value can each be set to 9. When each grayscale lookup table is set to a 19*19 format, the first grayscale value and the second grayscale value can each be set to 19. When each grayscale lookup table is set to a 30*30 format, the first grayscale value and the second grayscale value can each be set to 30.

[0217] For example, for the target grayscale value corresponding to the same first grayscale value and the same second grayscale value in different grayscale lookup tables, the target grayscale value decreases as the frequency level increases. For instance, taking grayscale lookup tables LUT1, LUT3, and LUT7 as examples, grayscale lookup tables LUT1, LUT3, and LUT7 may include a portion of the first grayscale value and a portion of the second grayscale value in 8 bits, as well as the target grayscale value corresponding to these first grayscale values ​​and second grayscale values. Figure 33 The grayscale lookup table LUT1 is shown. Figure 34 The grayscale lookup table LUT3 is shown in the diagram. Figure 35 The grayscale lookup table LUT7 is shown. Figures 33 to 35 The values ​​in the first row (e.g., 0, 16, 32, 48, 64, 80, 96, 112, 128, 144, 160, 176, 192, 208, 224, 240, 255) represent the first grayscale value, the values ​​in the first column (e.g., 0, 16, 32, 48, 64, 80, 96, 112, 128, 144, 160, 176, 192, 208, 224, 240, 255) represent the second grayscale value, and the remaining values ​​(e.g., ...) represent the second grayscale value. Figure 33 L1-1 to L17-17, Figure 34 Z1-1 to Z17-17, Figure 35 The H1-1 to H17-17) in it represent the target gray scale values. When the first gray scale value is 0 and the second gray scale value is 32, Figure 33 the target gray scale value in it is L3-1, Figure 34 the target gray scale value in it is Z3-1, Figure 35 the target gray scale value in it is H3-1. And, L3-1 < Z3-1 < H3-1. The same applies to the rest and will not be elaborated here.

[0218] It should be noted that Figures 33 to 35 the specific values of the first gray scale value and the second gray scale value shown in it are only for illustrative purposes. In actual applications, they can be determined according to the requirements of actual applications and are not limited here.

[0219] In some examples, according to the target gray scale look-up table and display data, a data voltage is loaded onto the data line, including: according to the original gray scale values of the display data corresponding to the sub-pixels in the previous row and the current row in the same column in the display data, determining the target gray scale value corresponding to the sub-pixels in the current row from the target gray scale look-up table. According to the determined target gray scale value, a data voltage is loaded onto the data line. Among them, the target gray scale value corresponding to the sub-pixels in the current row is greater than the original gray scale value corresponding to the sub-pixels in the current row. Exemplarily, the values in the first row of the gray scale look-up table can be corresponded to the original gray scale values of the display data corresponding to the sub-pixels in the previous row, and the values in the first column of the gray scale look-up table can be corresponded to the original gray scale values of the display data corresponding to the sub-pixels in the current row, so that the corresponding target gray scale value can be found, and thus a data voltage can be loaded onto the data line according to the found target gray scale value.

[0220] Exemplarily, combined with Figure 33 , when the target frequency level is frequency level Lve1, the look-up table determination circuit 245 retrieves the gray scale look-up table LUT1 from the memory 250 as the target gray scale look-up table. And the retrieved target gray scale look-up table is sent to the source driver circuit 120. According to the received display data, if the red sub-pixel R21 is the sub-pixel in the current row, the original gray scale value of the red sub-pixel R11 corresponding to the previous row is 0, and the original gray scale value of the red sub-pixel R21 corresponding to the current row is 32, then the target gray scale value corresponding to the red sub-pixel R21 is determined from the gray scale look-up table LUT4 as L3-1. And according to the target gray scale value of L3-1, a data voltage is loaded onto the data line DA1 so that the data voltage corresponding to the target gray scale value L3-1 is input into the red sub-pixel R21. The same applies to the rest and will not be elaborated here.

[0221] Exemplarily, combined with Figure 34When the target frequency level is frequency level Lve3, the lookup table determination circuit 245 retrieves the grayscale lookup table LUT3 from the memory 250 as the target grayscale lookup table. It then sends the retrieved target grayscale lookup table to the source driver circuit 120. Based on the received display data, if the red sub-pixel R21 is the current row sub-pixel, the original grayscale value corresponding to the red sub-pixel R11 is 0, and the original grayscale value corresponding to the red sub-pixel R21 is 32, the source driver circuit 120 determines the target grayscale value Z3-1 corresponding to the red sub-pixel R21 from the grayscale lookup table LUT3. Based on the target grayscale value Z3-1, it applies a data voltage to the data line DA1 so that the data voltage corresponding to the target grayscale value Z3-1 is input to the red sub-pixel R21. The rest are similar and will not be elaborated further here.

[0222] For example, referring to Figure 36, when the target frequency level is frequency level Lve7, the lookup table determination circuit 245 retrieves the grayscale lookup table LUT7 from the memory 250 as the target grayscale lookup table. The retrieved target grayscale lookup table is then sent to the source drive circuit 120. Based on the received display data, if the red sub-pixel R21 is the current row sub-pixel, the original grayscale value corresponding to the red sub-pixel R11 is 0, and the original grayscale value corresponding to the red sub-pixel R21 is 32, the source drive circuit 120 determines the target grayscale value H3-1 corresponding to the red sub-pixel R21 from the grayscale lookup table LUT7. Based on the target grayscale value H3-1, a data voltage is applied to the data line DA1 so that the data voltage corresponding to the target grayscale value H3-1 is input to the red sub-pixel R21. The rest are similar and will not be elaborated further here.

[0223] It should be noted that the above embodiments of this disclosure can be combined with each other. That is, the target voltage for generating the gate scan signal can be determined according to the target frequency level. The implementation method of controlling the display panel to load the gate scan signal onto the gate and to load the data line with data voltage according to the display data, so that the sub-pixels in the display panel input data voltage, can be compared with the implementation method of controlling the display panel to load the gate scan signal onto the gate and to load the data line with data voltage according to the target frequency level and display data, such that the interval between the end time of the voltage conversion edge when the data line starts loading data voltage and the start time of the data charging phase corresponding to the sub-pixel charging data voltage is the interval length corresponding to the target frequency level, and the implementation method of determining the target grayscale lookup table corresponding to the target frequency level from a pre-stored grayscale lookup table corresponding to multiple different frequency levels; wherein the grayscale lookup table includes: multiple different first grayscale values, multiple different second grayscale values, and a target grayscale value corresponding to any first grayscale value and any second grayscale value. The implementation methods of applying data voltage to the data lines based on the target grayscale lookup table and display data, so that the sub-pixels in the display panel input data voltage, can be arbitrarily combined, and will not be elaborated here.

[0224] Those skilled in the art will understand that embodiments of this disclosure can be provided as methods, systems, or computer program products. Therefore, this disclosure can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this disclosure can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0225] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a machine for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0226] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0227] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0228] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0229] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. A method for driving a display panel, comprising: Get the display data and current refresh rate corresponding to the current display frame; Based on the current refresh frequency and the pre-stored frequency levels corresponding to different refresh frequency ranges, determine the target frequency level corresponding to the current refresh frequency. Based on the target frequency level and the display data, control the data voltage supplied to the sub-pixels in the display panel; The step of controlling the sub-pixels in the display panel to be charged with data voltage according to the target frequency level and the display data includes: determining a target voltage for generating a gate scan signal according to the target frequency level; wherein: the target voltage for generating the gate scan signal is different for different frequency levels; controlling the display panel to apply a gate scan signal to the gate according to the target voltage, and applying a data voltage to the data line according to the display data, so that the sub-pixels in the display panel input data voltage; The target level includes an effective level; determining the target voltage for generating the gate scan signal based on the target frequency level includes: adjusting a first reference voltage for generating the effective level of the gate scan signal according to the target frequency level to obtain the target voltage of the effective level; wherein the target voltage of the effective level is different for different frequency levels; controlling the display panel to apply the gate scan signal to the gate according to the target voltage includes: controlling the display panel to apply the gate scan signal to the gate according to the obtained target voltage of the effective level; And / or, the target level includes an invalid level; determining the target voltage for generating the gate scan signal according to the target frequency level includes: adjusting the second reference voltage for generating the invalid level of the gate scan signal according to the target frequency level to obtain the target voltage of the invalid level; wherein, the target voltage of the invalid level is different for different frequency levels; controlling the display panel to apply the gate scan signal to the gate according to the target voltage includes: controlling the display panel to apply the gate scan signal to the gate according to the obtained target voltage of the invalid level.

2. The driving method for the display panel as described in claim 1, wherein, The first reference voltage is the first reference voltage corresponding to the set frequency level; the effective level is a high level; The step of adjusting the first reference voltage for generating the effective level of the gate scan signal according to the target frequency level to obtain the target voltage of the effective level includes: When the set frequency level is the minimum frequency level and the target frequency level is greater than the minimum frequency level, the first reference voltage is reduced by a first effective adjustment voltage to obtain the target voltage of the effective level; wherein, as the frequency level increases, the corresponding first effective adjustment voltage increases; When the set frequency level is the maximum frequency level, and the target frequency level is less than the maximum frequency level, the first reference voltage is increased by a second effective adjustment voltage to obtain the target voltage of the effective level; wherein, as the frequency level increases, the corresponding second effective adjustment voltage decreases; When the set frequency level is greater than the minimum frequency level and less than the maximum frequency level, and the target frequency level is less than the set frequency level, the first reference voltage is increased by a third effective adjustment voltage to obtain the target voltage of the effective level; wherein, as the frequency level increases, the corresponding third effective adjustment voltage decreases; When the set frequency level is greater than the minimum frequency level and less than the maximum frequency level, and the target frequency level is greater than the set frequency level, the first reference voltage is reduced by a fourth effective adjustment voltage to obtain the target voltage of the effective level; wherein, as the frequency level increases, the corresponding fourth effective adjustment voltage increases.

3. The driving method for the display panel as described in claim 1, wherein, The first reference voltage is the first reference voltage corresponding to the set frequency level; the effective level is a low level; The step of adjusting the first reference voltage for generating the effective level of the gate scan signal according to the target frequency level to obtain the target voltage of the effective level includes: When the set frequency level is the minimum frequency level and the target frequency level is greater than the minimum frequency level, the first reference voltage is increased by a fifth effective adjustment voltage to obtain the target voltage of the effective level; wherein, as the frequency level increases, the corresponding fifth effective adjustment voltage increases; When the set frequency level is the maximum frequency level, and the target frequency level is less than the maximum frequency level, the first reference voltage is reduced by a sixth effective adjustment voltage to obtain the target voltage of the effective level; wherein, as the frequency level increases, the corresponding sixth effective adjustment voltage decreases; When the set frequency level is greater than the minimum frequency level and less than the maximum frequency level, and the target frequency level is less than the set frequency level, the first reference voltage is reduced by a seventh effective adjustment voltage to obtain the target voltage of the effective level; wherein, as the frequency level increases, the corresponding seventh effective adjustment voltage decreases; When the set frequency level is greater than the minimum frequency level and less than the maximum frequency level, and the target frequency level is greater than the set frequency level, the first reference voltage is increased by an eighth effective adjustment voltage to obtain the target voltage of the effective level; wherein, as the frequency level increases, the corresponding eighth effective adjustment voltage increases.

4. The driving method for the display panel as described in claim 1, wherein, The second reference voltage is the second reference voltage corresponding to the set frequency level; the invalid level is a low level; The step of adjusting the second reference voltage that generates the invalid level of the gate scan signal according to the target frequency level to obtain the target voltage of the invalid level includes: When the set frequency level is the minimum frequency level and the target frequency level is greater than the minimum frequency level, the second reference voltage is increased by a first invalid adjustment voltage to obtain the target voltage of the invalid level; wherein, as the frequency level increases, the corresponding first invalid adjustment voltage increases; When the set frequency level is the maximum frequency level, and the target frequency level is less than the maximum frequency level, the second reference voltage is reduced by a second invalid adjustment voltage to obtain the target voltage of the invalid level; wherein, as the frequency level increases, the corresponding second invalid adjustment voltage decreases; When the set frequency level is greater than the minimum frequency level and less than the maximum frequency level, and the target frequency level is less than the set frequency level, the second reference voltage is reduced by a third invalid adjustment voltage to obtain the target voltage of the invalid level; wherein, as the frequency level increases, the corresponding third invalid adjustment voltage decreases; When the set frequency level is greater than the minimum frequency level and less than the maximum frequency level, and the target frequency level is greater than the set frequency level, the second reference voltage is increased by a fourth invalid adjustment voltage to obtain the target voltage of the invalid level; wherein, as the frequency level increases, the corresponding fourth invalid adjustment voltage increases.

5. The driving method for a display panel as described in claim 1, wherein, The second reference voltage is the second reference voltage corresponding to the set frequency level; the invalid level is a high level; The step of adjusting the second reference voltage that generates the invalid level of the gate scan signal according to the target frequency level to obtain the target voltage of the invalid level includes: When the set frequency level is the minimum frequency level and the target frequency level is greater than the minimum frequency level, the second reference voltage is reduced by a fifth invalid adjustment voltage to obtain the target voltage of the invalid level; wherein, as the frequency level increases, the corresponding fifth invalid adjustment voltage increases; When the set frequency level is the maximum frequency level, and the target frequency level is less than the maximum frequency level, the second reference voltage is increased by a sixth invalid adjustment voltage to obtain the target voltage of the invalid level; wherein, as the frequency level increases, the corresponding sixth valid adjustment voltage decreases; When the set frequency level is greater than the minimum frequency level and less than the maximum frequency level, and the target frequency level is less than the set frequency level, the second reference voltage is increased by a seventh invalid adjustment voltage to obtain the target voltage of the invalid level; wherein, as the frequency level increases, the corresponding seventh invalid adjustment voltage decreases; When the set frequency level is greater than the minimum frequency level and less than the maximum frequency level, and the target frequency level is greater than the set frequency level, the second reference voltage is reduced by an eighth invalid adjustment voltage to obtain the target voltage of the invalid level; wherein, as the frequency level increases, the corresponding eighth invalid adjustment voltage increases.

6. A method for driving a display panel, comprising: Get the display data and current refresh rate corresponding to the current display frame; Based on the current refresh frequency and the pre-stored frequency levels corresponding to different refresh frequency ranges, determine the target frequency level corresponding to the current refresh frequency. Based on the target frequency level and the display data, control the data voltage supplied to the sub-pixels in the display panel; The step of controlling the charging data voltage of the sub-pixels in the display panel according to the target frequency level and the display data includes: Based on the target frequency level and the display data, the display panel is controlled to apply a gate scan signal to the gate and apply a data voltage to the data lines in the display panel, such that the interval between the end time of the voltage conversion edge when the data line starts to apply the data voltage and the start time of the data charging phase corresponding to the sub-pixel that is charged with the data voltage is the interval corresponding to the target frequency level. In this context, increasing the refresh frequency within the refresh frequency range corresponds to increasing the frequency level and the corresponding interval duration.

7. The driving method for a display panel as described in claim 6, wherein, Applying data voltage to the data lines in the display panel includes: Based on the voltage conversion rate of the voltage conversion edge corresponding to the target frequency level, a data voltage is applied to the data lines in the display panel to adjust the interval duration; wherein, as the frequency level increases, the corresponding voltage conversion rate decreases.

8. The driving method for a display panel as described in claim 7, wherein, Applying data voltage to the data lines in the display panel according to the voltage conversion rate of the voltage conversion edge corresponding to the target frequency level includes: Based on the target frequency level, the output impedance corresponding to the target frequency level is selected so that the data voltage is applied to the data line after passing through the output impedance; wherein, as the frequency level increases, the output impedance increases, and the corresponding voltage conversion rate decreases.

9. The driving method for a display panel as described in claim 6, wherein, The start time of the voltage transition edge when the data line starts loading the data voltage is after the start time of the data charging stage corresponding to the sub-pixel that is being charged with the data voltage, and there is a transition time between the start time of the voltage transition edge when the data line starts loading the data voltage and the start time of the data charging stage corresponding to the sub-pixel that is being charged with the data voltage. The control of the display panel to apply a gate scan signal to the gate includes: Based on the conversion time corresponding to the target frequency level, the display panel is controlled to apply a gate scan signal to the gate to adjust the interval time; wherein, as the frequency level increases, the corresponding conversion time increases.

10. The driving method for a display panel as described in claim 9, wherein, The step of controlling the display panel to apply a gate scan signal to the gate according to the conversion time corresponding to the target frequency level includes: Based on the target frequency level, the first reference output time is obtained by adjusting the set level of the reference clock control signal to obtain the first target output time; wherein, as the frequency level increases, the corresponding first target output time is earlier. Based on the first target output time, the set level of the reference clock control signal is output to control the display panel to apply a gate scan signal to the gate.

11. The driving method for a display panel as described in claim 10, wherein, The first reference output time is the output time corresponding to the set frequency level; The step of adjusting the output time of the set level of the reference clock control signal according to the target frequency level to obtain the first target output time includes: When the set frequency level is the minimum frequency level, and the target frequency level is greater than the minimum frequency level, the first reference output time is advanced by the first clock adjustment period to obtain the first target output time; wherein, as the frequency level increases, the corresponding first clock adjustment period increases; When the set frequency level is the maximum frequency level, and the target frequency level is less than the maximum frequency level, the first reference output time is delayed by the second clock adjustment duration to obtain the first target output time; wherein, as the frequency level increases, the corresponding second clock adjustment duration decreases; When the set frequency level is greater than the minimum frequency level and less than the maximum frequency level, and the target frequency level is less than the set frequency level, the first reference output time is delayed by a third clock adjustment duration to obtain the first target output time; wherein, as the frequency level increases, the corresponding third clock adjustment duration decreases; When the set frequency level is greater than the minimum frequency level and less than the maximum frequency level, and the target frequency level is greater than the set frequency level, the first reference output time is advanced by the fourth clock adjustment period to obtain the first target output time; wherein, as the frequency level increases, the corresponding fourth clock adjustment period increases.

12. The driving method for a display panel as described in claim 6, wherein, Applying a data voltage to the data line includes: Based on the target frequency level, the second reference output time of the data voltage is adjusted to obtain the second target output time; wherein, the second target output time is different for different frequency levels; as the frequency level increases, the corresponding second target output time is later. Based on the second target output time, a data voltage is applied to the data line to adjust the interval duration.

13. The driving method for a display panel as described in claim 12, wherein, The second reference output time is the output time corresponding to the set frequency level; The step of adjusting the second reference output time of the data voltage according to the target frequency level to obtain the second target output time includes: When the set frequency level is the minimum frequency level, and the target frequency level is greater than the minimum frequency level, the second reference output time is delayed by the first data adjustment duration to obtain the second target output time; wherein, as the frequency level increases, the corresponding first data adjustment duration increases; When the set frequency level is the maximum frequency level, and the target frequency level is less than the maximum frequency level, the second reference output time is advanced by the second data adjustment time to obtain the second target output time; wherein, as the frequency level increases, the corresponding second data adjustment time decreases; When the set frequency level is greater than the minimum frequency level and less than the maximum frequency level, and the target frequency level is less than the set frequency level, the second reference output time is advanced by the third data adjustment duration to obtain the second target output time; wherein, as the frequency level increases, the corresponding third clock adjustment duration decreases; When the set frequency level is greater than the minimum frequency level and less than the maximum frequency level, and the target frequency level is greater than the set frequency level, the second reference output time is delayed by the fourth data adjustment duration to obtain the second target output time; wherein, as the frequency level increases, the corresponding fourth clock adjustment duration increases.

14. A method for driving a display panel, comprising: Get the display data and current refresh rate corresponding to the current display frame; Based on the current refresh frequency and the pre-stored frequency levels corresponding to different refresh frequency ranges, determine the target frequency level corresponding to the current refresh frequency. Based on the target frequency level and the display data, control the data voltage supplied to the sub-pixels in the display panel; The step of controlling the charging data voltage of the sub-pixels in the display panel according to the target frequency level and the display data includes: Based on the target frequency level, a target grayscale lookup table corresponding to the target frequency level is determined from a pre-stored grayscale lookup table that corresponds one-to-one with multiple different frequency levels. The grayscale lookup table includes: multiple different first grayscale values, multiple different second grayscale values, and a target grayscale value corresponding to any first grayscale value and any second grayscale value. Furthermore, for the same first grayscale value and the same second grayscale value corresponding to the same target grayscale value in different grayscale lookup tables, the target grayscale value corresponding to different frequency levels is different. Based on the target grayscale lookup table and the display data, a data voltage is applied to the data line, so that the sub-pixels in the display panel receive the data voltage.

15. The driving method for a display panel as described in claim 14, wherein, The step of applying a data voltage to the data line based on the target grayscale lookup table and the display data includes: Based on the original grayscale value of the display data corresponding to the sub-pixel of the previous row in the same column and the original grayscale value of the display data corresponding to the sub-pixel of the current row in the same column, the target grayscale value corresponding to the sub-pixel of the current row is determined from the target grayscale lookup table; wherein, the target grayscale value corresponding to the sub-pixel of the current row is greater than the original grayscale value corresponding to the sub-pixel of the current row. Based on the determined target grayscale value, a data voltage is applied to the data line.

16. The driving method for a display panel as described in claim 15, wherein, For the same first gray level value and the same second gray level value in different gray level lookup tables, the corresponding target gray level value decreases as the frequency level increases.

17. A driving device for a display panel, comprising: The acquisition circuit is configured to acquire the display data corresponding to the current display frame and the current refresh rate; The frequency level determination circuit is configured to determine the target frequency level corresponding to the current refresh frequency based on the current refresh frequency and the frequency levels corresponding to different refresh frequency ranges that are pre-stored one-to-one. The control circuit is configured to control the charging voltage of the sub-pixels in the display panel according to the target frequency level and the display data; The control circuit includes: A voltage determination circuit is configured to determine a target voltage for generating a gate scan signal based on the target frequency level; wherein: different frequency levels correspond to different target voltages for generating the gate scan signal. A level shifting circuit is configured to control the display panel to apply a gate scan signal to the gate according to the target voltage; The source drive circuit is configured to apply a data voltage to the data line according to the display data, so that the sub-pixels in the display panel are charged with the data voltage; The target level includes an effective level; determining the target voltage for generating the gate scan signal based on the target frequency level includes: adjusting a first reference voltage for generating the effective level of the gate scan signal according to the target frequency level to obtain the target voltage of the effective level; wherein the target voltage of the effective level is different for different frequency levels; controlling the display panel to apply the gate scan signal to the gate according to the target voltage includes: controlling the display panel to apply the gate scan signal to the gate according to the obtained target voltage of the effective level; And / or, the target level includes an invalid level; determining the target voltage for generating the gate scan signal according to the target frequency level includes: adjusting the second reference voltage for generating the invalid level of the gate scan signal according to the target frequency level to obtain the target voltage of the invalid level; wherein, the target voltage of the invalid level is different for different frequency levels; controlling the display panel to apply the gate scan signal to the gate according to the target voltage includes: controlling the display panel to apply the gate scan signal to the gate according to the obtained target voltage of the invalid level.

18. A driving device for a display panel, comprising: The acquisition circuit is configured to acquire the display data corresponding to the current display frame and the current refresh rate; The frequency level determination circuit is configured to determine the target frequency level corresponding to the current refresh frequency based on the current refresh frequency and the frequency levels corresponding to different refresh frequency ranges that are pre-stored one-to-one. The control circuit is configured to control the charging voltage of the sub-pixels in the display panel according to the target frequency level and the display data; The control circuit includes: The first driving circuit is configured to control the display panel to apply a gate scan signal to the gate according to the target frequency level; The second driving circuit is configured to apply a data voltage to the data lines in the display panel according to the target frequency level and the display data, such that the interval between the end time of the voltage conversion edge when the data line starts to apply the data voltage and the start time of the data charging phase corresponding to the sub-pixel that is charged with the data voltage is the interval corresponding to the target frequency level. In this context, increasing the refresh frequency within the refresh frequency range corresponds to increasing the frequency level and decreasing the interval duration.

19. A driving device for a display panel, comprising: The acquisition circuit is configured to acquire the display data corresponding to the current display frame and the current refresh rate; The frequency level determination circuit is configured to determine the target frequency level corresponding to the current refresh frequency based on the current refresh frequency and the frequency levels corresponding to different refresh frequency ranges that are pre-stored one-to-one. The control circuit is configured to control the charging voltage of the sub-pixels in the display panel according to the target frequency level and the display data; The control circuit includes: The lookup table determination circuit is configured to determine a target grayscale lookup table corresponding to the target frequency level from a pre-stored set of grayscale lookup tables that correspond one-to-one with different frequency levels; wherein the grayscale lookup table includes: multiple different first grayscale values, multiple different second grayscale values, and a target grayscale value corresponding to any first grayscale value and any second grayscale value; and, for the same first grayscale value and the same second grayscale value in different grayscale lookup tables, the target grayscale value corresponding to different frequency levels is different. The source drive circuit is configured to apply a data voltage to the data line according to the target grayscale lookup table and the display data, so that the sub-pixels in the display panel input the data voltage.

Images