Pixel circuit, driving method thereof and display device

Abstract

This disclosure provides a pixel circuit, its driving method, and a display device. In the pixel circuit, a first reset transistor is coupled between the gate of a driving transistor and an initialization signal terminal, and the gate is coupled to a reset control terminal; a compensation transistor is coupled between the gate of the driving transistor and a first electrode, and the gate is coupled to a first scan control terminal; a data write transistor is coupled between the second electrode of the driving transistor and a data signal terminal, and the gate is coupled to a second scan control terminal; a first light-emitting control transistor is coupled between the second electrode of the driving transistor and a first power supply terminal, and the gate is coupled to a light-emitting control terminal; a second light-emitting control transistor is coupled between the first electrode of the driving transistor and the first electrode of a light-emitting device, and the gate is coupled to a light-emitting control terminal; a second reset transistor is coupled between the first electrode of the light-emitting device and an initialization signal terminal, and the gate is coupled to a second scan control terminal; the second electrode of the light-emitting device is coupled to a second power supply terminal.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a pixel circuit, its driving method, and a display device. Background Technology

[0002] Currently, the technology of Active Matrix Organic Light Emitting Diode (AMOLED) flexible screens is becoming increasingly mature. Its characteristics such as flexibility, high contrast and low power consumption make it the next generation of display technology to replace Liquid Crystal Display (LCD).

[0003] In OLEDs, pixels are driven to emit light by the current generated by driving thin-film transistors (DTFTs) in a saturated state. However, current OLED panel manufacturing processes struggle to guarantee the uniformity of DTFT threshold voltages, leading to uneven brightness across pixels. Furthermore, DTFT hysteresis easily causes flickering and image retention issues; and low-grayscale flickering can occur when switching between different driving frequencies. All these problems negatively impact the display performance of the product. Summary of the Invention

[0004] This disclosure provides a pixel circuit, its driving method, and a display device for improving display performance while ensuring narrow bezels and low power consumption.

[0005] In a first aspect, embodiments of this disclosure provide a pixel circuit, comprising:

[0006] The system comprises a first reset transistor, a compensation transistor, a driving transistor, a data writing transistor, a first light-emitting control transistor, a second light-emitting control transistor, a second reset transistor, a storage capacitor, and a light-emitting device; wherein:

[0007] The first reset transistor is coupled between the gate of the driving transistor and the initialization signal terminal, and the gate is coupled to the reset control terminal;

[0008] The compensation transistor is coupled between the gate and the first electrode of the driving transistor, and the gate is coupled to the first scan control terminal.

[0009] The data writing transistor is coupled between the second terminal of the driving transistor and the data signal terminal, and its gate is coupled to the second scan control terminal.

[0010] The first light-emitting control transistor is coupled between the second terminal of the driving transistor and the first power supply terminal, and its gate is coupled to the light-emitting control terminal;

[0011] The second light-emitting control transistor is coupled between the first terminal of the driving transistor and the first terminal of the light-emitting device, and its gate is coupled to the light-emitting control terminal;

[0012] The second reset transistor is coupled between the first electrode of the light-emitting device and the initialization signal terminal, and its gate is coupled to the second scan control terminal;

[0013] The second electrode of the light-emitting device is coupled to the second power supply terminal;

[0014] The storage capacitor is coupled between the first power supply terminal and the gate of the driving transistor;

[0015] Wherein, the first scan control terminal is used to receive a first scan control signal, the second scan control terminal is used to receive a second scan control signal, the effective duration of the second scan control signal is longer than the effective duration of the first scan control signal, and the effective duration of the first scan control signal is covered by the effective duration of the second scan control signal. During the other effective durations of the second scan control signal excluding the covered portion, the data signal terminal is used to receive a constant reset signal, and during the duration of the covered portion, the data signal terminal is used to receive a data signal.

[0016] In one possible implementation, the reset control terminal, the first scan control terminal, and the second scan control terminal are each coupled to different gate drive units.

[0017] In one possible implementation, the reset control terminal is used to receive a reset control signal, the reset control signal and the first scan control signal are provided by different stage output terminals of the same first gate driving unit, and the reset control signal is earlier than the first scan control signal.

[0018] In one possible implementation, the reset control terminal is used to receive a reset control signal, the reset control signal and the second scan control signal are provided by different stage output terminals of the same second gate drive unit, and the reset control signal is earlier than the second scan control signal.

[0019] In one possible implementation, the first reset transistor, the compensation transistor, the driving transistor, the data writing transistor, the first light-emitting control transistor, the second light-emitting control transistor, and the second reset transistor are all P-type transistors.

[0020] In one possible implementation, the driving transistor, the data writing transistor, the first light-emitting control transistor, the second light-emitting control transistor, and the second reset transistor are all P-type transistors, and the first reset transistor and / or the compensation transistor are N-type transistors.

[0021] In one possible implementation, the active layers of the driving transistor, the data writing transistor, the first light-emitting control transistor, the second light-emitting control transistor, and the second reset transistor are made of low-temperature polycrystalline silicon, and the active layers of the first reset transistor and the compensation transistor are made of metal-oxide-semiconductor materials.

[0022] Secondly, embodiments of this disclosure also provide a display device, comprising: a plurality of pixel circuits as described in any of the above claims disposed in a display area, and a gate driving circuit disposed in a non-display area, the gate driving circuit being configured to provide corresponding signals to a reset control terminal, a first scan control terminal, and a second scan control terminal of the pixel circuits.

[0023] In one possible implementation, the gate driving circuit includes a first gate driving unit and a second gate driving unit, wherein the first gate driving unit is coupled to a first scan control terminal of each pixel circuit, and the second gate driving unit is coupled to a second scan control terminal of each pixel circuit.

[0024] In one possible implementation, the first gate driving unit is configured to provide a first scan control signal at a first frequency to the first scan control terminal; the second gate driving unit is configured to provide a second scan control signal at a second frequency to the second scan control terminal; wherein the second frequency is greater than the first frequency, and the effective duration of the second scan control signal is greater than the effective duration of the first scan control signal.

[0025] In one possible implementation, the gate driving circuit further includes a reset driving unit coupled to the reset control terminal of each pixel circuit.

[0026] In one possible implementation, the first gate driving unit is coupled to the reset control terminal of each pixel circuit, and the reset control terminal and the first scan control terminal of the same pixel circuit are respectively coupled to different stage output terminals of the first gate driving unit.

[0027] In one possible implementation, the second gate driving unit is coupled to the reset control terminal of each pixel circuit, and the reset control terminal and the second scan control terminal of the same pixel circuit are respectively coupled to different stage output terminals of the second gate driving unit.

[0028] Thirdly, embodiments of this disclosure also provide a method for driving a pixel circuit as described in any of the preceding claims, comprising:

[0029] Based on the current refresh rate of the display device and the reference refresh rate, the current display frame of the display device is divided into one write frame and N hold frames, where N is an integer greater than 1; wherein, the write frame includes a first reset phase and / or a second reset phase;

[0030] During the first reset phase, the data writing transistor and the driving transistor are turned on, and the constant reset signal is written to the second and first terminals of the driving transistor through the data signal terminal.

[0031] During the second reset phase, the data writing transistor is turned on, and the constant reset signal is written to the second terminal of the driving transistor through the data signal terminal.

[0032] In one possible implementation, the method further includes, for the held frame:

[0033] The reset control signal received by the reset control terminal and the first scan signal received by the first scan control terminal are both kept at invalid potentials.

[0034] Under the control of the second scan control terminal, the constant reset signal is written into the first terminal of the driving transistor through the data signal terminal.

[0035] In one possible implementation, the write frame includes an initialization phase, a first reset phase, a data write phase, a second reset phase, and a light emission phase, which are sequentially configured. The method further includes:

[0036] During the initialization phase, the first reset transistor and the driving transistor are turned on, and the initialization signal is written to the gate of the driving transistor through the initialization signal terminal.

[0037] During the data writing phase, the compensation transistor and the data writing transistor are turned on, the data signal is written to the second terminal of the driving transistor through the data signal terminal, and the threshold voltage of the driving transistor and the data signal are written to the gate of the driving transistor through the compensation transistor and stored in the storage capacitor.

[0038] During the light-emitting phase, the first light-emitting control transistor and the second light-emitting control transistor are turned on, and the light-emitting device emits light. Attached Figure Description

[0039] Figure 1This is a schematic diagram of one type of pixel circuit structure used in related technologies;

[0040] Figure 2 for Figure 1 The pixel circuit shown is one of the timing diagrams used in this circuit.

[0041] Figure 3 This is a schematic diagram of one possible structure of a pixel circuit provided in an embodiment of the present disclosure;

[0042] Figure 4 for Figure 3 The pixel circuit shown is one of the timing diagrams for the write frame.

[0043] Figure 5 This is a schematic diagram of one possible structure of a pixel circuit provided in an embodiment of the present disclosure;

[0044] Figure 6 This is a schematic diagram of one possible structure of a pixel circuit provided in an embodiment of the present disclosure;

[0045] Figure 7 This is a schematic diagram of one possible structure of a pixel circuit provided in an embodiment of the present disclosure;

[0046] Figure 8 for Figure 3 The pixel circuit shown is one of the timing diagrams for the holding frame.

[0047] Figure 9 for Figure 3 The diagram shows one possible operation of the pixel circuit during the initialization phase.

[0048] Figure 10 for Figure 3 The diagram shown illustrates one possible operation of the pixel circuit during the first reset phase.

[0049] Figure 11 for Figure 3 The diagram shows one possible operation of the pixel circuit during the data writing stage.

[0050] Figure 12 for Figure 3 The diagram shown illustrates one possible operation of the pixel circuit during the second reset phase.

[0051] Figure 13 for Figure 3 The diagram shows one possible operation of the pixel circuit during the light-emitting stage.

[0052] Figure 14 for Figure 3 The pixel circuit shown is one of the timing diagrams for the write frame.

[0053] Figure 15 This is a schematic diagram of one structure of a display device provided in an embodiment of the present disclosure;

[0054] Figure 16 This is a schematic diagram of one structure of a display device provided in an embodiment of the present disclosure;

[0055] Figure 17 This is a schematic diagram of one structure of a display device provided in an embodiment of the present disclosure;

[0056] Figure 18 This is a schematic diagram of one structure of a display device provided in an embodiment of the present disclosure;

[0057] Figure 19 This is a schematic diagram of one structure of a display device provided in an embodiment of the present disclosure;

[0058] Figure 20 A flowchart illustrating a method for driving a pixel circuit according to an embodiment of this disclosure;

[0059] Figure 21 A flowchart illustrating one method of driving a pixel circuit for a holding frame, as provided in an embodiment of this disclosure;

[0060] Figure 22 This is a flowchart of one method for driving a pixel circuit for writing a frame, provided as an embodiment of the present disclosure. Detailed Implementation

[0061] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0062] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. As used in this disclosure, the words “comprising” or “including” and similar terms mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, but do not exclude other elements or objects.

[0063] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0064] In related technologies, the following can be adopted: Figure 1 The pixel circuit shown is combined with Figure 2 The timing diagram shown aims to improve the aforementioned problems. The pixel circuit includes eight transistors: m1, m2, m3, m4, m5, m6, m7, and m8. m3 represents the DTFT, and n1, n2, and n3 represent the nodes where each transistor is coupled to the corresponding electrode of the DTFT. m1 and m2 are metal-oxide-semiconductor transistors, and m3 to m8 are low-temperature polysilicon transistors. In stage ①, n1, n2, and n3 are high-level reset and emit light; in stage ②, n1 is low-level reset, and the DTFT has a large Vgs; in stage ③, n1, n2, and n3 are low-level reset; in stage ④, data is written through the DA terminal, and the DTFT threshold voltage is compensated; in stage ⑤, the anode (corresponding to…)… Figure 3 In stage ⑥, the light emission control signal em is adjusted using pulse width modulation (PWM). In stage ⑦, the anode is reset, and n3 is reset to a high level. Using this in conjunction with the low-level reset of n3 in stage ⑤ can improve frequency switching flicker. Because in the use of… Figure 2 The timing diagram shown controls Figure 1 During the pixel circuit process shown, nodes n1, n2, and n3 can all be reset, nodes n1, n2, and n3 can be reset alternately using high and low levels, and the Vgs voltage of the DTFT can be increased, thereby further improving the hysteresis problem of the DTFT and ensuring the display effect.

[0065] However, in Figure 1 and Figure 2 In this design, the pixel circuit is essentially an 8T1C structure, requiring five sets of gate on array (GOA) circuits, three reset signals, and more complex timing. As a result, the increased number of transistors, GOAs, and reset signals are detrimental to increasing pixel density (Pixels Per Inch, PPI), narrowing the bezel, and reducing GOA power consumption.

[0066] In view of this, embodiments of the present disclosure provide a pixel circuit, its driving method, and a display device for improving display effects while ensuring narrow bezels and low power consumption design.

[0067] like Figure 3As shown, this disclosure provides a pixel circuit, which includes:

[0068] The system comprises a first reset transistor T1, a compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a second reset transistor T7, a storage capacitor C, and a light-emitting device 10; wherein:

[0069] The first reset transistor T1 is coupled between the gate of the driving transistor T3 and the initialization signal terminal Vinit, and the gate is coupled to the reset control terminal R;

[0070] The compensation transistor T2 is coupled between the gate and the first terminal of the driving transistor T3, and the gate is coupled to the first scan control terminal G.

[0071] The data writing transistor T4 is coupled between the second terminal of the driving transistor T3 and the data signal terminal D, and its gate is coupled to the second scan control terminal S.

[0072] The first light-emitting control transistor T5 is coupled between the second terminal of the driving transistor T3 and the first power supply terminal VDD, and its gate is coupled to the light-emitting control terminal EM.

[0073] The second light-emitting control transistor T6 is coupled between the first terminal of the driving transistor T3 and the first terminal of the light-emitting device 10, and its gate is coupled to the light-emitting control terminal EM;

[0074] The second reset transistor T7 is coupled between the first electrode of the light-emitting device 10 and the initialization signal terminal Vinit, and its gate is coupled to the second scan control terminal S;

[0075] The second electrode of the light-emitting device 10 is coupled to the second power supply terminal VSS;

[0076] The storage capacitor C is coupled between the first power supply terminal VDD and the gate of the driving transistor T3;

[0077] Wherein, the first scan control terminal G is used to receive a first scan control signal, the second scan control terminal S is used to receive a second scan control signal, the effective duration of the second scan control signal is longer than the effective duration of the first scan control signal, and the effective duration of the first scan control signal is covered by the effective duration of the second scan control signal. During the other effective durations of the second scan control signal excluding the covered portion, the data signal terminal D is used to receive a constant reset signal, and during the duration of the covered portion, the data signal terminal D is used to receive a data signal.

[0078] In the specific implementation process, it is still combined with Figure 3 As shown, the pixel circuit provided in this embodiment may include seven transistors, including a first reset transistor T1, a compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, and a second reset transistor T7. This is in contrast to... Figure 1 The pixel circuit shown reduces the number of transistors, which is beneficial for narrow bezel design. The first reset transistor T1 is coupled between the gate of the driving transistor T3 and the initialization signal terminal Vinit, and its gate is coupled to the reset control terminal R. Thus, when the first reset transistor T1 is turned on, the gate of the driving transistor T3 can be reset via the initialization signal terminal Vinit. The compensation transistor T2 is coupled between the gate of the driving transistor T3 and its first terminal, and its gate is coupled to the first scan control terminal G. The data write transistor T4 is coupled between the second terminal of the driving transistor T3 and the data signal terminal D, and its gate is coupled to the second scan control terminal S. When both the data write transistor T4 and the compensation transistor T2 are turned on, the threshold voltage of the driving transistor T3 and the data signal provided by the data signal terminal D can be written to the gate of the driving transistor T3, thereby compensating for the threshold voltage of the driving transistor T3.

[0079] Still combined Figure 3 As shown, the first light-emitting control transistor T5 is coupled between the second terminal of the driving transistor T3 and the first power supply terminal VDD, and its gate is coupled to the light-emitting control terminal EM. The first power supply terminal VDD can be a high-potential power supply terminal, providing a constant high-potential signal. The second light-emitting control transistor T6 is coupled between the first terminal of the driving transistor T3 and the first terminal of the light-emitting device 10, and its gate is coupled to the light-emitting control terminal EM. Thus, when both the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on, the light-emitting device 10 emits light. The second reset transistor T7 is coupled between the first terminal of the light-emitting device 10 and the initialization signal terminal Vinit, and its gate is coupled to the second scan control terminal S. Thus, when the second reset transistor T7 is turned on, the initialization signal provided by the initialization signal terminal Vinit can be written to the first terminal of the light-emitting device 10. When the first terminal of the light-emitting device 10 is anode, anode reset is achieved, thereby ensuring low-frequency display. The second terminal of the light-emitting device 10 is coupled to the second power supply terminal VSS, which can be a low-potential power supply terminal, providing a constant low-potential signal. The storage capacitor C is coupled between the first power supply terminal VDD and the gate of the driving transistor T3. The storage capacitor C ensures the stability of the gate potential of the driving transistor T3, thereby guaranteeing the driving effect.

[0080] Still combined Figure 3As shown, the first reset transistor T1, the compensation transistor T2, the driving transistor T3, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, and the second reset transistor T7 are all P-type transistors. Figure 4 As shown Figure 3 The pixel circuit shown is one of the timing diagrams for the write frame.

[0081] Still combined Figure 4 As shown, the first scan control terminal G receives the first scan control signal, and the second scan control terminal S receives the second scan control signal. The effective duration of the second scan control signal is longer than that of the first scan control signal. This allows the data signal terminal D to control the reset of the second electrode of the driving transistor T3 using the relatively longer effective duration of the second scan signal, thus ensuring the driving capability of the pixel circuit. Furthermore, the effective duration of the first scan control signal is covered by the effective duration of the second scan control signal. During the remaining effective duration of the second scan control signal (excluding the covered portion), the data signal terminal D receives a constant reset signal, and during the covered portion, it receives a data signal. This allows the required signal to be provided to the data signal terminal D within the desired control duration. On the one hand, during the remaining effective duration, the data signal terminal D receives a constant reset signal, ensuring that the potential of the first electrode of the driving transistor T3 is the same during frame writing and frame holding, thus avoiding the problem of frequency switching flicker. On the other hand, during the duration of the coverage, the data signal terminal D receives the data signal and writes the data signal and the threshold voltage of the driving transistor T3 into the gate of the driving transistor T3, thereby ensuring the uniformity of the threshold voltage of the driving transistor T3.

[0082] In one exemplary embodiment, the reset control terminal R, the first scan control terminal G, and the second scan control terminal S are respectively coupled to different gate driving units. Accordingly, the pixel circuit provided in this disclosure embodiment requires three different gate driving units for driving, compared to... Figure 1 In this respect, fewer gate drive units are required, which is more conducive to narrow bezel design.

[0083] In one exemplary embodiment, the reset control terminal R is used to receive a reset control signal. The reset control signal and the first scan control signal are provided by different stage output terminals of the same first gate driving unit, and the reset control signal is earlier than the first scan control signal. For example, the reset control signal can be turned on eight rows earlier in the pixel row of the display panel. That is, when the first scan control terminal of the current pixel row receives a valid first scan control signal, the reset control terminals of the eight pixel rows preceding the current pixel row simultaneously receive valid reset control signals. In other words, the reset control terminal R and the first scan control terminal G are respectively coupled to different stage output terminals of the same first gate driving unit, and the second scan control terminal S is coupled to other gate driving units different from the first gate driving unit. In this way, the pixel circuit provided in this embodiment requires two gate driving units to drive, compared to Figure 1 In this case, fewer gate drive units are required, which is more conducive to narrow bezel design. In addition, the reset control signal is earlier than the first scan control signal. This ensures that the initialization signal provided by the initialization signal terminal Vinit is written to the gate of the drive transistor T3 first, and then the compensation transistor T2 is turned on to perform threshold voltage compensation on the gate of the drive transistor T3, thereby ensuring the performance of the pixel circuit.

[0084] In one exemplary embodiment, the reset control terminal R is used to receive a reset control signal. The reset control signal and the second scan control signal are provided by different stage outputs of the same second gate driving unit, and the reset control signal precedes the second scan control signal. That is, the reset control terminal R and the second scan control terminal S are coupled to different stage outputs of the same second gate driving unit, and the first scan control terminal G is coupled to other gate driving units different from the second gate driving unit. Thus, the pixel circuit provided in this embodiment requires two gate driving units for driving, compared to... Figure 1 In this design, fewer gate drive units are required, which is more conducive to narrow bezel design. Furthermore, the reset control signal precedes the second scan control signal. This ensures that the initialization signal provided by the initialization signal terminal Vinit is first written to the gate of the drive transistor T3. Then, the data writing transistor T4 and the second reset transistor T7 are turned on, so that the signal provided by the data signal terminal D is written to the second terminal of the drive transistor T3, and the initialization signal provided by the initialization signal terminal Vinit is written to the first terminal of the light-emitting device 10, ensuring the effect of low-frequency display.

[0085] In this embodiment, the driving transistor T3, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, and the second reset transistor T7 are all P-type transistors, and the first reset transistor T1 and / or the compensation transistor T2 are N-type transistors.

[0086] In one exemplary embodiment, such as Figure 5 As shown, the driving transistor T3, data writing transistor T4, first light-emitting control transistor T5, second light-emitting control transistor T6, and second reset transistor T7 are all P-type transistors, while the first reset transistor T1 and compensation transistor T2 are both N-type transistors. (Still combined with...) Figure 5 As shown, the active layers of the driving transistor T3, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, and the second reset transistor T7 are made of low-temperature polycrystalline silicon, while the active layers of the first reset transistor T1 and the compensation transistor T2 are made of metal oxide semiconductor material.

[0087] Still combined Figure 5 As shown, in the pixel circuit provided in this embodiment, the first reset transistor T1 and the compensation transistor T2 can be N-type transistors with metal-oxide-semiconductor (MODS) material as the active layer. Therefore, in actual operation of the pixel circuit, the first reset transistor T1 and the compensation transistor T2 have relatively small leakage current. The driving transistor T3, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, and the second reset transistor T7 can be P-type transistors with low-temperature polysilicon (LTPS) material as the active layer. Thus, in actual operation of the pixel circuit, the driving transistor T3, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, and the second reset transistor T7 have higher mobility, lower power consumption, and can be made thinner. Figure 5 The pixel circuit shown is actually a low-temperature polysilicon+oxide (LTPO) pixel circuit that combines the two transistor fabrication processes of LTPS transistor and oxide transistor, thereby ensuring that the gate leakage current of the driving transistor T3 is small and the power consumption is low.

[0088] In the embodiments disclosed herein, such as Figure 6As shown, the first reset transistor T1, the driving transistor T3, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, and the second reset transistor T7 are all P-type transistors, and the compensation transistor T2 is an N-type transistor.

[0089] Still combined Figure 6 As shown, in the pixel circuit provided in this embodiment, the compensation transistor T2 can be an N-type transistor with a metal-oxide-semiconductor (MODS) material as the active layer. Therefore, in actual operation of the pixel circuit, the compensation transistor T2 has a smaller leakage current. The first reset transistor T1, driving transistor T3, data writing transistor T4, first light-emitting control transistor T5, second light-emitting control transistor T6, and second reset transistor T7 can be P-type transistors with low-temperature polysilicon (LTPS) material as the active layer. Thus, in actual operation of the pixel circuit, the first reset transistor T1, driving transistor T3, data writing transistor T4, first light-emitting control transistor T5, second light-emitting control transistor T6, and second reset transistor T7 have higher mobility, lower power consumption, and can be made thinner. Figure 6 The pixel circuit shown is actually an LTPO type pixel circuit, which combines low leakage current and low power consumption, ensuring the performance of the pixel circuit.

[0090] In the embodiments disclosed herein, such as Figure 7 As shown, the compensation transistor T2, the driving transistor T3, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, and the second reset transistor T7 are all P-type transistors, and the first reset transistor T1 is an N-type transistor.

[0091] Still combined Figure 7 As shown, in the pixel circuit provided in this embodiment, the first reset transistor T1 can be an N-type transistor with a metal-oxide-semiconductor (MODS) material as the active layer. In this way, the compensation transistor T2 has a smaller leakage current during actual operation of the pixel circuit. The compensation transistor T2, driving transistor T3, data writing transistor T4, first light-emitting control transistor T5, second light-emitting control transistor T6, and second reset transistor T7 can be P-type transistors with low-temperature polysilicon (LTPS) material as the active layer. That is, the corresponding transistors are LTPS transistors. In this way, during actual operation of the pixel circuit, the compensation transistor T2, driving transistor T3, data writing transistor T4, first light-emitting control transistor T5, second light-emitting control transistor T6, and second reset transistor T7 have higher mobility, lower power consumption, and can be made thinner. Thus, Figure 7The pixel circuit shown is actually an LTPO type pixel circuit, which combines low leakage current and low power consumption, ensuring the performance of the pixel circuit.

[0092] It should be noted that the light-emitting device 10 in this embodiment can be an electroluminescent diode, such as at least one of organic light-emitting diodes (OLEDs), quantum dot light-emitting diodes (QLEDs), and micro light-emitting diodes / mini light-emitting diodes, and is not limited herein. The light-emitting device 10 may include an anode, a light-emitting layer, and a cathode stacked together. Further, the light-emitting layer may include film layers such as a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer. Of course, in practical applications, the light-emitting device 10 can be designed according to the requirements of the actual application environment, and is not limited here.

[0093] The first and second terminals of the aforementioned transistors can be interchanged depending on their type and the signal at the signal terminal. For example, the first terminal can be the source and the second terminal the drain, or vice versa; no limitation is made here. The transistors can be thin-film transistors (TFTs) or metal-oxide-semiconductor field-effect transistors (MOSs); no limitation is made here. Of course, the specific type of each transistor can be set according to the actual application requirements; no limitation is made here.

[0094] The above are merely illustrative examples illustrating the specific structure of the pixel circuit provided in the embodiments of this disclosure. In specific implementations, the specific structure of the pixel circuit is not limited to the structure provided in the embodiments of this disclosure, but may also be other structures known to those skilled in the art. These are all within the protection scope of this invention, and are not specifically limited here.

[0095] The following is based on Figure 3 The pixel circuit structure shown and Figure 4 and Figure 8 The timing diagram shown is as follows, in which, Figure 4 for Figure 3 The shown pixel circuit corresponds to one type of timing diagram of the write frame. Figure 8 for Figure 3The timing diagram shown illustrates one possible holding frame for the pixel circuit, explaining the operation of the pixel circuit provided in this embodiment. The first power supply terminal VDD provides a high-level potential signal, and the second power supply terminal VSS provides a low-level potential signal. In specific implementations, the current display frame of the display device can be divided into one write frame and N holding frames based on the current refresh frequency and the reference refresh frequency, where N is an integer greater than 1. For example, if the current refresh frequency is 40Hz and the reference refresh frequency is 120Hz (three times the current refresh frequency), the current display frame can be divided into one write frame and two holding frames. Alternatively, if the current refresh frequency is 60Hz and the reference refresh frequency is 120Hz (twice the current refresh frequency), the current display frame can be divided into one write frame and one holding frame. Of course, the current display frame can also be divided according to actual application needs, and this is not limited here. Figure 4 In the timing diagram shown, a write frame includes an initialization phase t1, a first reset phase t2, a data write phase t3, a second reset phase t4, and a light emission phase t5, which are set sequentially. It should be noted that the embodiments disclosed herein are for better explanation of the pixel circuit provided and do not limit the specific implementation of this disclosure. In this context, "0" represents a low level and "1" represents a high level.

[0096] During the initialization phase t1, EM = 1, Reset = 0, Scan = 1, Gate = 1;

[0097] like Figure 9 The diagram shows one possible operation of the pixel circuit during initialization phase t1. During initialization phase t1, the first reset transistor T1 is turned on under the low-level control of the reset control signal provided by the reset control terminal R. When the driving transistor T3 is turned on, the initialization signal is written to the gate (i.e., node N1) of the driving transistor T3 through the initialization signal terminal Vinit and stored in the storage capacitor C. Furthermore, the potential of node N1 is: Vg = Vinit. Additionally, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned off under the high-level control of the light-emitting control signal provided by the light-emitting control terminal EM, and the light-emitting device 10 does not emit light. The data writing transistor T4 and the second reset transistor T7 are turned off under the high-level control of the second scan control signal provided by the second scan control terminal S. The compensation transistor T2 is turned off under the high-level control of the first scan control signal provided by the first scan control terminal G.

[0098] During the first reset phase t2, EM = 1, Reset = 1, Scan = 0, Gate = 1;

[0099] like Figure 10The diagram illustrates one possible operation of the pixel circuit during the first reset phase t2. During t2, the data writing transistor T4 is turned on under the low-level control of the second scan control signal provided by the second scan control terminal S. At this time, a large constant reset signal is written to the second terminal (node ​​N2) of the driving transistor T3 through the data signal terminal D. Furthermore, when the driving transistor T3 is turned on, this constant reset signal can be written to the first terminal (node ​​N1) of the driving transistor T3. In one exemplary embodiment, the constant reset signal is 7V, and the initialization signal is -3V. During the first reset phase, the potential difference between the gate and source of the driving transistor T3 is Vgs = -10V. This results in a large Vgs for the driving transistor T3, which can improve the filling state of the channel defect state from the previous image, thereby improving image retention. Furthermore, the second reset transistor T7 is turned on under the low-level control of the second scan control signal provided by the second scan control terminal S, which allows the initialization signal provided by the initialization signal terminal Vinit to be written into the first electrode (i.e., node N4) of the light-emitting device 10. When the first electrode of the light-emitting device 10 is the anode, an anode reset is achieved, thus ensuring low-frequency display. In addition, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned off under the high-level control of the light-emitting control signal provided by the light-emitting control terminal EM, and the light-emitting device 10 does not emit light. The first reset transistor T1 is turned off under the high-level control of the reset control signal provided by the reset control terminal R. The compensation transistor T2 is turned off under the high-level control of the first scan control signal provided by the first scan control terminal G.

[0100] During the data writing phase t3, EM=1, Reset=1, Scan=0, Gate=0;

[0101] like Figure 11The diagram shows one possible operation of the pixel circuit during the data writing stage t3. During data writing stage t3, compensation transistor T2 is turned on under the control of a low level of the first scan control signal provided by the first scan control terminal G. Data writing transistor T4 is turned on under the control of a low level of the second scan control signal provided by the second scan control terminal S. At this time, the data signal actually required for the light emission stage t5 can be written to the second terminal of driving transistor T3 through the data signal terminal D. Furthermore, the threshold voltage of driving transistor T3 and the data signal are written to the gate of driving transistor T3 through compensation transistor T2 until the potential of node N1 is: Vg = Vdata + Vth, where Vth represents the threshold voltage of driving transistor T3 and Vdata represents the voltage of the data signal. Moreover, the signal written to the gate of driving transistor T3 can be stored in storage capacitor C. In this way, after forming the current path between driving transistor T3 and light-emitting device 10, driving transistor T3 generates a driving current under the action of releasing the written signal from storage capacitor C, thereby controlling the light-emitting device 10 to emit light and ensuring the driving capability of the pixel circuit. Furthermore, the second reset transistor T7 is turned on under the low-level control of the second scan control signal provided by the second scan control terminal S, which allows the initialization signal provided by the initialization signal terminal Vinit to be written into the first electrode of the light-emitting device 10. When the first electrode of the light-emitting device 10 is the anode, an anode reset is achieved, thus ensuring low-frequency display. In addition, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned off under the high-level control of the light-emitting control signal provided by the light-emitting control terminal EM, and the light-emitting device 10 does not emit light. The first reset transistor T1 is turned off under the high-level control of the reset control signal provided by the reset control terminal R.

[0102] During the second reset phase t4, EM = 1, Reset = 1, Scan = 0, Gate = 1;

[0103] like Figure 12The diagram shows one possible operation of the pixel circuit during the second reset phase t4. During the second reset phase t4, the data writing transistor T4 is turned on under the low-level control of the second scan control signal provided by the second scan control terminal S. At this time, a constant reset signal can be written to the second terminal of the driving transistor T3 through the data signal terminal D. Correspondingly, the voltage of node N2 is a fixed voltage value. Since the potential of node N1 is Vg = Vdata + Vth, node N3 will also be refreshed to a certain fixed voltage value. Thus, before the light-emitting device 10 emits light, the potential of node N3 is the same in both the write frame and the hold frame under the same grayscale image, thereby avoiding the problem of frequency switching flicker. Furthermore, the second reset transistor T7 is turned on under the low-level control of the second scan control signal provided by the second scan control terminal S, and the initialization signal provided by the initialization signal terminal Vinit can be written to the first terminal of the light-emitting device 10. When the first terminal of the light-emitting device 10 is anode, anode reset is achieved, thereby ensuring low-frequency display. Furthermore, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are cut off under the control of a high-level light-emitting control signal provided by the light-emitting control terminal EM, and the light-emitting device 10 does not emit light. The first reset transistor T1 is cut off under the control of a high-level reset control signal provided by the reset control terminal R. The compensation transistor T2 is cut off under the control of a high-level first scan control signal provided by the first scan control terminal G. In this way, regardless of which frame is written, the potential of node N3 can be guaranteed to be the same in both the write frame and the hold frame, effectively avoiding the problem of frequency switching flicker.

[0104] During the luminescence phase t5, EM = 0, Reset = 1, Scan = 1, Gate = 1;

[0105] like Figure 13 The diagram shows one possible operation of the pixel circuit during the light-emitting stage t5. During this stage, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on under the control of a low-level light-emitting control signal provided by the light-emitting control terminal EM, causing the light-emitting device 10 to emit light. Simultaneously, the first reset transistor T1 is turned off under the control of a high-level reset control signal provided by the reset control terminal R. The compensation transistor T2 is turned off under the control of a high-level first scan control signal provided by the first scan control terminal G. The data writing transistor T4 and the second reset transistor T7 are turned off under the control of a high-level second scan control signal provided by the second scan control terminal S.

[0106] It should be noted that, Figures 9 to 13 The direction indicated by the middle arrow is the direction of the current in the corresponding stage.

[0107] In this embodiment of the disclosure, for the hold frame, both the reset control signal received by the reset control terminal and the first scan signal received by the first scan control terminal can be kept at invalid potentials. Under the control of the second scan control terminal, a constant reset signal is written to the first terminal of the driving transistor through the data signal terminal. Figure 3 Taking the pixel circuit shown as an example, we will still combine it with Figure 8 As shown, for the hold frame, the reset control signal provided by the reset control terminal R remains high, and the first scan control signal provided by the first scan control terminal G remains high. Accordingly, node N1 is not reset or written to. In this way, under the control of the second scan signal provided by the second scan control terminal S, a constant reset signal is written to the first terminal of the driving transistor T3 through the data signal terminal D, ensuring that the potential of node N3 is the same in both the write frame and the hold frame under the same grayscale image, thus avoiding the problem of frequency switching flicker.

[0108] In one exemplary embodiment, for Figure 3 The pixel circuit shown, when the reset control terminal R and the second scan control terminal S are respectively coupled to different output terminals of the same second gate driving unit, can write frames using... Figure 14 The timing diagram shown. Still combined with... Figure 14 As shown, the write frame includes stages a, b, c, d, and e, set sequentially. In stage a, node N1 is reset. In stage b, node N1 is reset to a low level. A higher constant reset signal applied through data signal terminal D resets nodes N2 and N3 to a high level, resulting in a higher gate-source voltage for driving transistor T3, thus improving the hysteresis phenomenon of driving transistor T3. In stage c, the data signal actually needed for the light-emitting stage is written to the gate of driving transistor T3 through data signal terminal D. In stage d, node N3 is reset again to ensure that the potential of node N3 in the write frame and the hold frame is the same, thus improving low-grayscale flicker. At time e, the light-emitting device 10 emits light. Furthermore, the specific working process of the pixel circuit in stages a to e is as described above. Figure 4 The general principles are the same, and will not be described in detail here. Furthermore, in this exemplary embodiment, the holding frame can still be used... Figure 8 The timing diagram shown illustrates the specific working process of the pixel circuit as described above. Figure 8 They are largely the same, so I will not go into details here.

[0109] It should be noted that, in one exemplary embodiment, the write frame of the pixel circuit provided in this disclosure may also include an initialization stage t1, a first reset stage t2, a data write stage t3, and a light emission stage t5 in sequence. In this case, the working process of the pixel circuit in each stage can be referred to the description of the relevant parts above, and will not be described in detail here.

[0110] In one exemplary embodiment, the write frame of the pixel circuit provided in this disclosure may also include an initialization stage t1, a data writing stage t3, a second reset stage t4, and a light emission stage t5 in sequence. In this case, the working process of the pixel circuit in each stage can be referred to the description of the relevant parts above, and will not be described in detail here.

[0111] Based on the same publicly disclosed concept, such as Figure 15 As shown, this disclosure also provides a display device, which includes: a plurality of pixel circuits 100 as described above disposed in a display area A, and a gate driving circuit 200 disposed in a non-display area B. The gate driving circuit 200 is used to provide corresponding signals to the reset control terminal R, the first scan control terminal G, and the second scan control terminal S of the pixel circuits 100.

[0112] In practical implementation, one possible distribution diagram of display area A and non-display area B can be as follows: Figure 15 As shown, the display area A and the non-display area B can also be divided according to the actual application needs, which will not be described in detail here.

[0113] In one exemplary embodiment, such as Figure 16 As shown, the gate driving circuit 200 includes a first gate driving unit 201 and a second gate driving unit 202. The first gate driving unit 201 is coupled to the first scan control terminal G of each pixel circuit 100, and the second gate driving unit 202 is coupled to the second scan control terminal S of each pixel circuit 100.

[0114] Still combined Figure 16 As shown, the first gate driving unit 201 is configured to provide a first scan control signal at a first frequency to the first scan control terminal G; the second gate driving unit 202 is configured to provide a second scan control signal at a second frequency to the second scan control terminal S; wherein the second frequency is greater than the first frequency, and the effective duration of the second scan control signal is greater than the effective duration of the first scan control signal. In this way, the signal provided by the data signal terminal D can be fully written to the second terminal of the driving transistor T3 by using a second scan control signal with a relatively large effective duration and frequency, thereby ensuring the driving capability of the pixel circuit.

[0115] In one exemplary embodiment, such as Figure 17 As shown, the gate driving circuit 200 further includes a reset driving unit 203, which is coupled to the reset control terminal R of each pixel circuit 100.

[0116] In one exemplary embodiment, such as Figure 18As shown, the first gate driving unit 201 is coupled to the reset control terminal R of each pixel circuit 100, and the reset control terminal R and the first scan control terminal G of the same pixel circuit 100 are respectively coupled to different output terminals of the first gate driving unit 201.

[0117] In one exemplary embodiment, such as Figure 19 As shown, the second gate driving unit 202 is coupled to the reset control terminal R of each pixel circuit 100, and the reset control terminal R and the second scan control terminal S of the same pixel circuit 100 are respectively coupled to different output terminals of the second gate driving unit 202.

[0118] Since the principle by which this display device solves the problem is similar to that of the aforementioned pixel circuit 100, the implementation of this display device can refer to the implementation of the aforementioned pixel circuit 100 section, and the repeated parts will not be described again.

[0119] In specific implementations, the display device provided in this disclosure can be a small-sized AMOLED, which allows for a relatively long data writing time per line. A large, constant reset signal provided by the data signal terminal D can be used to reset the first electrode of the driving transistor. Correspondingly, the display device can be any product or component with a display function, such as a watch, bracelet, or mobile phone. Other essential components of this display device are understood by those skilled in the art and are not described in detail here, nor should they be construed as limiting this disclosure.

[0120] Based on the same disclosed concept, this disclosure also provides a driving method for the aforementioned pixel circuit, including:

[0121] S101: Based on the current refresh frequency of the display device and the reference refresh frequency, the current display frame of the display device is divided into one write frame and N hold frames, where N is an integer greater than 1; wherein, the write frame includes a first reset phase and / or a second reset phase;

[0122] S102: In the first reset phase, the data writing transistor and the driving transistor are turned on, and the constant reset signal is written to the second and first terminals of the driving transistor through the data signal terminal;

[0123] S103: In the second reset phase, the data writing transistor is turned on, and the constant reset signal is written to the second terminal of the driving transistor through the data signal terminal.

[0124] In one exemplary embodiment, it may be in accordance with Figure 20The steps S101 to S103 are executed sequentially. In one exemplary embodiment, step S102 may be executed only after step S101. In another exemplary embodiment, step S103 may be executed only after step S101. Of course, the execution steps of the write frame can be set according to the actual application needs. The specific implementation process of the corresponding execution steps of the write frame can be referred to the aforementioned method. Figure 3 The pixel circuit shown and Figure 4 The descriptions of the corresponding parts of the timing diagram shown are not repeated here.

[0125] In the embodiments disclosed herein, such as Figure 21 As shown, for the held frame, the method further includes:

[0126] S201: Keep both the reset control signal received by the reset control terminal and the first scan signal received by the first scan control terminal at an invalid potential;

[0127] S202: Under the control of the second scan control terminal, the constant reset signal is written into the first pole of the driving transistor through the data signal terminal.

[0128] In one exemplary embodiment, the specific implementation process of steps S201 to S202 can be referred to the aforementioned method. Figure 3 The pixel circuit shown and Figure 4 The descriptions of the corresponding parts of the timing diagram shown are not repeated here.

[0129] In this embodiment of the disclosure, the write frame includes an initialization phase, a first reset phase, a data write phase, a second reset phase, and a light emission phase, which are sequentially configured. The method further includes:

[0130] S301: During the initialization phase, the first reset transistor and the driving transistor are turned on, and the initialization signal is written to the gate of the driving transistor through the initialization signal terminal;

[0131] S302: During the data writing stage, the compensation transistor and the data writing transistor are turned on, the data signal is written to the second terminal of the driving transistor through the data signal terminal, and the threshold voltage of the driving transistor and the data signal are written to the gate of the driving transistor through the compensation transistor and stored in the storage capacitor.

[0132] S303: During the light-emitting stage, the first light-emitting control transistor and the second light-emitting control transistor are turned on, and the light-emitting device emits light.

[0133] In one exemplary embodiment, combined with Figure 22 As shown, the specific implementation process of steps S301, S102, S303, S103, and S303 can be referred to the aforementioned method. Figure 3 The pixel circuit shown and Figure 4 The descriptions of the corresponding parts of the timing diagram shown are not repeated here.

[0134] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0135] Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include such modifications and variations.

Claims

1. A pixel circuit, wherein, include: The system comprises a first reset transistor, a compensation transistor, a driving transistor, a data writing transistor, a first light-emitting control transistor, a second light-emitting control transistor, a second reset transistor, a storage capacitor, and a light-emitting device; wherein: The first reset transistor is coupled between the gate of the driving transistor and the initialization signal terminal, and the gate is coupled to the reset control terminal; The compensation transistor is coupled between the gate and the first electrode of the driving transistor, and the gate is coupled to the first scan control terminal. The data writing transistor is coupled between the second terminal of the driving transistor and the data signal terminal, and its gate is coupled to the second scan control terminal. The first light-emitting control transistor is coupled between the second terminal of the driving transistor and the first power supply terminal, and its gate is coupled to the light-emitting control terminal; The second light-emitting control transistor is coupled between the first terminal of the driving transistor and the first terminal of the light-emitting device, and its gate is coupled to the light-emitting control terminal; The second reset transistor is coupled between the first electrode of the light-emitting device and the initialization signal terminal, and its gate is coupled to the second scan control terminal; The second electrode of the light-emitting device is coupled to the second power supply terminal; The storage capacitor is coupled between the first power supply terminal and the gate of the driving transistor; Wherein, the first scan control terminal is used to receive a first scan control signal, the second scan control terminal is used to receive a second scan control signal, the effective duration of the second scan control signal is longer than the effective duration of the first scan control signal, and the effective duration of the first scan control signal is covered by the effective duration of the second scan control signal. During the other effective durations of the second scan control signal excluding the covered portion, the data signal terminal is used to receive a constant reset signal, and during the duration of the covered portion, the data signal terminal is used to receive a data signal.

2. The pixel circuit of claim 1, wherein, The reset control terminal, the first scan control terminal, and the second scan control terminal are each coupled to different gate drive units.

3. The pixel circuit of claim 1, wherein, The reset control terminal is used to receive a reset control signal. The reset control signal and the first scan control signal are provided by different output terminals of the same first gate driving unit, and the reset control signal is earlier than the first scan control signal.

4. The pixel circuit of claim 1, wherein, The reset control terminal is used to receive a reset control signal. The reset control signal and the second scan control signal are provided by different output terminals of the same second gate driving unit, and the reset control signal is earlier than the second scan control signal.

5. The pixel circuit of any one of claims 1-4, wherein, The first reset transistor, the compensation transistor, the driving transistor, the data writing transistor, the first light-emitting control transistor, the second light-emitting control transistor, and the second reset transistor are all P-type transistors.

6. The pixel circuit of any one of claims 1-4, wherein, The driving transistor, the data writing transistor, the first light-emitting control transistor, the second light-emitting control transistor, and the second reset transistor are all P-type transistors, and the first reset transistor and / or the compensation transistor are N-type transistors.

7. The pixel circuit of claim 6, wherein, The active layers of the driving transistor, the data writing transistor, the first light-emitting control transistor, the second light-emitting control transistor, and the second reset transistor are made of low-temperature polycrystalline silicon, while the active layers of the first reset transistor and the compensation transistor are made of metal-oxide-semiconductor materials.

8. A display device, wherein, include: The display area includes a plurality of pixel circuits as described in any one of claims 1-7, and a gate driving circuit is provided in a non-display area, wherein the gate driving circuit is used to provide corresponding signals to the reset control terminal, the first scan control terminal and the second scan control terminal of the pixel circuits.

9. The display device of claim 8, wherein, The gate driving circuit includes a first gate driving unit and a second gate driving unit. The first gate driving unit is coupled to a first scan control terminal of each pixel circuit, and the second gate driving unit is coupled to a second scan control terminal of each pixel circuit.

10. The display device of claim 9, wherein, The first gate driving unit is configured to provide a first scan control signal at a first frequency to the first scan control terminal; the second gate driving unit is configured to provide a second scan control signal at a second frequency to the second scan control terminal; wherein the second frequency is greater than the first frequency, and the effective duration of the second scan control signal is greater than the effective duration of the first scan control signal.

11. The display device as claimed in claim 9, wherein, The gate driving circuit further includes a reset driving unit, which is coupled to the reset control terminal of each pixel circuit.

12. The display device as claimed in claim 11, wherein, The first gate driving unit is coupled to the reset control terminal of each pixel circuit, and the reset control terminal and the first scan control terminal of the same pixel circuit are respectively coupled to different output terminals of the first gate driving unit.

13. The display device as claimed in claim 11, wherein, The second gate driving unit is coupled to the reset control terminal of each pixel circuit, and the reset control terminal and the second scan control terminal of the same pixel circuit are respectively coupled to different stage output terminals of the second gate driving unit.

14. A driving method of a pixel circuit as claimed in any one of claims 1 to 7, wherein, include: Based on the current refresh rate of the display device and the reference refresh rate, the current display frame of the display device is divided into one write frame and N hold frames, where N is an integer greater than 1; wherein, the write frame includes a first reset phase and / or a second reset phase; During the first reset phase, the data writing transistor and the driving transistor are turned on, and the constant reset signal is written to the second and first terminals of the driving transistor through the data signal terminal. During the second reset phase, the data writing transistor is turned on, and the constant reset signal is written to the second terminal of the driving transistor through the data signal terminal.

15. The driving method of claim 14, wherein, For the held frame, the method further includes: The reset control signal received by the reset control terminal and the first scan signal received by the first scan control terminal are both kept at invalid potentials. Under the control of the second scan control terminal, the constant reset signal is written into the first terminal of the driving transistor through the data signal terminal.

16. The driving method of claim 15, wherein, The write frame includes an initialization phase, a first reset phase, a data write phase, a second reset phase, and a light emission phase, which are sequentially configured. The method further includes: During the initialization phase, the first reset transistor and the driving transistor are turned on, and the initialization signal is written to the gate of the driving transistor through the initialization signal terminal. During the data writing phase, the compensation transistor and the data writing transistor are turned on, the data signal is written to the second terminal of the driving transistor through the data signal terminal, and the threshold voltage of the driving transistor and the data signal are written to the gate of the driving transistor through the compensation transistor and stored in the storage capacitor. During the light-emitting phase, the first light-emitting control transistor and the second light-emitting control transistor are turned on, and the light-emitting device emits light.

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