A low leakage delay type power-on reset circuit

Abstract

The present invention discloses a low leakage delay type power-on reset circuit, which relates to the technical field of reset circuits. When the system power supply voltage starts to rise, the first NMOS tube and the second NMOS tube output a reference voltage to control the gate of the first PMOS tube. When the system power supply voltage is insufficient to turn on the first PMOS tube, the first PMOS tube is turned off and does not charge the capacitor. The pull-down compensation circuit pulls the voltage of the capacitor down to a low level. As the system power supply voltage increases, the first PMOS tube is turned on and gradually charges the capacitor to a high level. The reset signal RSTN also changes from a low level to a high level, and the circuit enters a steady-state mode. After entering the steady state, the third PMOS tube and the sixth PMOS tube are turned off, cutting off the leakage path of the power-on detection circuit and the pull-down compensation circuit, thereby greatly reducing leakage. The present application solves the problem of excessive static power consumption of the current power-on reset circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of reset circuits, and in particular to a low leakage delay type power-on reset circuit. Background Art

[0002] With the development of integrated circuits, power consumption has gradually become a key issue that limits the application of integrated circuits. As a necessary module in the integrated circuit system, the power consumption of the power-on reset circuit directly affects the power consumption of the digital system. Since the power-on reset circuit is a normally open unit in the system, it is impossible to reduce its power consumption in steady state through low-power means such as power gating. Therefore, it is very important to develop a low-leakage power-on reset circuit. Summary of the invention

[0003] The purpose of the present invention is to provide a low leakage delay type power-on reset circuit, aiming to solve the problem of excessively high static power consumption of the current power-on reset circuit.

[0004] In order to solve the above technical problems, the present invention adopts the following technical solutions:

[0005] An aspect of an embodiment of the present invention provides a low leakage delay type power-on reset circuit, the reset circuit comprising: a power-on detection circuit, the input end of the power-on detection circuit is connected to a detection system power supply, when the system power supply changes from a low level to a high level, the output end of the power-on detection circuit outputs a high level signal, when the system power supply changes from a high level to a low level, the output end of the power-on detection circuit stops outputting a high level signal; a power-off detection circuit, the input end of the power-off detection circuit is connected to a detection system power supply, when the system power supply changes from a low level to a high level, the output end of the power-off detection circuit outputs a high level signal, when the system power supply changes from a high level to a low level, the output end of the power-off detection circuit outputs a low level signal; an AND gate, the first input end of the AND gate is connected to the output end of the power-on detection circuit, the second input end of the AND gate is connected to the output end of the power-off detection circuit, when the system power supply changes from a low level to a high level, the output end of the AND gate outputs a high level stop reset signal, when the system power supply changes from a high level to a low level, the output end of the AND gate outputs a low level reset signal.

[0006] In some embodiments, the power-on detection circuit includes a first NMOS tube, a second NMOS tube, a first PMOS tube and a capacitor, the drain of the first NMOS tube is connected to a system power supply, the gate of the first NMOS tube is grounded, the source of the first NMOS tube is connected to the drain of the second NMOS tube, the gate of the second NMOS tube and the gate of the first PMOS tube, the source of the second NMOS tube is grounded, the source of the first PMOS tube is connected to the system power supply, the drain of the first PMOS tube is connected to one end of the capacitor and the first input end of the AND gate, and the other end of the capacitor is grounded.

[0007] In some embodiments, the power-on detection circuit further includes a second PMOS tube, a source of the second PMOS tube is connected to a system power supply, and a gate of the second PMOS tube is connected to a drain of the second PMOS tube and a source of the first PMOS tube.

[0008] In some embodiments, the power-on detection circuit also includes a third PMOS tube, the source of the third PMOS tube is connected to the system power supply, the drain of the third PMOS tube is connected to the drain of the first NMOS tube, and the gate of the third PMOS tube is used to receive the reset signal.

[0009] In some embodiments, the power-off detection circuit includes a first inverter and a second inverter, the input end of the first inverter is used to receive system power, the output end of the first inverter is connected to the input end of the second inverter, and the output end of the second inverter is connected to the second input end of the AND gate.

[0010] In some embodiments, the first inverter includes a third NMOS tube and a fourth PMOS tube, the source of the fourth PMOS tube is connected to the first input terminal of the AND gate, the gate of the fourth PMOS tube is connected to the gate of the third NMOS tube and the system power supply, the drain of the fourth PMOS tube is connected to the drain of the third NMOS tube, and the source of the third NMOS tube is grounded; the second inverter includes a fourth NMOS tube and a fifth PMOS tube, the source of the fifth PMOS tube is connected to the system power supply, and the gate of the fifth PMOS tube is connected to the gate of the fourth NMOS tube, the drain of the fourth PMOS tube and the drain of the third NMOS tube.

[0011] In some embodiments, the reset circuit also includes a pull-down compensation circuit, which is respectively connected to the first input terminal of the AND gate, a system power supply and a location. When the system power supply changes from a low level to a high level, the pull-down circuit is turned off. When the system power supply changes from a high level to a low level, the pull-down circuit pulls down the potential of the first input terminal of the AND gate.

[0012] In some embodiments, the pull-down compensation circuit includes a sixth PMOS tube, a unidirectional conduction element and a current mirror circuit, the source of the sixth PMOS tube is connected to the system power supply, the gate of the sixth PMOS tube is used to receive the reset signal, the drain of the sixth PMOS tube is connected to the input end of the unidirectional conduction element, the output end of the unidirectional conduction element is connected to the first input end of the current mirror circuit and the control end of the current mirror circuit, the second input end of the current mirror circuit is connected to the first input end of the AND gate, and both output ends of the current mirror circuit are grounded.

[0013] In some embodiments, the unidirectional conducting element includes a seventh PMOS tube, an eighth PMOS tube and a ninth PMOS tube, the source of the seventh PMOS tube is connected to the drain of the sixth PMOS tube, the gate of the seventh PMOS tube is connected to the drain of the seventh PMOS tube and the source of the eighth PMOS tube, the gate of the eighth PMOS tube is connected to the drain of the eighth PMOS tube and the source of the ninth PMOS tube, and the gate of the ninth PMOS tube is connected to the drain of the ninth PMOS tube, the first input end of the current mirror circuit and the control end of the current mirror circuit.

[0014] In some embodiments, the current mirror circuit includes a fifth NMOS tube and a sixth NMOS tube, the source of the fifth NMOS tube and the source of the sixth NMOS tube are both grounded, the drain of the fifth NMOS tube is connected to the first input terminal of the AND gate, and the gate of the fifth NMOS tube is connected to the gate of the sixth NMOS tube, the drain of the sixth NMOS tube, the gate of the ninth PMOS tube and the drain of the ninth PMOS tube.

[0015] A low leakage delay type power-on reset circuit according to an embodiment of the present invention has at least the following beneficial effects: Traditional power-on reset circuits require high static power consumption, making them difficult to be applied to edge application scenarios with high requirements for low power consumption. In response to the above problems, the low leakage delay type power-on reset circuit of the present application adopts a delay type structure, which cuts off all leakage paths in the circuit in steady state, thereby greatly optimizing the static power consumption of the circuit.

[0016] It is to be understood that the foregoing general description and the following detailed description are exemplary only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 FIG. 4 is a schematic diagram of a low leakage delay type power-on reset circuit according to an embodiment. DETAILED DESCRIPTION

[0019] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0020] The terms "first", "second", and "third" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", and "third" may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0021] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "connected", "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal connection of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0022] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these example embodiments are provided so that the description of the present disclosure will be more comprehensive and complete and the concepts of the example embodiments will be fully conveyed to those skilled in the art. The accompanying drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and thus their repeated description will be omitted.

[0023] The technical solution of the embodiment of the present application is briefly described below:

[0024] According to some embodiments, Figure 1 As shown, the present application provides a low leakage delay type power-on reset circuit, the reset circuit comprising:

[0025] A power-on detection circuit, wherein the input end of the power-on detection circuit is connected to the detection system power supply VDD, and when the system power supply VDD changes from a low level to a high level, the output end of the power-on detection circuit outputs a high level signal, and when the system power supply VDD changes from a high level to a low level, the output end of the power-on detection circuit stops outputting the high level signal;

[0026] A power-off detection circuit, wherein the input end of the power-off detection circuit is connected to the detection system power supply VDD, and when the system power supply VDD changes from a low level to a high level, the output end of the power-off detection circuit outputs a high level signal, and when the system power supply VDD changes from a high level to a low level, the output end of the power-off detection circuit outputs a low level signal;

[0027] An AND gate AND, wherein a first input end of the AND gate AND is connected to an output end of the power-on detection circuit, a second input end of the AND gate AND is connected to an output end of the power-off detection circuit, when a system power supply VDD changes from a low level to a high level, the output end of the AND gate AND outputs a high-level stop reset signal RSTN, and when the system power supply VDD changes from a high level to a low level, the output end of the AND gate AND outputs a low-level reset signal RSTN.

[0028] The following is combined with the appendix of this manual Figure 1 , the preferred implementation modes of the present disclosure are further elaborated in detail.

[0029] According to some embodiments, Figure 1 As shown, the power-on detection circuit includes a first NMOS tube NM1, a second NMOS tube NM2, a first PMOS tube PM1 and a capacitor C, the drain of the first NMOS tube NM1 is connected to the system power supply VDD, the gate of the first NMOS tube NM1 is grounded VSS, the source of the first NMOS tube NM1 is connected to the drain of the second NMOS tube NM2, the gate of the second NMOS tube NM2 and the gate of the first PMOS tube PM1, the source of the second NMOS tube NM2 is grounded VSS, the source of the first PMOS tube PM1 is connected to the system power supply VDD, the drain of the first PMOS tube PM1 is connected to one end of the capacitor C and the first input end of the AND gate AND, and the other end of the capacitor C is grounded VSS.

[0030] Based on the working principle of the above embodiment, when the system power supply VDD gradually increases from a low level until the source of the first NMOS tube NM1 outputs a stable reference voltage, the second NMOS tube NM2 is similar to a unidirectional conducting diode for current limiting. When the source voltage of the first NMOS tube NM1 gradually increases to the reference voltage, the first PMOS tube PM1 is turned on, and the capacitor C is gradually charged to a high level, and the first input end of the AND gate AND receives a high level. At the same time, when the system power supply VDD changes from a low level to a high level, the output end of the power-off detection circuit outputs a high level signal. The second input end of the AND gate AND also receives a high level, and the AND gate AND outputs a high level stop reset signal RSTN, and the circuit enters a steady-state mode. When the system power supply VDD changes from a high level to a low level, the source voltage of the first NMOS tube NM1 is lower than the turn-on voltage of the first PMOS tube PM1, the first PMOS tube PM1 is turned off, and the capacitor C is not charged. At the same time, when the system power supply VDD changes from a high level to a low level, the output end of the power-off detection circuit outputs a low level signal, and the AND gate AND outputs a low level reset signal RSTN.

[0031] According to some embodiments, Figure 1 As shown, the power-on detection circuit further includes a second PMOS tube PM2, a source of the second PMOS tube PM2 is connected to a system power supply VDD, and a gate of the second PMOS tube PM2 is connected to a drain of the second PMOS tube PM2 and a source of the first PMOS tube PM1.

[0032] Based on the working principle of the above embodiment, the second PMOS tube PM2 mainly plays the role of preventing current backflow. When the voltage of the system power supply VDD drops, the path from the capacitor C to the system power supply VDD is cut off, so as to prevent the capacitor C from charging the system power supply VDD through the first PMOS tube PM1, causing the voltage on the capacitor C to drop as the voltage of the system power supply VDD drops, thereby causing the power-off detection circuit to fail.

[0033] According to some embodiments, Figure 1 As shown, the power-on detection circuit also includes a third PMOS tube PM3, the source of the third PMOS tube PM3 is connected to the system power supply VDD, the drain of the third PMOS tube PM3 is connected to the drain of the first NMOS tube NM1, and the gate of the third PMOS tube PM3 is used to receive the reset signal RSTN.

[0034] Based on the working principle of the above embodiment, since the reset signal RSTN is also at a low level when the system power VDD is at a low level, when the system power VDD gradually increases from a low level to a high level in the initial stage, the third PMOS tube PM3 is in a conducting state until the source of the first NMOS tube NM1 outputs a stable reference voltage, the first PMOS tube PM1 is turned on, and the capacitor C is gradually charged to a high level, and the first input end of the AND gate AND receives a high level. At the same time, when the system power VDD changes from a low level to a high level, the output end of the power-off detection circuit outputs a high level signal. The second input end of the AND gate AND also receives a high level, and the AND gate AND outputs a high level stop reset signal RSTN, and the circuit enters a steady-state mode. After entering the steady state, the third PMOS tube PM3 is turned off, cutting off the leakage path of the power-on detection circuit, thereby greatly reducing leakage.

[0035] According to some embodiments, Figure 1 As shown, the power-off detection circuit includes a first inverter and a second inverter, the input end of the first inverter is used to receive the system power supply VDD, the output end of the first inverter is connected to the input end of the second inverter, and the output end of the second inverter is connected to the second input end of the AND gate AND.

[0036] According to some embodiments, Figure 1 As shown, the first inverter includes a third NMOS tube NM3 and a fourth PMOS tube PM4, the source of the fourth PMOS tube PM4 is connected to the first input terminal of the AND gate AND, the gate of the fourth PMOS tube PM4 is connected to the gate of the third NMOS tube NM3 and the system power supply VDD, the drain of the fourth PMOS tube PM4 is connected to the drain of the third NMOS tube NM3, and the source of the third NMOS tube NM3 is grounded VSS;

[0037] The second inverter includes a fourth NMOS transistor NM4 and a fifth PMOS transistor PM5, a source of the fifth PMOS transistor PM5 is connected to a system power supply VDD, and a gate of the fifth PMOS transistor PM5 is connected to a gate of the fourth NMOS transistor NM4, a drain of the fourth PMOS transistor PM4 and a drain of the third NMOS transistor NM3.

[0038] According to some embodiments, Figure 1 As shown, the reset circuit also includes a pull-down compensation circuit, which is respectively connected to the first input terminal of the AND gate AND, the system power supply VDD and the ground VSS. When the system power supply VDD changes from a low level to a high level, the pull-down circuit is turned off. When the system power supply VDD changes from a high level to a low level, the pull-down circuit pulls down the potential of the first input terminal of the AND gate AND.

[0039] According to some embodiments, Figure 1 As shown, the pull-down compensation circuit includes a sixth PMOS tube PM6, a unidirectional conduction element and a current mirror circuit, the source of the sixth PMOS tube PM6 is connected to the system power supply VDD, the gate of the sixth PMOS tube PM6 is used to receive the reset signal RSTN, the drain of the sixth PMOS tube PM6 is connected to the input end of the unidirectional conduction element, the output end of the unidirectional conduction element is connected to the first input end of the current mirror circuit and the control end of the current mirror circuit, the second input end of the current mirror circuit is connected to the first input end of the AND gate AND, and both output ends of the current mirror circuit are grounded VSS.

[0040] According to some embodiments, Figure 1 As shown, the unidirectional conducting element includes a seventh PMOS tube PM7, an eighth PMOS tube PM8 and a ninth PMOS tube PM9, the source of the seventh PMOS tube PM7 is connected to the drain of the sixth PMOS tube PM6, the gate of the seventh PMOS tube PM7 is connected to the drain of the seventh PMOS tube PM7 and the source of the eighth PMOS tube PM8, the gate of the eighth PMOS tube PM8 is connected to the drain of the eighth PMOS tube PM8 and the source of the ninth PMOS tube PM9, and the gate of the ninth PMOS tube PM9 is connected to the drain of the ninth PMOS tube PM9, the first input end of the current mirror circuit and the control end of the current mirror circuit.

[0041] According to some embodiments, Figure 1 As shown, the current mirror circuit includes a fifth NMOS tube NM5 and a sixth NMOS tube NM6, the source of the fifth NMOS tube NM5 and the source of the sixth NMOS tube NM6 are both grounded to VSS, the drain of the fifth NMOS tube NM5 is connected to the first input end of the AND gate AND, and the gate of the fifth NMOS tube NM5 is connected to the gate of the sixth NMOS tube NM6, the drain of the sixth NMOS tube NM6, the gate of the ninth PMOS tube PM9 and the drain of the ninth PMOS tube PM9.

[0042] The working principle of the present application is that when the voltage of the system power supply VDD starts to rise, the first NMOS tube NM1 and the second NMOS tube NM2 generate a reference voltage to control the gate of the first PMOS tube PM1. When the voltage of the system power supply VDD is not enough to turn on the first PMOS tube PM1, the first PMOS tube PM1 is turned off and does not charge the capacitor C. At this time, the voltage of the capacitor C is pulled down to a low level by the pull-down compensation circuit. In the pull-down compensation circuit, the seventh PMOS tube PM7, the eighth PMOS tube PM8 and the ninth PMOS tube PM9 are diode-connected to limit the current of the fifth NMOS tube NM5 and the sixth NMOS tube NM6, so as to avoid the voltage of the capacitor C being unable to be charged to a high level due to excessive pull-down current. As the voltage of the system power supply VDD increases, the first PMOS tube PM1 is turned on, and the capacitor C is gradually charged to a high level, and the reset signal RSTN also changes from a low level to a high level, and the circuit enters a steady-state mode. After entering the steady state, the third PMOS tube PM3 and the sixth PMOS tube PM6 are turned off, cutting off the leakage path of the power-on detection circuit and the pull-down compensation circuit, thereby greatly reducing leakage. The gate of the first PMOS tube PM1 receives the level through the second NMOS tube NM2, and the system power VDD continues to charge the capacitor C through the second PMOS tube PM2 and the first PMOS tube PM1, so that the first input end of the AND gate AND maintains a high level. When the voltage of the system power VDD begins to drop, the power-off detection circuit starts to work. The power-off detection circuit is composed of two-stage inverters. The power supply of the first inverter is connected to the capacitor C, and the gate is connected to the system power VDD. When the voltage of the system power VDD drops below half of the voltage of the capacitor C, the first inverter of the power-off detection circuit flips, and the gate of the second inverter of the power-off detection circuit is connected to the output of the first inverter, and the power supply is connected to the system power VDD. When the first inverter flips, the second inverter will also flip accordingly, thereby causing the reset signal RSTN to flip to a low level.

[0043] Traditional power-on reset circuits require high static power consumption, making them difficult to apply to edge applications that have high requirements for low power consumption. The low leakage delay type power-on reset circuit of the present application adopts a delay type structure, which cuts off all leakage paths in the circuit in steady state, thus greatly optimizing the static power consumption of the circuit.

[0044] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0045] Although the present disclosure has been described with reference to several typical embodiments, it should be understood that the terms used are illustrative and exemplary, rather than restrictive. Since the present disclosure can be implemented in a variety of forms without departing from the spirit or essence of the present application, it should be understood that the above-mentioned embodiments are not limited to any of the foregoing details, but should be widely interpreted within the spirit and scope defined by the appended claims, so all changes and modifications falling within the scope of the claims or their equivalents should be covered by the appended claims.

Claims

1. A low leakage delay type power-on reset circuit, characterized in that: The reset circuit comprises: A power-on detection circuit, wherein the input end of the power-on detection circuit is connected to the detection system power supply, and when the system power supply changes from a low level to a high level, the output end of the power-on detection circuit outputs a high level signal, and when the system power supply changes from a high level to a low level, the output end of the power-on detection circuit stops outputting the high level signal; A power-off detection circuit, wherein the input end of the power-off detection circuit is connected to the detection system power supply, and when the system power supply changes from a low level to a high level, the output end of the power-off detection circuit outputs a high level signal, and when the system power supply changes from a high level to a low level, the output end of the power-off detection circuit outputs a low level signal; An AND gate, wherein a first input end of the AND gate is connected to an output end of the power-on detection circuit, a second input end of the AND gate is connected to an output end of the power-off detection circuit, and when a system power source changes from a low level to a high level, the output end of the AND gate outputs a high-level stop reset signal, and when a system power source changes from a high level to a low level, the output end of the AND gate outputs a low-level reset signal; The power-on detection circuit includes a first NMOS tube, a second NMOS tube, a first PMOS tube, a third PMOS tube and a capacitor, the drain of the first NMOS tube is connected to a system power supply, the gate of the first NMOS tube is grounded, the source of the first NMOS tube is connected to the drain of the second NMOS tube, the gate of the second NMOS tube and the gate of the first PMOS tube, the source of the second NMOS tube is grounded, the source of the first PMOS tube is connected to the system power supply, the drain of the first PMOS tube is connected to one end of the capacitor and the first input end of the AND gate, the other end of the capacitor is grounded, the source of the third PMOS tube is connected to the system power supply, the drain of the third PMOS tube is connected to the drain of the first NMOS tube, and the gate of the third PMOS tube is used to receive the reset signal; A pull-down compensation circuit, wherein the pull-down compensation circuit is connected to the first input terminal of the AND gate, a system power supply, and a ground respectively, and when the system power supply changes from a low level to a high level, the pull-down circuit is turned off, and when the system power supply changes from a high level to a low level, the pull-down circuit pulls down the potential of the first input terminal of the AND gate; The pull-down compensation circuit includes a sixth PMOS tube, a unidirectional conductive element and a current mirror circuit, the source of the sixth PMOS tube is connected to the system power supply, the gate of the sixth PMOS tube is used to receive the reset signal, and the drain of the sixth PMOS tube is connected to the input end of the unidirectional conductive element.

2. The reset circuit according to claim 1, characterized in that: The power-on detection circuit further includes a second PMOS tube, a source of the second PMOS tube is connected to a system power supply, and a gate of the second PMOS tube is connected to a drain of the second PMOS tube and a source of the first PMOS tube.

3. The reset circuit according to claim 1, characterized in that: The power-off detection circuit includes a first inverter and a second inverter, the input end of the first inverter is used to receive system power, the output end of the first inverter is connected to the input end of the second inverter, and the output end of the second inverter is connected to the second input end of the AND gate.

4. The reset circuit according to claim 3, characterized in that: The first inverter comprises a third NMOS tube and a fourth PMOS tube, the source of the fourth PMOS tube is connected to the first input terminal of the AND gate, the gate of the fourth PMOS tube is connected to the gate of the third NMOS tube and the system power supply, the drain of the fourth PMOS tube is connected to the drain of the third NMOS tube, and the source of the third NMOS tube is grounded; The second inverter includes a fourth NMOS tube and a fifth PMOS tube, the source of the fifth PMOS tube is connected to the system power supply, and the gate of the fifth PMOS tube is connected to the gate of the fourth NMOS tube, the drain of the fourth PMOS tube and the drain of the third NMOS tube.

5. The reset circuit according to claim 1, characterized in that: The output end of the unidirectional conducting element is connected to the first input end of the current mirror circuit and the control end of the current mirror circuit, the second input end of the current mirror circuit is connected to the first input end of the AND gate, and both output ends of the current mirror circuit are grounded.

6. The reset circuit according to claim 1, characterized in that: The unidirectional conducting element includes a seventh PMOS tube, an eighth PMOS tube and a ninth PMOS tube, the source of the seventh PMOS tube is connected to the drain of the sixth PMOS tube, the gate of the seventh PMOS tube is connected to the drain of the seventh PMOS tube and the source of the eighth PMOS tube, the gate of the eighth PMOS tube is connected to the drain of the eighth PMOS tube and the source of the ninth PMOS tube, and the gate of the ninth PMOS tube is connected to the drain of the ninth PMOS tube, the first input end of the current mirror circuit and the control end of the current mirror circuit.

7. The reset circuit according to claim 6, characterized in that: The current mirror circuit includes a fifth NMOS tube and a sixth NMOS tube, the source of the fifth NMOS tube and the source of the sixth NMOS tube are both grounded, the drain of the fifth NMOS tube is connected to the first input end of the AND gate, and the gate of the fifth NMOS tube is connected to the gate of the sixth NMOS tube, the drain of the sixth NMOS tube, the gate of the ninth PMOS tube and the drain of the ninth PMOS tube.

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