A sliding ping-pong signal processing system for increasing radar data rate

Abstract

The application provides a sliding ping-pong signal processing system for improving radar data rate, which comprises: a high-speed AD sampling module for collecting target echo signals; a signal preprocessing FPGA module connected with the high-speed AD sampling module, including a digital down-conversion unit, a pulse compression unit and a coherent accumulation unit, for carrying out digital down-conversion, pulse compression and coherent accumulation processing on the collected target echo signals, generating subdivided pulse group accumulation data, carrying out FFT transformation on the subdivided pulse group accumulation data, and obtaining coherent accumulation results; a data cache module with an input end connected with the signal preprocessing FPGA module and an output end connected with a DSP data stream operation processing module; the data cache module includes a second SRAM storage unit and a third SRAM storage unit, which are respectively connected with the DSP data stream operation processing module, so as to realize sliding ping-pong processing of the coherent accumulation results. The application improves radar data rate and data processing real-time performance.

Description

Technical Field

[0001] This invention relates to the field of radar data processing technology, and more specifically, to a sliding ping-pong signal processing system for improving radar data rate. Background Technology

[0002] In modern radar signal processing, a large amount of radar echo data is needed to analyze and study various characteristics of target echo signals. This necessitates high-precision data acquisition of radar signals at intermediate frequencies (IFs). High-precision data acquisition requires high sampling rates and large data transmission volumes. Simultaneously, in radar signal preprocessing, data transfer between signal processing steps such as digital down-conversion, pulse compression, and coherent accumulation is quite frequent, and excessively long data waiting periods significantly reduce system processing speed. Therefore, high-speed real-time processing, transmission, and storage of data become critical issues that must be addressed in the construction of radar signal data acquisition systems.

[0003] In typical radar signal processing, the data between pulse compression and filtering processes is usually implemented using independent pulse compression and filtering modules coupled with external SRAM (Static Random-Access Memory), or using an FPGA (Field Programmable Gate Array) coupled with external SRAM. However, these methods suffer from problems in practical radar signal processing, such as excessively long data waiting periods, intra-frame operating mode switching, and coherent accumulation during frequency hopping. Existing technologies have not provided solutions to these issues. Summary of the Invention

[0004] The purpose of this invention is to provide a sliding ping-pong signal processing system for improving radar data rate and data processing speed. It reduces the waiting period for coherent accumulation data processing through hardware design, thereby improving radar data rate and real-time performance. At the same time, it uses an FPGA data processing module to replace part of the software work, reducing the computational burden on the system software.

[0005] To achieve the above objectives, the present invention provides a sliding ping-pong signal processing system for improving radar data rate, comprising: a high-speed AD sampling module for acquiring target echo signals; a signal preprocessing FPGA module connected to the high-speed AD sampling module, including a digital down-conversion unit, a pulse compression unit, and a coherent accumulation unit, for performing digital down-conversion, pulse compression, and coherent accumulation processing on the acquired target echo signals to generate subdivided pulse group accumulation data and perform FFT transformation to obtain coherent accumulation results; the coherent accumulation unit is connected to a first SRAM storage unit for reading the subdivided pulse group accumulation data to shorten the data waiting period of coherent accumulation; a data buffer module, whose input is connected to the signal preprocessing FPGA module and whose output is connected to a DSP data stream processing module, for reading and transmitting the coherent accumulation results; the data buffer module includes a second SRAM storage unit and a third SRAM storage unit, which are respectively connected to the DSP data stream processing module, and the second SRAM storage unit and the third SRAM storage unit are continuously switched to realize the sliding ping-pong processing of the coherent accumulation results.

[0006] Preferably, the digital down-conversion unit includes a first FIR filter and a correspondingly connected first dual-port RAM, used to digitally down-convert the acquired target echo signal, filter and extract the baseband signal through the first FIR filter to generate a baseband signal, and store the baseband signal in the first dual-port RAM.

[0007] Preferably, the pulse compression unit includes a second FIRT filter and a correspondingly connected second dual-port RAM; the pulse compression unit is connected to the digital down-conversion unit, and performs pulse compression processing on the baseband signal stored in the first dual-port RAM according to the radar operating mode to form K repetition frequency pulse data.

[0008] Preferably, the coherent accumulation unit includes an FFT processor and a third dual-port RAM; the coherent accumulation unit is connected to the pulse compression unit, and uses K repetition frequency pulse data in the second dual-port RAM as frame data for coherent accumulation.

[0009] Preferably, the third dual-port RAM subdivides the K repetition frequency pulse data into N subdivided pulse groups to accumulate data, and the accumulation number of each subdivided pulse group is K / N.

[0010] Preferably, the first SRAM storage unit is communicatively connected to the third dual-port RAM in the coherent accumulation unit, and is used to read the third dual-port RAM to complete the accumulation data of the subdivided pulse group.

[0011] Preferably, the coherent accumulation unit uses the number of accumulated data in the subdivided pulse group as the data processing cycle, reads the first SRAM storage unit frame by frame, and transmits the data located in the same distance gate of different pulses to the FFT processor for FFT transformation.

[0012] Optionally, if the radar operating mode is switched, two pulse signal data storage formats exist within the same frame of data. Zero-value interpolation is performed based on the pulse signal with the larger pulse width. Zero-value interpolation is performed from the end of the pulse range gate of the pulse signal with the smaller pulse width, so that the number of pulse range gates is unified in the two operating modes. FFT is performed on the data within the same pulse range gate in different pulse signal data.

[0013] Preferably, if random frequency hopping occurs within the same frame of data, causing discontinuity in the phase between signal pulses, the data at different carrier frequencies f1 and f2 within the frame are corrected; the pulse data collected at carrier frequencies f1 and f2 are retained respectively, the remaining pulse data are replaced with zero values, FFT is performed on the data within the same distance gate in the pulse signals at different carrier frequencies, and finally the weighted average of the two FFT results is stored.

[0014] Preferably, the data cache module includes an input data stream selection logic control unit and an output data stream selection logic control unit. The input data stream selection logic control unit is located at the input terminals of the second SRAM storage unit and the third SRAM storage unit, and the output data stream selection logic control unit is located at the output terminals of the second SRAM storage unit and the third SRAM storage unit. This allows the data cache module to switch between the second SRAM storage unit and the third SRAM storage unit in a rhythmic and coordinated manner, transmitting the coherent accumulation result to the DSP data stream processing module for processing.

[0015] In summary, compared with the prior art, the sliding ping-pong signal processing system for improving radar data rate provided by the present invention has the following beneficial effects:

[0016] (1) On the basis of improving the radar's ability to detect weak targets through long-term accumulation, the data waiting period of coherent accumulation can be shortened, thereby improving the radar data rate and the real-time performance of data processing.

[0017] (2) This invention takes into account the changes in radar operating parameters within the data frame and solves the problem of inconsistent pulse signal range gate format during coherent accumulation caused by different pulse widths;

[0018] (3) This invention considers random frequency hopping within the frame, which solves the problem of discontinuous phase between signal pulses caused by the hopping of pulse carrier frequency;

[0019] (4) By setting a second SRAM storage unit and a third SRAM storage unit in the data cache module, the present invention serves as two buffer SRAMs for alternating reading and writing, thereby saving the waiting time during data reading and writing and improving the data processing efficiency of the system.

[0020] (5) This invention replaces part of the work of software with hardware, reduces the burden of system software operation, and improves data processing speed and system performance. Attached Figure Description

[0021] Figure 1 This is a block diagram of the sliding ping-pong signal processing system for improving radar data rate according to the present invention;

[0022] Figure 2 This is a schematic diagram of the data storage format in the SRAM of the sliding ping-pong signal processing system for improving radar data rate according to the present invention.

[0023] Figure 3 This is a schematic diagram of data interpolation for the sliding ping-pong signal processing system for improving radar data rate according to the present invention;

[0024] Figure 4 This is a schematic diagram of data correction for the sliding ping-pong signal processing system for improving radar data rate according to the present invention. Detailed Implementation

[0025] The following will be combined with the appendix in the embodiments of the present invention. Figure 1 ~Attached Figure 4 The technical solutions, structural features, objectives and effects achieved in the embodiments of the present invention will be described in detail.

[0026] It should be noted that the accompanying drawings are in a very simplified form and use non-precise proportions. They are only used to facilitate and clarify the purpose of illustrating the embodiments of the present invention, and are not intended to limit the implementation conditions of the present invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportional relationship, or adjustments to the size should still fall within the scope of the technical content disclosed in the present invention, provided that they do not affect the effects and objectives that the present invention can produce.

[0027] It should be noted that, in this invention, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only the expressly listed elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus.

[0028] like Figure 1 As shown, Figure 1 The block diagram of the sliding ping-pong signal processing system for improving radar data rate provided by the present invention includes: a high-speed AD sampling module 1 for acquiring target echo signals; a signal preprocessing FPGA module 2 connected to the high-speed AD sampling module 1, which performs digital down-conversion, pulse compression, and coherent accumulation processing on the acquired target echo signals to generate subdivided pulse group accumulation data, and performs FFT transformation on the subdivided pulse group accumulation data to obtain coherent accumulation results; a data buffer module 3, whose input end is connected to the signal preprocessing FPGA module 2 and whose output end is connected to a DSP data stream processing module 4; the data buffer module 3 includes a second SRAM storage unit 31 and a third SRAM storage unit 32, which are respectively connected to the DSP (Digital Signal Processing) data stream processing module 4 to realize sliding ping-pong processing of the coherent accumulation results.

[0029] In this embodiment, the high-speed AD sampling module 1 includes four detection channels, through which four target echo signals are acquired. For example, Figure 1 As shown, the signal preprocessing FPGA module 2 includes a digital downconversion unit 21, a pulse compression unit 22, and a coherent accumulation unit 23. The digital downconversion unit 21 includes a first FIR filter 211 and a correspondingly connected first dual-port RAM (Random Access Memory) 212, which is used to digitally downconvert the acquired target echo signal, filter and extract the baseband signal through the first FIR filter 211 to generate the baseband signal, and store the baseband signal in the first dual-port RAM 212.

[0030] Furthermore, such as Figure 1 As shown, the pulse compression unit 22 includes a second FIRT filter 221 and a correspondingly connected second dual-port RAM 222. The pulse compression unit 22 is connected to the digital down-conversion unit 21 and performs pulse compression processing on the baseband signal stored in the first dual-port RAM 212 according to the radar operating mode. Specifically, in this embodiment, the second FIRT filter 221 reads the baseband signal and performs a k-point FFT on the baseband signal (k = 2048 in this embodiment). The FFT result is multiplied by the matching coefficients and then an IFFT is performed to obtain a 16-bit I-channel pulse compression result and a 16-bit Q-channel pulse compression result. Then, the 16-bit I-channel pulse compression result and the 16-bit Q-channel pulse compression result are concatenated to form 2048 repetition rate pulse data, which are stored in the second dual-port RAM 222 for subdivision and pulse group accumulation.

[0031] To obtain the range-Doppler two-dimensional distribution map of the target echo signal and improve the signal-to-noise ratio for moving target detection (MTD), it is necessary to rearrange the compressed repetition frequency pulse data and perform FFT transformation on the data within the same range gate in different pulses, i.e., to perform a coherent accumulation process. For example... Figure 1 As shown, in this embodiment, the coherent accumulation unit 23 includes an FFT processor 231 and a third dual-port RAM 232; the coherent accumulation unit 23 is connected to the pulse compression unit 22, and uses 2048 repetition pulse data in the second dual-port RAM 222 as frame data for coherent accumulation.

[0032] Furthermore, since the coherent accumulation waiting period = number of pulse accumulations × pulse compression signal processing period, and the data volume of the number of pulse accumulations is generally large, requiring large memory resources, the repetition frequency pulse data in a frame is subdivided into several subdivided pulse group accumulation data, and then coherent accumulation is performed.

[0033] Specifically, in this embodiment, to shorten the data waiting period for coherent accumulation and improve the radar data rate, the third dual-port RAM 232 subdivides the 2048 repetition pulse data into N groups (N=8 in this embodiment), meaning that the accumulated data in each subdivided pulse group is 256. The formula for calculating the accumulated storage data in each subdivided pulse group is: Data volume = Number of 4 detection channels × Number of accumulated pulse groups of 256 × Number of FFT and IFFT points of 2048 × 32 data bits. In this embodiment, the radar data processing frame period is shortened from the waiting time for 2048 repetition pulse data to the waiting time for 256 repetition pulse data, thus shortening the data waiting period for coherent accumulation and improving the radar data rate.

[0034] Furthermore, due to the large number of pulse accumulations, the signal preprocessing FPGA module 2 also includes a first SRAM storage unit 24. This first SRAM storage unit 24 is communicatively connected to the third dual-port RAM 232 in the coherent accumulation unit 23, and is used to read the accumulated data of the subdivided pulse group from the third dual-port RAM 232. In this embodiment, after the third dual-port RAM 232 has completed the accumulation of the subdivided pulse group, it generates a read signal. Using 2048 repetition frequency pulse data as the frame data size, the first SRAM storage unit 24 splices and stores the accumulated subdivided pulse group. Therefore, the formula for calculating the amount of data stored in the first SRAM storage unit 24 is: Data amount = Number of 4 detection channels × Number of 2048 pulse accumulations × Number of 2048 FFT and IFFT points × 32 data bits.

[0035] The data storage format of the first SRAM storage unit 24 is as follows: Figure 2As shown in (a), the coherent accumulation unit 23 uses the accumulation number of subdivided pulse group accumulated data as the data processing cycle, reads the first SRAM storage unit 24 frame by frame, and transmits the data located in the same distance gate of different pulses to the FFT processor 231 for FFT transformation. In this embodiment, using the accumulation time of 256 repetition pulses as the data processing cycle, the FFT processor 231 performs k-point FFT transformation on each column vector (i.e., the data located in the same distance gate of different pulses) of the frame-by-frame data stored in the first SRAM storage unit 24, and transmits the FFT transformation results according to... Figure 2 (b) Place it so that, Figure 2 Each row of data in (b) corresponds to the data within the sampling range -f r / 2 to f r Between / 2, the interval is f r The various frequencies of / k facilitate reading from the second SRAM memory cell 31 and the third SRAM memory cell 32, where f r This is the pulse repetition frequency.

[0036] Furthermore, because the AD data acquisition time and number of acquisition points of the high-speed AD sampling module 1 differ in different radar operating modes, this may lead to different pulse range gate numbers within a frame. Since FFT transformation can only be performed when the pulse range gates are the same, data interpolation is required for the data acquired in different operating modes. A schematic diagram of data interpolation is shown below when the radar operating mode is switched. Figure 3 As shown, when the radar operating mode switches from the first operating mode A to the second operating mode B within a frame, two pulse signal data storage formats exist within the same frame, and zero-value interpolation is performed based on the larger pulse width. In this embodiment, the pulse width in the second operating mode B is greater than the pulse width in the first operating mode A. Therefore, zero-value interpolation is performed on the pulse range gates in the first operating mode A from the end, so that the number of pulse range gates in the two operating modes is unified. Finally, FFT is performed on the data within the same pulse range gate located in different pulses.

[0037] Furthermore, if random frequency hopping occurs within a frame, the phase discontinuity between signal pulses due to the frequency jumps of the pulse carrier will render the traditional coherent accumulation method inapplicable. Therefore, data correction is needed for intra-frame frequency hopping, such as... Figure 4 As shown, data at different carrier frequencies f1 and f2 within a frame are corrected. Pulse data acquired at carrier frequencies f1 and f2 are retained respectively, and the remaining pulse data are replaced with zero values. FFT is performed on the data within the same distance gate of the pulse signals at different carrier frequencies. Finally, the weighted average of the two FFT results is stored to reduce the loss of signal-to-noise ratio.

[0038] Furthermore, the coherent accumulation result obtained by the coherent accumulation unit 23 is transmitted to the DSP data stream processing module 4 through the data cache module 3. To improve the data exchange speed, the data cache module 3 is equipped with two second SRAM storage units 31 and a third SRAM storage unit 32 to perform sliding ping-pong processing on the coherent accumulation result. Simultaneously, the data cache module 3 is equipped with an input data stream selection logic control unit 33 and an output data stream selection logic control unit 34. The input data stream selection logic control unit 33 is located at the input terminals of the second SRAM storage units 31 and the third SRAM storage units 32, and the output data stream selection logic control unit 34 is located at the output terminals of the second SRAM storage units 31 and the third SRAM storage units 32. This allows for the sequential and coordinated switching of the second SRAM storage units 31 and the third SRAM storage units 32, ensuring that the coherent accumulation result is continuously and without interruption sent to the DSP data stream processing module 4 for processing.

[0039] In summary, the sliding ping-pong signal processing system for improving radar data rate provided by the present invention shortens the data waiting period of coherent accumulation by subdividing the pulse accumulation number in coherent accumulation into small pulse groups through the setting of the first SRAM storage unit 24; at the same time, the accumulation time of the subdivided pulse groups is used as the radar data processing frame period, thereby improving the radar data rate and the real-time performance of data processing; furthermore, by setting the second SRAM storage unit 31 and the third SRAM storage unit 32 in the data cache module 3 as two buffer SRAMs for alternating reading and writing, the waiting time during data reading and writing is saved, thereby improving the data processing efficiency of the system.

[0040] Although the present invention has been described in detail through the preferred embodiments above, it should be understood that the above description should not be considered as a limitation of the present invention. Various modifications and substitutions to the present invention will be apparent to those skilled in the art after reading the above description. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. A sliding ping-pong signal processing system for improving radar data rate, characterized in that, include: A high-speed AD sampling module (1) is used to acquire the target echo signal; The signal preprocessing FPGA module (2), which is connected to the high-speed AD sampling module (1), includes a digital down-conversion unit (21), a pulse compression unit (22) and a coherent accumulation unit (23), which is used to perform digital down-conversion, pulse compression and coherent accumulation processing on the acquired target echo signal, generate subdivided pulse group accumulation data and perform FFT transformation to obtain coherent accumulation results; The coherent accumulation unit (23) is connected to a first SRAM storage unit (24) for reading the accumulated data of the subdivided pulse groups to shorten the data waiting period of coherent accumulation; the coherent accumulation unit (23) includes an FFT processor (231) and a third dual-port RAM (232); the third dual-port RAM (232) subdivides K repetition frequency pulse data into N subdivided pulse group accumulated data, and the accumulation number of each subdivided pulse group accumulated data is... ; The first SRAM storage unit (24) is communicatively connected to the third dual-port RAM (232) in the coherent accumulation unit (23) and is used to read the third dual-port RAM (232) to complete the accumulation data of the subdivided pulse group; The coherent accumulation unit (23) uses the number of accumulated data in the subdivided pulse group as the data processing cycle, reads the first SRAM storage unit (24) frame by frame, and transmits the data in the same distance gate in different pulses to the FFT processor (231) for FFT transformation; If the radar operating mode is switched, there are two pulse signal data storage formats in the same frame of data. Zero-value interpolation is performed based on the pulse signal with larger pulse width. Zero-value interpolation is performed on the pulse range gate of the pulse signal with smaller pulse width from the end, so that the number of pulse range gates is unified in the two operating modes. FFT is performed on the data in the same pulse range gate in different pulse signal data. If random frequency hopping occurs within the same frame of data, it causes phase discontinuity between signal pulses, affecting different carrier frequencies within the frame. , The following data was corrected; each was retained. and The pulse data acquired at the carrier frequency is replaced with zero values ​​for the remaining pulse data. The data within the same distance gate in the pulse signals located at different carrier frequencies are subjected to FFT. Finally, the weighted average of the FFT results of the two is stored. The data buffer module (3) has its input end connected to the signal preprocessing FPGA module (2) and its output end connected to the DSP data stream operation and processing module (4), which is used to read and transmit the coherent accumulation result; The data cache module (3) includes a second SRAM storage unit (31) and a third SRAM storage unit (32), which are respectively connected to the DSP data stream operation and processing module (4). The second SRAM storage unit (31) and the third SRAM storage unit (32) are switched continuously to realize the sliding ping-pong processing of the coherent accumulation result.

2. The sliding ping-pong signal processing system for improving radar data rate as described in claim 1, characterized in that, The digital downconversion unit (21) includes a first FIR filter (211) and a correspondingly connected first dual-port RAM (212), which is used to digitally downconvert the acquired target echo signal, filter and extract the baseband signal through the first FIR filter (211) to generate the baseband signal, and store the baseband signal in the first dual-port RAM (212).

3. The sliding ping-pong signal processing system for improving radar data rate as described in claim 2, characterized in that, The pulse compression unit (22) includes a second FIRT filter (221) and a correspondingly connected second dual-port RAM (222); the pulse compression unit (22) is connected to the digital down-conversion unit (21) and performs pulse compression processing on the baseband signal stored in the first dual-port RAM (212) according to the radar working mode to form K repetition frequency pulse data.

4. The sliding ping-pong signal processing system for improving radar data rate as described in claim 3, characterized in that, The coherent accumulation unit (23) is connected to the pulse compression unit (22) and uses K repetition frequency pulse data in the second dual-port RAM (222) as frame data for coherent accumulation.

5. The sliding ping-pong signal processing system for improving radar data rate as described in claim 1, characterized in that, The data cache module (3) is equipped with an input data stream selection logic control unit (33) and an output data stream selection logic control unit (34). The input data stream selection logic control unit (33) is located at the input terminals of the second SRAM storage unit (31) and the third SRAM storage unit (32), and the output data stream selection logic control unit (34) is located at the output terminals of the second SRAM storage unit (31) and the third SRAM storage unit (32). This enables the data cache module (3) to switch between the second SRAM storage unit (31) and the third SRAM storage unit (32) in a rhythmic and coordinated manner, and transmit the coherent accumulation result to the DSP data stream operation and processing module (4) for processing.

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