Pixel driving circuit and driving method thereof, display panel and display device
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BOE TECHNOLOGY GROUP CO LTD
- Filing Date
- 2022-07-22
- Publication Date
- 2026-07-24
Smart Images
Figure CN117769736B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of display technology, and in particular to a pixel driving circuit and its driving method, a display panel, and a display device. Background Technology
[0002] In related technologies, pixel driving circuits typically provide driving current to the light-emitting unit based on the voltage of the data signal; that is, the pixel driving circuit controls the grayscale of the sub-pixel unit through the voltage of the data signal. However, this pixel driving circuit architecture suffers from problems such as high power consumption and low grayscale adjustment accuracy.
[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention
[0004] According to one aspect of this disclosure, a pixel driving circuit is provided, wherein the pixel driving circuit is used to drive a light-emitting unit to emit light, the pixel driving circuit comprising: a driving circuit, a first light-emitting control circuit, and a first digital circuit; the driving circuit is connected to a first power supply terminal, a first node, and a light-emitting unit, and is used to provide a driving current to the light-emitting unit using the first power supply terminal according to the voltage of the first node; the first light-emitting control circuit is connected to a first digital signal terminal and is connected in series with the driving circuit between the first power supply terminal and the light-emitting unit, and is used to conduct or cut off the current path between the first power supply terminal and the light-emitting unit in response to a first digital signal of the first digital signal terminal; the first digital circuit includes a first signal conversion circuit, the first signal conversion circuit being connected to a first analog signal terminal and a first digital signal terminal, and is used to input the first digital signal to the first digital signal terminal according to the first analog signal of the first analog signal terminal.
[0005] In one exemplary embodiment of this disclosure, the first digital circuit further includes: a first switching unit, which is connected between the first signal conversion circuit and the first analog signal terminal, and is used to connect the first signal conversion circuit and the first analog signal terminal in response to a signal from the first data write signal terminal.
[0006] In one exemplary embodiment of this disclosure, the first digital circuit further includes: a first detection circuit, which is connected to the first digital signal terminal, the first analog signal terminal, and the first data read signal terminal, and is used to transmit the signal from the first digital signal terminal to the first analog signal terminal in response to the signal from the first data read signal terminal.
[0007] In one exemplary embodiment of this disclosure, the first signal conversion circuit includes: a first inverter and a second inverter, wherein the input terminal of the first inverter is connected to the first analog signal terminal and the output terminal is connected to the first digital signal terminal; the input terminal of the second inverter is connected to the first digital signal terminal and the output terminal is connected to the input terminal of the first inverter.
[0008] In one exemplary embodiment of this disclosure, the driving circuit includes: a driving transistor, wherein a first terminal of the driving transistor is connected to the first power supply terminal, a second terminal is connected to a second node, and a gate is connected to the first node. The first light-emitting control circuit includes: a first transistor, wherein a first terminal of the first transistor is connected to the second node, a second terminal is connected to the light-emitting unit, and a gate is connected to the first digital signal terminal.
[0009] In one exemplary embodiment of this disclosure, the first switching unit includes: a second transistor, the first terminal of the second transistor being connected to the first analog signal terminal, the second terminal being connected to the first signal conversion circuit, and the gate being connected to the first data write signal terminal.
[0010] In one exemplary embodiment of this disclosure, the first signal conversion circuit includes: a first inverter, the input terminal of which is connected to the first analog signal terminal, and the output terminal of which is connected to the first digital signal terminal; the first detection circuit is further configured to invert the signal transmitted from the first digital signal terminal to the first analog signal terminal.
[0011] In one exemplary embodiment of this disclosure, the first detection circuit includes: a third inverter and a third transistor. The input terminal of the third inverter is connected to the first digital signal terminal; the first terminal of the third transistor is connected to the first analog signal terminal, the second terminal is connected to the output terminal of the third inverter, and the gate is connected to the first data readout signal terminal.
[0012] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes: a first data writing circuit, which is connected to the first node, a data signal terminal, and a first gate driving signal terminal, and is used to transmit the signal of the data signal terminal to the first node in response to the signal of the first gate driving signal terminal.
[0013] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes: a second data writing circuit, which is connected to the first node, a data signal terminal, and a second gate driving signal terminal, and is used to transmit the signal of the data signal terminal to the first node in response to the signal of the second gate driving signal terminal; the conduction levels of the first data writing circuit and the second data writing circuit have opposite polarities.
[0014] In one exemplary embodiment of this disclosure, the first data writing circuit includes: a fourth transistor, the first terminal of the fourth transistor being connected to the data signal terminal, the second terminal being connected to the first node, and the gate being connected to the first gate drive signal terminal; the second data writing circuit includes: a fifth transistor, the first terminal of the fifth transistor being connected to the data signal terminal, the second terminal being connected to the first node, and the gate being connected to the second gate drive signal terminal; in the fourth transistor and the fifth transistor, one transistor is an N-type transistor and the other transistor is a P-type transistor.
[0015] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes: a second light-emitting control circuit and a second digital circuit. The second light-emitting control circuit is connected to a second digital signal terminal and is connected in series with the driving circuit between the first power supply terminal and the light-emitting unit. It is used to respond to a second digital signal from the second digital signal terminal to turn on or off the current path between the first power supply terminal and the light-emitting unit. The second digital circuit includes a second signal conversion circuit, which is connected to a second analog signal terminal and a second digital signal terminal. It is used to input the second digital signal to the second digital signal terminal according to the second analog signal from the second analog signal terminal.
[0016] In one exemplary embodiment of this disclosure, the second digital circuit further includes: a second switching unit and a second detection circuit. The second switching unit is connected between the second signal conversion circuit and the second analog signal terminal, and is used to connect the second signal conversion circuit and the second analog signal terminal in response to a signal from the second data write signal terminal. The second detection circuit is connected to the second digital signal terminal, the second analog signal terminal, and the second data read signal terminal, and is used to transmit the signal from the second digital signal terminal to the second analog signal terminal in response to a signal from the second data read signal terminal.
[0017] In one exemplary embodiment of this disclosure, the second signal conversion circuit includes a fourth inverter and a fifth inverter. The input terminal of the fourth inverter is connected to the second analog signal terminal, and its output terminal is connected to the second digital signal terminal. The input terminal of the fifth inverter is connected to the second digital signal terminal, and its output terminal is connected to the input terminal of the fourth inverter. The second light-emitting control circuit includes a sixth transistor. The first electrode of the sixth transistor is connected to the first light-emitting control circuit, the second electrode is connected to the light-emitting unit, and the gate is connected to the second digital signal terminal. The second detection circuit is further configured to invert the signal transmitted from the second digital signal terminal to the second analog signal terminal. The second detection circuit includes a sixth inverter and a seventh transistor. The input terminal of the sixth inverter is connected to the second digital signal terminal. The first electrode of the seventh transistor is connected to the second analog signal terminal, the second electrode is connected to the output terminal of the sixth inverter, and the gate is connected to the second data readout signal terminal.
[0018] In one exemplary embodiment of this disclosure, the light-emitting unit is a micro light-emitting diode.
[0019] According to one aspect of this disclosure, a pixel driving circuit driving method is provided, wherein the driving method is used to drive the aforementioned pixel driving circuit, the driving method comprising:
[0020] During the data writing phase, a data signal is input to the first node;
[0021] During the light-emitting stage, the first signal conversion circuit inputs the first digital signal to the first digital signal terminal based on the first analog signal from the first analog signal terminal.
[0022] Specifically, at least in some grayscale levels, the grayscale of the sub-pixel where the pixel driving circuit is located is adjusted using the duty cycle of the effective level in the first digital signal.
[0023] In one exemplary embodiment of this disclosure, the driving method includes:
[0024] At high grayscale, the grayscale of the sub-pixel where the pixel driving circuit is located is adjusted by the voltage of the first node;
[0025] At low gray levels, the gray level of the sub-pixel where the pixel driving circuit is located is adjusted by using the duty cycle of the effective level in the first digital signal.
[0026] In one exemplary embodiment of this disclosure, when the first digital circuit further includes a first detection circuit, the driving method further includes:
[0027] During the detection phase, the first detection circuit is used to transmit the signal from the first digital signal terminal to the first analog signal terminal.
[0028] In one exemplary embodiment of this disclosure, when the pixel driving circuit includes a second light-emitting control circuit and a second digital circuit, the driving method further includes:
[0029] At least in some grayscale levels, the grayscale of the sub-pixel where the pixel driving circuit is located is adjusted by utilizing the duty cycle of the overlapping period of the effective level in the first digital signal and the effective level in the second digital signal.
[0030] According to one aspect of this disclosure, a display panel is provided, wherein the pixel driving circuit described above is included.
[0031] According to one aspect of this disclosure, a display device is provided, wherein the display panel described above is included.
[0032] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description
[0033] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.
[0034] Figure 1 A schematic diagram of an exemplary embodiment of the pixel driving circuit of this disclosure;
[0035] Figure 2 for Figure 1 A schematic diagram of the structure of a medium inverter;
[0036] Figure 3 for Figure 1 The diagram shows the timing of various control signals in a driving method of a pixel driving circuit.
[0037] Figure 4 This is a schematic diagram of another exemplary embodiment of the pixel driving circuit of this disclosure;
[0038] Figure 5 This is a schematic diagram of another exemplary embodiment of the pixel driving circuit of this disclosure;
[0039] Figure 6 for Figure 5 The diagram shows a timing diagram of some control signals in a driving method of a pixel driving circuit.
[0040] Figure 7 This is a schematic diagram of another exemplary embodiment of the pixel driving circuit of this disclosure. Detailed Implementation
[0041] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.
[0042] The terms “a,” “one,” and “the” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended meaning of inclusion and that there may be other elements / components / etc. in addition to the listed elements / components / etc.
[0043] This exemplary embodiment first provides a pixel driving circuit, such as Figure 1 The diagram shown is a schematic representation of an exemplary embodiment of the pixel driving circuit of this disclosure. The pixel driving circuit is used to drive the light-emitting unit L to emit light. The pixel driving circuit may include: a driving circuit 1, a first light-emitting control circuit 21, and a first digital circuit 41. The driving circuit 1 is connected to a first power supply terminal VDD, a first node N1, and the light-emitting unit L, and is used to provide a driving current to the light-emitting unit L using the first power supply terminal VDD according to the voltage of the first node N1. The other electrode of the light-emitting unit L can be connected to a second power supply terminal VSS. The first light-emitting control circuit 21 is connected to a first digital signal terminal DS1 and is connected in series with the driving circuit 1 between the first power supply terminal VDD and the light-emitting unit L, and is used to respond to a first digital signal from the first digital signal terminal DS1 to turn on or off the current path between the first power supply terminal VDD and the light-emitting unit L. The first digital circuit 41 includes a first signal conversion circuit 51, which is connected to a first analog signal terminal BL1 and the first digital signal terminal DS1, and is used to input the first digital signal to the first digital signal terminal DS1 according to the first analog signal from the first analog signal terminal BL1.
[0044] In this exemplary embodiment, during the data writing phase, a data signal can be input to the first node N1; during the light emission phase, the driving circuit 1 can input a driving current to the light emission unit L using the first power supply terminal VDD based on the data signal from the first node N1; simultaneously, a first analog signal can be input to the first analog signal terminal BL1. The first analog signal may include alternately output active and inactive levels, and correspondingly, the first digital signal may include alternately output active and inactive levels. When the first digital signal is active, the first light emission control circuit 21 conducts the current path between the first power supply terminal VDD and the light emission unit L; when the first digital signal is inactive, the first light emission control circuit 21 turns off the current path between the first power supply terminal VDD and the light emission unit L. The larger the duty cycle of the active level in the first digital signal, the greater the brightness of the light emission unit L; correspondingly, the smaller the duty cycle of the active level in the first digital signal, the smaller the brightness of the light emission unit L. Thus, the pixel driving circuit can adjust the grayscale of the sub-pixel where the pixel driving circuit is located by controlling the duty cycle of the active level in the first digital signal.
[0045] It should be noted that the effective level refers to the voltage level that can drive the target circuit to conduct, while the ineffective level refers to the voltage level that can drive the target circuit to turn off. For example, when the target circuit is an N-type transistor, the effective level is high and the ineffective level is low.
[0046] In this exemplary embodiment, the pixel driving circuit can control the grayscale of the sub-pixel using only the data signal of the first node at high grayscale levels, and the duty cycle of the effective level in the first digital signal can be 100%. At low grayscale levels, the pixel driving circuit can control the grayscale of the sub-pixel using only the duty cycle of the effective level in the first digital signal, and the voltage of the first node N1 can remain unchanged in the low grayscale range. This setting allows the output current of the driving circuit 1 to remain at a high value. Since the light-emitting unit L has higher luminous efficiency at higher driving current, this setting can improve the luminous efficiency of the light-emitting unit L and reduce the power consumption of the pixel driving circuit. In a display panel with a maximum grayscale of 255, the low grayscale can be 0 grayscale to 40 grayscale, for example, the low grayscale can be 0 grayscale, 20 grayscale, and 40 grayscale; the high grayscale can be 41 grayscale to 255 grayscale, for example, the high grayscale can be 41 grayscale, 100 grayscale, 150 grayscale, 200 grayscale, and 255 grayscale.
[0047] It should be understood that in other exemplary embodiments, the pixel driving circuit may also have other driving methods. For example, the pixel driving circuit may simultaneously control the grayscale of the sub-pixel at each grayscale level using the duty cycle of the effective level in the data signal of the first node and the first digital signal. By adjusting the duty cycle of the effective level in the first digital signal, the grayscale corresponding to the original data signal can be further subdivided, thereby improving the control accuracy of the grayscale.
[0048] In this exemplary embodiment, the first digital circuit 41 can convert the first analog signal into a first digital signal. The logic 1 and logic 0 of the first digital signal are both stable potentials, thereby improving the stability of grayscale adjustment.
[0049] In this exemplary embodiment, as Figure 1 As shown, the first digital circuit 41 may further include: a first switching unit 61, which is connected between the first signal conversion circuit 51 and the first analog signal terminal BL1, and is used to connect the first signal conversion circuit 51 and the first analog signal terminal BL1 in response to the signal of the first data write signal terminal Wdw1.
[0050] In this exemplary embodiment, as Figure 1 As shown, the first digital circuit 41 may further include: a first detection circuit 71, which is connected to the first digital signal terminal DS1, the first analog signal terminal BL1, and the first data read signal terminal Wdr1, and is used to respond to the signal of the first data read signal terminal Wdr1 to transmit the signal of the first digital signal terminal DS1 to the first analog signal terminal BL1.
[0051] In this exemplary embodiment, as Figure 1 As shown, the first signal conversion circuit 51 may include a first inverter I1 and a second inverter I2. The input terminal of the first inverter I1 is connected to the first analog signal terminal BL1, and the output terminal is connected to the first digital signal terminal DS1. The input terminal of the second inverter I2 is connected to the first digital signal terminal DS1, and the output terminal is connected to the input terminal of the first inverter I1. It should be understood that in other exemplary embodiments, the first signal conversion circuit 51 may also have other structures. For example, the first signal conversion circuit 51 may be an analog-to-digital converter, or it may consist only of the first inverter I1.
[0052] In this exemplary embodiment, as Figure 1 As shown, the driving circuit 1 may include a driving transistor DT, with its first terminal connected to the first power supply terminal VDD, its second terminal connected to the second node N2, and its gate connected to the first node N1. The first light-emitting control circuit 21 includes a first transistor T1, with its first terminal connected to the second node N2, its second terminal connected to the light-emitting unit L, and its gate connected to the first digital signal terminal DS1. It should be understood that the first light-emitting control circuit 21 may also be connected between the first power supply terminal VDD and the driving circuit 1.
[0053] In this exemplary embodiment, as Figure 1As shown, the first switching unit 61 may include: a second transistor T2, the first terminal of the second transistor T2 is connected to the first analog signal terminal BL1, the second terminal is connected to the first signal conversion circuit 51, and the gate is connected to the first data write signal terminal Wdw1.
[0054] In this exemplary embodiment, as Figure 1 As shown, the first detection circuit 71 is further used to invert the signal transmitted from the first digital signal terminal DS1 to the first analog signal terminal BL1. The first detection circuit 71 may include: a third inverter I3 and a third transistor T3. The input terminal of the third inverter I3 is connected to the first digital signal terminal DS1; the first terminal of the third transistor T3 is connected to the first analog signal terminal BL1, the second terminal is connected to the output terminal of the third inverter I3, and the gate is connected to the first data read signal terminal Wdr1.
[0055] In this exemplary embodiment, as Figure 1 As shown, the pixel driving circuit further includes: a first data writing circuit 81, which is connected to the first node N1, a data signal terminal Da, and a first gate driving signal terminal G1, and is used to transmit the signal of the data signal terminal Da to the first node N1 in response to the signal of the first gate driving signal terminal G1. The first data writing circuit 81 may include: a fourth transistor T4, the first terminal of which is connected to the data signal terminal Da, the second terminal of which is connected to the first node N1, and the gate of which is connected to the first gate driving signal terminal G1.
[0056] In this exemplary embodiment, as Figure 1 As shown, the pixel driving circuit may also include a capacitor C, which is connected between the first node N1 and the second node N2.
[0057] In this exemplary embodiment, the driving transistor DT, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 can be N-type transistors, the first power supply terminal VDD can be a high-level power supply terminal, and the second power supply terminal VSS can be a low-level power supply terminal. It should be understood that in other exemplary embodiments, the driving transistor DT, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 can also be P-type transistors.
[0058] like Figure 2 As shown, Figure 1A schematic diagram of the inverter structure. In this exemplary embodiment, each inverter may include an N-type transistor NT and a P-type transistor PT. The first terminal of the N-type transistor NT is connected to the low-level signal terminal VGL, the second terminal is connected to the output terminal OUT of the inverter, and the gate is connected to the input terminal IN of the inverter; the first terminal of the P-type transistor PT is connected to the high-level signal terminal VGH, the second terminal is connected to the output terminal OUT of the inverter, and the gate is connected to the input terminal IN of the inverter.
[0059] like Figure 3 As shown, Figure 1 The diagram shows the timing diagram of various control signals in a driving method of the pixel driving circuit. G1 represents the timing diagram of the signals at the first gate driving signal terminal, Wdw1 represents the timing diagram of the signals at the first data write signal terminal, BL1 represents the timing diagram of the signals at the first analog signal terminal, and Wdr1 represents the timing diagram of the signals at the first data read signal terminal.
[0060] The pixel driving circuit driving method can include three stages: a data writing stage t1, a light emission stage t2, and a detection stage t3. In the data writing stage t1, the first gate driving signal terminal G1 outputs a high-level signal, the fourth transistor T4 is turned on, and the data signal terminal Da inputs a data signal to the first node N1. In the light emission stage t2, the data signal on the first node N1 drives the driving transistor DT to input a driving current to the second node N2. Simultaneously, the first data writing signal terminal Wdw1 outputs a high-level signal, the second transistor T2 is turned on, and the first analog signal terminal BL1 inputs a first analog signal to the first signal conversion circuit 51. The first analog signal includes alternating high and low levels. When the first analog signal is high, the first inverter I1 converts the first analog signal into a low-level digital signal and transmits it to the first digital signal terminal DS1. When the first analog signal is low, the first inverter I1 converts the first analog signal into a high-level digital signal and transmits it to the first digital signal terminal DS1. The second inverter I2 can invert the first digital signal at the first digital signal terminal DS1 and transmit it to the input terminal of the first inverter I1. The second inverter I2 and the first inverter I1 can form a latch structure, which can improve the stability of the signal at the input terminal of the first inverter I1. The first digital signal on the first digital signal terminal DS1 can control the first transistor T1 to turn on or off, thereby controlling the grayscale of the sub-pixel. In the detection stage t3: the first data read signal terminal Wdr1 outputs a high level, the third transistor T3 turns on, the third inverter I3 inverts the signal at the first digital signal terminal DS1 and transmits it to the first analog signal terminal BL1, so that the voltage on the first analog signal terminal BL1 can be detected by the external detection circuit to detect whether the logic signal on the first digital signal terminal DS1 is correct.
[0061] In this exemplary embodiment, the detection phase t3 can be located in the blank phase between frames. For example... Figure 3 As shown, during the light emission stage t2, the first data write signal terminal Wdw1 can continuously output a high-level signal. It should be understood that in other exemplary embodiments, the detection stage t3 can also be located in other time periods. Furthermore, in other exemplary embodiments, during the light emission stage t2, the first data write signal terminal Wdw1 can also output multiple high-level pulse signals. The high-level pulse signals output by the first data write signal terminal Wdw1 correspond one-to-one with the low-level pulse signals output by the first analog signal terminal BL1, and the high-level pulse signals output by the first data write signal terminal Wdw1 and the corresponding low-level pulse signals output by the first analog signal terminal BL1 at least partially overlap in the output time period.
[0062] like Figure 1 As shown, when the data signal voltage that the data signal terminal Da needs to write to the first node N1 is large, the gate-source voltage difference of the fourth transistor T4 is small. This gate-source voltage difference of the fourth transistor T4 is equal to the voltage difference between the first gate drive signal terminal G1 and the first node N1. A small gate-source voltage difference may prevent the fourth transistor T4 from conducting. That is, the data signal terminal Da cannot write the required data signal voltage to the first node N1.
[0063] Based on this, such as Figure 4 The diagram shown illustrates another exemplary embodiment of the pixel driving circuit of this disclosure. In this exemplary embodiment, the pixel driving circuit may further include: a second data writing circuit 82, connected to the first node N1, a data signal terminal Da, and a second gate driving signal terminal G2, used to transmit the signal of the data signal terminal Da to the first node N1 in response to the signal of the second gate driving signal terminal G2; the conduction levels of the first data writing circuit 81 and the second data writing circuit 82 have opposite polarities. The second data writing circuit 82 may include: a fifth transistor T5, the first terminal of the fifth transistor T5 connected to the data signal terminal Da, the second terminal connected to the first node N1, and the gate connected to the second gate driving signal terminal G2; the fifth transistor T5 may be a P-type transistor. When the data signal voltage that the data signal terminal Da needs to write to the first node N1 is relatively large, the fifth transistor T5 can be turned on through the second gate drive signal terminal G2. Since the fifth transistor T5 is a P-type transistor, the smaller the gate-source voltage difference of the fifth transistor T5, the more fully the fifth transistor T5 is turned on. Specifically, the gate-source voltage difference of the fifth transistor T5 is equal to the voltage difference between the second gate drive signal terminal G2 and the data signal terminal Da. Therefore, the data signal terminal Da can input a larger voltage to the first node N1 through the fifth transistor T5. This setting improves the range of data signal voltage settings.
[0064] In this exemplary embodiment, during the data writing phase, the fourth transistor T4 and the fifth transistor T5 can be turned on simultaneously. It should be understood that in other exemplary embodiments, the fifth transistor T5 may be turned on when the data signal voltage is high, and the fourth transistor may be turned on when the data signal voltage is low. Furthermore, in other exemplary embodiments, the fourth transistor T4 may be a P-type transistor, and the fifth transistor T5 may be an N-type transistor.
[0065] In this exemplary embodiment, to avoid flickering in the light-emitting unit L, the first analog signal terminal BL1 needs to output a low-level pulse signal at a higher frequency. However, due to limitations in the driving capability of the circuit providing the first analog signal to the first analog signal terminal BL1, the pulse duration of the low-level pulse signal output by the first analog signal terminal BL1 in high-frequency output mode cannot be too short. This results in the duty cycle of the high level on the first digital signal terminal DS1 not being too small, meaning the duty cycle adjustment range of the high level on the first digital signal terminal DS1 is limited.
[0066] Based on this, such as Figure 5 The diagram shown is a structural schematic of another exemplary embodiment of the pixel driving circuit of this disclosure. In this exemplary embodiment, the pixel driving circuit may further include: a second light-emitting control circuit 22 and a second digital circuit 42. The second light-emitting control circuit 22 is connected to a second digital signal terminal DS2 and is connected in series with the driving circuit 1 between the first power supply terminal VDD and the light-emitting unit L, and is used to conduct or cut off the current path between the first power supply terminal VDD and the light-emitting unit L in response to a second digital signal from the second digital signal terminal DS2. The second digital circuit 42 includes a second signal conversion circuit 52, which is connected to a second analog signal terminal BL2 and the second digital signal terminal DS2, and is used to input the second digital signal to the second digital signal terminal DS2 according to the second analog signal from the second analog signal terminal BL2.
[0067] In this exemplary embodiment, as Figure 5 As shown, the second digital circuit 42 further includes: a second switching unit 62 and a second detection circuit 72. The second switching unit 62 is connected between the second signal conversion circuit 52 and the second analog signal terminal BL2, and is used to connect the second signal conversion circuit 52 and the second analog signal terminal BL2 in response to the signal of the second data write signal terminal Wdw2. The second detection circuit 72 is connected to the second digital signal terminal DS2, the second analog signal terminal BL2, and the second data read signal terminal Wdr2, and is used to transmit the signal of the second digital signal terminal DS2 to the second analog signal terminal BL2 in response to the signal of the second data read signal terminal Wdr2.
[0068] In this exemplary embodiment, as Figure 5 As shown, the second signal conversion circuit 52 may include: a fourth inverter I4 and a fifth inverter I5. The input terminal of the fourth inverter I4 is connected to the second analog signal terminal BL2, and the output terminal is connected to the second digital signal terminal DS2. The input terminal of the fifth inverter I5 is connected to the second digital signal terminal DS2, and the output terminal is connected to the input terminal of the fourth inverter I4. The second light-emitting control circuit 22 may include: a sixth transistor T6. The first terminal of the sixth transistor T6 is connected to the first light-emitting control circuit 21, the second terminal is connected to the light-emitting unit L, and the gate is connected to the second digital signal terminal DS2. The second detection circuit 72 is further used to invert the signal transmitted from the second digital signal terminal DS2 to the second analog signal terminal BL2. The second detection circuit 72 may include: a sixth inverter I6 and a seventh transistor T7. The input terminal of the sixth inverter I6 is connected to the second digital signal terminal DS2. The first terminal of the seventh transistor T7 is connected to the second analog signal terminal BL2, the second terminal is connected to the output terminal of the sixth inverter I6, and the gate is connected to the second data read signal terminal Wdr2.
[0069] like Figure 6 As shown, Figure 5 The diagram shows a timing diagram of some control signals in a driving method of a pixel driving circuit. Wdw1 represents the timing diagram of the signal on the first data write signal terminal, Wdw2 represents the timing diagram of the signal on the second data write signal terminal, DS1 represents the timing of the signal on the first digital signal terminal, and DS2 represents the timing of the signal on the second digital signal terminal.
[0070] During the light-emitting phase t2, the first analog signal on the first analog signal terminal BL1 and the second analog signal on the second analog signal terminal BL2 can have different timing sequences, so that the first digital signal on the first digital signal terminal DS1 and the second digital signal on the second digital signal terminal DS2 have different timing sequences. The high-level periods of the first digital signal and the second digital signal can partially overlap. For example... Figure 6 As shown, during the overlapping period t of the high levels of the first and second digital signals, the first transistor T1 and the sixth transistor T6 are simultaneously turned on, and the light-emitting unit L emits light. According to Figure 6 It can be seen that when the lighting frequency of the light-emitting unit L remains unchanged, Figure 6 The pixel driving circuit shown can achieve a shorter single-light-up time for the light-emitting unit L, thereby enabling smaller grayscale adjustments.
[0071] In this exemplary embodiment, as Figure 1 As shown, the first digital circuit 41 is integrated into the pixel driving circuit architecture of the 3T1C; as Figure 5As shown, the first digital circuit 41 and the second digital circuit 42 are integrated into the 5T1C pixel driving circuit architecture. It should be understood that in other exemplary embodiments, the first digital circuit 41 and / or the second digital circuit 42 may also be integrated into pixel driving circuits with other architectures. For example, as... Figure 7 The diagram shown is a structural schematic of another exemplary embodiment of the pixel driving circuit of this disclosure. The first digital circuit 41 and the second digital circuit 42 can be integrated into the pixel driving circuit architecture of the 7T1C. In addition to the first digital circuit 41 and the second digital circuit 42, the pixel driving circuit may also include: a driving transistor M3, a first transistor M1, a second transistor M2, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and a capacitor C. Specifically, the first terminal of the fourth transistor M4 is connected to the data signal terminal Da, the second terminal of the fourth transistor M4 is connected to the first terminal of the driving transistor M3, and the gate of the fourth transistor M4 is connected to the first gate driving signal terminal G1; the first terminal of the fifth transistor M5 is connected to the first power supply terminal VDD, the second terminal of the fifth transistor M5 is connected to the first terminal of the driving transistor M3, and the gate of the fifth transistor M5 is connected to the first digital signal terminal DS1; the gate of the driving transistor M3 is connected to node N; the first terminal of the second transistor M2 is connected to node N, the second terminal of the second transistor M2 is connected to the second terminal of the driving transistor M3, and the gate of the second transistor M2 is connected to the second gate driving signal terminal G. 2; The first electrode of the sixth transistor M6 is connected to the second electrode of the driving transistor M3, the second electrode of the sixth transistor M6 is connected to the second electrode of the seventh transistor M7, the gate of the sixth transistor M6 is connected to the second digital signal terminal DS2, the first electrode of the seventh transistor M7 is connected to the second initial signal terminal ViniM2, and the gate of the seventh transistor M7 is connected to the second reset signal terminal Re2; the second electrode of the first transistor M1 is connected to node N, the first electrode of the first transistor M1 is connected to the first initial signal terminal ViniM1, and the gate of the first transistor M1 is connected to the first reset signal terminal Re1; the first electrode of the capacitor C is connected to node N, and the second electrode of the capacitor C is connected to the first power supply terminal VDD. This pixel driving circuit can be connected to a light-emitting unit L, which is used to drive the light-emitting unit L to emit light. The first electrode of the light-emitting unit L can be connected to the second electrode of the sixth transistor M6, and the second electrode of the light-emitting unit can be connected to the second power supply terminal VSS. The first transistor M1 and the second transistor M2 can be N-type transistors, while the driving transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 can be P-type transistors.
[0072] In this exemplary embodiment, the light-emitting unit L can be a micro light-emitting diode (Micro LED), a mini light-emitting diode (Mini LED), etc., with the size of the mini LED being approximately 100-300 μm; the size of the micro LED is less than 100 μm. The pixel driving circuit can be a CMOS pixel driving circuit integrated on a silicon substrate. That is, the backplane in the display panel can include silicon, such as polycrystalline silicon or monocrystalline silicon, and the backplane can be referred to as a silicon substrate or silicon-based backplane. The transistors in the pixel driving circuit are formed in the silicon substrate using CMOS technology. In some embodiments, the silicon-based transistors formed in the silicon substrate include a silicon substrate. Compared with glass-based thin-film transistors, silicon-based transistors have the following advantages: First, the size of silicon-based transistors is tens to hundreds of nanometers, while the size of glass-based thin-film transistors is several micrometers to tens of micrometers, and the size of silicon-based transistors is small. Second, the conduction time of silicon-based transistors is tens of picoseconds, while that of glass-based thin-film transistors is between tens and hundreds of nanoseconds, indicating a faster conduction time for silicon-based transistors. Third, silicon-based transistors are more stable than transistors fabricated on glass substrates, and pixel driving circuits composed of glass-based transistors do not require threshold voltage compensation. It should be understood that in other exemplary embodiments, the light-emitting unit can also be other types of light-emitting diodes.
[0073] This exemplary embodiment also provides a pixel driving circuit driving method, wherein the driving method is used to drive the aforementioned pixel driving circuit, and the driving method includes:
[0074] During the data writing phase, a data signal is input to the first node;
[0075] During the light-emitting stage, the first signal conversion circuit inputs the first digital signal to the first digital signal terminal based on the first analog signal from the first analog signal terminal.
[0076] Specifically, at least in some grayscale levels, the grayscale of the sub-pixel where the pixel driving circuit is located is adjusted using the duty cycle of the effective level in the first digital signal.
[0077] In this exemplary embodiment, the driving method includes:
[0078] At high grayscale, the grayscale of the sub-pixel where the pixel driving circuit is located is adjusted by the voltage of the first node;
[0079] At low gray levels, the gray level of the sub-pixel where the pixel driving circuit is located is adjusted by using the duty cycle of the effective level in the first digital signal.
[0080] In this exemplary embodiment, when the first digital circuit includes a first detection circuit, the driving method further includes:
[0081] During the detection phase, the first detection circuit is used to transmit the signal from the first digital signal terminal to the first analog signal terminal.
[0082] In this exemplary embodiment, when the pixel driving circuit includes a second light-emitting control circuit and a second digital circuit, the driving method further includes:
[0083] At least in some grayscale levels, the grayscale of the sub-pixel where the pixel driving circuit is located is adjusted by utilizing the duty cycle of the overlapping period of the effective level in the first digital signal and the effective level in the second digital signal.
[0084] This exemplary embodiment also provides a display panel, wherein the display panel may include the pixel driving circuit described above.
[0085] This exemplary embodiment also provides a display device, wherein the display device includes the display panel described above. The display device can be a VR (Virtual Reality), AR (Augmented Reality), mobile phone, tablet computer, or other display device.
[0086] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.
[0087] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is defined only by the appended claims.
Claims
1. A pixel driving circuit, wherein, The pixel driving circuit is used to drive the light-emitting unit to emit light, and the pixel driving circuit includes: A driving circuit, connected to a first power supply terminal, a first node, and a light-emitting unit, is used to provide driving current to the light-emitting unit using the first power supply terminal according to the voltage of the first node. A first light-emitting control circuit is connected to a first digital signal terminal and is connected in series with the driving circuit between the first power supply terminal and the light-emitting unit. It is used to respond to a first digital signal from the first digital signal terminal to turn on or off the current path between the first power supply terminal and the light-emitting unit. A first digital circuit, the first digital circuit including a first signal conversion circuit, the first signal conversion circuit being connected to a first analog signal terminal and a first digital signal terminal, for inputting the first digital signal to the first digital signal terminal according to the first analog signal of the first analog signal terminal; The second light-emitting control circuit is connected to the second digital signal terminal and is connected in series with the driving circuit between the first power supply terminal and the light-emitting unit. It is used to respond to the second digital signal of the second digital signal terminal to turn on or off the current path between the first power supply terminal and the light-emitting unit. The second digital circuit includes a second signal conversion circuit, which is connected to a second analog signal terminal and a second digital signal terminal, and is used to input the second digital signal to the second digital signal terminal according to the second analog signal of the second analog signal terminal. The effective level periods of the first digital signal and the effective level periods of the second digital signal partially overlap.
2. The pixel driving circuit according to claim 1, wherein, The first digital circuit also includes: A first switching unit is connected between the first signal conversion circuit and the first analog signal terminal, and is used to connect the first signal conversion circuit and the first analog signal terminal in response to a signal from the first data write signal terminal.
3. The pixel driving circuit according to claim 1, wherein, The first digital circuit also includes: A first detection circuit is connected to the first digital signal terminal, the first analog signal terminal, and the first data read signal terminal, and is used to respond to the signal of the first data read signal terminal to transmit the signal of the first digital signal terminal to the first analog signal terminal.
4. The pixel driving circuit according to claim 1, wherein, The first signal conversion circuit includes: The first inverter has its input terminal connected to the first analog signal terminal and its output terminal connected to the first digital signal terminal. The second inverter has its input terminal connected to the first digital signal terminal and its output terminal connected to the input terminal of the first inverter.
5. The pixel driving circuit according to claim 1, wherein, The driving circuit includes: A driving transistor has its first terminal connected to the first power supply terminal, its second terminal connected to the second node, and its gate connected to the first node. The first light-emitting control circuit includes: The first transistor has a first electrode connected to the second node, a second electrode connected to the light-emitting unit, and a gate connected to the first digital signal terminal.
6. The pixel driving circuit according to claim 2, wherein, The first switching unit includes: The second transistor has its first terminal connected to the first analog signal terminal, its second terminal connected to the first signal conversion circuit, and its gate connected to the first data write signal terminal.
7. The pixel driving circuit according to claim 3, wherein, The first signal conversion circuit includes: The first inverter has its input terminal connected to the first analog signal terminal and its output terminal connected to the first digital signal terminal. The first detection circuit is also used to invert the signal transmitted from the first digital signal terminal to the first analog signal terminal.
8. The pixel driving circuit according to claim 7, wherein, The first detection circuit includes: The third inverter has its input terminal connected to the first digital signal terminal. The third transistor has its first terminal connected to the first analog signal terminal, its second terminal connected to the output terminal of the third inverter, and its gate connected to the first data read signal terminal.
9. The pixel driving circuit according to claim 1, wherein, The pixel driving circuit also includes: A first data writing circuit is connected to the first node, a data signal terminal, and a first gate drive signal terminal, and is used to transmit the signal from the data signal terminal to the first node in response to the signal from the first gate drive signal terminal.
10. The pixel driving circuit according to claim 9, wherein, The pixel driving circuit also includes: The second data writing circuit is connected to the first node, the data signal terminal, and the second gate drive signal terminal, and is used to transmit the signal of the data signal terminal to the first node in response to the signal of the second gate drive signal terminal. The conduction levels of the first data writing circuit and the second data writing circuit have opposite polarities.
11. The pixel driving circuit according to claim 10, wherein, The first data writing circuit includes: The fourth transistor has its first terminal connected to the data signal terminal, its second terminal connected to the first node, and its gate connected to the first gate drive signal terminal. The second data writing circuit includes: The fifth transistor has its first terminal connected to the data signal terminal, its second terminal connected to the first node, and its gate connected to the second gate drive signal terminal. In the fourth and fifth transistors, one transistor is an N-type transistor and the other transistor is a P-type transistor.
12. The pixel driving circuit according to claim 1, wherein, The second digital circuit also includes: The second switching unit is connected between the second signal conversion circuit and the second analog signal terminal, and is used to connect the second signal conversion circuit and the second analog signal terminal in response to the signal of the second data write signal terminal. The second detection circuit is connected to the second digital signal terminal, the second analog signal terminal, and the second data read signal terminal, and is used to respond to the signal of the second data read signal terminal to transmit the signal of the second digital signal terminal to the second analog signal terminal.
13. The pixel driving circuit according to claim 12, wherein, The second signal conversion circuit includes: The fourth inverter has its input terminal connected to the second analog signal terminal and its output terminal connected to the second digital signal terminal. The fifth inverter has its input terminal connected to the second digital signal terminal and its output terminal connected to the input terminal of the fourth inverter. The second light-emitting control circuit includes: The sixth transistor has its first electrode connected to the first light-emitting control circuit, its second electrode connected to the light-emitting unit, and its gate connected to the second digital signal terminal. The second detection circuit is also used to invert the signal transmitted from the second digital signal terminal to the second analog signal terminal; The second detection circuit includes: The sixth inverter has its input terminal connected to the second digital signal terminal; The seventh transistor has its first terminal connected to the second analog signal terminal, its second terminal connected to the output terminal of the sixth inverter, and its gate connected to the second data read signal terminal.
14. The pixel driving circuit according to claim 1, wherein, The light-emitting unit is a micro light-emitting diode.
15. A pixel driving circuit driving method, wherein, The driving method is used to drive the pixel driving circuit according to any one of claims 1-14, the driving method comprising: During the data writing phase, a data signal is input to the first node; During the light-emitting stage, the first signal conversion circuit inputs the first digital signal to the first digital signal terminal based on the first analog signal from the first analog signal terminal. Specifically, at least in some grayscale levels, the grayscale of the sub-pixel where the pixel driving circuit is located is adjusted using the duty cycle of the effective level in the first digital signal.
16. The pixel driving circuit driving method according to claim 15, wherein, The driving method includes: At high grayscale, the grayscale of the sub-pixel where the pixel driving circuit is located is adjusted by the voltage of the first node; At low gray levels, the gray level of the sub-pixel where the pixel driving circuit is located is adjusted by using the duty cycle of the effective level in the first digital signal.
17. The pixel driving circuit driving method according to claim 15, wherein, When the first digital circuit further includes a first detection circuit, the driving method further includes: During the detection phase, the first detection circuit is used to transmit the signal from the first digital signal terminal to the first analog signal terminal.
18. The pixel driving circuit driving method according to claim 15, wherein, When the pixel driving circuit includes a second light-emitting control circuit and a second digital circuit, the driving method further includes: At least in some grayscale levels, the grayscale of the sub-pixel where the pixel driving circuit is located is adjusted by utilizing the duty cycle of the overlapping period of the effective level in the first digital signal and the effective level in the second digital signal.
19. A display panel, wherein, Includes the pixel driving circuit according to any one of claims 1-14.
20. A display device, wherein, Includes the display panel as described in claim 19.