Chip, preparation method thereof, display panel and electronic device

Abstract

The application provides a chip and a preparation method thereof, a display panel and an electronic device, and relates to the technical field of semiconductors. The chip can form a two-dimensional electron gas at the interface between a channel and a passivation layer, improve the carrier concentration of the channel, and thus improve the driving current of the transistor. The chip comprises a substrate and a transistor arranged on the substrate. The transistor comprises a gate, a gate dielectric, a channel, a first electrode, a second electrode and a passivation layer. The gate, the gate dielectric and the channel are arranged in layers on the substrate, and the gate dielectric is used to electrically isolate the channel from the gate. The first electrode, the second electrode and the passivation layer are arranged on at least part of the surface of the channel, and the passivation layer is at least partially located between the first electrode and the second electrode. The surface of the channel comprises a first surface in contact with the passivation layer and a second surface in contact with the first electrode and the second electrode. The material of the channel comprises an oxide semiconductor, and the oxygen vacancy concentration of the first surface is greater than the oxygen vacancy concentration of the part of the channel other than the first surface and the second surface.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a chip and its fabrication method, a display panel, and an electronic device. Background Technology

[0002] In the display field, active matrix driving display technology based on thin-film transistors (TFTs) is a key technology supporting large-area flat panel displays. Among them, improving the performance of TFTs is crucial for optimizing display effects. In display driving, the main performance indicators of TFTs include field-effect mobility, drive current, subthreshold swing, and on / off ratio. TFTs using indium gallium zinc oxide (IGZO) as the channel material have high field-effect mobility, low subthreshold swing, extremely low leakage current, and low cost, and are widely used in large-area flat panel displays.

[0003] The field-effect mobility of indium gallium zinc oxide TFTs fabricated using existing technologies can reach 10 cm⁻¹. 2 The current is around / V·s, but for the application requirements of next-generation display technologies, such as organic light emitting diode (OLED) and micro light emitting diode (micro-LED) display devices, the driving current needs to be further increased. Summary of the Invention

[0004] To address the aforementioned technical problems, this application provides a chip and its fabrication method, a display panel, and an electronic device, which can form a two-dimensional electron gas at the interface between the channel and the passivation layer, thereby increasing the carrier concentration in the channel and thus increasing the driving current of the transistor, enabling the transistor to be widely used in displays such as OLED, micro-LED, mini LED, and QLED.

[0005] In a first aspect, this application provides a chip including a substrate and a transistor disposed on the substrate. The transistor includes a gate, a gate dielectric, a channel, a first electrode, a second electrode, and a passivation layer. The gate, gate dielectric, and channel are stacked on the substrate, and the gate dielectric is used to electrically isolate the channel from the gate. The first electrode, the second electrode, and the passivation layer are disposed on at least a portion of the surface of the channel, and the passivation layer is at least partially located between the first electrode and the second electrode. The surface of the channel includes a first surface and a second surface, the first surface being in contact with the passivation layer, and the second surface being in contact with the first electrode and the second electrode. The material of the channel includes an oxide semiconductor, and the oxygen vacancy concentration on the first surface is greater than the oxygen vacancy concentration in the portion of the channel other than the first and second surfaces.

[0006] Those skilled in the art will understand that an oxygen vacancy refers to a vacancy formed when an oxygen atom (or oxygen ion) escapes from the crystal lattice of a metal oxide or other oxygen-containing compound, resulting in oxygen loss. Alternatively, it can be described as a defect left by an oxygen atom (or oxygen ion) escaping from its crystal lattice. Based on this, when the channel material includes an oxide semiconductor, by providing a defect-rich passivation layer on the first surface of the channel, the oxygen vacancy concentration on the first surface is made greater than the oxygen vacancy concentration outside the first and second surfaces of the channel, thereby achieving a situation where the defects on the first surface are greater than the defects outside the first and second surfaces of the channel.

[0007] The first surface has a large number of defects, which can affect the heterojunction at the interface between the first surface and the passivation layer, thereby forming a two-dimensional electron gas at the interface between the first surface and the passivation layer, increasing the carrier concentration in the channel, and thus increasing the driving current of the transistor, thereby improving the brightness, contrast and color saturation of the display, making the transistor widely used in various types of displays.

[0008] In some possible implementations, the oxygen vacancy concentration on the second surface is also greater than the oxygen vacancy concentration in the portion of the channel other than the first and second surfaces. That is, a defect-rich passivation layer is formed not only on the first surface but also on the second surface; subsequently, a portion on the second surface is removed, resulting in defects on both the first and second surfaces. Therefore, the passivation layer is positioned on the first...

[0009] The first and second electrodes on the two surfaces form a Schottky contact with the channel, thereby improving the switching characteristics of the transistor and avoiding the problem that the off-state current of the transistor increases due to excessively high carrier concentration, which would reduce the switching characteristics of the transistor.

[0010] In some possible implementations where the first and second electrodes are formed first, followed by the passivation layer, the passivation layer can be located not only in the region between the first and second electrodes but also on the side of the first and second electrodes facing away from the substrate. Compared to the approach of forming the first and second electrodes first, in the approach of forming the passivation layer first, a first film layer can be formed on the channel, completely covering the surface of the channel. Then, the first film layer is etched to obtain the passivation layer. Since the first film layer has many defects, whenever the first film layer has been formed on the first and second surfaces of the channel, both surfaces will have defects. Even if the first film layer on the second surface is etched, the second surface still has defects, allowing the first and second electrodes disposed on the channel to form a Schottky contact with the channel. This improves the switching characteristics of the transistor and avoids the problem of increased off-state current due to excessively high carrier concentration, which leads to a decrease in the transistor's switching characteristics.

[0011] In some possible implementations, multi-metal oxides can generate more defects during deposition. Therefore, the passivation layer material includes multi-metal oxides. In this way, by depositing a passivation layer containing multi-metal oxides on the channel, the oxygen vacancy concentration on the first surface can be greater than the oxygen vacancy concentration in the portion of the channel outside the first and second surfaces. For example, the passivation layer material includes at least one of gallium oxide, magnesium oxide, and titanium dioxide.

[0012] Secondly, this application provides a method for fabricating a chip, the chip including a transistor. The method for fabricating the transistor includes: sequentially forming a gate, a gate dielectric, and a channel on a substrate; stacking the gate, gate dielectric, and channel, with the gate dielectric used to electrically isolate the channel from the gate; forming a first electrode, a second electrode, and a passivation layer on at least a portion of the surface of the channel, with the passivation layer at least partially located between the first electrode and the second electrode; the surface of the channel includes a first surface and a second surface, the first surface contacting the passivation layer, and the second surface contacting the first electrode and the second electrode. The material of the channel includes an oxide semiconductor, and the oxygen vacancy concentration on the first surface is greater than the oxygen vacancy concentration in the portion of the channel other than the first and second surfaces.

[0013] In some possible implementations, forming a first electrode, a second electrode, and a passivation layer on at least a portion of the surface of the channel includes: forming a first film layer on the surface of the channel, the first film layer completely covering the channel; etching the first film layer to obtain a passivation layer; and forming the first electrode and the second electrode on opposite sides of the passivation layer.

[0014] In some possible implementations, forming a first electrode, a second electrode, and a passivation layer on at least a portion of the surface of the channel includes: forming a first electrode and a second electrode on a portion of the surface of the channel; and forming a passivation layer between the first electrode and the second electrode.

[0015] In some possible implementations, the passivation layer is also located on the side of the first and second electrodes facing away from the substrate.

[0016] The second aspect and any implementation thereof correspond to the first aspect and any implementation thereof, respectively. The technical effects of the second aspect and any implementation thereof are similar to those of the first aspect and any implementation thereof, and will not be repeated here.

[0017] Thirdly, this application provides a chip including a substrate and a transistor disposed on the substrate. The transistor includes: a first electrode, a stacked structure, a gate dielectric, a channel, a second electrode, and a passivation layer. The first electrode and the stacked structure are stacked on the substrate, and the stacked structure has a cutout portion. Along the direction from the substrate to the first electrode, the stacked structure includes a first spacer layer, a gate, and a second spacer layer stacked on top of each other. The gate dielectric fills the cutout portion, and the channel is at least partially located in the cutout portion. The gate dielectric is located on the sidewall of the cutout portion and is used to electrically isolate the channel from the gate. The channel is in contact with the first electrode. The second electrode and the passivation layer are disposed on at least a portion of the surface of the channel. The surface of the channel includes a first surface and a second surface. The first surface is in contact with the passivation layer, and the second surface is in contact with the second electrode. The material of the channel includes an oxide semiconductor, and the oxygen vacancy concentration on the first surface is greater than the oxygen vacancy concentration in the portion of the channel other than the first and second surfaces.

[0018] Those skilled in the art will understand that an oxygen vacancy refers to a vacancy formed when an oxygen atom (or oxygen ion) escapes from the crystal lattice of a metal oxide or other oxygen-containing compound, resulting in oxygen loss. Alternatively, it can be described as a defect left by an oxygen atom (or oxygen ion) escaping from its crystal lattice. Based on this, when the channel material includes an oxide semiconductor, by providing a defect-rich passivation layer on the first surface of the channel, the oxygen vacancy concentration on the first surface is made greater than the oxygen vacancy concentration outside the first and second surfaces of the channel, thereby achieving a situation where the defects on the first surface are greater than the defects outside the first and second surfaces of the channel.

[0019] The first surface has a large number of defects, which can affect the heterojunction at the interface between the first surface and the passivation layer, thereby forming a two-dimensional electron gas at the interface between the first surface and the passivation layer, increasing the carrier concentration in the channel, and thus increasing the driving current of the transistor, thereby improving the brightness, contrast and color saturation of the display, making the transistor widely used in various types of displays.

[0020] In some possible implementations, the oxygen vacancy concentration on the second surface is also greater than the oxygen vacancy concentration in the portion of the channel other than the first and second surfaces. That is, the defect-rich passivation layer is formed not only on the first surface but also on the second surface. Subsequently, a portion on the second surface is removed, resulting in defects on both the first and second surfaces. Therefore, the second electrode disposed on the second surface forms a Schottky contact with the channel, thereby improving the switching characteristics of the transistor and avoiding the problem of the transistor's switching characteristics decreasing due to an increase in the off-state current caused by excessively high carrier concentration.

[0021] In some possible implementations, multi-metal oxides can generate more defects during deposition. Therefore, the passivation layer material includes multi-metal oxides. In this way, by depositing a passivation layer containing multi-metal oxides on the channel, the oxygen vacancy concentration on the first surface can be greater than the oxygen vacancy concentration in the portion of the channel outside the first and second surfaces. For example, the passivation layer material includes at least one of gallium oxide, magnesium oxide, and titanium dioxide.

[0022] In some possible implementations, the relative positions of the channel, the second electrode, and the passivation layer can include the following:

[0023] In the first case, the channel is located within the cutout portion and does not extend beyond it; the passivation layer is also located within the cutout portion and is disposed on the surface of the channel. The second electrode is disposed on the side of the channel and passivation layer facing away from the substrate.

[0024] In the second scenario, the channel extends from the cutout to the side of the second spacer layer facing away from the substrate; the passivation layer is located in the cutout and is disposed on a portion of the channel surface. The second electrode is disposed on the side of the channel and passivation layer facing away from the substrate.

[0025] In the third scenario, the channel extends from the cutout portion to the side of the second spacer layer facing away from the substrate. The passivation layer further includes a continuous first passivation layer and a second passivation layer. The first passivation layer is disposed in the cutout portion and contacts the portion of the channel located in the cutout portion; the second passivation layer is located outside the cutout portion and contacts the portion of the channel located outside the cutout portion. The second electrode is located on the sidewall of the passivation layer and on the side of the channel facing away from the substrate.

[0026] In the fourth scenario, the channel extends from the cutout portion to the side of the second spacer layer facing away from the substrate. The passivation layer further includes a continuous first passivation layer and a second passivation layer. The first passivation layer is disposed in the cutout portion and contacts the portion of the channel located in the cutout portion; the second passivation layer is located outside the cutout portion and contacts the portion of the channel located outside the cutout portion. The second electrode extends from the side of the channel facing away from the substrate to the side of the second passivation layer facing away from the substrate.

[0027] In the fifth case, the channel is located within the cutout and does not extend beyond it; the passivation layer is located outside the cutout and is situated on the side of the channel facing away from the substrate. The second electrode is located on the sidewall of the passivation layer and is situated on the side of the channel facing away from the substrate.

[0028] In the sixth case, the channel is located within the cutout and does not extend outside the cutout; the passivation layer is located outside the cutout and is disposed on the side of the channel away from the substrate. The second electrode extends from the side of the channel away from the substrate to the side of the passivation layer away from the substrate.

[0029] Compared to the first, fifth, and sixth scenarios, the second through fourth scenarios have a larger contact area between the second electrode and the channel, resulting in lower contact resistance. For the fifth and sixth scenarios, the requirements for preparing the passivation layer are more stringent; the cutout area should be under vacuum during passivation layer formation. However, for the first through fourth scenarios, the requirements for preparing the passivation layer are less stringent; a vacuum is not required for the cutout area during passivation layer formation.

[0030] For cases one through six, the passivation layer can be formed first, followed by the second electrode. Based on the order of forming the passivation layer and the second electrode, compared to the scheme of forming the second electrode first and then the passivation layer, the scheme of forming the passivation layer first and then the second electrode can not only increase the channel carrier concentration, but also improve the transistor's on / off ratio.

[0031] Fourthly, this application provides a method for fabricating a chip, the chip including a transistor. The method for fabricating the transistor includes: sequentially forming a first electrode and a stacked structure on a substrate, the stacked structure including a first spacer layer, a gate, and a second spacer layer stacked together, and a cutout portion formed in the stacked structure. A gate dielectric and a channel are filled in the cutout portion, the gate dielectric being located on the sidewall of the cutout portion, and the channel being at least partially located in the cutout portion. The gate dielectric is used to electrically isolate the channel from the gate, and the channel is in contact with the first electrode. A passivation layer and a second electrode are formed on at least a portion of the surface of the channel, the surface of the channel including a first surface and a second surface, the first surface being in contact with the passivation layer, and the second surface being in contact with the second electrode. The material of the channel includes an oxide semiconductor, and the oxygen vacancy concentration on the first surface is greater than the oxygen vacancy concentration in the portion of the channel other than the first and second surfaces.

[0032] In some possible implementations, the channel extends from the cutout to the side of the second spacer layer facing away from the substrate; a passivation layer and a second electrode are formed on at least a portion of the surface of the channel, including: forming a first film layer and a protective layer on the surface of the channel; etching the first film layer under the protection of the protective layer to obtain a passivation layer; the passivation layer includes a continuous first passivation layer and a second passivation layer, the first passivation layer being disposed in the cutout; the second passivation layer being located outside the cutout and contacting the portion of the channel located outside the cutout. A second electrode is formed, the second electrode being located on the sidewall of the passivation layer and on the side of the channel facing away from the substrate; or, the second electrode extends from the side of the channel facing away from the substrate to the side of the passivation layer facing away from the substrate.

[0033] Fifthly, this application provides a display panel, the display panel including an array substrate, the array substrate including the chip described in the first aspect or the third aspect.

[0034] The fifth aspect and any implementation thereof correspond to the first aspect and any implementation thereof, respectively. The technical effects of the fifth aspect and any implementation thereof are similar to those of the first aspect and any implementation thereof, and will not be repeated here.

[0035] Sixthly, this application provides an electronic device, including the chip described in the first or third aspect, or the display panel described in the fifth aspect.

[0036] The sixth aspect and any implementation thereof correspond to the first aspect and any implementation thereof, respectively. The technical effects of the sixth aspect and any implementation thereof are similar to those of the first aspect and any implementation thereof, and will not be repeated here. Attached Figure Description

[0037] Figure 1a This is a schematic diagram of an electronic device, using a mobile phone as an example.

[0038] Figure 1b This is a schematic diagram of a display structure, using a mobile phone as an example.

[0039] Figure 2 This is a schematic diagram of the structure of the display panel provided in an embodiment of this application;

[0040] Figure 3a This is a schematic diagram of the chip structure provided in an embodiment of this application;

[0041] Figure 3b This is a schematic diagram of the chip structure provided in an embodiment of this application;

[0042] Figure 3c This is a schematic diagram of the chip structure provided in an embodiment of this application;

[0043] Figure 3d This is a schematic diagram of the chip structure provided in an embodiment of this application;

[0044] Figure 4a for Figure 3a Enlarged view of region A in the middle;

[0045] Figure 4b for Figure 3a Enlarged view of region A in the middle;

[0046] Figure 4c A graph showing the change in oxygen vacancy concentration in the channel provided in an embodiment of this application;

[0047] Figure 5 This is a flowchart illustrating the fabrication process of the chip provided in an embodiment of this application.

[0048] Figure 6a This is a diagram illustrating the chip fabrication process provided in an embodiment of this application.

[0049] Figure 6b This is a diagram illustrating the chip fabrication process provided in an embodiment of this application.

[0050] Figure 6c This is a diagram illustrating the chip fabrication process provided in an embodiment of this application.

[0051] Figure 6d This is a diagram illustrating the chip fabrication process provided in an embodiment of this application.

[0052] Figure 6e This is a diagram illustrating the chip fabrication process provided in an embodiment of this application.

[0053] Figure 6f This is a diagram illustrating the chip fabrication process provided in an embodiment of this application.

[0054] Figure 7a This is a schematic diagram of the chip structure provided in an embodiment of this application;

[0055] Figure 7b This is a schematic diagram of the chip structure provided in an embodiment of this application;

[0056] Figure 8a This is a schematic diagram of the chip structure provided in an embodiment of this application;

[0057] Figure 8b This is a schematic diagram of the chip structure provided in an embodiment of this application;

[0058] Figure 9a This is a schematic diagram of the chip structure provided in an embodiment of this application;

[0059] Figure 9b This is a schematic diagram of the chip structure provided in an embodiment of this application;

[0060] Figure 10a for Figure 8a Enlarged view of region B in the middle;

[0061] Figure 10b for Figure 8a Enlarged view of region B in the middle;

[0062] Figure 11 This is a flowchart illustrating the fabrication process of the chip provided in an embodiment of this application.

[0063] Figure 12a This is a diagram illustrating the chip fabrication process provided in an embodiment of this application.

[0064] Figure 12b This is a diagram illustrating the chip fabrication process provided in an embodiment of this application.

[0065] Figure 12c This is a diagram illustrating the chip fabrication process provided in an embodiment of this application.

[0066] Figure 12d This is a diagram illustrating the chip fabrication process provided in an embodiment of this application.

[0067] Figure 12e This is a diagram illustrating the chip fabrication process provided in an embodiment of this application.

[0068] Figure 12f This is a diagram illustrating the chip fabrication process provided in an embodiment of this application.

[0069] Figure 13a This is a diagram illustrating the chip fabrication process provided in an embodiment of this application.

[0070] Figure 13b This is a diagram illustrating the chip fabrication process provided in an embodiment of this application.

[0071] Figure 14a This is a diagram illustrating the chip fabrication process provided in an embodiment of this application.

[0072] Figure 14b This is a diagram illustrating the fabrication process of the chip provided in an embodiment of this application. Detailed Implementation

[0073] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0074] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0075] The terms "first" and "second," etc., used in the specification and claims of this application are used to distinguish different objects, not to describe a specific order of objects. For example, "first target object" and "second target object," etc., are used to distinguish different target objects, not to describe a specific order of target objects.

[0076] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0077] In the description of the embodiments in this application, unless otherwise stated, "multiple" means two or more. For example, multiple processing units means two or more processing units; multiple systems means two or more systems.

[0078] This application provides an electronic device, which may be a device containing transistors, such as a consumer electronics product, a home electronics product, an automotive electronics product, a financial terminal product, or a communication electronics product.

[0079] Consumer electronics include mobile phones, tablet computers, laptops, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, and drones. Home electronics include smart door locks, televisions, smart speakers, refrigerators, and robot vacuum cleaners. In-vehicle electronics include car navigation systems and in-vehicle displays. Financial terminal products include automated teller machines (ATMs) and self-service terminals. Communication electronics include servers, memory, radar, base stations, and other devices containing transistors.

[0080] like Figure 1a As shown, taking a mobile phone as an example, the mobile phone includes a display. In the embodiments of this application, the display can be an OLED display, a quantum dot light emitting diode (QLED) display, a micro-LED display, a sub-millimeter light emitting diode (mini LED) display, a liquid crystal display (LCD), etc.

[0081] In one example, such as Figure 1bAs shown, taking an OLED display as an example, an OLED display may include a frame 1, a cover plate 2, a display panel 3, a circuit board 4, and other electronic components, including a camera. The display panel 3, the circuit board 4, and other electronic components are disposed in a cavity formed by the frame 1 and the cover plate 2. The cover plate 2 is disposed on the light-emitting side of the display panel 3, and the circuit board 4 is disposed on the side of the display panel 3 opposite to the cover plate 2.

[0082] like Figure 2 As shown, the display panel 3 may include an array substrate 31 and an encapsulation layer 32. The array substrate 31 includes a substrate 10 and thin-film transistors (hereinafter referred to as transistors) 311, a planarization layer 313, and a plurality of light-emitting devices 312 stacked on the substrate 10. The transistor 311 includes a channel, a first electrode, a second electrode, a gate dielectric, and a gate. The light-emitting device 312 includes an anode 3121, a light-emitting layer 3122, and a cathode 3123 stacked on the substrate 10. The anode 3121 is electrically connected to the second electrode through a via in the planarization layer 313. By applying a voltage to the anode 3121 and the cathode 3123, holes can be injected from the anode 3121 and electrons can be injected from the cathode 3123, causing electrons and holes to meet in the light-emitting layer 3122 to form excitons, thereby exciting the light-emitting layer 3122 to emit light. At the same time, by adjusting the voltage input to the anode 3121, the display brightness of the OLED display can also be adjusted. The first electrode is the source and the second electrode is the drain; or, the first electrode is the drain and the second electrode is the source.

[0083] In the embodiments of this application, the channel material may include oxide semiconductor materials such as IGZO, indium gallium oxide, and indium zinc oxide. TFTs using oxide semiconductors such as IGZO as channel materials have high field-effect mobility, low subthreshold swing, extremely low leakage current, and low cost, and are widely used in large-area flat panel displays.

[0084] In related technologies, although the field-effect mobility of transistors containing IGZO as the channel material can reach 10 cm⁻¹, 2 The current is around / V·s, but for the application requirements of next-generation display technologies, such as OLED, micro-LED, mini LED, and QLED displays, the driving current needs to be further increased.

[0085] The preceding text, using the transistor in display panel 3 as an example, pointed out that the drive current of transistors in related technologies still needs to be further improved before they can be widely used in more types of displays. Of course, transistors can also be used in other electronic devices or other modules of electronic devices, and this application does not limit this application. Transistors in other electronic devices and other modules of electronic devices may also have the problem of needing further improvement in drive current. For ease of description, the following explanation uses the need for further improvement in the drive current of transistors in display panels as an example.

[0086] Based on this, such as Figures 3a-3c As shown, this application embodiment provides a chip, which includes a substrate 10 and a transistor disposed on the substrate 10. The transistor includes the aforementioned gate 11, gate dielectric 12, channel 13, first electrode 14, and second electrode 15. In addition, the transistor in this application embodiment further includes a passivation layer 16.

[0087] like Figures 3a-3c As shown, a gate 11, a gate dielectric 12, and a channel 13 are sequentially stacked on a substrate 10. The gate dielectric 12 is used to electrically isolate the channel 13 from the gate 11. A first electrode 14, a second electrode 15, and a passivation layer 16 are disposed on at least a portion of the surface of the channel 13, with the passivation layer 16 at least partially located between the first electrode 14 and the second electrode 15. The surface of the channel 13 includes a first surface and a second surface. The first surface contacts the passivation layer 16, and the second surface contacts the first electrode 14 and the second electrode 15. The channel 13 includes sidewalls, an upper surface, and a lower surface. The sidewalls are located at the ends of the channel 13, and the upper and lower surfaces are adjacent to each other. The orthographic projections of the upper and lower surfaces onto the substrate 10 coincide. At the coincident position, the distance from the upper surface to the substrate 10 is always greater than the distance from the lower surface to the substrate 10. In this application, the first electrode 14, the second electrode 15, and the passivation layer 16 are all disposed on the upper surface, which includes both the first and second surfaces.

[0088] The channel 13 is made of an oxide semiconductor, and the oxygen vacancy concentration on the first surface is greater than the oxygen vacancy concentration on the portion of the channel 13 other than the first and second surfaces. Since the first surface is in contact with the passivation layer 16, the oxygen vacancy concentration on the first surface is the same as the oxygen vacancy concentration on the surface of the passivation layer 16 facing the channel 13. The oxygen vacancy concentration on the first surface is equal to the oxygen vacancy concentration on the surface of the passivation layer 16 facing the channel 13, and is also equal to the oxygen vacancy concentration at the interface between the first surface and the passivation layer 16.

[0089] Those skilled in the art will understand that an oxygen vacancy refers to a vacancy formed when an oxygen atom (or oxygen ion) escapes from the crystal lattice of a metal oxide or other oxygen-containing compound, resulting in oxygen loss. Alternatively, it can be described as a defect left by an oxygen atom (or oxygen ion) escaping from its crystal lattice. Based on this, when the material of the channel 13 includes an oxide semiconductor, by providing a defect-rich passivation layer 16 on the first surface of the channel 13, the oxygen vacancy concentration on the first surface is made greater than the oxygen vacancy concentration outside the first and second surfaces of the channel 13, thereby achieving a situation where the defects on the first surface are greater than the defects in the portion of the channel 13 outside the first and second surfaces.

[0090] The first surface has a large number of defects, which can affect the heterojunction at the interface between the first surface and the passivation layer, thereby forming a two-dimensional electron gas at the interface between the first surface and the passivation layer, increasing the carrier concentration in the channel, and thus increasing the driving current of the transistor, thereby improving the brightness, contrast and color saturation of the display, making the transistor widely used in various types of displays.

[0091] Among them, multi-metal oxides can generate more defects during the deposition process. Therefore, the material of the passivation layer 16 can include multi-metal oxides. In this way, by depositing a passivation layer 16 containing multi-metal oxides on the channel 13, the oxygen vacancy concentration on the first surface can be greater than the oxygen vacancy concentration in the portion of the channel 13 other than the first and second surfaces.

[0092] In some possible implementations, the material of the channel 13 includes, but is not limited to, at least one of IGZO, indium gallium oxide, and indium zinc oxide, and the material of the passivation layer 16 includes, but is not limited to, at least one of gallium oxide, magnesium oxide, and titanium dioxide. Wherein, if the material of the passivation layer 16 includes one of gallium oxide, magnesium oxide, and titanium dioxide, then the material of the passivation layer 16 is a binary metal oxide; if the material of the passivation layer 16 includes at least one of gallium oxide, magnesium oxide, and titanium dioxide, then the material of the passivation layer 16 is a more multi-element metal oxide other than a binary metal oxide, such as a ternary metal oxide.

[0093] In this embodiment of the application, the electrical performance of the transistor can be tested to conclude that the driving current of the transistor has been improved.

[0094] Alternatively, the display panel can be disassembled, and the channel layer and passivation layer of the device can be accurately cut out using a focused ion beam. The microstructure of the transistor can be observed and elemental analyzed using an electron microscope to see if the passivation layer 16 contains at least one of the following element groups (the element group includes gallium and oxygen, or magnesium and oxygen, or titanium and oxygen). If it contains at least one element group, it means that the material of the passivation layer 16 includes a multi-metal oxide, and the oxygen vacancy concentration on the first surface is greater than the oxygen vacancy concentration in the portion of the channel 13 other than the first and second surfaces.

[0095] Alternatively, taking the material of channel 13, including but not limited to IGZO, as an example, X-ray photoelectron spectroscopy (XPS) can be performed on the channel 13 of the transistor to observe the binding energy peaks of indium, gallium, zinc, and oxygen. If a significant peak splitting phenomenon is observed in the binding energy peak of indium, it indicates that there are interface defects at the interface between channel 13 and passivation layer 16, and the oxygen vacancy concentration on the first surface is greater than the oxygen vacancy concentration in the part of channel 13 other than the first and second surfaces.

[0096] In some possible implementations, the first electrode 14, the second electrode 15, and the passivation layer 16 are disposed on at least a portion of the surface of the channel 13, meaning that the first electrode 14, the second electrode 15, and the passivation layer 16 completely cover the upper surface of the channel 13, or the first electrode 14, the second electrode 15, and the passivation layer 16 partially cover the upper surface of the channel 13.

[0097] Figure 3a The channel 13 shown has two opposing double-step structures. The passivation layer 16 is located on the second step, and the surfaces of the first electrode 14 and the second electrode 15 facing the substrate 10 are stepped, extending from the first step of the channel 13 to the second step. Furthermore, as... Figure 3d As shown, the first electrode, the second electrode 15, and the passivation layer 16 can all be disposed on the second step.

[0098] In some possible implementations, the passivation layer 16 is at least partially located between the first electrode 14 and the second electrode 15, which can be categorized into the following cases: Figure 3a As shown, the passivation layer 16 fills the space between the first electrode 14 and the second electrode 15, but the passivation layer 16 does not completely fill the area between the first electrode 14 and the second electrode 15; or, as... Figure 3b As shown, the passivation layer 16 fills the space between the first electrode 14 and the second electrode 15, and the passivation layer 16 exactly fills the area between the first electrode 14 and the second electrode 15; or, as... Figure 3c As shown, the passivation layer 16 is filled between the first electrode 14 and the second electrode 15, and in addition to filling the area between the first electrode 14 and the second electrode 15, the passivation layer 16 is also located on the side of the first electrode 14 and the second electrode 15 away from the substrate 10.

[0099] Of course, without departing from the spirit of this application, the passivation layer 16 may also be disposed in other locations. This application embodiment does not limit this, as long as the passivation layer 16 contacts the channel 13 and does not cause the transistor to fail.

[0100] for Figure 3a and Figure 3b The structure shown can be formed by first forming the passivation layer 16, and then forming the first electrode 14 and the second electrode 15; or, the first electrode 14 and the second electrode 15 can be formed first, and then the passivation layer 16 can be formed.

[0101] for Figure 3c The structure shown first forms a first electrode 14 and a second electrode 15, and then forms a passivation layer 16.

[0102] Based on the order in which the passivation layer 16 is formed, and the first electrode 14 and the second electrode 15 are formed, compared to Figure 3c The structure shown, Figure 3a and Figure 3b The structure shown not only increases the carrier concentration in channel 13, but also improves the on / off ratio of the transistor.

[0103] refer to Figure 3a and Figure 3b In the case where a passivation layer 16 is formed first, followed by the formation of the first electrode 14 and the second electrode 15, a first film layer can be formed first on the channel 13, completely covering the surface of the channel 13. Next, the first film layer is etched to obtain the passivation layer 16. Since the material of the first film layer (passivation layer 16) includes a multi-metal oxide, a large number of defects can be generated during the deposition of the multi-metal oxide. Therefore, if... Figure 4b As shown, as long as a first film layer has been formed on the first and second surfaces of the channel 13, the first and second surfaces of the channel 13 will have defects. Even if the first film layer is etched on the second surface, the second surface of the channel 13 will still have defects, and the oxygen vacancy concentration on the second surface will be greater than the oxygen vacancy concentration in the portion of the channel 13 other than the first and second surfaces.

[0104] Furthermore, because the second surface of the channel 13 has defects, the first electrode 14 and the second electrode 15 disposed on the second surface form a Schottky contact with the channel 13, thereby improving the switching characteristics of the transistor and avoiding the problem that the off-state current of the transistor increases due to excessively high carrier concentration, which leads to a decrease in the switching characteristics of the transistor.

[0105] The fact that "the upper surface of channel 13 is defective" can also be verified through electrical performance testing, elemental analysis, XPS testing, and other methods.

[0106] Furthermore, because a first film layer has been formed on the first and second surfaces (or the first surface) of the channel 13, oxygen vacancy concentration may also exist in the portion of the channel 13 located outside the first and second surfaces. Moreover, the oxygen vacancy concentration in the channel 13 gradually decreases along the first direction from the passivation layer 16 towards the channel 13. It should be understood that, as... Figure 4c As shown, along the first direction, the oxygen vacancy concentration in channel 13 gradually decreases. Figure 4c The darker the black color, the greater the oxygen vacancy concentration. However, the oxygen vacancy concentrations of the first and second surfaces (or the first surface) are still greater than the oxygen vacancy concentrations of the parts outside the first and second surfaces in channel 13.

[0107] In the case where a first film layer has been formed on both the first and second surfaces, the embodiments of this application do not limit the relationship between the oxygen vacancy concentration on the first surface and the oxygen vacancy concentration on the second surface. The oxygen vacancy concentration on the first surface may be greater than that on the second surface, or the oxygen vacancy concentration on the first surface may be equal to that on the second surface, or the oxygen vacancy concentration on the first surface may be less than that on the second surface.

[0108] In another embodiment, this application also provides a method for fabricating a chip, such as... Figures 3a-3b As shown, the chip includes transistors. Figure 5 As shown, the transistor fabrication process can be achieved through the following steps:

[0109] S110, such as Figure 6a and Figure 6b As shown, a gate 11, a gate dielectric 12, and a channel 13 are sequentially formed on a substrate 10. The gate dielectric 12 is disposed between the gate 11 and the channel 13, and the gate dielectric 12 completely covers the sidewall of the gate 11, so as to electrically isolate the gate 11 and the channel 13 by means of the gate dielectric 13.

[0110] S120, such as Figures 3a-3c As shown, a first electrode 14, a second electrode 15, and a passivation layer 16 are formed on at least a portion of the surface of the channel 13, with the passivation layer 16 at least partially located between the first electrode 14 and the second electrode 15. The surface of the channel 13 includes a first surface and a second surface, with the first surface in contact with the passivation layer 16 and the second surface in contact with the first electrode 14 and the second electrode 15. The material of the channel 13 includes an oxide semiconductor, and the oxygen vacancy concentration on the first surface is greater than the oxygen vacancy concentration in the portion of the channel 13 other than the first and second surfaces.

[0111] Those skilled in the art will understand that an oxygen vacancy refers to a vacancy formed when an oxygen atom (or oxygen ion) escapes from the crystal lattice of a metal oxide or other oxygen-containing compound, resulting in oxygen loss. Alternatively, it can be described as a defect left by an oxygen atom (or oxygen ion) escaping from its crystal lattice. Based on this, when the material of the channel 13 includes an oxide semiconductor, by providing a defect-rich passivation layer 16 on the first surface of the channel 13, the oxygen vacancy concentration on the first surface is made greater than the oxygen vacancy concentration outside the first and second surfaces of the channel 13, thereby achieving a situation where the defects on the first surface are greater than the defects in the portion of the channel 13 outside the first and second surfaces.

[0112] The first surface has a large number of defects, which can affect the heterojunction at the interface between the first surface and the passivation layer, thereby forming a two-dimensional electron gas at the interface between the first surface and the passivation layer, increasing the carrier concentration in the channel, and thus increasing the driving current of the transistor, thereby improving the brightness, contrast and color saturation of the display, making the transistor widely used in various types of displays.

[0113] Among them, multi-metal oxides can generate more defects during the deposition process. Therefore, the material of the passivation layer 16 can include multi-metal oxides. In this way, by depositing a passivation layer 16 containing multi-metal oxides on the channel 13, the oxygen vacancy concentration on the first surface can be greater than the oxygen vacancy concentration in the portion of the channel 13 other than the first and second surfaces.

[0114] In some possible implementations, the material of the channel 13 includes, but is not limited to, at least one of IGZO, indium gallium oxide, and indium zinc oxide, and the material of the passivation layer 16 includes, but is not limited to, at least one of gallium oxide, magnesium oxide, and titanium dioxide. Wherein, if the material of the passivation layer 16 includes one of gallium oxide, magnesium oxide, and titanium dioxide, then the material of the passivation layer 16 is a binary metal oxide; if the material of the passivation layer 16 includes at least one of gallium oxide, magnesium oxide, and titanium dioxide, then the material of the passivation layer 16 is a more multi-element metal oxide other than a binary metal oxide, such as a ternary metal oxide.

[0115] In some possible implementations, the first electrode 14, the second electrode 15, and the passivation layer 16 are disposed on at least a portion of the surface of the channel 13, meaning that the first electrode 14, the second electrode 15, and the passivation layer 16 completely cover the upper surface of the channel 13, or the first electrode 14, the second electrode 15, and the passivation layer 16 partially cover the upper surface of the channel 13.

[0116] Figure 3a The channel 13 shown has two opposing double-step structures. The passivation layer 16 is located on the second step, and the surfaces of the first electrode 14 and the second electrode 15 facing the substrate 10 are stepped, extending from the first step of the channel 13 to the second step. Furthermore, as... Figure 3d As shown, the first electrode, the second electrode 15, and the passivation layer 16 can all be disposed on the second step.

[0117] In some possible implementations, the first electrode 14, the second electrode 15, and the passivation layer 16 can be formed in the following two ways:

[0118] The first method, such as Figure 6c As shown, a first film layer 161 is first formed on the channel 13, completely covering the surface of the channel 13. Then, as... Figure 6dAs shown, the first film layer 161 is etched to obtain the passivation layer 16. Next, as... Figure 3a and Figure 3b As shown, a first electrode 14 and a second electrode 15 are formed on opposite sides of the passivation layer 16. The passivation layer 16 formed in the first manner is located between the first electrode 13 and the second electrode 15, and the passivation layer 16 may not completely fill the area between the first electrode 14 and the second electrode 15, or the passivation layer 16 may just fill the area between the first electrode 14 and the second electrode 15.

[0119] The second method, such as Figure 6e As shown, a second film layer 141 is first formed on the channel 13, completely covering the surface of the channel 13. Then, as... Figure 6f As shown, the second film layer 141 is etched to obtain the first electrode 14 and the second electrode 15. Next, as... Figures 3a-3c As shown, a passivation layer 16 is formed on the first surface of the channel 13. Figure 3a and Figure 3b As shown, the passivation layer 16 can be located between the first electrode 14 and the second electrode 15; or, as... Figure 3c As shown, the passivation layer 16 is located not only between the first electrode 14 and the second electrode 15, but also on the side of the first electrode 14 and the second electrode 15 that is away from the substrate 10.

[0120] Compared to the second method, the first film layer 161 formed using the first method can completely cover the first and second surfaces of the channel 13. Since the material of the first film layer (passivation layer 16) includes multi-metal oxides, a large number of defects can be generated during the deposition of multi-metal oxides. Therefore, as... Figure 4b As shown, as long as a first film layer has been formed on the first and second surfaces of the channel 13, the first and second surfaces of the channel 13 will have defects. Even if the first film layer on the second surface is etched, the second surface of the channel 13 will still have defects, and the oxygen vacancy concentration on the second surface will be greater than the oxygen vacancy concentration in the portion of the channel 13 other than the first and second surfaces.

[0121] Furthermore, because a first film layer has been formed on the first and second surfaces (or the first surface) of the channel 13, oxygen vacancy concentration may also exist in the portion of the channel 13 located outside the first and second surfaces. Moreover, the oxygen vacancy concentration in the channel 13 gradually decreases along the first direction from the passivation layer 16 towards the channel 13. It should be understood that, as... Figure 4c As shown, along the first direction, the oxygen vacancy concentration of the channel 13 gradually decreases, but still satisfies that the oxygen vacancy concentration of the first surface and the second surface (or the first surface) is greater than the oxygen vacancy concentration of the portion of the channel 13 outside the first surface and the second surface.

[0122] In the case where a first film layer has been formed on both the first and second surfaces, the embodiments of this application do not limit the relationship between the oxygen vacancy concentration on the first surface and the oxygen vacancy concentration on the second surface. The oxygen vacancy concentration on the first surface may be greater than that on the second surface, or the oxygen vacancy concentration on the first surface may be equal to that on the second surface, or the oxygen vacancy concentration on the first surface may be less than that on the second surface.

[0123] In yet another embodiment, this application also provides another type of chip, such as... Figures 7a-9b As shown, the chip includes a substrate 10 and transistors disposed on the substrate 10. Each transistor includes a first electrode 14 and a stacked structure having a cutout portion. Along the direction from the substrate 10 to the first electrode 14, the stacked structure includes a first spacer layer 17, a gate 11, and a second spacer layer 18 stacked together. The first spacer layer 17 is located between the first electrode 14 and the gate 11, enabling electrical isolation between the first electrode 14 and the gate 11.

[0124] The transistor also includes a gate dielectric 12 and a channel 13. The gate dielectric 12 is located on the sidewall of the cutout portion, and the channel 13 is at least partially located in the cutout portion. The channel 13 is disposed on the side of the gate dielectric 12 opposite to the gate 11, and the gate dielectric 12 is used to electrically isolate the gate 11 from the channel 13. Furthermore, a portion of the channel 13 facing the substrate 10 is in contact with the first electrode 14.

[0125] Since the channel 13 in the cutout is in contact with the first electrode 14, and the first electrode 14 is disposed between the stacked structure and the substrate 10, the cutout should penetrate the first spacer layer 17, the gate 11, and the second spacer layer 18 to expose the surface of the first electrode 14 facing the channel 13.

[0126] The transistor also includes a second electrode 15 and a passivation layer 16, which are disposed on at least a portion of the surface of the channel 13. A second spacer layer 18 covers the surface of the gate 11 facing the second electrode 15, thereby preventing the gate 11 from being electrically connected to the second electrode 15.

[0127] The surface of the channel 13 includes a first surface and a second surface. The first surface contacts the passivation layer 16, and the second surface contacts the second electrode 15. The channel 13 includes sidewalls, an upper surface, and a lower surface. The sidewalls are located at the ends of the channel 13, and the upper and lower surfaces are adjacent to each other. Assuming that the orthographic projections of the upper and lower surfaces onto the substrate 10 correspond one-to-one, then at the one-to-one corresponding positions, the distance from the upper surface to the substrate 10 is always greater than the distance from the lower surface to the substrate 10. In this application, the first electrode 14, the second electrode 15, and the passivation layer 16 are all disposed on the upper surface, which includes the first surface and the second surface.

[0128] The channel 13 is made of an oxide semiconductor, and the oxygen vacancy concentration on the first surface is greater than the oxygen vacancy concentration on the portion of the channel 13 other than the first and second surfaces. Since the first surface is in contact with the passivation layer 16, the oxygen vacancy concentration on the first surface is the same as the oxygen vacancy concentration on the surface of the passivation layer 16 facing the channel 13. The oxygen vacancy concentration on the first surface is equal to the oxygen vacancy concentration on the surface of the passivation layer 16 facing the channel 13, and is also equal to the oxygen vacancy concentration at the interface between the first surface and the passivation layer 16.

[0129] Those skilled in the art will understand that an oxygen vacancy refers to a vacancy formed when an oxygen atom (or oxygen ion) escapes from the crystal lattice of a metal oxide or other oxygen-containing compound, resulting in oxygen loss. Alternatively, it can be described as a defect left by an oxygen atom (or oxygen ion) escaping from its crystal lattice. Based on this, when the material of the channel 13 includes an oxide semiconductor, by providing a defect-rich passivation layer 16 on the first surface of the channel 13, the oxygen vacancy concentration on the first surface is made greater than the oxygen vacancy concentration outside the first and second surfaces of the channel 13, thereby achieving a situation where the defects on the first surface are greater than the defects in the portion of the channel 13 outside the first and second surfaces.

[0130] The first surface has a large number of defects, which can affect the heterojunction at the interface between the first surface and the passivation layer, thereby forming a two-dimensional electron gas at the interface between the first surface and the passivation layer, increasing the carrier concentration in the channel, and thus increasing the driving current of the transistor, thereby improving the brightness, contrast and color saturation of the display, making the transistor widely used in various types of displays.

[0131] Among them, multi-metal oxides can generate more defects. Therefore, the material of the passivation layer 16 includes multi-metal oxides. In this way, by depositing the passivation layer 16 containing multi-metal oxides on the channel 13, the oxygen vacancy concentration on the first surface can be greater than the oxygen vacancy concentration in the portion of the channel 13 other than the first and second surfaces.

[0132] In some possible implementations, the material of the channel 13 includes, but is not limited to, at least one of IGZO, indium gallium oxide, and indium zinc oxide, and the material of the passivation layer 16 includes, but is not limited to, at least one of gallium oxide, magnesium oxide, and titanium dioxide. Wherein, if the material of the passivation layer 16 includes one of gallium oxide, magnesium oxide, and titanium dioxide, then the material of the passivation layer 16 is a binary metal oxide; if the material of the passivation layer 16 includes at least one of gallium oxide, magnesium oxide, and titanium dioxide, then the material of the passivation layer 16 is a more multi-element metal oxide other than a binary metal oxide, such as a ternary metal oxide.

[0133] In this embodiment of the application, the electrical performance of the transistor can be tested to conclude that the driving current of the transistor has been improved.

[0134] Alternatively, the display panel can be disassembled, and the channel layer and passivation layer of the device can be accurately cut out using a focused ion beam. The microstructure of the transistor can be observed and elemental analyzed using an electron microscope to see if the passivation layer 16 contains at least one of the following element groups (the element group includes gallium and oxygen, or magnesium and oxygen, or titanium and oxygen). If it contains at least one element group, it means that the material of the passivation layer 16 includes a multi-metal oxide, and the oxygen vacancy concentration on the first surface is greater than the oxygen vacancy concentration in the portion of the channel 13 other than the first and second surfaces.

[0135] Alternatively, taking the material of the channel 13, including but not limited to IGZO, as an example, the channel 13 of the transistor can be subjected to photoelectron spectroscopy to observe the binding energy peaks of indium, gallium, zinc and oxygen elements. If the binding energy peak of indium element shows obvious peak splitting, it indicates that there is an interface defect at the interface between the channel 13 and the passivation layer 16, and the oxygen vacancy concentration on the first surface is greater than the oxygen vacancy concentration in the part of the channel 13 other than the first and second surfaces.

[0136] In some possible implementations, the second electrode 15 and the passivation layer 16 are disposed on at least a portion of the surface of the channel 13, meaning that the second electrode 15 and the passivation layer 16 completely cover the upper surface of the channel 13, or the second electrode 15 and the passivation layer 16 partially cover the upper surface of the channel 13.

[0137] In some possible implementations, the channel 13 is at least partially located within the hollow portion. This means that the channel 13 is entirely located within the hollow portion, or a portion of the channel 13 is located within the hollow portion and another portion is located outside the hollow portion. The location and structure of the passivation layer 16 vary depending on the location and structure of the channel 13. For example, the passivation layer 16 may be located within the hollow portion, or, in addition to being located within the hollow portion, it may also be located outside the hollow portion. Correspondingly, the location of the second electrode 15 is also related to the location of the passivation layer 16. Specifically, the following cases will be discussed:

[0138] The first case, such as Figure 7a As shown, the channel 13 is disposed in the cutout portion and does not extend from the cutout portion to the outside of the cutout portion; the passivation layer 16 is also located in the cutout portion and is disposed on the first surface of the channel 13. The second electrode 15 is disposed on the side of the channel 13 and the passivation layer 16 away from the substrate 10.

[0139] The second scenario, such as Figure 7b As shown, the channel 13 extends from the cutout to the side of the second spacer layer 18 facing away from the substrate 10; the passivation layer 16 is located in the cutout and is disposed on the first surface of the channel 13. The second electrode 15 is disposed on the side of the channel 13 and the passivation layer 16 facing away from the substrate 10.

[0140] The third scenario, such as Figure 8a As shown, the channel 13 extends from the cutout portion to the side of the second spacer layer 18 facing away from the substrate 10. The passivation layer 16 further includes a continuous first passivation layer 161 and a second passivation layer 162. The first passivation layer 161 is disposed in the cutout portion and contacts the portion of the channel 13 located in the cutout portion; the second passivation layer 162 is located outside the cutout portion and contacts the portion of the channel 13 located outside the cutout portion. The second electrode 15 is located on the sidewall of the passivation layer 16 and on the side of the channel 13 facing away from the substrate 10.

[0141] The fourth case, such as Figure 8b As shown, the channel 13 extends from the cutout portion to the side of the second spacer layer 18 opposite to the substrate 10. The passivation layer 16 further includes a continuous first passivation layer 161 and a second passivation layer 162. The first passivation layer 161 is disposed in the cutout portion and contacts the portion of the channel 13 located in the cutout portion; the second passivation layer 162 is located outside the cutout portion and contacts the portion of the channel 13 located outside the cutout portion. The second electrode 15 extends from the side of the channel 13 opposite to the substrate 10 to the side of the second passivation layer 16 opposite to the substrate 10.

[0142] The fifth situation, such as Figure 9a As shown, the channel 13 is located in the cutout portion and does not extend outside the cutout portion; the passivation layer 16 is located outside the cutout and is disposed on the side of the channel 13 away from the substrate 10. The second electrode 15 is located on the sidewall of the passivation layer 16 and is located on the side of the channel 13 away from the substrate 10.

[0143] The sixth case, such as Figure 9b As shown, the channel 13 is located in the cutout portion and does not extend outside the cutout portion; the passivation layer 16 is located outside the cutout and is disposed on the side of the channel 13 away from the substrate 10. The second electrode 15 extends from the side of the channel 13 away from the substrate 10 to the side of the passivation layer 16 away from the substrate 10.

[0144] Compared to the first, fifth, and sixth scenarios, the second through fourth scenarios have a larger contact area and lower contact resistance between the second electrode 15 and the channel 13. For the fifth and sixth scenarios, the requirements for preparing the passivation layer 16 are higher; the cutout area should be under vacuum during the formation of the passivation layer 16. However, for the first through fourth scenarios, the requirements for preparing the passivation layer 16 are lower; the cutout area does not need to be under vacuum during the formation of the passivation layer 16.

[0145] like Figures 7a-9b As shown, for cases one through six, a passivation layer 16 can be formed first, followed by the formation of the second electrode 15.

[0146] like Figure 9aAs shown, for the fifth case, a second electrode 15 can be formed first, followed by a passivation layer 16.

[0147] Based on the order in which the passivation layer 16 and the second electrode 15 are formed, compared to the scheme of forming the second electrode 15 first and then the passivation layer 16, the scheme of forming the passivation layer 16 first and then the second electrode 15 can not only increase the carrier concentration of the channel 13, but also improve the switching ratio of the transistor.

[0148] Specifically, in the case where the passivation layer 16 is formed first, followed by the second electrode 15, a first film layer 161 can be formed on the channel 13, completely covering the surface of the channel 13. Next, the first film layer 161 is etched to obtain the passivation layer 16. Since the material of the first film layer 161 includes a multi-metal oxide, a large number of defects can be generated during the deposition of the multi-metal oxide. Therefore, if... Figure 10b As shown, as long as the first film layer 161 has been formed on the first and second surfaces of the channel 13, the first and second surfaces of the channel 13 will have defects. Even if the first film layer 161 on the second surface is etched, the second surface of the channel 13 will still have defects, and the oxygen vacancy concentration on the second surface will be greater than the oxygen vacancy concentration in the portion of the channel 13 other than the first and second surfaces.

[0149] Furthermore, because the second surface of the channel 13 has defects, the second electrode 15 disposed on the second surface forms a Schottky contact with the channel 13, thereby improving the switching characteristics of the transistor and avoiding the problem that the off-state current of the transistor increases due to excessively high carrier concentration, which leads to a decrease in the switching characteristics of the transistor.

[0150] The fact that "the upper surface of channel 13 is defective" can also be verified through electrical performance testing, elemental analysis, XPS testing, and other methods.

[0151] Furthermore, because a first film layer has been formed on the first and second surfaces (or the first surface) of the channel 13, oxygen vacancy concentrations may also exist in the portion of the channel 13 located outside the first and second surfaces. Moreover, the oxygen vacancy concentration in the channel 13 gradually decreases along the first direction from the passivation layer 16 towards the channel 13. It should be understood that while the oxygen vacancy concentration in the channel 13 gradually decreases along the first direction, it still satisfies the condition that the oxygen vacancy concentrations on the first and second surfaces (or the first surface) are greater than the oxygen vacancy concentrations in the portion of the channel 13 located outside the first and second surfaces.

[0152] In the case where a first film layer has been formed on both the first and second surfaces, the embodiments of this application do not limit the relationship between the oxygen vacancy concentration on the first surface and the oxygen vacancy concentration on the second surface. The oxygen vacancy concentration on the first surface may be greater than that on the second surface, or the oxygen vacancy concentration on the first surface may be equal to that on the second surface, or the oxygen vacancy concentration on the first surface may be less than that on the second surface.

[0153] In another embodiment, this application also provides a method for fabricating a chip, such as... Figures 7a-9b As shown, the chip includes transistors. Figure 11 As shown, the transistor fabrication process can be achieved through the following steps:

[0154] S210, such as Figures 12a-12d As shown, a first electrode 14 and a stacked structure are sequentially formed on the substrate 10. The stacked structure includes a first spacer layer 17, a gate 11, and a second spacer layer 18 stacked together, and a cutout portion is provided in the stacked structure. The first spacer layer 17 is located between the first electrode 14 and the gate 11, which enables the first electrode 14 and the gate 11 to be electrically isolated.

[0155] Specifically, such as Figure 12a As shown, a first electrode 14 and a third film layer 171 are sequentially formed on the substrate 10. Next, as... Figure 12b As shown, a fourth film layer 111 is formed on the side of the third film layer 171 facing away from the substrate 10. Figure 12c As shown, a fifth film layer 181 is formed on the side of the fourth film layer 111 facing away from the substrate 10. Next, as... Figure 12d As shown, the fifth film layer 181, the fourth film layer 111, and the third film layer 171 are partially removed to obtain a stacked structure with a cutout. The stacked structure includes a first spacer layer 17, a gate 11, and a second spacer layer 18 stacked sequentially. That is, the second spacer layer 18 is obtained after the fifth film layer 181 is partially removed, the gate 11 is obtained after the fourth film layer 111 is partially removed, and the first spacer layer 17 is obtained after the third film layer is partially removed.

[0156] S220, such as Figure 12e and Figure 12f As shown, the gate dielectric 12 is filled in the hollow part. The gate dielectric is located on the side wall of the hollow part. The gate dielectric 12 is used to electrically isolate the gate 11 from the channel 13 to be formed.

[0157] Specifically, such as Figure 12e As shown, a sixth film layer 121 is formed on the side of the first electrode 14 facing away from the substrate 10, on the sidewall of the hollow portion, and on the side of the second spacer layer 18 facing away from the substrate 10; then, as... Figure 12f As shown, the sixth film layer 121 is partially removed to obtain the gate dielectric 12 located on the side wall of the hollowed-out portion.

[0158] S230, such as Figure 13a and Figure 13b As shown, a channel 13 is formed, and the channel 13 is at least partially located in the hollow portion, and the channel 13 is in contact with the first pole 14.

[0159] Since the channel 13 in the cutout is in contact with the first electrode 14, and the first electrode 14 is disposed between the stacked structure and the substrate 10, the cutout should penetrate the first spacer layer 17, the gate 11, and the second spacer layer 18 to expose the surface of the first electrode 14 facing the channel 13.

[0160] In some possible ways of implementation, such as Figure 13a As shown, the channel 13 is located within the openwork section and does not extend beyond the openwork section. Alternatively, as... Figure 13b As shown, the channel 13 extends from the cutout to the side of the second spacer layer 18 opposite to the substrate 10.

[0161] S240, such as Figures 7a-9b As shown, a passivation layer 16 and a second electrode 15 are formed on at least a portion of the surface of the channel 13. A second spacer layer 18 covers the surface of the gate 11 facing the second electrode 15, preventing electrical connection between the gate 11 and the second electrode 15. The surface of the channel 13 includes a first surface and a second surface, the first surface contacting the passivation layer 16 and the second surface contacting the second electrode 15. The material of the channel 13 includes an oxide semiconductor, and the oxygen vacancy concentration on the first surface is greater than the oxygen vacancy concentration in the portion of the channel 13 other than the first and second surfaces.

[0162] Those skilled in the art will understand that an oxygen vacancy refers to a vacancy formed when an oxygen atom (or oxygen ion) escapes from the crystal lattice of a metal oxide or other oxygen-containing compound, resulting in oxygen loss. Alternatively, it can be described as a defect left by an oxygen atom (or oxygen ion) escaping from its crystal lattice. Based on this, when the material of the channel 13 includes an oxide semiconductor, by providing a defect-rich passivation layer 16 on the first surface of the channel 13, the oxygen vacancy concentration on the first surface is made greater than the oxygen vacancy concentration outside the first and second surfaces of the channel 13, thereby achieving a situation where the defects on the first surface are greater than the defects in the portion of the channel 13 outside the first and second surfaces.

[0163] The first surface has a large number of defects, which can affect the heterojunction at the interface between the first surface and the passivation layer, thereby forming a two-dimensional electron gas at the interface between the first surface and the passivation layer, increasing the carrier concentration in the channel, and thus increasing the driving current of the transistor, thereby improving the brightness, contrast and color saturation of the display, making the transistor widely used in various types of displays.

[0164] Among them, multi-metal oxides can generate more defects during the deposition process. Therefore, the material of the passivation layer 16 can include multi-metal oxides. In this way, by depositing a passivation layer 16 containing multi-metal oxides on the channel 13, the oxygen vacancy concentration on the first surface can be greater than the oxygen vacancy concentration in the portion of the channel 13 other than the first and second surfaces.

[0165] In some possible implementations, the material of the channel 13 includes, but is not limited to, at least one of IGZO, indium gallium oxide, and indium zinc oxide, and the material of the passivation layer 16 includes, but is not limited to, at least one of gallium oxide, magnesium oxide, and titanium dioxide. Wherein, if the material of the passivation layer 16 includes one of gallium oxide, magnesium oxide, and titanium dioxide, then the material of the passivation layer 16 is a binary metal oxide; if the material of the passivation layer 16 includes at least one of gallium oxide, magnesium oxide, and titanium dioxide, then the material of the passivation layer 16 is a more multi-element metal oxide other than a binary metal oxide, such as a ternary metal oxide.

[0166] In some possible implementations, the second electrode 15 and the passivation layer 16 are disposed on at least a portion of the surface of the channel 13, meaning that the second electrode 15 and the passivation layer 16 completely cover the upper surface of the channel 13, or the second electrode 15 and the passivation layer 16 partially cover the upper surface of the channel 13.

[0167] In some possible implementations, the channel 13 is at least partially located within the hollow portion. This means that the channel 13 is entirely located within the hollow portion, or a portion of the channel 13 is located within the hollow portion and another portion is located outside the hollow portion. The location and structure of the passivation layer 16 vary depending on the location and structure of the channel 13. For example, the passivation layer 16 may be located within the hollow portion, or, in addition to being located within the hollow portion, it may also be located outside the hollow portion. Correspondingly, the location of the second electrode 15 is also related to the location of the passivation layer 16. Specifically, the following cases will be discussed:

[0168] The first case, such as Figure 7a As shown, the channel 13 formed in step S230 is disposed in the cutout portion and does not extend from the cutout portion to the outside of the cutout portion. Next, a passivation layer 16 is formed in the cutout portion, and the passivation layer 16 is disposed on the first surface of the channel 13. Next, a second electrode 15 is formed on the second surface of the channel 13 and on the side of the passivation layer 16 facing away from the substrate 10.

[0169] The second scenario, such as Figure 7bAs shown, the channel 13 formed in step S230 extends from the cutout to the side of the second spacer layer 18 facing away from the substrate 10. Next, a passivation layer 16 is formed in the cutout and disposed on the first surface of the channel 13. Then, a second electrode 15 is formed on the second surface of the channel 13 and the side of the passivation layer 16 facing away from the substrate 10.

[0170] The third scenario, such as Figure 8a As shown, the channel 13 formed in step S230 extends from the cutout to the side of the second spacer layer 18 facing away from the substrate 10. Next, as... Figure 14a As shown, a first film layer 161 is formed on the first and second surfaces of the channel 13, and then, as... Figure 14b As shown, a protective layer 20 is formed on the surface of the first film layer 161. Under the protection of the protective layer 20, the first film layer 161 is partially removed to form a passivation layer 16. The passivation layer 16 includes a continuous first passivation layer 161 and a second passivation layer 162. The first passivation layer 161 is disposed in the cutout portion and contacts the portion of the channel 13 located in the cutout portion. The second passivation layer 162 is located outside the cutout portion and contacts the portion of the channel 13 located outside the cutout portion. Next, a second electrode 15 is formed. The second electrode 15 is located on the sidewall of the passivation layer 16 and on the side of the channel 13 opposite to the substrate 10.

[0171] The fourth case, such as Figure 8b As shown, the channel 13 formed in step S230 extends from the cutout to the side of the second spacer layer 18 facing away from the substrate 10. Next, as... Figure 14a As shown, a first film layer 161 is formed on the first and second surfaces of the channel 13, and then, as... Figure 14b As shown, a protective layer 20 is formed on the surface of the first film layer 161. Under the protection of the protective layer 20, the first film layer 161 is partially removed to form a passivation layer 16. The passivation layer 16 includes a continuous first passivation layer 161 and a second passivation layer 162. The first passivation layer 161 is disposed in the hollow portion and contacts the portion of the channel 13 located in the hollow portion. The second passivation layer 162 is located outside the hollow portion and contacts the portion of the channel 13 located outside the hollow portion. Next, a second electrode 15 is formed, extending from the side of the channel 13 away from the substrate 10 to the side of the second passivation layer 16 away from the substrate 10.

[0172] The fifth situation, such as Figure 9a As shown, the channel 13 formed in step S230 is located in the cutout portion and does not extend outside the cutout portion. Next, a passivation layer 16 is formed, which is located outside the cutout and is disposed on the side of the channel 13 away from the substrate 10. Next, a second electrode 15 is formed, which is located on the sidewall of the passivation layer 16 and is located on the side of the channel 13 away from the substrate 10.

[0173] The sixth case, such as Figure 9b As shown, the channel 13 formed in step S230 is located in the cutout portion and does not extend outside the cutout portion. Next, a passivation layer 16 is formed, which is located outside the cutout and is disposed on the side of the channel 13 away from the substrate 10. Next, a second electrode 15 is formed, which extends from the side of the channel 13 away from the substrate 10 to the side of the passivation layer 16 away from the substrate 10.

[0174] Compared to the first, fifth, and sixth scenarios, the second through fourth scenarios have a larger contact area and lower contact resistance between the second electrode 15 and the channel 13. For the fifth and sixth scenarios, the requirements for preparing the passivation layer 16 are higher; the cutout area should be under vacuum during the formation of the passivation layer 16. However, for the first through fourth scenarios, the requirements for preparing the passivation layer 16 are lower; the cutout area does not need to be under vacuum during the formation of the passivation layer 16.

[0175] Compared to the approach of forming the second electrode 15 first and then the passivation layer 16, all six cases described above involve forming the passivation layer 16 first and then the second electrode 15. In this way, the first film layer 161 used to form the passivation layer 16 can completely cover the upper surface of the channel 13. Since the material of the first film layer 161 includes multi-metal oxides, a large number of defects can be generated during the deposition of multi-metal oxides. Therefore, as... Figure 10b As shown, both the first and second surfaces of the channel 13 have defects, and the oxygen vacancy concentrations on both surfaces are greater than those on the portions of the channel 13 outside the first and second surfaces. Furthermore, the second electrode 15 disposed on the channel 13 forms a Schottky contact with the channel 13, thereby improving the switching characteristics of the transistor and preventing an increase in the off-state current due to excessively high carrier concentration, which would otherwise degrade the switching characteristics of the transistor.

[0176] Furthermore, because a first film layer has been formed on the first and second surfaces (or the first surface) of the channel 13, oxygen vacancy concentrations may also exist in the portion of the channel outside the first and second surfaces. Moreover, the oxygen vacancy concentration in the channel 13 gradually decreases along the first direction from the passivation layer 16 towards the channel 13. It should be understood that while the oxygen vacancy concentration in the channel 13 gradually decreases along the first direction, it still satisfies the condition that the oxygen vacancy concentrations on the first and second surfaces (or the first surface) are greater than the oxygen vacancy concentrations in the portion of the channel 13 outside the first and second surfaces.

[0177] In the case where a first film layer has been formed on both the first and second surfaces, the embodiments of this application do not limit the relationship between the oxygen vacancy concentration on the first surface and the oxygen vacancy concentration on the second surface. The oxygen vacancy concentration on the first surface may be greater than that on the second surface, or the oxygen vacancy concentration on the first surface may be equal to that on the second surface, or the oxygen vacancy concentration on the first surface may be less than that on the second surface.

[0178] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A chip, characterized in that, Includes a substrate and a transistor disposed on the substrate, the transistor comprising: A gate, a gate dielectric, and a channel are stacked on the substrate, wherein the gate, the gate dielectric, and the channel are used to electrically isolate the channel from the gate; A first electrode, a second electrode, and a passivation layer are disposed on at least a portion of the surface of the channel, with at least a portion of the passivation layer located between the first electrode and the second electrode. The surface of the channel includes a first surface and a second surface, with the first surface in contact with the passivation layer and the second surface in contact with the first electrode and the second electrode. The material of the channel includes an oxide semiconductor, and the oxygen vacancy concentration of the first surface is greater than the oxygen vacancy concentration of the portion of the channel other than the first surface and the second surface.

2. The chip according to claim 1, characterized in that, The oxygen vacancy concentration on the second surface is also greater than the oxygen vacancy concentration in the portion of the channel other than the first and second surfaces.

3. The chip according to claim 1, characterized in that, The passivation layer is also located on the side of the first electrode and the second electrode opposite to the substrate.

4. The chip according to any one of claims 1-3, characterized in that, The passivation layer is made of a multi-metal oxide.

5. The chip according to claim 4, characterized in that, The passivation layer is made of at least one of gallium oxide, magnesium oxide, and titanium dioxide.

6. A method for fabricating a chip, characterized in that, The chip includes transistors, and the method for fabricating the transistors includes: A gate, a gate dielectric, and a channel are sequentially formed on a substrate; the gate, the gate dielectric, and the channel are stacked, and the gate dielectric is used to electrically isolate the channel from the gate; A first electrode, a second electrode, and a passivation layer are formed on at least a portion of the surface of the channel; the passivation layer is at least partially located between the first electrode and the second electrode; the surface of the channel includes a first surface and a second surface, the first surface being in contact with the passivation layer, and the second surface being in contact with the first electrode and the second electrode; wherein the material of the channel includes an oxide semiconductor, and the oxygen vacancy concentration of the first surface is greater than the oxygen vacancy concentration of the portion of the channel other than the first surface and the second surface.

7. The method for fabricating a chip according to claim 6, characterized in that, The formation of a first electrode, a second electrode, and a passivation layer on at least a portion of the surface of the channel includes: A first film layer is formed on the surface of the channel, the first film layer completely covering the channel; The first film layer is etched to obtain the passivation layer; The first electrode and the second electrode are formed on opposite sides of the passivation layer.

8. The method for fabricating a chip according to claim 6, characterized in that, The formation of a first electrode, a second electrode, and a passivation layer on at least a portion of the surface of the channel includes: The first electrode and the second electrode are formed on a portion of the surface of the channel; The passivation layer is formed between the first electrode and the second electrode.

9. The method for fabricating a chip according to claim 8, characterized in that, The passivation layer is also located on the side of the first electrode and the second electrode opposite to the substrate.

10. A chip, characterized in that, The chip includes a substrate and transistors disposed on the substrate, the transistors comprising: A first electrode and a stacked structure are stacked on the substrate, and the stacked structure has a cutout portion; along the direction from the substrate to the first electrode, the stacked structure includes a first spacer layer, a gate, and a second spacer layer stacked together. A gate dielectric and a channel, wherein the gate dielectric is filled in the cutout portion, and the channel is at least partially located in the cutout portion; the gate dielectric is located on the sidewall of the cutout portion, and the gate dielectric is used to electrically isolate the channel from the gate electrode; the channel is in contact with the first electrode. A second electrode and a passivation layer are disposed on at least a portion of the surface of the channel; the surface of the channel includes a first surface and a second surface, the first surface being in contact with the passivation layer and the second surface being in contact with the second electrode; wherein the material of the channel includes an oxide semiconductor, and the oxygen vacancy concentration of the first surface is greater than the oxygen vacancy concentration of the portion of the channel other than the first surface and the second surface.

11. The chip according to claim 10, characterized in that, The oxygen vacancy concentration on the second surface is also greater than the oxygen vacancy concentration in the portion of the channel other than the first and second surfaces.

12. The chip according to claim 10 or 11, characterized in that, The passivation layer is made of a multi-metal oxide.

13. The chip according to claim 12, characterized in that, The passivation layer is made of at least one of gallium oxide, magnesium oxide, and titanium dioxide.

14. The chip according to any one of claims 10-13, characterized in that, The channel is disposed in the cutout portion, or the channel extends from the cutout portion to the side of the second spacer layer opposite to the substrate; The passivation layer is located in the hollowed-out portion; The second electrode is disposed on the side of the channel and the passivation layer away from the substrate.

15. The chip according to any one of claims 10-13, characterized in that, The channel extends from the cutout to the side of the second spacer layer opposite to the substrate; The passivation layer further includes a continuous first passivation layer and a second passivation layer, wherein the first passivation layer is disposed in the hollow portion; The second passivation layer is located outside the cutout portion and contacts the portion of the channel located outside the cutout portion; The second electrode is located on the sidewall of the passivation layer and on the side of the channel opposite to the substrate; or, the second electrode extends from the side of the channel opposite to the substrate to the side of the second passivation layer opposite to the substrate.

16. The chip according to any one of claims 10-13, characterized in that, The channel is located in the hollowed-out portion, and the passivation layer is located outside the hollowed-out portion; The second electrode is located on the sidewall of the passivation layer and on the side of the channel opposite to the substrate; or, the second electrode extends from the side of the channel opposite to the substrate to the side of the passivation layer opposite to the substrate.

17. A method for fabricating a chip, characterized in that, The chip includes transistors, and the method for fabricating the transistors includes: A first electrode and a stacked structure are sequentially formed on a substrate. The stacked structure includes a first spacer layer, a gate, and a second spacer layer stacked together, and a cutout portion is provided in the stacked structure. The cutout portion is filled with a gate dielectric and a channel, the gate dielectric is located on the sidewall of the cutout portion, the channel is at least partially located in the cutout portion, the gate dielectric is used to electrically isolate the channel from the gate, and the channel is in contact with the first electrode; A passivation layer and a second electrode are formed on at least a portion of the surface of the channel; the surface of the channel includes a first surface and a second surface, the first surface being in contact with the passivation layer and the second surface being in contact with the second electrode; wherein the material of the channel includes an oxide semiconductor, and the oxygen vacancy concentration of the first surface is greater than the oxygen vacancy concentration of the portion of the channel other than the first surface and the second surface.

18. The method for fabricating a chip according to claim 17, characterized in that, The channel extends from the cutout to the side of the second spacer layer opposite to the substrate; the formation of a passivation layer and a second electrode on at least a portion of the surface of the channel includes: A first film layer and a protective layer are sequentially formed on the surface of the channel. Under the protection of the protective layer, the first film layer is etched to obtain the passivation layer. The passivation layer includes a continuous first passivation layer and a second passivation layer. The first passivation layer is disposed in the hollow portion and contacts the portion of the channel located in the hollow portion. The second passivation layer is located outside the hollow portion and contacts the portion of the channel located outside the hollow portion. A second electrode is formed, which is located on the sidewall of the passivation layer and on the side of the channel opposite to the substrate; or, the second electrode extends from the side of the channel opposite to the substrate to the side of the passivation layer opposite to the substrate.

19. A display panel, characterized in that, The display panel includes an array substrate, which includes the chip according to any one of claims 1-5 or any one of claims 10-16.

20. An electronic device, characterized in that, Includes the chip as described in any one of claims 1-5 or any one of claims 10-16, or the display panel as described in claim 19.

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