An in-core bidirectional timer suitable for multi-core systems
By configuring an internal bidirectional timer for each core in a multi-core system and utilizing the kernel clock to implement timing functionality, the problems of timing delay and low timing accuracy of peripheral timers are solved, and independent and precise timing for each core in a multi-core system is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIJING MICROELECTRONICS TECH INST
- Filing Date
- 2023-12-07
- Publication Date
- 2026-07-24
AI Technical Summary
In existing multi-core systems, peripheral timers cannot achieve precise timing functions, resulting in timing delays and low timing response accuracy.
In a multi-core system, each kernel is configured with a private internal bidirectional timer, including a rise timer, a countdown timer, an adder, and an internal timer interrupt module. The timing function is implemented using the kernel clock, and the timing accuracy is achieved through necessary configuration and simple comparison.
It implements independent timing functions for each core in a multi-core system, avoiding inter-core interference and competition, ensuring accurate timing, and meeting the application requirements of high-performance multi-core systems.
Smart Images
Figure CN117784881B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a method for implementing a bidirectional timer within a core in a multi-core system, which can achieve precise up-count or down-count timing functions and is applicable to single-core or multi-core processor cores and other fields. Background Technology
[0002] Processors typically connect to peripheral timers to implement timing functions. Peripheral timers are generally connected to the processor via a bus. Because they exist independently of the processor, they offer greater configuration flexibility. However, compared to on-core timers, the propagation path between peripheral timers and the processor is longer, resulting in timing delays and lower processing accuracy. This is especially true as processors evolve towards high-performance multi-core architectures, where task contention can cause timer signals to be delayed, affecting the accuracy of timing responses. Processors generally have their own core clock, with a clock counter incrementing by 1 every clock cycle to record the passage of time. Summary of the Invention
[0003] The technical problem solved by this invention is to overcome the shortcomings of existing technologies and provide a method for implementing an intra-core bidirectional timer suitable for multi-core systems. This method solves the problem that peripheral timers in multi-core systems cannot achieve precise timing functions, effectively reuses the intra-core clock, and achieves timing functions through necessary configuration and simple comparison. In a multi-core system, each core can have its own independent private timer, without inter-core interference and competition, enabling collaborative work of the multi-core system.
[0004] The technical solution of this invention is: an intra-core bidirectional timer suitable for multi-core systems, wherein each core clock in the multi-core system is configured with a private intra-core bidirectional timer; the intra-core bidirectional timer includes: a rise timer, a countdown timer, an adder, and an intra-core timer interrupt module;
[0005] The kernel clock output is connected to the adder and the on-core timer interrupt module, respectively.
[0006] The boost timer is used to implement the absolute time point timing function, sending the configured absolute time point to the core timer interrupt module;
[0007] The countdown timer is used to implement the relative time point timing function, and sends the configured countdown value to the adder;
[0008] The adder converts the configured countdown value into a rising countdown value, and then sends the converted rising countdown value to the core timer interrupt module via the rising timer.
[0009] The kernel timer interrupt module generates an interrupt signal when the kernel clock counts up to the configured absolute time point, based on the kernel clock time value and the countdown value, to notify the interrupt controller that the timer has ended; it also generates an interrupt signal when the countdown value decreases to 0, based on the kernel clock time value and the countdown value, to notify the interrupt controller that the timer has ended.
[0010] Preferably, the rise timer includes a rise timer value register for configuring the rise timer value uval. The kernel timer interrupt module compares the configured value uval with the kernel clock time value tnum. When uval = tnum, an interrupt signal is generated to realize the rise timer timing function.
[0011] Preferably, the timing accuracy is adjusted by adjusting the effective number of bits in the boost register, with the maximum accuracy being the same as the core clock frequency, that is, the number of bits in the boost register is the same as the number of bits in the core clock count value.
[0012] Preferably, the countdown timer includes a countdown value register for configuring the countdown value dval. The countdown starts from the time ctime determined by the kernel clock. When the countdown value dval decreases to zero, the countdown ends and an interrupt signal is generated, thus realizing the fixed interval timing function.
[0013] Preferably, the timing accuracy and timing range are adjusted by adjusting the effective number of bits in the countdown value register.
[0014] Preferably, the adder adds the configured time ctime to the configured countdown value dval, and stores the result dcval in the countdown value register. Thus, the countdown function can be realized by comparing dcval with the kernel clock time value tnum, without the need for an additional countdown clock.
[0015] Preferably, the on-core timer interrupt module includes an interrupt clear register, an interrupt control register, and a comparator;
[0016] The interrupt clear register implements the interrupt clearing function;
[0017] The interrupt control register enables and disables interrupts, and masks and demasks interrupts.
[0018] The comparator compares the current kernel clock time tnum with the configured timer value uval or dcval. When tnum = uval or tnum = dcval, that is, when the system clock reaches the specified time, it generates an interrupt signal irq and passes it to the interrupt controller.
[0019] Preferably, interrupts are cleared by configuring the interrupt clear register in software. They are not cleared automatically. After clearing, the next timing function can be configured normally.
[0020] Preferably, if both the countdown and up-countdown registers are configured simultaneously, the time point configured earlier will be overwritten by the time point configured later, meaning that the timing function configured earlier is invalid, while the timing function configured later is valid.
[0021] The beneficial effects of this invention compared with the prior art are as follows: Based on the existing kernel timer, this invention realizes the bidirectional timing function within the kernel with minimal overhead. In a multi-core system, each core can have its own private kernel timer, which can ensure the timing function is accurate and error-free, meet the higher application requirements of multi-core architecture, and has a wide range of application space and market prospects.
[0022] (1) Low resource consumption; based on the existing kernel clock, timing function can be achieved through necessary configuration and simple comparison.
[0023] (2) The timing configuration is flexible. It can realize the absolute time timing function by stepping up the timer or the relative time timing function by counting down the timer.
[0024] (3) The timing accuracy is adjustable. For timing applications that require high precision, the timing accuracy can be the same as the kernel clock. For timing applications that require low power consumption, the timing accuracy can also be achieved through shift storage. The accuracy of the up-countdown and down-countdown can be different.
[0025] (4) The counting period range is large, and the timing period can be the same as the kernel clock timing range. Attached Figure Description
[0026] Figure 1 This is a schematic diagram of an implementation method for an in-core bidirectional timer applicable to a multi-core system according to the present invention. Detailed Implementation
[0027] This invention relates to an intra-core bidirectional timer suitable for multi-core systems. It implements timing functionality based on the existing kernel clock, supporting both up-count and down-count timing, with configurable timing accuracy. In a multi-core system, each core can have its own private intra-core timer, ensuring accurate timing and meeting the higher application requirements of multi-core architectures, thus possessing broad application potential and market prospects. Figure 1 As shown, the in-core bidirectional timer of this invention includes: a rise timer, a countdown timer, an adder, and an in-core timer interrupt module;
[0028] The ramp-up timer implements absolute time timing, i.e., timing at fixed points in time based on the kernel clock. When the kernel timer ramp-up register is configured, ramp-up timing is enabled, generating an interrupt signal at the specified time point. The countdown timer implements relative time timing, i.e., timing at fixed time intervals. When the kernel timer countdown register is configured, countdown timing is enabled, starting from the current time point and ending when the countdown value reaches zero, generating an interrupt signal. If both ramp-up and countdown registers are configured simultaneously, the time point configured earlier will be overwritten by the time point configured later; that is, the earlier configured timing function is invalid, and the later configured timing function is valid. The adder converts the configured countdown value into a ramp-up value, thus enabling both ramp-up and countdown timing functions using a single kernel clock. The kernel timer interrupt module generates an interrupt signal at the timing point, notifying the interrupt controller that the timing has ended.
[0029] like Figure 1 As shown, the core timer interrupt module includes an interrupt clear register, an interrupt control register, and a comparator. The interrupt clear register implements the interrupt clearing function. It needs to be cleared by configuring the core timer interrupt clear register through software. It will not be cleared automatically. After clearing, the next timer function can be configured normally.
[0030] The interrupt control register enables and disables interrupts, and masks and unmasks interrupts. When the timer needs to send a notification signal when the timer reaches its set time, the interrupt function is enabled but not masked. In this case, interrupt handling is required before execution can continue. When the timer function is required but interrupt handling is not desired, the interrupt can be enabled but the interrupt can be masked. In this case, the timer will pull the interrupt pending bit in the interrupt control register high when the timer reaches its set time, and then execution can continue. When the timer function is not needed, the interrupt is disabled and masked by default.
[0031] The comparator compares the current kernel clock time tnum with the configured timer value uval or dcval. When tnum = uval or tnum = dcval, that is, when the system clock reaches the specified time, it generates an interrupt signal irq and passes it to the interrupt controller.
[0032] This invention utilizes the kernel clock to implement an in-core timing function, which consumes fewer resources compared to general timer designs and enables the reuse of the kernel clock. Moreover, it can achieve ultra-long timing functions to meet the application requirements of long-life processors. Compared to traditional off-core timers, it saves the time for timing signals to be transmitted to the kernel via the bus, avoids the impact of inter-core competition in multi-core systems on timing tasks, and enables more accurate timing functions.
[0033] Taking a 1GHz core and application requirements of at least 30 years as an example, such as Figure 1As shown, the kernel timer implementation method used in this invention is as follows: The timing function is implemented based on the existing kernel clock's timing value. An up-counting timer implements absolute time timing, meaning that when the kernel clock timing time tnum equals the configuration value uval of the up-counting value register, a timer interrupt is triggered. A countdown timer implements relative time timing, meaning that starting from the time ctime when the countdown register is configured, the value of the countdown register decrements by 1 every clock cycle, and when it reaches zero, the timing ends and an interrupt is triggered. The timing precision can be adjusted by expanding or shifting the number of bits in the configuration value.
[0034] Example:
[0035] The main clock frequency is 1GHz, and the core clock count increments by 1 every 1ns. To meet the application requirements of a long lifespan of no less than 30 years, the core clock count is configured with 60 bits, and its lifespan is 2. 60 ns≈1.15*10 9 s≈1.92*10 7 min≈320255h≈13343day≈36.5year.
[0036] To meet the maximum time-capable up-counting requirement, a 60-bit up-counting value register can be configured to achieve precise timing control with an accuracy of 1ns. If accuracy to 1s is required instead of 1ns, the up-counting value register can be configured to 31 bits. The result of left-shifting the configuration value by 29 bits is compared with the timing value of the kernel clock to achieve up-counting accuracy of 1s.
[0037] The countdown function does not require an additional countdown timer. Instead, the configuration value dval of the countdown value register is added to the kernel clock value ctime at the configured time. The resulting dcval = dval + ctime is stored in the countdown value register. The value of the countdown value register is then compared with the kernel clock value; if they are equal, an interrupt signal is generated. This achieves a fixed time interval of dcval - ctime = dval. The configuration precision control principle for the countdown is the same as that for the countdown: if precision to 1 ns is required, the countdown value register is set to 60 bits; if precision to 1 second is required, the countdown value register is set to 31 bits. When performing addition, the value dval in the countdown value register is shifted left by 29 bits before being added to the current time ctime. Configurations for other precision requirements can be deduced similarly.
[0038] The interrupt output function of the core timer is implemented through the core timer interrupt module. Whether it's a countdown or a rise timer, as long as the value uval or dcval in the rise timer register is equal to the current kernel clock's countdown value tnum, an interrupt signal is generated indicating that the timing has arrived. The interrupt signal of the core timer can be masked by configuring the interrupt control register, preventing it from being output to the interrupt controller. After an interrupt signal is generated, the current interrupt needs to be cleared by configuring the interrupt clear register. After clearing, the timing function can be reconfigured for the next time.
[0039] The above description is only the best specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the protection scope of the present invention.
[0040] The contents not described in detail in this specification are common knowledge to those skilled in the art.
Claims
1. A bidirectional timer within a core for multi-core systems, characterized in that, Each core clock in the multi-core system is configured with a private in-core bidirectional timer; the in-core bidirectional timer includes: a rise timer, a countdown timer, an adder, and an in-core timer interrupt module; The kernel clock output is connected to the adder and the on-core timer interrupt module, respectively. The boost timer is used to implement the absolute time point timing function, sending the configured absolute time point to the core timer interrupt module; The countdown timer is used to implement the relative time point timing function, and sends the configured countdown value to the adder; The adder converts the configured countdown value into a rising countdown value, and then sends the converted rising countdown value to the core timer interrupt module via the rising timer. The kernel timer interrupt module generates an interrupt signal when the kernel clock counts up to the configured absolute time point, based on the kernel clock time value and the countdown value, to notify the interrupt controller that the timer has ended; it also generates an interrupt signal when the countdown value decreases to 0, based on the kernel clock time value and the countdown value, to notify the interrupt controller that the timer has ended.
2. The bidirectional timer within the core according to claim 1, characterized in that: The rise timer includes a rise timer value register for configuring the rise timer value uval. The kernel timer interrupt module compares the configured value uval with the kernel clock time value tnum. When uval = tnum, an interrupt signal is generated to realize the rise timer timing function.
3. The bidirectional timer within the core according to claim 2, characterized in that: The timing precision is adjusted by changing the number of significant bits in the rise timer register. The maximum precision is the same as the core clock frequency, meaning the maximum number of significant bits in the rise timer register is the same as the maximum number of significant bits in the core clock count.
4. The bidirectional timer within the core according to claim 1, characterized in that: The countdown timer includes a countdown value register, which is used to configure the countdown value dval. The countdown starts from the time ctime, which is determined by the kernel clock. When the countdown value dval decreases to zero, the countdown ends and an interrupt signal is generated, thus realizing the fixed interval timing function.
5. The bidirectional timer within the core according to claim 4, characterized in that: The timing precision and timing range can be adjusted by changing the number of valid bits in the countdown value register.
6. The bidirectional timer within the core according to claim 4, characterized in that: The adder adds the configured time ctime to the configured countdown value dval, and stores the result dcval in the countdown value register. The countdown function can be implemented by comparing dcval with the kernel clock time value tnum, without the need for an additional countdown clock.
7. The bidirectional timer within the core according to claim 6, characterized in that: The on-core timer interrupt module includes an interrupt clear register, an interrupt control register, and a comparator; The interrupt clear register implements the interrupt clearing function; The interrupt control register enables and disables interrupts, and masks and demasks interrupts. The comparator compares the current kernel clock time tnum with the configured timer value uval or dcval. When tnum = uval or tnum = dcval, that is, when the system clock reaches the specified time, it generates an interrupt signal irq and passes it to the interrupt controller.
8. The bidirectional timer within the core according to claim 7, characterized in that: The generated interrupts can be cleared by configuring the interrupt clear register in the software. They will not be cleared automatically. After clearing, the next timing function can be configured normally.
9. The in-core bidirectional timer according to any one of claims 1 to 8, characterized in that: If both the countdown and up registers are configured simultaneously, the time point configured first will be overwritten by the time point configured later. In other words, the timing function configured first will be invalid, while the timing function configured later will be valid.