Anti-jamming radio frequency receiving assembly

Abstract

This invention provides an anti-interference radio frequency (RF) receiver component, comprising an antenna module, a down-conversion module, an anti-interference processing module, and an up-conversion module. The component performs down-conversion, anti-interference, and up-conversion processing on the received initial RF signal to obtain a target RF signal that meets the requirements, which is then transmitted to the subsequent receiver for processing. While ensuring anti-interference RF reception, the anti-interference processing module adjusts the attenuation of the two digitally controlled attenuators in each down-conversion channel of the down-conversion module and the operating mode of the adjustable low-noise amplifier. This effectively and automatically adjusts the gain of the down-conversion channel, ensuring that the down-conversion channel always operates in linear mode, preventing distortion due to saturation, maintaining high linearity and low noise characteristics, thereby improving anti-interference performance.

Description

Technical Field

[0001] This invention relates to the field of radio frequency communication technology, and in particular to an anti-interference radio frequency receiving component. Background Technology

[0002] The existing BeiDou navigation anti-interference radio frequency components mainly consist of an antenna module, a down-conversion module, a clock module, an anti-interference processing module, an up-conversion module, and a pass-through module. The down-conversion module includes multiple down-conversion channels, each containing a front-end low-noise amplifier unit and a down-conversion unit, which performs filtering, amplification, and frequency conversion of satellite signals. The front-end low-noise amplifier unit mainly consists of a two-stage amplifier and a three-stage filter, while the down-conversion unit mainly consists of a mixer, an intermediate frequency amplifier, and an LC filter.

[0003] However, existing BeiDou navigation anti-interference radio frequency components have at least the following drawbacks:

[0004] 1. The number of downconverter channels is large, and the workload of hardware debugging is large. In order to meet the amplitude consistency index between each downconverter channel, hardware debugging is the only way.

[0005] 2. The anti-interference performance of the system is affected by the linearity of the down-conversion channel. The down-conversion channel of the existing solution adopts a fixed gain mode. When the system is in a strong electromagnetic interference environment (such as interference signal power greater than -30dBm), the down-conversion channel is prone to saturation distortion and operates in a nonlinear state, which may lead to navigation and positioning failure.

[0006] Therefore, there is an urgent need for an anti-interference radio frequency receiving technology that can achieve automatic gain control. In a strong electromagnetic interference environment, it can automatically adjust the gain of the downconversion channel so that the downconversion channel always works within the linear range and maintains high linearity and low noise characteristics. Summary of the Invention

[0007] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an anti-interference radio frequency (RF) receiving technology solution. This solution combines an antenna module, a down-conversion module, an anti-interference processing module, and an up-conversion module to design an anti-interference RF receiving component. The received initial RF signal undergoes down-conversion, anti-interference processing, and up-conversion processing to obtain a target RF signal that meets the requirements, which is then transmitted to the subsequent receiver for processing. While ensuring anti-interference RF reception, the anti-interference processing module adjusts the attenuation of the two digitally controlled attenuators in each down-conversion channel of the down-conversion module and the operating mode of the adjustable low-noise amplifier. This automatically adjusts the gain of the down-conversion channel, ensuring that the down-conversion channel always operates in linear mode, preventing distortion due to saturation and maintaining high linearity and low noise characteristics.

[0008] To achieve the above-mentioned objectives and other related objectives, the technical solution provided by the present invention is as follows.

[0009] An anti-interference radio frequency receiver component, comprising:

[0010] An antenna module includes multiple antenna elements, which receive an initial radio frequency signal;

[0011] The downconversion module is connected to the antenna module and includes multiple downconversion channels. Each downconversion channel is connected to a corresponding antenna element. Each downconversion channel includes two digitally controlled attenuators and an adjustable low-noise amplifier. The downconversion channel amplifies, filters, and downconverts the initial radio frequency signal to obtain an intermediate frequency signal.

[0012] An anti-interference processing module, connected to the down-conversion module, performs analog-to-digital conversion sampling and detection on the intermediate frequency signal to obtain a digital intermediate frequency signal. It then determines the magnitude of the interference signal in the digital intermediate frequency signal and adjusts the attenuation of the two digitally controlled attenuators in the down-conversion channel and the operating mode of the adjustable low-noise amplifier according to the magnitude of the interference signal. This automatically adjusts the gain of the down-conversion channel so that it always operates in linear mode. Finally, it eliminates the interference signal and converts the digital intermediate frequency signal from digital to analog to obtain an analog intermediate frequency signal.

[0013] The upconversion module is connected to the anti-interference processing module to filter and upconvert the analog intermediate frequency signal to obtain the target radio frequency signal.

[0014] Optionally, the downconversion channel includes a low-noise amplifier unit and a downconversion unit. The low-noise amplifier unit includes three filters, two digitally controlled attenuators, an adjustable low-noise amplifier, and a low-noise amplifier. The first filter, the low-noise amplifier, the second filter, the first digitally controlled attenuator, the adjustable low-noise amplifier, the second digitally controlled attenuator, and the third filter are cascaded in sequence. The input terminal of the first filter is connected to the initial radio frequency signal.

[0015] Optionally, the low-noise amplifier is a limiting low-noise amplifier, and the adjustable low-noise amplifier has two operating modes: a pass-through mode and an amplification mode. The operating mode of the adjustable low-noise amplifier is switched by adjusting the enable port, thereby adjusting the gain of the adjustable low-noise amplifier.

[0016] Optionally, the downconversion unit includes a downconverter, an intermediate frequency amplifier, and a first LC filter. The radio frequency terminal of the downconverter is connected to the output terminal of the third filter, the local oscillator terminal of the downconverter is connected to the first local oscillator signal, the intermediate frequency terminal of the downconverter is connected to the input terminal of the intermediate frequency amplifier, the output terminal of the intermediate frequency amplifier is connected to the input terminal of the first LC filter, and the output terminal of the first LC filter outputs the intermediate frequency signal.

[0017] Optionally, the downconverter and the intermediate frequency amplifier in the multiple downconversion channels are integrated into a multi-channel anti-interference radio frequency chip. The multi-channel anti-interference radio frequency chip has multiple parallel downconversion amplification channels, in which the downconverter and the intermediate frequency amplifier are arranged sequentially.

[0018] Optionally, the anti-interference processing module includes:

[0019] An analog-to-digital converter chip performs analog-to-digital conversion sampling and detection on the intermediate frequency signal to obtain the digital intermediate frequency signal;

[0020] A field-programmable gate array (FPGA) chip, connected to the analog-to-digital converter (ADC) chip, determines the magnitude of interference signals in the digital intermediate frequency (IF) signal and outputs three control signals to the two digitally controlled attenuators and the adjustable low-noise amplifier in the down-conversion channel according to the interference signals. This adjusts the attenuation of the two digitally controlled attenuators and the operating mode of the adjustable low-noise amplifier, thereby automatically adjusting the gain of the down-conversion channel to ensure that the down-conversion channel always operates in linear mode, and then eliminating the interference signals.

[0021] A digital-to-analog converter chip is connected to the field-programmable gate array chip to perform digital-to-analog conversion on the digital intermediate frequency signal to obtain the analog intermediate frequency signal.

[0022] Optionally, the upconversion module includes a second LC filter, an upconverter, two surface acoustic wave (SAW) filters, and two π-type attenuators. The input of the second LC filter is connected to the analog intermediate frequency (IF) signal, the output of the second LC filter is connected to the IF terminal of the upconverter, the local oscillator terminal of the upconverter is connected to the second local oscillator signal, the radio frequency (RF) terminal of the upconverter is connected to the input of the first SAW filter, the output of the first SAW filter is connected to the input of the first π-type attenuator, the output of the first π-type attenuator is connected to the input of the second SAW filter, the output of the second SAW filter is connected to the input of the second π-type attenuator, and the output of the second π-type attenuator outputs the target RF signal.

[0023] Optionally, the anti-interference radio frequency receiving component further includes a clock module, which provides the first local oscillator signal to the down-conversion module, provides the second local oscillator signal to the up-conversion module, and provides a sampling clock to the anti-interference processing module.

[0024] Optionally, the clock module includes a crystal oscillator, an RF phase-locked loop, and a clock phase-locked loop. The crystal oscillator generates a reference clock, the RF phase-locked loop generates a first local oscillator signal and a second local oscillator signal based on the reference clock, and the clock phase-locked loop generates the sampling clock based on the reference clock.

[0025] Optionally, the field-programmable gate array chip is configured as follows:

[0026] Based on the initial values ​​assigned to the attenuation of the two digitally controlled attenuators in each downconversion channel, each downconversion channel operates in linear mode and the amplitude of each downconversion channel is consistent.

[0027] Based on the magnitude of the interference signal, the attenuation of the two digitally controlled attenuators in each downconversion channel and the operating mode of the adjustable low-noise amplifier are adjusted to correspondingly reduce the gain of the downconversion channel, so that the downconversion channel always operates in linear mode.

[0028] Optionally, the field-programmable gate array chip is configured as follows:

[0029] When adjusting the amplitude of each of the downconversion channels, the initial attenuation value of the first digitally controlled attenuator is the first attenuation value, the initial attenuation value of the second digitally controlled attenuator is the second attenuation value, the adjustable low-noise amplifier operates in the amplification mode, and the gain change of the adjustable low-noise amplifier when switching from the amplification mode to the pass-through mode is the third attenuation value.

[0030] When adjusting the gain of each of the downconversion channels, if the sum of the target attenuation value of the downconversion channel and the second attenuation value is less than the third attenuation value, then the target attenuation value of the downconversion channel is added to the first digitally controlled attenuator, and the attenuation value of the first digitally controlled attenuator is adjusted to the sum of the first attenuation value and the target attenuation value. The attenuation value of the second digitally controlled attenuator remains unchanged from the second attenuation value, and the adjustable low-noise amplifier still operates in the amplification mode.

[0031] When adjusting the gain of each of the downconversion channels, if the sum of the target attenuation value of the downconversion channel and the second attenuation value is equal to the third attenuation value, then the target attenuation value of the downconversion channel is added to the adjustable low noise amplifier, the adjustable low noise amplifier is switched from the amplification mode to the pass-through mode, the attenuation value of the first digitally controlled attenuator remains unchanged at the first attenuation value, and the attenuation value of the second digitally controlled attenuator becomes zero;

[0032] When adjusting the gain of each of the downconversion channels, if the sum of the target attenuation value of the downconversion channel and the second attenuation value is greater than the third attenuation value, then the target attenuation value of the downconversion channel is added to the adjustable low-noise amplifier and one of the digitally controlled attenuators, the adjustable low-noise amplifier is switched from the amplification mode to the pass-through mode, the attenuation value of one of the digitally controlled attenuators remains unchanged from the initial attenuation value, and the attenuation value of the other digitally controlled attenuator is adjusted.

[0033] As described above, the anti-interference radio frequency receiving component of the present invention has at least the following beneficial effects:

[0034] An anti-interference RF receiver component is designed by combining an antenna module, a down-conversion module, an anti-interference processing module, and an up-conversion module. It performs down-conversion, anti-interference, and up-conversion processing on the received initial RF signal to obtain the target RF signal that meets the requirements, which is then transmitted to the subsequent receiver for processing. While ensuring anti-interference RF reception, the anti-interference processing module adjusts the attenuation of the two digitally controlled attenuators in each down-conversion channel of the down-conversion module and the operating mode of the adjustable low-noise amplifier. This automatically adjusts the gain of the down-conversion channel, ensuring it always operates in linear mode without distortion due to saturation, maintaining high linearity and low noise characteristics. Simultaneously, the anti-interference processing module allows for software control and adjustment of the amplitude of each down-conversion channel, eliminating the need for hardware debugging and reducing the workload. Attached Figure Description

[0035] Figure 1 The diagram shows the structural block diagram of the anti-interference radio frequency component for BeiDou navigation in the prior art.

[0036] Figure 2 Displayed as Figure 1 Block diagram of the low-noise amplifier unit in the intermediate-to-low frequency conversion module.

[0037] Figure 3 Displayed as Figure 1 Block diagram of the downconverter unit within the downconverter module.

[0038] Figure 4 The diagram shown is a structural block diagram of the anti-interference radio frequency receiving component in this invention.

[0039] Figure 5 The diagram shown is a structural block diagram of the low-noise amplifier unit within the downconversion module of this invention.

[0040] Figures 6-7 The diagram shown is a circuit diagram of the low-noise amplifier unit within the downconverter module in an optional embodiment of the present invention.

[0041] Figure 8 The diagram shown is a structural block diagram of the downconverter unit within the downconverter module of this invention.

[0042] Figure 9 The diagram shown is a circuit diagram of the downconverter unit within the downconverter module in an optional embodiment of the present invention.

[0043] Figure 10 The diagram shown is a structural block diagram of the upconversion module in this invention.

[0044] Figure 11 The diagram shown is a circuit diagram of the upconversion module in an optional embodiment of the present invention.

[0045] Figure 12 The diagram shown is a circuit diagram of the clock module in an optional embodiment of the present invention.

[0046] Figure 13 The diagram shows the changes in the noise figure and OIP3 index of the frequency converter channel during the attenuation control process in an optional embodiment of the present invention. Detailed Implementation

[0047] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0048] Please see Figures 1 to 13 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show components relevant to the present invention and are not drawn according to the actual number, shape, and size of the components in implementation. In actual implementation, the form, quantity, and proportion of each component can be arbitrarily changed, and the component layout may be more complex. The structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and are not intended to limit the implementation conditions of the present invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effects and objectives of the present invention, should still fall within the scope of the technical content disclosed in the present invention.

[0049] As mentioned above in the background section, the inventors discovered that, as Figure 1As shown, the existing BeiDou navigation anti-interference radio frequency (RF) components mainly consist of an antenna module, a down-conversion module, a clock module, an anti-interference processing module, an up-conversion module, and a pass-through module. The initial RF signal is pre-processed by the down-conversion channel in the down-conversion module and then sent to the anti-interference processing module to eliminate interference. Finally, it is sent to the up-conversion channel in the up-conversion module for up-conversion and output to the receiver for processing, thus achieving anti-interference navigation and positioning functions. Simultaneously, the anti-interference processing module controls the switches in the down-conversion and up-conversion channels by outputting high and low level control signals, respectively. This allows the pass-through channel in the pass-through module to be connected when the RF components lose normal power, enabling the pass-through channel to operate using output port power.

[0050] In detail, such as Figure 1 As shown, the downconversion module includes multiple downconversion channels. Each downconversion channel comprises a front-end low-noise amplifier unit and a back-end downconversion unit, performing filtering, amplification, and frequency conversion of the satellite signal. The front-end low-noise amplifier unit mainly consists of a two-stage amplifier and a three-stage filter, such as... Figure 2 As shown, the downconversion unit mainly consists of a mixer, an intermediate frequency amplifier, and an LC filter, as follows: Figure 3 As shown.

[0051] However, existing BeiDou navigation anti-interference radio frequency components have at least the following drawbacks:

[0052] 1. The number of downconverter channels is large, and the workload of hardware debugging is large. In order to meet the amplitude consistency index between each downconverter channel, hardware debugging is the only way.

[0053] 2. The anti-interference performance of the system is affected by the linearity of the down-conversion channel. The down-conversion channel of the existing solution adopts a fixed gain mode. When the system is in a strong electromagnetic interference environment (such as interference signal power greater than -30dBm), the down-conversion channel is prone to saturation distortion and operates in a nonlinear state, which may lead to navigation and positioning failure.

[0054] Based on this, the present invention provides an anti-interference radio frequency (RF) receiving technology solution: an anti-interference RF receiving component is designed by combining an antenna module, a down-conversion module, an anti-interference processing module, and an up-conversion module. The received initial RF signal is down-converted, anti-interference processed, and up-converted to obtain a target RF signal that meets the requirements, which is then transmitted to the subsequent receiver for processing. While ensuring anti-interference RF reception, the anti-interference processing module adjusts the attenuation of the two digitally controlled attenuators in each down-conversion channel of the down-conversion module and the operating mode of the adjustable low-noise amplifier to automatically adjust the gain of the down-conversion channel, ensuring that the down-conversion channel always operates in linear mode and does not distort due to saturation, maintaining high linearity and low noise characteristics. At the same time, the anti-interference processing module performs software control and adjustment of the amplitude of each down-conversion channel of the down-conversion module, eliminating the need for hardware debugging and reducing the workload of debugging.

[0055] Specifically, such as Figure 4 As shown, the present invention provides an anti-interference radio frequency receiving component, which includes:

[0056] The antenna module includes multiple antenna elements, which receive an initial radio frequency signal (not shown in the figure);

[0057] The downconversion module, connected to the antenna module, includes multiple downconversion channels, each corresponding to a different antenna element. Each downconversion channel includes two digitally controlled attenuators (i.e., digitally controlled attenuator 1 and digitally controlled attenuator 2) and an adjustable low-noise amplifier (i.e., low-noise amplifier LNA2). The downconversion channel amplifies, filters, and downconverts the initial radio frequency signal to obtain an intermediate frequency signal (not shown in the figure).

[0058] The anti-interference processing module, connected to the down-conversion module, performs analog-to-digital conversion sampling and detection on the intermediate frequency signal to obtain a digital intermediate frequency signal (not shown in the figure). It determines the magnitude of the interference signal in the digital intermediate frequency signal and then adjusts the attenuation of the two digitally controlled attenuators in the down-conversion channel and the operating mode of the adjustable low-noise amplifier according to the magnitude of the interference signal to automatically adjust the gain of the down-conversion channel so that the down-conversion channel always works in linear mode. Then, it eliminates the interference signal and obtains an analog intermediate frequency signal (not shown in the figure) from the digital intermediate frequency signal through digital-to-analog conversion.

[0059] The upconversion module, connected to the anti-interference processing module, filters and upconverts the analog intermediate frequency signal to obtain the target radio frequency signal (not shown in the figure). The target radio frequency signal is then transmitted to the receiver for processing, realizing anti-interference data reception and acquisition, and realizing specific functions, such as the navigation and positioning function of a satellite navigation system.

[0060] In detail, such as Figure 4 and Figure 5As shown, the downconversion channel includes a low-noise amplifier unit and a downconversion unit. The low-noise amplifier unit includes three filters (i.e., filters 1 to 3), two digitally controlled attenuators (i.e., digitally controlled attenuator 1 and digitally controlled attenuator 2), an adjustable low-noise amplifier (i.e., low-noise amplifier LNA2), and a low-noise amplifier (i.e., noise amplifier LNA1). The first filter (i.e., filter 1), the low-noise amplifier (i.e., noise amplifier LNA1), the second filter (i.e., filter 2), the first digitally controlled attenuator (i.e., digitally controlled attenuator 1), the adjustable low-noise amplifier (i.e., low-noise amplifier LNA2), the second digitally controlled attenuator (i.e., digitally controlled attenuator 2), and the third filter (i.e., filter 3) are cascaded in sequence. The input terminal of the first filter is connected to the initial RF signal (not shown in the figure).

[0061] More specifically, in an optional embodiment of the invention, such as Figures 6-7 As shown, the low-noise amplifier unit includes a filter chip U1, a low-noise amplifier chip U2, a filter chip U3, a digitally controlled attenuator chip U4, an adjustable low-noise amplifier chip U5, a digitally controlled attenuator chip U6, and a filter chip U7 cascaded together, as well as peripheral circuitry composed of resistors, capacitors, and inductors. For details, please refer to [link to relevant documentation]. Figures 6-7 This will not be elaborated upon here.

[0062] Among them, the low-noise amplifier chip U2 is a limiting low-noise amplifier with a maximum input power of ≥10W and a limiting output amplitude of 20dBm, ensuring that each unit device is not damaged when a strong signal is input; the digitally controlled attenuator chips U4 and U6 have a step size of 1dB, an attenuation range of 31dB, and an insertion loss of 1dB; the adjustable low-noise amplifier chip U5 has two operating modes: pass-through mode and amplification mode. The operating mode of the adjustable low-noise amplifier chip U5 can be switched by adjusting the enable port, thereby adjusting the gain of the adjustable low-noise amplifier chip U5. When it is operating in amplification mode, the gain is about 21dB, and when it is in pass-through mode, the gain is about -1dB.

[0063] In detail, such as Figure 8 As shown, the downconversion unit includes a downconverter, an intermediate frequency amplifier, and a first LC filter. The RF terminal of the downconverter is connected to the output terminal of the third filter, the local oscillator terminal of the downconverter is connected to the first local oscillator signal, the intermediate frequency terminal of the downconverter is connected to the input terminal of the intermediate frequency amplifier, the output terminal of the intermediate frequency amplifier is connected to the input terminal of the first LC filter, and the output terminal of the first LC filter outputs intermediate frequency signals (IFout1~IFout4).

[0064] More specifically, in an optional embodiment of the invention, such as Figure 9As shown, the downconverters and intermediate frequency amplifiers in multiple downconversion channels are integrated into a single multi-channel anti-interference RF chip U8. The multi-channel anti-interference RF chip U8 has multiple parallel downconversion amplification channels, each containing a downconverter and an intermediate frequency amplifier. Multiple input terminals of the multi-channel anti-interference RF chip U8 are connected to the outputs of multiple low-noise amplifier units, and each output terminal of the multi-channel anti-interference RF chip U8 is connected to a first LC filter composed of a filter chip U9, outputting multiple intermediate frequency signals.

[0065] For example, the multi-channel anti-interference RF chip U8 can use a four-channel RF receiving circuit, which can realize down-conversion and amplification of four 1.15GHz to 2.5GHz frequency band RF signals. It adopts a single down-conversion structure and integrates functional modules such as downconverter, intermediate frequency amplifier, RF phase-locked loop, and low dropout linear power supply (LDO), which has high integration, low noise, and high linearity.

[0066] In detail, the anti-interference processing module includes:

[0067] The analog-to-digital converter chip performs analog-to-digital conversion sampling and detection on the intermediate frequency signal to obtain the digital intermediate frequency signal;

[0068] A field-programmable gate array (FPGA) chip, connected to an analog-to-digital converter (ADC) chip, determines the magnitude of interference signals in the digital intermediate frequency (IF) signal and outputs three control signals corresponding to the interference signals to two digitally controlled attenuators and an adjustable low-noise amplifier (e.g., in the down-conversion channel). Figure 4 As shown), the attenuation of the two digitally controlled attenuators in the downconversion channel and the operating mode of the adjustable low-noise amplifier are adjusted, thereby automatically adjusting the gain of the downconversion channel so that the downconversion channel always works in linear mode, and then eliminating interference signals.

[0069] The digital-to-analog converter chip connects to the field-programmable gate array chip to perform digital-to-analog conversion on the digital intermediate frequency signal to obtain the analog intermediate frequency signal.

[0070] In detail, such as Figure 10As shown, the upconversion module includes a second LC filter, an upconverter, two surface acoustic wave (SAW) filters (SAW filter 1 and SAW filter 2) and two π-type attenuators (π-type attenuator 1 and π-type attenuator 2). The input of the second LC filter is connected to the analog intermediate frequency signal (not shown in the figure), the output of the second LC filter is connected to the intermediate frequency terminal of the upconverter, the local oscillator terminal of the upconverter is connected to the second local oscillator signal, the RF terminal of the upconverter is connected to the input of the first SAW filter (SAW filter 1), the output of the first SAW filter is connected to the input of the first π-type attenuator (π-type attenuator 1), the output of the first π-type attenuator is connected to the input of the second SAW filter (SAW filter 2), the output of the second SAW filter is connected to the input of the second π-type attenuator (π-type attenuator 2), and the output of the second π-type attenuator outputs the target RF signal (RFout).

[0071] More specifically, in an optional embodiment of the invention, such as Figure 11 As shown, the analog intermediate frequency signal is first filtered by the second LC filter and then converted to a radio frequency signal by the upconverter chip U10. After being filtered by two stages of radio frequency surface acoustic wave filter chips U11 to U12 and attenuated by two π-type attenuators, the target radio frequency signal is finally output.

[0072] In detail, such as Figure 4 As shown, the anti-interference radio frequency receiving component also includes a clock module, which provides a first local oscillator signal to the down-conversion module, a second local oscillator signal to the up-conversion module, and a sampling clock to the anti-interference processing module.

[0073] More specifically, in an optional embodiment of the invention, such as Figure 12 As shown, the clock module includes a crystal oscillator, an RF phase-locked loop (PLL), and a clock PLL. The crystal oscillator generates a reference clock, the RF PLL generates a first local oscillator signal and a second local oscillator signal based on the reference clock, and the clock PLL generates a sampling clock based on the reference clock. The crystal oscillator consists of a crystal oscillator chip U13 and surrounding resistors and capacitors. The RF PLL uses the integrated PLL from the previously mentioned anti-interference RF chip. The clock PLL consists of the clock PLL chip U13 and surrounding circuitry, which will not be described in detail here.

[0074] In detail, in this invention, software debugging is mainly based on the field-programmable gate array (FPGA) chip inside the anti-interference processing module to adjust the amplitude and gain of each down-conversion channel. The FPGA chip is configured as follows:

[0075] 1) Based on the initial values ​​of the attenuation of the two digitally controlled attenuators in each downconversion channel, each downconversion channel operates in linear mode and the amplitude of each downconversion channel is consistent.

[0076] 2) Based on the magnitude of the interference signal, adjust the attenuation of the two digitally controlled attenuators in each downconversion channel and the operating mode of the adjustable low-noise amplifier to reduce the gain of the downconversion channel accordingly, so that the downconversion channel always operates in linear mode.

[0077] More specifically, in this invention, the field-programmable gate array chip is configured as follows:

[0078] S1. When adjusting the amplitude of each downconversion channel, the initial attenuation value of the first digitally controlled attenuator is the first attenuation value, the initial attenuation value of the second digitally controlled attenuator is the second attenuation value, the adjustable low-noise amplifier is working in amplification mode, and the gain change of the adjustable low-noise amplifier when switching from amplification mode to pass-through mode is the third attenuation value.

[0079] S2. When adjusting the gain of each downconversion channel, if the sum of the target attenuation value and the second attenuation value of the downconversion channel is less than the third attenuation value, then the target attenuation value of the downconversion channel is added to the first digitally controlled attenuator. The attenuation value of the first digitally controlled attenuator is adjusted to the sum of the first attenuation value and the target attenuation value. The attenuation value of the second digitally controlled attenuator remains unchanged at the second attenuation value. The low-noise amplifier still works in amplification mode.

[0080] S3. When adjusting the gain of each downconversion channel, if the sum of the target attenuation value and the second attenuation value of the downconversion channel is equal to the third attenuation value, then add all the target attenuation values ​​of the downconversion channel to the adjustable low noise amplifier, switch the adjustable low noise amplifier from the amplification mode to the pass-through mode, keep the attenuation value of the first digitally controlled attenuator unchanged from the first attenuation value, and make the attenuation value of the second digitally controlled attenuator zero.

[0081] S4. When adjusting the gain of each downconversion channel, if the sum of the target attenuation value and the second attenuation value of the downconversion channel is greater than the third attenuation value, then the target attenuation value of the downconversion channel is added to the adjustable low-noise amplifier and a digitally controlled attenuator. The adjustable low-noise amplifier is switched from amplification mode to pass-through mode. The attenuation value of one digitally controlled attenuator remains unchanged from its initial attenuation value, and the attenuation value of the other digitally controlled attenuator is adjusted.

[0082] In detail, in an optional embodiment of the present invention, the low-noise amplifier chip U2 is a limiting low-noise amplifier with a maximum input power of ≥10W and a limiting output amplitude of 20dBm, ensuring that each unit device is not damaged when a strong signal is input; the digitally controlled attenuator chips U4 and U6 have a step size of 1dB, an attenuation range of 31dB, and an insertion loss of 1dB; the adjustable low-noise amplifier chip U5 has two operating modes: pass-through mode and amplification mode. The operating mode of the adjustable low-noise amplifier chip U5 is switched by adjusting the enable port, thereby adjusting the gain of the adjustable low-noise amplifier chip U5. When it operates in amplification mode, the gain is about 21dB, and when it operates in pass-through mode, the gain is about -1dB.

[0083] Based on this, through simulation using SysCalc software, the gain of the downconversion channel was found to be 39.7dB, the noise figure to be 1.5dB, and the OIP3 to be 31.93dBm. Meanwhile, for the initial state gain of each downconversion channel, based on the configuration of the field-programmable gate array chip, an initial value was assigned to each of the two digitally controlled attenuators in each downconversion channel, so that the amplitude of each downconversion channel was 40dB±dB.

[0084] Subsequently, based on the configuration of the field-programmable gate array chip, the gain of each down-conversion channel is automatically adjusted and controlled.

[0085] The antenna array receives satellite signals, which enter the down-conversion channel. After amplification, filtering, and mixing, the intermediate frequency signal is output and then enters the anti-interference processing unit for processing. Based on the power of the interference signal detected by A / D sampling, the attenuation of the two digitally controlled attenuators in the down-conversion channel and the working mode control port of the adjustable low-noise amplifier are controlled by the field-programmable gate array chip to realize automatic gain control of the down-conversion channel, ensuring that the down-conversion channel operates in linear mode when strong interference signals are input.

[0086] In detail, in an optional embodiment of the present invention, the gain control range of the down-conversion channel is 0–25 dB, in 1 dB steps, as detailed below:

[0087] Let the target attenuation value be A, the initial attenuation of the first digitally controlled attenuator be 00dB, the initial attenuation of the second digitally controlled attenuator be B, and the gain change of the adjustable low-noise amplifier when switching from amplification mode to pass-through mode be C.

[0088] 1. When the attenuation range of the target attenuation value is 0 to 9 dB (A+B<C), the attenuation is entirely added to the first CNC attenuator.

[0089] As the target attenuation value increases, the noise figure and OIP3 performance deteriorate slightly. When the target attenuation value is 9dB, simulation experiments show that the gain of the downconversion channel is 30.7dB, the noise figure is 2.35dB, and the OIP3 is 31.53dBm.

[0090] 2. When the target attenuation value is 10dB (A+B=C), the adjustable low-noise amplifier is switched from amplification mode to pass-through mode. At the same time, the attenuation values ​​of the first CNC attenuator and the second CNC attenuator 2 are all 0dB. At this time, the simulation results show that the gain of the downconversion channel is 29.7dB, the noise figure is 1.92dB, and the OIP3 is 33.71dBm.

[0091] 3. When the target attenuation value is within the range of 10dB to 20dB (A+B>C), the adjustable low-noise amplifier is switched from amplification mode to pass-through mode. The remaining attenuation is added to either the first or second digitally controlled attenuator, with almost identical effects. For example, when the target attenuation value is 15dB, based on the above operation, the simulation shows that the downconverter channel has a gain of 24.7dB, a noise figure of 2.94dB, an OIP3 of 31.80dBm, and an input signal power of -10dBm. The downconverter channel remains in a linear operating state.

[0092] As shown in the simulation experiments above, in this embodiment of the invention, when the gain of the downconversion channel is within the range of 25dB to 40dB (i.e., the attenuation range of the target attenuation value is 0dB to 15dB), the gain of the downconversion channel can be effectively adjusted by controlling the attenuation of the two digitally controlled attenuators and the operating mode of the adjustable low-noise amplifier. This ensures that the downconversion channel always operates in the linear region, with a noise figure of less than 3.0dB and an OIP3 index greater than 31.5dBm. This achieves low noise and high OIP3 index for the downconversion channel at different gains, thereby improving anti-interference performance. The changes in the noise figure and OIP3 index of the downconversion channel during the attenuation control process are as follows: Figure 13 As shown.

[0093] In detail, by Figure 13 The performance specifications of the downconversion channel are as follows:

[0094] 1. Channel isolation: ≥60dB;

[0095] 2. OIP3: ≥30dBm (intermediate frequency signal output 0dBm, dual-frequency signal with a frequency interval of 1MHz);

[0096] 3. Inter-channel gain difference: ≤1.0dB;

[0097] 4. Phase difference between channels: ≤8°;

[0098] 5. Resistance to burnout: ≥10W.

[0099] The above implementation results show that the anti-interference RF component proposed in this invention, by controlling the attenuation of the two digitally controlled attenuators and the operating mode of the adjustable low-noise amplifier in the downconversion channel through a field-programmable gate array (FPGA) chip, can effectively achieve automatic gain control of the downconversion channel. This ensures that the downconversion channel always operates in linear mode under strong interference signal input, without distortion due to gain saturation. It achieves low noise figure and high OIP3 performance at different gains, thereby improving anti-interference performance. Based on the FPGA chip control, this solution also changes the problem of downconversion channel gain consistency debugging from hardware debugging to software debugging, improving product debugging efficiency. Furthermore, it features miniaturization and versatility, and can be widely used in various RF communication systems, such as satellite navigation systems.

[0100] In summary, the anti-interference RF receiving component provided by this invention combines an antenna module, a down-conversion module, an anti-interference processing module, and an up-conversion module. It performs down-conversion, anti-interference, and up-conversion processing on the received initial RF signal to obtain a target RF signal that meets the requirements, which is then transmitted to the subsequent receiver for processing. While ensuring anti-interference RF reception, the anti-interference processing module adjusts the attenuation of the two digitally controlled attenuators in each down-conversion channel of the down-conversion module and the operating mode of the adjustable low-noise amplifier. This effectively and automatically adjusts the gain of the down-conversion channel, ensuring it always operates in linear mode without distortion due to saturation, maintaining high linearity and low noise characteristics, thereby improving anti-interference performance. Based on the control of a field-programmable gate array (FPGA) chip, the amplitude of each down-conversion channel of the down-conversion module can be software-controlled and adjusted through the anti-interference processing module, eliminating the need for hardware debugging and reducing the workload. Furthermore, it features miniaturization and versatility, making it widely applicable to various RF communication systems.

[0101] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. An anti-interference radio frequency receiving component, characterized in that, include: An antenna module includes multiple antenna elements, which receive an initial radio frequency signal; A downconversion module, connected to the antenna module, includes multiple downconversion channels, each corresponding to one of the antenna elements. Each downconversion channel includes two digitally controlled attenuators and an adjustable low-noise amplifier. The downconversion channel amplifies, filters, and downconverts the initial radio frequency signal to obtain an intermediate frequency signal. The downconversion channel also includes a low-noise amplifier unit and a downconversion unit. The low-noise amplifier unit includes three filters, two digitally controlled attenuators, an adjustable low-noise amplifier, and a low-noise amplifier. The first filter, the low-noise amplifier, the second filter, the first digitally controlled attenuator, the adjustable low-noise amplifier, the second digitally controlled attenuator, and the third filter are cascaded sequentially. The input of the first filter is connected to the initial radio frequency signal. An anti-interference processing module, connected to the down-conversion module, performs analog-to-digital conversion sampling and detection on the intermediate frequency signal to obtain a digital intermediate frequency signal. It then determines the magnitude of the interference signal in the digital intermediate frequency signal and adjusts the attenuation of the two digitally controlled attenuators in the down-conversion channel and the operating mode of the adjustable low-noise amplifier according to the magnitude of the interference signal. This automatically adjusts the gain of the down-conversion channel so that it always operates in linear mode. Finally, it eliminates the interference signal and converts the digital intermediate frequency signal from digital to analog to obtain an analog intermediate frequency signal. The upconversion module is connected to the anti-interference processing module to filter and upconvert the analog intermediate frequency signal to obtain the target radio frequency signal.

2. The anti-interference radio frequency receiving component according to claim 1, characterized in that, The low-noise amplifier is a limiting low-noise amplifier. The adjustable low-noise amplifier has two operating modes: a pass-through mode and an amplification mode. The operating mode of the adjustable low-noise amplifier can be switched by adjusting the enable port, thereby adjusting the gain of the adjustable low-noise amplifier.

3. The anti-interference radio frequency receiving component according to claim 1, characterized in that, The downconversion unit includes a downconverter, an intermediate frequency amplifier, and a first LC filter. The radio frequency terminal of the downconverter is connected to the output terminal of the third filter. The local oscillator terminal of the downconverter is connected to the first local oscillator signal. The intermediate frequency terminal of the downconverter is connected to the input terminal of the intermediate frequency amplifier. The output terminal of the intermediate frequency amplifier is connected to the input terminal of the first LC filter. The output terminal of the first LC filter outputs the intermediate frequency signal.

4. The anti-interference radio frequency receiving component according to claim 3, characterized in that, The downconverter and intermediate frequency amplifier in the multiple downconversion channels are integrated into a multi-channel anti-interference radio frequency chip. The multi-channel anti-interference radio frequency chip has multiple parallel downconversion amplification channels, in which the downconverter and the intermediate frequency amplifier are arranged sequentially.

5. The anti-interference radio frequency receiving component according to claim 2, characterized in that, The anti-interference processing module includes: An analog-to-digital converter chip performs analog-to-digital conversion sampling and detection on the intermediate frequency signal to obtain the digital intermediate frequency signal; A field-programmable gate array (FPGA) chip, connected to the analog-to-digital converter (ADC) chip, determines the magnitude of interference signals in the digital intermediate frequency (IF) signal and outputs three control signals to the two digitally controlled attenuators and the adjustable low-noise amplifier in the down-conversion channel according to the interference signals. This adjusts the attenuation of the two digitally controlled attenuators and the operating mode of the adjustable low-noise amplifier, thereby automatically adjusting the gain of the down-conversion channel to ensure that the down-conversion channel always operates in linear mode, and then eliminating the interference signals. A digital-to-analog converter chip is connected to the field-programmable gate array chip to perform digital-to-analog conversion on the digital intermediate frequency signal to obtain the analog intermediate frequency signal.

6. The anti-interference radio frequency receiving component according to claim 3, characterized in that, The upconversion module includes a second LC filter, an upconverter, two surface acoustic wave (SAW) filters, and two π-type attenuators. The input of the second LC filter is connected to the analog intermediate frequency (IF) signal, and the output of the second LC filter is connected to the IF terminal of the upconverter. The local oscillator terminal of the upconverter is connected to the second local oscillator signal. The radio frequency (RF) terminal of the upconverter is connected to the input of the first SAW filter. The output of the first SAW filter is connected to the input of the first π-type attenuator. The output of the first π-type attenuator is connected to the input of the second SAW filter. The output of the second SAW filter is connected to the input of the second π-type attenuator. The output of the second π-type attenuator outputs the target RF signal.

7. The anti-interference radio frequency receiving component according to claim 6, characterized in that, The anti-interference radio frequency receiving component further includes a clock module, which provides the first local oscillator signal to the down-conversion module, provides the second local oscillator signal to the up-conversion module, and also provides a sampling clock to the anti-interference processing module.

8. The anti-interference radio frequency receiving component according to claim 7, characterized in that, The clock module includes a crystal oscillator, an RF phase-locked loop, and a clock phase-locked loop. The crystal oscillator generates a reference clock, the RF phase-locked loop generates a first local oscillator signal and a second local oscillator signal based on the reference clock, and the clock phase-locked loop generates the sampling clock based on the reference clock.

9. The anti-interference radio frequency receiving component according to claim 5, characterized in that, The field-programmable gate array chip is configured as follows: Based on the initial values ​​assigned to the attenuation of the two digitally controlled attenuators in each downconversion channel, each downconversion channel operates in linear mode and the amplitude of each downconversion channel is consistent. Based on the magnitude of the interference signal, the attenuation of the two digitally controlled attenuators in each downconversion channel and the operating mode of the adjustable low-noise amplifier are adjusted to correspondingly reduce the gain of the downconversion channel, so that the downconversion channel always operates in linear mode.

10. The anti-interference radio frequency receiving component according to claim 9, characterized in that, The field-programmable gate array chip is configured as follows: When adjusting the amplitude of each of the downconversion channels, the initial attenuation value of the first digitally controlled attenuator is the first attenuation value, the initial attenuation value of the second digitally controlled attenuator is the second attenuation value, the adjustable low-noise amplifier operates in the amplification mode, and the gain change of the adjustable low-noise amplifier when switching from the amplification mode to the pass-through mode is the third attenuation value. When adjusting the gain of each of the downconversion channels, if the sum of the target attenuation value of the downconversion channel and the second attenuation value is less than the third attenuation value, then the target attenuation value of the downconversion channel is added to the first digitally controlled attenuator, and the attenuation value of the first digitally controlled attenuator is adjusted to the sum of the first attenuation value and the target attenuation value. The attenuation value of the second digitally controlled attenuator remains unchanged from the second attenuation value, and the adjustable low-noise amplifier still operates in the amplification mode. When adjusting the gain of each of the downconversion channels, if the sum of the target attenuation value of the downconversion channel and the second attenuation value is equal to the third attenuation value, then the target attenuation value of the downconversion channel is added to the adjustable low noise amplifier, the adjustable low noise amplifier is switched from the amplification mode to the pass-through mode, the attenuation value of the first digitally controlled attenuator remains unchanged at the first attenuation value, and the attenuation value of the second digitally controlled attenuator becomes zero; When adjusting the gain of each of the downconversion channels, if the sum of the target attenuation value of the downconversion channel and the second attenuation value is greater than the third attenuation value, then the target attenuation value of the downconversion channel is added to the adjustable low-noise amplifier and one of the digitally controlled attenuators, the adjustable low-noise amplifier is switched from the amplification mode to the pass-through mode, the attenuation value of one of the digitally controlled attenuators remains unchanged from the initial attenuation value, and the attenuation value of the other digitally controlled attenuator is adjusted.

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