Driving method and display device

Abstract

A driving method and a display device are disclosed. The driving method is applied to a display panel, the display panel including multiple rows of scan lines, multiple columns of data lines, and multiple rows and columns of pixel circuits, the pixel circuits being electrically connected to corresponding row scan lines and corresponding column data lines respectively; the driving method includes: controlling a first charging time (t1) to be greater than 0.5 times a second charging time (t2), and controlling the first charging time (t1) to be less than the second charging time (t2); the first charging time (t1) is the time for charging the pixel circuit of the A-row and M-column through the A-th data voltage on the M-th column data line; the second charging time (t2) is the time for charging the pixel circuit of the B-row and M-column through the A-th data voltage and the B-th data voltage; this can improve display uniformity.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a driving method and a display device. Background Technology

[0002] The charging rate of related display products is low, which causes many patterns to fail to display properly or display abnormally, especially checkerboard patterns, H2Line patterns, and H3Line patterns, where the boundaries are not clear. Summary of the Invention

[0003] In one aspect, embodiments of the present invention provide a driving method applied to a display panel, the display panel including multiple rows of scan lines, multiple columns of data lines, and multiple rows and columns of pixel circuits, the pixel circuits being electrically connected to corresponding rows of scan lines and corresponding columns of data lines respectively; the driving method includes:

[0004] The first charging time is controlled to be greater than 0.5 times the second charging time, and the first charging time is controlled to be less than the second charging time.

[0005] Wherein, the first charging time is the time for the A-row M-column pixel circuit to be charged by the A-th data voltage on the M-th column data line;

[0006] The second charging time is the time it takes for the pixel circuit in row B and column M to be charged by the data voltage in data line A and data line B.

[0007] A, B, and M are all positive integers.

[0008] Optionally, the pixel circuit in row A and column M is electrically connected to the scan line in row A, and the pixel circuit in row B and column M is electrically connected to the scan line in row B; the scan line in row A is used to provide the scan signal in row A, and the scan line in row B is used to provide the scan signal in row B.

[0009] The driving method includes controlling the time interval between the falling edge time of the A-row scan signal and the falling edge time of the B-row scan signal to be less than half the time for charging the B-row M-column pixel circuit by the A-row data voltage and the B-row data voltage.

[0010] Optionally, the Ath data voltage is the same as the Bth data voltage.

[0011] Optionally, the effective pulse width of the A-row scan signal is the same as the effective pulse width of the B-row scan signal.

[0012] Optionally, the effective pulse width of the A-row scan signal is greater than the effective pulse width of the B-row scan signal.

[0013] Optionally, in the Nth frame, the pixel circuit in row A and column M is an even-numbered pixel circuit, and the pixel circuit in row B and column M is an odd-numbered pixel circuit; N is an integer.

[0014] Optionally, in the (N+1)th frame, the pixel circuit in row A and column M is an odd-numbered pixel circuit, and the pixel circuit in row B and column M is an even-numbered pixel circuit; N is a positive integer.

[0015] Optionally, the A-th data voltage and the B-th data voltage are the same data voltage; the pixel circuit in the A-th row and M-th column is electrically connected to the A-th row scan line, and the pixel circuit in the B-th row and M-th column is electrically connected to the B-th row scan line; the A-th row scan line is used to provide the A-th row scan signal, and the B-th row scan line is used to provide the B-th row scan signal;

[0016] The driving method further includes: controlling the first time to be greater than the second time;

[0017] The first time is the time when the Mth column data line begins to provide the Ath data voltage, and the time interval between the falling edge time of the Ath row scan signal;

[0018] The second time is the time interval between the falling edge time of the A-line scan signal and the falling edge time of the B-line scan signal.

[0019] Optionally, the pixel circuit in row A and column M is electrically connected to the scan line in row A, and the pixel circuit in row B and column M is electrically connected to the scan line in row B.

[0020] The A-row scan line is used to provide the A-row scan signal, and the B-row scan line is used to provide the B-row scan signal;

[0021] The effective pulse width of the scan signal in row A is not equal to the effective pulse width of the scan signal in row B.

[0022] In a second aspect, embodiments of the present invention provide a driving method applied to a display panel, the display panel including multiple rows of scan lines, multiple columns of data lines, and multiple rows and columns of pixel circuits, the pixel circuits being electrically connected to corresponding rows of scan lines and corresponding columns of data lines respectively; the driving method includes:

[0023] When the fall time of the A-row scan signal provided by the A-row scan line is less than the fall time of the B-row scan signal provided by the B-row scan line, the third time is controlled to be greater than the fourth time.

[0024] The third time is the time from when the Mth column data line starts providing the Ath data voltage to the time when the Ath row Mth column pixel circuit starts to decrease, and the time interval between these two times.

[0025] The fourth time is the time from when the Mth column data line starts providing the Bth data voltage to the time when the pixel circuit of the Bth row and Mth column starts to decrease, and the time interval between these two times.

[0026] A, B, and M are all positive integers, and A is not equal to B.

[0027] Optionally, the A-th data voltage is not equal to the B-th data voltage.

[0028] Optionally, the time interval between the time when the potential of the A-row scan signal begins to fall and the time when the M-column data line stops providing the A-data voltage is greater than the time interval between the time when the potential of the B-row scan signal begins to fall and the time when the M-column data line stops providing the B-data voltage.

[0029] Optionally, the driving method is applied to a display panel, the display panel including a first gate driving circuit and a second gate driving circuit;

[0030] The first gate driving circuit and the second gate driving circuit share a pull-up node; both the first gate driving circuit and the second gate driving circuit are connected to a first clock signal terminal that provides a first clock signal and a second clock signal terminal that provides a second clock signal.

[0031] When the potential of the first clock signal changes from a first level to a second level, the potential of the pull-up node is the first voltage value; when the potential of the second clock signal changes from a first level to a second level, the potential of the pull-up node is the second voltage value; the first voltage value and the second voltage value are not equal.

[0032] When the potential of the first clock signal changes from high to low, the potential of the pull-up node becomes the third voltage value; when the potential of the second clock signal changes from high to low, the potential of the pull-up node becomes the fourth voltage value; the third voltage value and the fourth voltage value are not equal.

[0033] In a third aspect, embodiments of the present invention provide a driving method applied to a display panel, the display panel including multiple rows of scan lines, multiple columns of data lines and multiple rows and columns of pixel circuits, the pixel circuits being electrically connected to the corresponding row of scan lines and the corresponding column of data lines respectively;

[0034] When the A data voltage provided by the Mth column data line is different from the B data voltage provided by the Mth column data line, the time for charging the Bth row Mth column pixel circuit through the B data voltage is controlled to be greater than the charging time threshold.

[0035] A, B, and M are all positive integers, and A and B are not equal.

[0036] Optionally, the charging time threshold is the scan time of one line.

[0037] Optionally, the pixel circuit in row A and column M is electrically connected to the scan line in row A, and the pixel circuit in row B and column M is electrically connected to the scan line in row B; the scan line in row A is used to provide the scan signal in row A, and the scan line in row B is used to provide the scan signal in row B.

[0038] The effective pulse width of the scan signal in row A is less than the effective pulse width of the scan signal in row B.

[0039] Optionally, the step of controlling the charging time of the pixel circuit in the Bth row and Mth column via the Bth data voltage to be greater than a charging time threshold includes:

[0040] By increasing the time interval between the falling edge time of the A-row scan signal and the falling edge time of the B-row scan signal, the charging time for the B-row M-column pixel circuit by the B-row data voltage is controlled to be greater than the charging time threshold.

[0041] In a fourth aspect, embodiments of the present invention provide a display device, including a display panel, a timing controller, and a driving module;

[0042] The timing controller includes a storage unit and a comparison unit;

[0043] The storage unit stores specific images;

[0044] The comparison unit is used to compare the screen to be displayed with a specific screen. When the screen to be displayed and the specific screen are the same or partially the same, an indication signal is provided to the driving module.

[0045] The driving module is used to invoke the driving method described above when it receives the indication signal.

[0046] Optionally, the display device according to at least one embodiment of the present invention further includes a display control circuit; the timing controller is used to provide a first input clock signal and a second input clock signal to the display control circuit;

[0047] The display control circuit is used to provide and output multiple output clock signals according to the first input clock signal and the second input clock signal;

[0048] The drive module is used to generate a corresponding scan signal based on the output clock signal.

[0049] Optionally, the display device according to at least one embodiment of the present invention further includes a display control circuit; the driving module includes an odd-numbered row driving circuit and an even-numbered row driving circuit;

[0050] The timing controller is used to provide the display control circuit with a first input clock signal, a second input clock signal, a third input clock signal and a fourth input clock signal;

[0051] The display control circuit is used to provide a first set of output clock signals to the odd-row driving circuit according to the first input clock signal and the second input clock signal, and to provide a second set of output clock signals to the even-row driving circuit according to the third input clock signal and the fourth input clock signal;

[0052] The odd row driving circuit is used to generate a corresponding odd row scanning signal according to the first set of output clock signals;

[0053] The even-row driving circuit is used to generate corresponding even-row scanning signals based on the second set of output clock signals. Attached Figure Description

[0054] Figure 1A This is a timing diagram corresponding to the driving method described in at least one embodiment of the present invention;

[0055] Figure 1B This is the screen displayed when an H2Line display malfunctions.

[0056] Figure 1C This refers to the display screen when the H2Line screen is displayed normally. Figure 2 This is a timing diagram corresponding to the driving method described in at least one embodiment of the present invention;

[0057] Figure 3 This is a timing diagram corresponding to the driving method described in at least one embodiment of the present invention;

[0058] Figure 4 This is a timing diagram corresponding to the driving method described in at least one embodiment of the present invention;

[0059] Figure 5A This is a timing diagram corresponding to the driving method described in at least one embodiment of the present invention;

[0060] Figure 5B Is with Figure 5A The timing diagram of the corresponding scan signals;

[0061] Figure 5C yes Figure 5A The timing diagram of the scanning signal shown in the embodiment of the present invention and Figure 5B A comparison diagram of the timing diagrams of the relevant scan signals is shown;

[0062] Figure 6A It is a waveform diagram of the potential of the pull-up node PU;

[0063] Figure 6B This is a circuit diagram of at least one embodiment of a gate drive circuit employing a pull-up node PU;

[0064] Figure 6C It is a waveform diagram of the potential of the pull-up node PU;

[0065] Figure 7 This is a timing diagram corresponding to the driving method described in at least one embodiment of the present invention.

[0066] Figure 8 This is a timing diagram corresponding to the driving method described in at least one embodiment of the present invention;

[0067] Figure 9A This is a timing diagram corresponding to the driving method described in at least one embodiment of the present invention;

[0068] Figure 9B Is with Figure 9A The timing diagram of the corresponding scan signals;

[0069] Figure 9C yes Figure 9A The timing diagram of the scanning signal shown in the embodiment of the present invention and Figure 9B A comparison diagram of the timing diagrams of the relevant scan signals is shown;

[0070] Figure 10 This is a schematic diagram showing the connection relationship between the timing controller and the driving module in the display device according to at least one embodiment of the present invention;

[0071] Figure 11 This is a structural diagram of the display device according to at least one embodiment of the present invention;

[0072] Figure 12 This is a schematic diagram of the signal transmission relationship between the timing controller, data driver, and level converter in the display device according to at least one embodiment of the present invention;

[0073] Figure 13 Structural diagram of the display device according to at least one embodiment of the present invention;

[0074] Figure 14 This is the present invention. Figure 13 The timing diagram shows the operation of at least one embodiment of the display device. Detailed Implementation

[0075] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0076] The driving method described in at least one embodiment of the present invention is applied to a display panel, the display panel including multiple rows of scan lines, multiple columns of data lines, and multiple rows and columns of pixel circuits, wherein the pixel circuits are electrically connected to corresponding rows of scan lines and corresponding columns of data lines respectively; the driving method includes:

[0077] The first charging time is controlled to be greater than 0.5 times the second charging time, and the first charging time is controlled to be less than the second charging time.

[0078] Wherein, the first charging time is the time for the A-row M-column pixel circuit to be charged by the A-th data voltage on the M-th column data line;

[0079] The second charging time is the time it takes to charge the pixel circuit in row B and column M using the A-th data voltage and the B-th data voltage on the M-th column data line;

[0080] A, B, and M are all positive integers.

[0081] In specific implementation, the A-th data voltage and the B-th data voltage can be the same. Since the charging time for the B-th row and M-th column pixel circuit is sufficient, but the charging time for the A-th row and M-th column pixel circuit is insufficient, at least one embodiment of the present invention sets the first charging time to be greater than 0.5 times the second charging time. This ensures that the charging time for the A-th row and M-th column pixel circuit is increased while the charging time for the B-th row and M-th column pixel circuit remains unchanged, thereby improving the charging rate of the A-th row and M-th column pixel circuit and enhancing display uniformity.

[0082] In at least one embodiment of the present invention, B is greater than A, and BA can be equal to 1, but is not limited thereto.

[0083] In practice, when A and B are not equal, the voltage of data A and the voltage of data B may be different.

[0084] Optionally, the pixel circuit in row A and column M is electrically connected to the scan line in row A, and the pixel circuit in row B and column M is electrically connected to the scan line in row B; the scan line in row A is used to provide the scan signal in row A, and the scan line in row B is used to provide the scan signal in row B.

[0085] The driving method includes: controlling the time interval between the falling edge time of the A-row scan signal and the falling edge time of the B-row scan signal to be less than half the time for charging the B-row M-column pixel circuit by the A-row data voltage and the B-row data voltage, so as to control the first charging time to be greater than 0.5 times the second charging time, and controlling the first charging time to be less than the second charging time.

[0086] In at least one embodiment of the present invention, the falling edge time of the A-row scan signal is the time when the falling edge of the A-row scan signal occurs, and the falling edge time of the B-row scan signal is the time when the falling edge of the B-row scan signal occurs.

[0087] The time interval between the falling edge time of the A-row scan signal and the falling edge time of the B-row scan signal can be: the time interval between the time point when the potential of the A-row scan signal drops to a low potential and the time point when the potential of the B-row scan signal drops to a low potential.

[0088] In at least one embodiment of the present invention, the Ath data voltage and the Bth data voltage may be the same, but are not limited thereto.

[0089] Optionally, the effective pulse width of the A-row scan signal is the same as the effective pulse width of the B-row scan signal.

[0090] Optionally, the effective pulse width of the A-row scan signal is greater than the effective pulse width of the B-row scan signal.

[0091] like Figure 1A As shown, Vd represents the data voltage provided by the Mth column data line, SA represents the scan signal for the Ath row, and SB represents the scan signal for the Bth row.

[0092] In at least one embodiment of the present invention, B may be equal to A+1, but is not limited thereto.

[0093] like Figure 1A As shown, the first charging time t1 is the time for the pixel circuit in the Ath row and Mth column to be charged by the Ath data voltage;

[0094] The second charging time, labeled t2, is the time during which the pixel circuit in row B and column M is charged using the data voltages A and B.

[0095] like Figure 1A As shown, t1 is greater than 0.5 times t2, and t1 is less than t2.

[0096] exist Figure 1A In at least one embodiment shown, both the Ath data voltage and the Bth data voltage are low voltages.

[0097] like Figure 1A As shown, the effective pulse width of the A-row scan signal SA is different from that of the B-row scan signal SB, and the effective pulse width of the A-row scan signal SA is greater than that of the B-row scan signal SB.

[0098] In such Figure 1AIn at least one embodiment shown, the effective pulse width of the A-row scan signal SA can be the duration during which the potential of the A-row scan signal SA remains high.

[0099] The effective pulse width of the B-th row scan signal SB can be the duration during which the potential of the B-th row scan signal SB remains at a high voltage.

[0100] Figure 1A The timing sequence shown can be the timing sequence corresponding to the H2Line Pattern.

[0101] H2Line Pattern refers to a pattern with two rows of light and two rows of dark.

[0102] In high-resolution products, HSR (Hardware Super Resolution) timing ensures that even-numbered rows are charged, while the charging time for odd-numbered rows is halved. At high refresh rates and high resolutions, the 1H time (which is the charging time for one row of pixels, and is related to the display panel's resolution and refresh rate) is relatively short, resulting in excessively short charging times for odd-numbered rows. In at least one embodiment of this invention, the falling edge of the odd-numbered row scan signal can be appropriately delayed to increase the charging time of the odd-numbered row pixel circuits without affecting the charging time of the even-numbered row pixel circuits. As seen in the actual H2Line 255 footage, conventional HSR timing results in three rows of pixels being lit due to insufficient charging and incorrect charging. It should be noted that in this invention, odd and even rows are relative concepts. For example, if row a is an odd row, then row a+1 can be defined as an even row.

[0103] When displaying the H2Line screen, such as Figure 1B As shown, when there is a display error, three lines of pixels are highlighted.

[0104] Two lines of dark pixels, as... Figure 1C As shown, when the display is normal, it shows a screen with two rows of pixels bright and two rows of pixels dark.

[0105] like Figure 2 As shown, S1 is the first row scan signal, S2 is the second row scan signal, S3 is the third row scan signal, S4 is the fourth row scan signal, S5 is the fifth row scan signal, and so on. S11 is the eleventh row scan signal, and S12 is the twelfth row scan signal.

[0106] exist Figure 2 In the diagram, t11 represents the time during which the first row and M column pixel circuit is charged using the first data voltage, and t12 represents the time during which the second row and M column pixel circuit is charged using the first data voltage.

[0107] The time t21 is the time to charge the third row and M column pixel circuit with the second data voltage, and the time t22 is the time to charge the fourth row and M column pixel circuit with the second data voltage.

[0108] The time labeled t31 is the time to charge the pixel circuit in the fifth row and M column using the third data voltage, and the time labeled t32 is the time to charge the pixel circuit in the sixth row and M column using the third data voltage.

[0109] The time for charging the pixel circuit in the seventh row and M column using the fourth data voltage is labeled t41, and the time for charging the pixel circuit in the eighth row and M column using the fourth data voltage is labeled t42.

[0110] The time labeled t51 is the time to charge the pixel circuit in the ninth row and Mth column using the fifth data voltage, and the time labeled t52 is the time to charge the pixel circuit in the tenth row and Mth column using the fifth data voltage.

[0111] The time t61 represents the time for charging the pixel circuit in the eleventh row and Mth column using the sixth data voltage, and the time t62 represents the time for charging the pixel circuit in the twelfth row and Mth column using the sixth data voltage.

[0112] like Figure 2 As shown, t12 is greater than t11, and t11 is greater than 0.5 times t12; t22 is greater than t21, and t21 is greater than 0.5 times t22; t32 is greater than t31, and t31 is greater than 0.5 times t32; t42 is greater than t41, and t41 is greater than 0.5 times t42; t52 is greater than t51, and t51 is greater than 0.5 times t52; t62 is greater than t61, and t61 is greater than 0.5 times t62.

[0113] exist Figure 2 In the diagram, S6 represents the sixth scan signal, S7 represents the seventh scan signal, S8 represents the eighth scan signal, S9 represents the ninth scan signal, and S10 represents the tenth scan signal.

[0114] exist Figure 2 In at least one of the embodiments shown, the effective pulse width of S1 can be the same as the effective pulse width of S2, the effective pulse width of S3 can be the same as the effective pulse width of S4, the effective pulse width of S5 can be the same as the effective pulse width of S6, the effective pulse width of S7 can be the same as the effective pulse width of S8, the effective pulse width of S9 can be the same as the effective pulse width of S10, and the effective pulse width of S11 can be the same as the effective pulse width of S12.

[0115] exist Figure 2In at least one embodiment shown, the effective pulse width of S1 can be: the duration for which the potential of S1 remains high; the effective pulse width of S2 can be: the duration for which the potential of S2 remains high; the effective pulse width of S3 can be: the duration for which the potential of S3 remains high; the effective pulse width of S4 can be: the duration for which the potential of S4 remains high; the effective pulse width of S5 can be: the duration for which the potential of S5 remains high; the effective pulse width of S6 can be: the duration for which the potential of S6 remains high; the effective pulse width of S7 can be: the duration for which the potential of S7 remains high; the effective pulse width of S8 can be: the duration for which the potential of S8 remains high; the effective pulse width of S9 can be: the duration for which the potential of S9 remains high; the effective pulse width of S10 can be: the duration for which the potential of S10 remains high; the effective pulse width of S11 can be: the duration for which the potential of S11 remains high; and the effective pulse width of S12 can be: the duration for which the potential of S12 remains high.

[0116] In at least one embodiment of the present invention, in the Nth frame, the pixel circuit in the Ath row and Mth column is an even-numbered row pixel circuit, and the pixel circuit in the Bth row and Mth column is an odd-numbered row pixel circuit; N is an integer.

[0117] In at least one embodiment of the present invention, in the N+1th frame, the pixel circuit in row A and column M is an odd-numbered row pixel circuit, and the pixel circuit in row B and column M is an even-numbered row pixel circuit; N is a positive integer.

[0118] like Figure 3 As shown, in the HSR timing, in odd-numbered frames, the even-numbered pulses of the TP signal are blanked, meaning the two rows of data signals are identical. The charging time for the pixel circuit in odd-numbered rows is 2 hours, ensuring sufficient charging time. Even-numbered rows are interpolated data between adjacent rows, i.e., reference data. Figure 3 For S1, if S1 is defined as the first row scan signal, then the first row pixel circuit (connected to the first row scan signal S1) charges the first data voltage Vd1 for 2 hours; the third row pixel circuit (connected to the third row scan signal S3) charges the third data voltage Vd3 for 2 hours; and the fifth row pixel circuit (connected to the fifth row scan signal S5) charges the fifth data voltage Vd5 for 2 hours. The second row pixel circuit (connected to the second row scan signal S2) charges the first data voltage Vd1 and the third data voltage Vd3. During the overlap of the effective levels (high levels) of S1 and S2, the second row pixel circuit is charged with the first data voltage Vd1, which is the pre-charge voltage for the second row. The third data voltage Vd3 is the actual data voltage required to charge the second row pixel circuit. (Refer to...) Figure 3As shown, for odd-numbered row pixel circuits, the actual charging time for the data voltage is 2 hours, while for even-numbered row pixel circuits, the actual charging time for their respective row's data voltage is less than 2 hours. To improve display quality and balance the charging difference between odd-numbered and even-numbered row pixel circuits, the falling edge of the even-numbered row scan signal can be shifted later. In this case, the effective pulse width corresponding to each row scan signal can be the same, as shown in the reference... Figure 3 The effective pulse widths corresponding to S1, S2, S3, S4, S5, and S6 are the same, such as the high-level pulse widths. Of course, it is also possible to both move the effective pulse width of the even-numbered row scanning signal and adjust the pulse width of the even-numbered row scanning signal, that is, increase the pulse width of the even-numbered row scanning signal to improve the display quality. This is not limited here.

[0119] like Figure 3 As shown, the falling edge of the even-numbered row scan signal can be shifted backward, that is, the effective pulse of the even-numbered row can be moved backward, in order to increase the charging time for the even-numbered row pixel circuit, thereby improving display uniformity. (Refer to...) Figure 3 The actual charging time of the third data voltage Vd3 in the second row pixel circuit (which is connected to the second row scanning signal S2) is greater than 1 hour. If it is not moved, the actual charging time of the third data voltage Vd3 in the second row pixel circuit is less than or equal to 1 hour. Therefore, the embodiment of the present invention can balance the charging time of different rows and improve the display quality.

[0120] exist Figure 3 In the diagram, TP is the data voltage trigger control signal; S1 is the first row scan time, S2 is the second row scan time, S3 is the third row scan time, S4 is the fourth row scan time, S5 is the fifth row scan time, and S6 is the sixth row scan time.

[0121] When the potential of the TP signal rises from low level to high level, the corresponding data line changes the data voltage it provides. That is, the rising edge of the TP signal triggers the data signal to be written. Optionally, the falling edge of the TP signal can also trigger the data signal to be written, which is not limited here.

[0122] like Figure 3 As shown, the falling edge of S2 is shifted backward, the falling edge of S4 is shifted backward, and the falling edge of S6 is shifted backward to improve the charging time of even-numbered pixel circuits that actually require less charging, such as the charging time of the second row of pixel circuits, the charging time of the fourth row of pixel circuits, and the charging time of the sixth row of pixel circuits.

[0123] exist Figure 3 In the diagram, the signal labeled STV1 is the start signal; the signal labeled Vd1 is the first data voltage; the signal labeled Vd3 is the third data voltage; the signal labeled Vd5 is the fifth data voltage; and the signal labeled Vd7 is the seventh data voltage.

[0124] exist Figure 3 In the diagram, Vd1, Vd3, Vd5, and Vd7, indicated by the dashed box, represent the data voltages on the M-th data line during that time period.

[0125] like Figure 4 As shown, in the HSR timing, in even-numbered frames, the odd number of pulses of the TP signal are blanked, meaning the two rows of data signals are identical. The charging time for the pixel circuit in even-numbered rows is 2 hours, ensuring sufficient charging time. Odd-numbered rows are interpolated data between adjacent rows, and reference data is used. Figure 4 For S2, if S2 is defined as the second row scan signal, then the second row pixel circuit (connected to the second row scan signal S2) charges the second data voltage Vd2 for 2 hours; the fourth row pixel circuit (connected to the fourth row scan signal S4) charges the fourth data voltage Vd4 for 2 hours; and the sixth row pixel circuit (connected to the sixth row scan signal S6) charges the sixth data voltage Vdd for 2 hours. The third row pixel circuit (connected to the third row scan signal S3) charges the second data voltage Vd2 and the fourth data voltage Vd4. During the overlap of the effective levels (high levels) of S2 and S3, the third row pixel circuit is charged with the second data voltage Vd2, which is the pre-charge voltage for the third row. The fourth data voltage Vd4 is the actual data voltage required to charge the third row pixel circuit. (Refer to...) Figure 4 As shown, for even-numbered row pixel circuits, the actual charging time for the data voltage is 2 hours, while for odd-numbered row pixel circuits, the actual charging time for their respective row's data voltage is less than 2 hours. To improve display quality and balance the charging difference between odd-numbered and even-numbered row pixel circuits, the falling edge of the odd-numbered row scan signal can be shifted later. In this case, the effective pulse width corresponding to each row scan signal can be the same, as shown in the reference... Figure 4 The effective pulse widths corresponding to S1, S2, S3, S4, S5, and S6 are the same, such as the high-level pulse widths being the same. Of course, it is also possible to both move the effective pulse width of the odd-numbered row scanning signal and adjust the pulse width of the odd-numbered row scanning signal, that is, increase the pulse width of the odd-numbered row scanning signal to improve the display quality. This is not limited here.

[0126] like Figure 4 As shown, the falling edge of the odd-row scan signal can be shifted backward, that is, the effective pulse of the odd-row can be moved backward, thereby increasing the charging time for the odd-row pixel circuit and improving display uniformity. (Reference) Figure 4The actual charging time of the fourth data voltage Vd4 in the third row pixel circuit (which is connected to the third row scanning signal S3) is greater than 1 hour. If it is not moved, the actual charging time of the fourth data voltage Vd4 in the third row pixel circuit is less than or equal to 1 hour. Therefore, the embodiment of the present invention can balance the charging time of different rows and improve the display quality.

[0127] exist Figure 4 In the diagram, TP is the data voltage trigger control signal; S1 is the first row scan time, S2 is the second row scan time, S3 is the third row scan time, S4 is the fourth row scan time, S5 is the fifth row scan time, and S6 is the sixth row scan time.

[0128] When the potential of the TP signal rises from low level to high level, the corresponding data line changes the data voltage it provides. That is, the rising edge of the TP signal triggers the data signal to be written. Optionally, the falling edge of the TP signal can also trigger the data signal to be written, which is not limited here.

[0129] like Figure 4 As shown, the falling edge of S1 is shifted backward, the falling edge of S3 is shifted backward, and the falling edge of S5 is shifted backward to improve the charging time of the odd-numbered pixel circuits that actually require less charging, such as the charging time of the first row of pixel circuits, the charging time of the third row of pixel circuits, and the charging time of the fifth row of pixel circuits.

[0130] exist Figure 4 In the diagram, the voltage labeled STV1 is the start signal; the voltage labeled Vd2 is the second data voltage; the voltage labeled Vd4 is the fourth data voltage; and the voltage labeled Vd6 is the sixth data voltage.

[0131] exist Figure 4 In the diagram, Vd2, Vd4, and Vd6, indicated by the dashed box, represent the data voltages on the M-th data line during that time period.

[0132] It should be noted that the present invention can also blank odd-numbered rows of data in odd-numbered frames and even-numbered rows of data in even-numbered frames; this is not limited here. Specifically, blanking in this invention can be performed after the complete image data output by the system chip (SOC) is processed by the timing controller (TCON), or the image input to the SOC can be the processed image data, i.e., only retaining odd-numbered or even-numbered rows of data signals. The specific blanking method is not limited here.

[0133] In at least one embodiment of the present invention, the A-th data voltage and the B-th data voltage are the same data voltage; the pixel circuit of the A-th row and the M-th column is electrically connected to the A-th row scan line, and the pixel circuit of the B-th row and the M-th column is electrically connected to the B-th row scan line; the A-th row scan line is used to provide the A-th row scan signal, and the B-th row scan line is used to provide the B-th row scan signal;

[0134] The driving method further includes: controlling the first time to be greater than the second time;

[0135] The first time is the time when the Mth column data line begins to provide the Ath data voltage, and the time interval between the falling edge time of the Ath row scan signal;

[0136] The second time is the time interval between the falling edge time of the A-line scan signal and the falling edge time of the B-line scan signal.

[0137] In Normal display mode, scanning signal phase adjustment can also be used to improve issues of incorrect charging and insufficient charging in some Pattern displays. For example... Figure 5A As shown, taking H2Line images as an example, the charging time of odd-row pixel circuits can be increased by delaying the phase of the odd-row scanning signal, thereby increasing their charging rate.

[0138] exist Figure 5A In the diagram, Vd represents the data voltage provided by the Mth column data line, SA represents the first row scan signal, and SB represents the second row scan signal.

[0139] exist Figure 5A In at least one embodiment shown, both the Ath data voltage and the Bth data voltage are low voltages.

[0140] like Figure 5A As shown, the time interval between the start of the Mth column data line providing the Ath data voltage and the falling edge time of the Ath row scan signal SA is the first time t01;

[0141] The time interval between the falling edge time of the scan signal in row A and the falling edge time of the scan signal in row B is the second time t02;

[0142] By setting the first time t01 to be greater than the second time t02, that is, delaying the phase of the A-row scanning signal SA, the charging time of the A-row M-column pixel circuit is increased, so that the charging time of the A-row M-column pixel circuit is greater than 1H time, and the charging time of the B-row M-column pixel circuit is equal to 2H time.

[0143] Optionally, the pixel circuit in row A and column M is electrically connected to the scan line in row A, and the pixel circuit in row B and column M is electrically connected to the scan line in row B.

[0144] The A-row scan line is used to provide the A-row scan signal, and the B-row scan line is used to provide the B-row scan signal;

[0145] The effective pulse width of the scan signal in row A is not equal to the effective pulse width of the scan signal in row B.

[0146] like Figure 5A As shown, the effective pulse width of the scan signal SA in row A is not equal to the effective pulse width of the scan signal SB in row B;

[0147] The effective pulse width of the scan signal SA in row A is greater than the effective pulse width of the scan signal SB in row B.

[0148] The effective pulse width of the A-th row scan signal SA is the duration during which the potential of SA remains at a high voltage.

[0149] The effective pulse width of the B-row scan signal SB is the duration during which the potential of SB remains at a high voltage.

[0150] like Figure 5A As shown, the high-level pulse width of the data voltage Vd is equal to the low-level pulse width of the data voltage Vd.

[0151] For reference Figure 5A The scanning signal phase adjustment scheme shown can improve the problem of insufficient pixel charging in the dividing lines by delaying the overall or partial phase of the scanning signal, or advancing the overall or partial phase of the scanning signal, for patterns such as checkerboard patterns, H3Line patterns (H3Line patterns can be three bright lines and three dark lines), and crosstalk patterns.

[0152] Figure 5B Is with Figure 5A The corresponding timing diagram of the scan signals. For example... Figure 5B As shown, the first time t01 is equal to the second time t02, and the effective pulse width of the A-row scan signal SA is equal to the effective pulse width of the B-row scan signal SB.

[0153] Figure 5C yes Figure 5A The timing diagram of the scanning signal shown in the embodiment of the present invention and Figure 5B The comparison diagram shows the timing diagrams of the relevant scan signals.

[0154] The driving method described in at least one embodiment of the present invention is applied to a display panel, the display panel including multiple rows of scan lines, multiple columns of data lines, and multiple rows and columns of pixel circuits, wherein the pixel circuits are electrically connected to corresponding rows of scan lines and corresponding columns of data lines respectively; the driving method includes:

[0155] When the fall time of the A-row scan signal provided by the A-row scan line is less than the fall time of the B-row scan signal provided by the B-row scan line, the third time is controlled to be greater than the fourth time.

[0156] The third time is the time from when the Mth column data line starts providing the Ath data voltage to the time when the Ath row Mth column pixel circuit starts to decrease, and the time interval between these two times.

[0157] The fourth time is the time from when the Mth column data line starts providing the Bth data voltage to the time when the pixel circuit of the Bth row and Mth column starts to decrease, and the time interval between these two times.

[0158] A, B, and M are all positive integers, and A is not equal to B.

[0159] In at least one embodiment of the present invention, when the fall time of the scan signal in row A is less than the fall time of the scan signal in row B, the time interval between the time when the data line in column M starts to provide the data voltage in row A to the pixel circuit in column M of row A and the time when the potential of the scan signal in row A starts to fall can be set to be greater than the time interval between the time when the data line in column M starts to provide the data voltage in row B to the pixel circuit in column M of row B and the time when the potential of the scan signal in row B starts to fall. This makes the charging time of the pixel circuit in column M of row A and the charging time of the pixel circuit in column M of row B approximately the same, thereby improving display uniformity.

[0160] In at least one embodiment of the present invention, the fall time of the A-row scan signal is: the time interval between the point at which the potential of the A-row scan signal begins to fall from a high voltage and the point at which the potential of the A-row scan signal falls to a low voltage.

[0161] The fall time of the B-th row scan signal is the time interval between the point when the potential of the B-th row scan signal starts to fall from a high voltage to the point when the potential of the B-th row scan signal falls to a low voltage.

[0162] In at least one embodiment of the present invention, the Ath data voltage is not equal to the Bth data voltage, but this is not a limitation.

[0163] Optionally, the driving method is applied to a display panel, the display panel including a first gate driving circuit and a second gate driving circuit;

[0164] The first gate driving circuit and the second gate driving circuit share a pull-up node; both the first gate driving circuit and the second gate driving circuit are connected to a first clock signal terminal that provides a first clock signal and a second clock signal terminal that provides a second clock signal.

[0165] When the potential of the first clock signal changes from a first level to a second level, the potential of the pull-up node is the first voltage value; when the potential of the second clock signal changes from a first level to a second level, the potential of the pull-up node is the second voltage value; the first voltage value and the second voltage value are not equal.

[0166] When the potential of the first clock signal changes from high to low, the potential of the pull-up node becomes the third voltage value; when the potential of the second clock signal changes from high to low, the potential of the pull-up node becomes the fourth voltage value; the third voltage value and the fourth voltage value are not equal.

[0167] In at least one embodiment of the present invention, the first level can be a low level and the second level can be a high level, but is not limited thereto.

[0168] Figure 6A This is a timing diagram of the potential of the pull-up node PU.

[0169] In at least one embodiment of the present invention, adjacent row gate driving circuits share a pull-up node. At this time, since the potentials of the pull-up nodes corresponding to the adjacent row gate driving signals are different, the charging of adjacent row gate driving circuits is different. Therefore, the driving method described in the embodiments of the present invention improves the above-mentioned charging difference problem by changing the timing of the scan signal (the scan signal can be a gate driving signal).

[0170] Figure 6B This is a circuit diagram of at least one embodiment of a gate drive circuit employing a pull-up node PU, wherein the gate drive circuit generates two levels of gate drive signals under the control of the pull-up node PU.

[0171] like Figure 6B As shown, at least one embodiment of the gate drive circuit includes a first transistor M1, a second transistor M2 and a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, a first capacitor C01, an eighth transistor M8, a ninth transistor M9, a first output transistor MO1, a second output transistor MO2, a first carry output transistor MC1, a first output reset transistor MF1, a second output reset transistor MF2, and a first carry reset transistor MR1;

[0172] The gate of the first transistor M1 is electrically connected to the first input terminal I1, the source of the first transistor M1 is electrically connected to the first input voltage terminal VI1, and the drain of the first transistor M1 is electrically connected to the pull-up node PU.

[0173] The gate of the second transistor M2 is electrically connected to the first reset terminal R1, the source of the second transistor M2 is electrically connected to the pull-up node PU, and the drain of the second transistor M2 is electrically connected to the first low voltage terminal LVSS.

[0174] The gate of the third transistor M3 is electrically connected to the first pull-down node PD1, the source of the third transistor M3 is electrically connected to the pull-up node PU, and the drain of the third transistor M3 is electrically connected to the first low-voltage terminal LVSS.

[0175] The gate and source of the fourth transistor M4 are both electrically connected to the first control voltage terminal VDDO, and the drain of the fourth transistor M4 is electrically connected to the first pull-down control node.

[0176] The gate of the fifth transistor M5 is electrically connected to the first pull-down control node, the source of the fifth transistor M5 is electrically connected to the first control voltage terminal VDDO, and the drain of the fifth transistor M5 is electrically connected to the first pull-down node PD1.

[0177] The gate of the sixth transistor M6 is electrically connected to the pull-up node PU, the source of the sixth transistor M6 is electrically connected to the first pull-down node PD1, and the drain of the sixth transistor M6 is electrically connected to the first low-voltage terminal LVSS.

[0178] The gate of the seventh transistor M7 is electrically connected to the pull-up node PU, the source of the seventh transistor M7 is electrically connected to the first pull-down control node, and the drain of the seventh transistor M7 is electrically connected to the first low voltage terminal LVSS.

[0179] The gate of the eighth transistor M8 is electrically connected to the first input voltage terminal VI1, the source of the eighth transistor M8 is electrically connected to the pull-up node PU, and the drain of the eighth transistor M8 is electrically connected to the first low voltage terminal LVSS.

[0180] The gate of the ninth transistor M9 is electrically connected to the frame reset terminal TR, the source of the ninth transistor M9 is electrically connected to the pull-up node PU, and the drain of the ninth transistor M9 is electrically connected to the first low voltage terminal LVSS.

[0181] The gate of the first output transistor MO1 is electrically connected to the pull-up node PU, the source of the first output transistor MO1 is electrically connected to the first clock signal terminal K1, and the drain of the first output transistor MO1 is electrically connected to the first scan signal output terminal G1.

[0182] The gate of the second output transistor MO2 is electrically connected to the pull-up node PU, the source of the second output transistor MO2 is electrically connected to the second clock signal terminal K2, and the drain of the second output transistor MO2 is electrically connected to the second scan signal output terminal G2.

[0183] The gate of the first carry output transistor MC1 is electrically connected to the pull-up node PU, the source of the first carry output transistor MC1 is electrically connected to the first carry clock signal terminal KC1, and the drain of the first carry output transistor MC1 is electrically connected to the first carry signal output terminal Co1.

[0184] The gate of the first output reset transistor MF1 is electrically connected to the first pull-down node PD1, the source of the first output reset transistor MF1 is electrically connected to the first scan signal output terminal G1, and the drain of the first output reset transistor MF1 is electrically connected to the second low voltage terminal VSS.

[0185] The gate of the second output reset transistor MF2 is electrically connected to the first pull-down node PD1, the source of the second output reset transistor MF2 is electrically connected to the second scan signal output terminal G2, and the drain of the second output reset transistor MF2 is electrically connected to the second low voltage terminal VSS.

[0186] The gate of the first carry reset transistor MR1 is electrically connected to the first pull-down node PD1, the source of the first carry reset transistor MR1 is electrically connected to the first carry signal output terminal Co1, and the drain of the first carry reset transistor MR1 is electrically connected to the first low voltage terminal LVSS.

[0187] The first terminal of the first capacitor C01 is electrically connected to the pull-up node PU, and the second terminal of the first capacitor C01 is electrically connected to the second scan signal output terminal G2.

[0188] like Figure 6B When at least one embodiment of the gate drive circuit shown is in operation, I1 is electrically connected to the first carry signal output terminal of the adjacent previous stage gate drive circuit, and VI1 is electrically connected to the first drive signal output terminal of the adjacent previous stage gate drive circuit.

[0189] When I1 provides a high voltage signal, M1 turns on, as shown below. Figure 6C As shown, the potential of PU is pulled up to a high voltage. At this time, K1, K2 and KC1 all provide low voltage signals, so G1, G2 and Co1 all output low voltage signals. M4 is turned on, and M6 and M7 are turned on to control the potential of PD1 to a low voltage. The transistors whose gates are electrically connected to PD1 are turned off.

[0190] Then, the potential of the first clock signal provided by K1 changes from low to high, as follows: Figure 6C As shown, the potential of PU is raised to a higher potential. Within the first time t1, the potential of the pull-up node PU rises by a first potential height Vg1, and the potential of the pull-up node PU becomes a first voltage value Vb1.

[0191] Then, the potential of the second clock signal provided by K2 jumps from low level to high level, such as... Figure 6C As shown, the potential of PU is raised to a higher potential. During the second time t2, the potential of the pull-up node PU rises to a second potential height Vg2, and the potential of the pull-up node PU becomes a second voltage value Vb2.

[0192] Then, the potential of the first clock signal provided by K1 changes from high level to low level, such as... Figure 6C As shown, the potential of PU is lowered to a lower potential. During the third time t3, the potential of the pull-up node PU drops by the third potential height Vg3, and the potential of the pull-up node PU becomes the third voltage value Vb3.

[0193] Then, the potential of the second clock signal provided by K2 changes from high level to low level, such as... Figure 6C As shown, the potential of PU is lowered to a lower potential. During the fourth time t4, the potential of the pull-up node PU drops by the fourth potential height Vg4, and the potential of the pull-up node PU becomes the fourth voltage value Vb4. At this time, the potential of the pull-up node PU can be low level.

[0194] When the potential of PU is high, MO1, MO2 and MC1 are turned on, G1 is connected to K1, G2 is connected to K2, Co1 is connected to KC1, G1 outputs the corresponding first drive signal, G2 outputs the corresponding second drive signal, and Co1 outputs the corresponding first carry signal.

[0195] When the potential of PU is low, M4 is turned on, M6 and M7 are turned off, the potential of the first pull-down control node is high, M5 is turned on, the potential of PD1 is high, MF1, MF2 and MR1 are turned on, and G1, G2 and Co1 all output low level.

[0196] like Figure 6B In at least one embodiment of the gate drive circuit shown, when the potential of PU drops from high to low when the potential of the second clock signal provided by K2 drops from high to low, the potential of PU is lower than that of the first clock signal provided by K1 drops from high to low. Therefore, the fall time of the second scan signal provided by the second scan signal output terminal G2 is greater than the fall time of the first scan signal provided by the first scan signal output terminal G1.

[0197] like Figure 7As shown, Vd represents the data voltage provided by the Mth column data line; S1 represents the first row scan line; and S2 represents the second row scan line.

[0198] The first data voltage is a high voltage signal, and the second data voltage is a low voltage signal;

[0199] The third time t03 is the time between when the first data voltage is supplied to the first row and the first column of the pixel circuit from the start of the Mth column data line and the time when the potential of the first row scan signal begins to drop;

[0200] The fourth time t04 is the time from when the second data voltage is provided to the second row and the second column of the pixel circuit from the start of the Mth column data line, to the time when the potential of the second row scan signal begins to drop, and the time interval between them.

[0201] Since the fall time of S2 is greater than the fall time of S1, by setting t03 to be greater than t04, the time for charging the first row and M column pixel circuit by increasing the first data voltage is made possible. Optionally, the charging time of the first row and M column pixel circuit is approximately equal to the charging time of the second row and M column pixel circuit by the voltage of the second data. It should be noted that the first row and the second row here are examples and do not represent the actual first row and the second row in the display panel. They can be any other adjacent rows of pixels, which is not limited here.

[0202] like Figure 7 As shown, the data charging time for a scan line with a falling edge delay is less than the data charging time for a scan line without a falling edge delay; for example, the data charging time of the first row pixel circuit (the first row pixel circuit is connected to the first row scan signal S1) is less than the data charging time of the second row pixel circuit (the second row pixel circuit is connected to the second row scan signal S2).

[0203] Optionally, the time interval between the time when the potential of the A-row scan signal begins to fall and the time when the M-column data line stops providing the A-data voltage is greater than the time interval between the time when the potential of the B-row scan signal begins to fall and the time when the M-column data line stops providing the B-data voltage.

[0204] like Figure 8 As shown, in Figure 7 On this basis,

[0205] The time interval between the time when the potential of the first row scan signal S1 begins to decrease and the time when the data line of the Mth column stops providing the first data voltage is the fifth time t05;

[0206] The time interval between the time when the potential of the second row scanning signal S2 begins to decrease and the time when the data line of the Mth column stops providing the second data voltage is the sixth time t06;

[0207] t05 is greater than t06.

[0208] exist Figure 8 In at least one embodiment shown, the fifth time t05 is the first GOE time (GOE time can be the data voltage delay time), and the sixth time t06 is the second GOE time.

[0209] The driving method described in at least one embodiment of the present invention is applied to a display panel, the display panel including multiple rows of scan lines, multiple columns of data lines and multiple rows and columns of pixel circuits, the pixel circuits being electrically connected to the corresponding row scan lines and the corresponding column data lines respectively;

[0210] When the A data voltage provided by the Mth column data line is different from the B data voltage provided by the Mth column data line, the time for charging the Bth row Mth column pixel circuit through the B data voltage is controlled to be greater than the charging time threshold.

[0211] A, B, and M are all positive integers, and A and B are not equal.

[0212] In practical implementation, when the A-th data voltage is different from the B-th data voltage, the charging time of the B-th row and M-th column pixel circuit through the B-th data voltage can be controlled to be greater than the charging time threshold, so as to improve the charging time of the first row pixel circuit after the data voltage conversion, improve the problem of insufficient charging, and improve the first row display problem at the boundary.

[0213] exist Figure 9A In the diagram, Vd represents the data voltage provided by the Mth column data line, SA represents the scan signal for the Ath row, and SB represents the scan signal for the Bth row.

[0214] like Figure 9A As shown, when the chessboard pattern (e.g., black and white intervals in the row direction and black and white intervals in the column direction) changes from black to white, for example, from grayscale 0 to grayscale 255 (or other low grayscale to high grayscale), the voltage of data A is low and the voltage of data B is high. In this embodiment of the invention, the falling edge of the scanning signal of row A is advanced, and the data voltage provided by the data line of column M is synchronously controlled to change from low voltage to high voltage, so as to increase the charging time of the first row pixel circuit after the image conversion (the first row pixel circuit after the image conversion is the row B pixel circuit), thereby improving the problem of insufficient charging time of the first row pixel circuit after the image conversion. At the same time, the last row pixel circuit before the image conversion (the last row pixel circuit before the image conversion is the row A pixel circuit) is not affected in its charging because the pre-charging voltage and the actual voltage are the same.

[0215] Optionally, the charging time threshold can be 1 hour, but is not limited to this.

[0216] like Figure 9A As shown, the A data voltage provided by the Mth column data line is different from the B data voltage provided by the Mth column data line. The time for charging the pixel circuit of the Bth row and Mth column by the B data voltage is the third charging time t3.

[0217] The third charging time t3 is greater than 1H, which is increased to the charging time of the pixel circuit in the B row and M column of the B data voltage.

[0218] Figure 9B It corresponds to Figure 9A The timing diagram of the relevant scan signals, Figure 9C yes Figure 9A The timing diagram of the scanning signal described in the corresponding embodiment of the present invention is as follows: Figure 9B The comparison diagram shows the timing diagrams of the relevant scan signals.

[0219] like Figure 9C As shown, in at least one embodiment of the present invention, the charging time for the pixel circuit in row B and column M using the B data voltage is greater than 1 hour, while in related technologies, the charging time for the pixel circuit in row B and column M using the B data voltage is equal to 1 hour. By employing the driving method described in at least one embodiment of the present invention, the charging time for the pixel circuit in row B and column M using the B data voltage can be increased.

[0220] Regarding the checkerboard pattern, taking the black-to-white conversion as an example, in the first row after conversion, due to the significant difference between the pre-charged data voltage and the actual data voltage to be charged, when the actual charging time is 1 hour, there is an insufficient charging problem for high-resolution and high-refresh-rate display products, resulting in the first row appearing dark at the boundary. At least one embodiment of this invention preemptively shuts off the scanning signal for row A and simultaneously provides the data voltage for row B in advance, thereby increasing the charging time of the pixel circuit in the first row after conversion and improving the problem of insufficient charging time.

[0221] In at least one embodiment of the present invention, the pixel circuit in row A and column M is electrically connected to the scan line in row A, and the pixel circuit in row B and column M is electrically connected to the scan line in row B; the scan line in row A is used to provide the scan signal in row A, and the scan line in row B is used to provide the scan signal in row B;

[0222] The effective pulse width of the scan signal in row A is less than the effective pulse width of the scan signal in row B.

[0223] like Figure 9A As shown, the effective pulse width of the scan signal SA in row A is smaller than the effective pulse width of the scan signal SB in row B.

[0224] The effective pulse width of the A-th row scan signal SA is the duration during which the potential of the A-th row scan signal SA remains at a high voltage.

[0225] The effective pulse width of the B-th row scan signal SB is the duration during which the potential of the B-th row scan signal SB remains at a high voltage.

[0226] Optionally, the step of controlling the charging time of the pixel circuit in the Bth row and Mth column via the Bth data voltage to be greater than a charging time threshold includes:

[0227] By increasing the time interval between the falling edge time of the A-row scan signal and the falling edge time of the B-row scan signal, the charging time for the B-row M-column pixel circuit by the B-row data voltage is controlled to be greater than the charging time threshold.

[0228] In specific implementation, the time interval between the falling edge time of the A-row scan signal and the falling edge time of the B-row scan signal can be increased to control the charging time of the B-row M-column pixel circuit by the B-data voltage to be greater than the charging time threshold; for example, the charging time of the B-row M-column pixel circuit by the B-data voltage can be increased by advancing the falling edge time of the A-row scan signal.

[0229] At least one embodiment of the present invention proposes three driving methods for improving uneven charging within the display panel and increasing pixel charging rate, as follows:

[0230] (1) In the case of insufficient charging time of odd-numbered row pixel circuits or even-numbered row pixel circuits in HSR mode, the phase adjustment of the scanning signal can be used to increase the charging time of odd-numbered row pixel circuits or even-numbered row pixel circuits and improve the charging rate of odd-numbered row pixel circuits or even-numbered row pixel circuits.

[0231] (2) For pixel circuits where the pre-charge and actual charging voltages are the same or similar, reduce the duty cycle of the scanning signal to end the charging process earlier. At the same time, advance the data voltage signal of the next row of pixel circuits. This can improve the charging rate of the next row of pixel circuits while ensuring the charging of the previous row of pixel circuits. This solution can improve the charging rate of pixel circuits at the pattern boundaries of checkerboard, H2Line, H3Line and Crosstalk patterns, and improve defects such as image retention and fine pitch. It can effectively improve product quality, especially for the problem of insufficient charging in 8K display products.

[0232] (3) For the current architecture of drive modules where the fall time of adjacent two or several rows of scan signals differs, the charging rate can be made comparable by periodically adjusting the GOE time.

[0233] The above driving methods can be used individually or in combination of at least two to improve display quality; no limitation is made here.

[0234] The display device described in this embodiment of the invention includes a display panel, a timing controller, and a driving module;

[0235] like Figure 10 As shown, the timing controller TC includes a storage unit 101 and a comparison unit 102;

[0236] The storage unit 101 stores a specific image;

[0237] The comparison unit 102 is used to compare the screen to be displayed with a specific screen. When the screen to be displayed and the specific screen are the same or partially the same, it provides an indication signal to the driving module G0. Optionally, the data signal and / or the gate driving circuit GOA signal can be adjusted and changed through the timing controller. For different specific screens, the above driving method is called.

[0238] The drive module G0 is used to invoke the aforementioned drive method when it receives the indication signal.

[0239] In at least one embodiment of the present invention, the above driving method can be implemented by adding a screen detection function. When the comparison unit finds that the screen to be displayed is the same as a specific screen, it provides an indication signal to the driving module to call the driving method described in at least one embodiment of the present invention. The screen to be displayed can be input by the system chip SOC. The specific screen here is, for example, an H2Line screen, an H3Line screen, a checkerboard screen, an HSR mode screen, etc.

[0240] In at least one embodiment of the present invention, when the charging voltage of two adjacent rows of pixel circuits or several adjacent rows of pixel circuits is the same or similar, and there is a grayscale jump in the next row of pixel circuits, the driving method can be started to adjust the duty cycle and phase of the scanning signal and / or data signal, which is not limited to a specific pattern.

[0241] exist Figure 11 In the diagram, TC is the timing controller, LS is the level converter, and P0 is the display panel.

[0242] exist Figure 11 In the diagram, GOA1 represents the first driving circuit included in the driving module, GOA2 represents the second driving circuit included in the driving module, D1 represents the first data driving chip, and DC represents the Cth data driving chip, where C is an integer greater than 1.

[0243] At least one embodiment of the present invention relates to scanning signal timing adjustment, scanning signal pulse width adjustment, and data voltage timing adjustment, all of which can be implemented by a timing controller TC. Scanning signal timing adjustment and data voltage timing adjustment can be implemented using the current timing controller TC, while scanning signal pulse width adjustment requires a newly developed IC (integrated circuit) to adjust the scanning signal pulse width at specific locations.

[0244] exist Figure 12 In the diagram, TC is the timing controller, X1 is the data voltage signal, X2 is the scan signal, DI is the data driver, and LS is the level converter.

[0245] like Figure 12 As shown, the timing controller TC requires a screen detection function and pre-stores the patterns to be detected (the patterns to be detected can be, for example, H2Line, H3Line, checkerboard, or Crosstalk screens). After the front-end SOC signal (input signal) is input to the timing controller TC, the timing controller TC performs pattern detection and comparison. When the pattern to be displayed is the same as the pre-stored pattern, the timing controller TC correspondingly changes the data voltage signal X1 and the scan signal X2. For different patterns to be displayed, the timing controller TC can perform different processing methods, thereby realizing different adjustment methods for different patterns.

[0246] The display device according to at least one embodiment of the present invention may further include a display control circuit; the timing controller is used to provide a first input clock signal and a second input clock signal to the display control circuit;

[0247] The display control circuit is used to provide and output multiple output clock signals according to the first input clock signal and the second input clock signal;

[0248] The drive module is used to generate a corresponding scan signal based on the output clock signal.

[0249] exist Figure 13 In the diagram, P1 is the power management circuit, TC is the timing controller, 120 is the display driver circuit, and G0 is the driver module.

[0250] The device labeled TG is a timing generator, the device labeled R1 is a register, the device labeled O1 is an oscillator, the device labeled LS1 is a first level converter, and the device labeled LS2 is a second level converter.

[0251] The following lines are labeled: VDD (first high voltage signal), VGH (second high voltage signal), LVGL (first low voltage signal), VGL (second low voltage signal), STV_IN1 (first input start signal), STV_IN2 (second input start signal), LC_IN (GOA noise reduction input signal), CLK_IN1 (first input clock signal), CLK_IN2 (second input clock signal), Te (clock stop signal); SCL (clock line), SDA (bidirectional data line); PR (protection circuit); GND (ground).

[0252] The signal labeled STV1 is the first start signal, STV2 is the second start signal, LC1 is the first GOA noise reduction output signal, LC2 is the second GOA noise reduction output signal, CLK1 is the first clock signal, CLK2 is the second clock signal, CLK3 is the third clock signal, CLK4 is the fourth clock signal, CLK5 is the fifth clock signal, CLK6 is the sixth clock signal, CLK7 is the seventh clock signal, CLK8 is the eighth clock signal, CLK1 is the first clock signal, CLK2 is the second clock signal, CLK9 is the ninth clock signal, and CLK10 is the tenth clock signal; the signal labeled DIS_VGL is the third low voltage signal, and DIS_LVGL is the fourth low voltage signal.

[0253] exist Figure 14 In this diagram, STV_IN1 is the first input start signal, CLK_IN1 is the first input clock signal, CLK_IN2 is the second input clock signal, and Te is the clock stop signal; STV1 is the first start signal, CLK1 is the first clock signal, CLK2 is the second clock signal, CLK3 is the third clock signal, CLK4 is the fourth clock signal, CLK5 is the fifth clock signal, CLK6 is the sixth clock signal, CLK7 is the seventh clock signal, CLK8 is the eighth clock signal, CLK1 is the first clock signal, CLK2 is the second clock signal, CLK9 is the ninth clock signal, and CLK10 is the tenth clock signal.

[0254] Figure 13When the first level converter LS1 is working, the front end of LS1 receives the first input clock signal CLK_IN1 and the second input clock signal CLK_IN2 from the timing controller TC. The timing generator TG generates the required clock signals, and then LS1 performs level conversion to obtain the first clock signal CLK1 to the tenth clock signal CLK10.

[0255] The first level converter LS1 generates the first clock signals CLK1 to the tenth clock signals CLK10 in the following way: the rising edge of CLK_IN1 is the rising edge of each clock signal. For example, the first ten rising edges of CLK_IN1 are the first rising edges of the first clock signals CLK1 to the tenth clock signals CLK10 in sequence, the eleventh to twentieth rising edges of CLK_IN1 are the second rising edges of the first clock signals CLK1 to the tenth clock signals CLK10 in sequence, and so on. The rising edge of CLK_IN2 is the falling edge of each clock signal. The first ten rising edges of CLK_IN2 are the first falling edges of the first clock signals CLK1 to the tenth clock signals CLK10 in sequence, the eleventh to twentieth rising edges of CLK_IN2 are the second falling edges of the first clock signals CLK1 to the tenth clock signals CLK10 in sequence, and so on.

[0256] The duty cycle and timing of the scan signal, as described in at least one embodiment of the present invention, can be modified by a timing controller by controlling the rising edge positions of CLK_IN1 and CLK_IN2. For example, to reduce the time during which the first potential of CLK1 remains high, this can be achieved by delaying the arrival time of the first rising edge of CLK_IN1, or by advancing the arrival time of the first rising edge of CLK_IN2.

[0257] In at least one embodiment of the present invention, when it is necessary to delay the odd-row scanning signal or the even-row scanning signal, two level converters can be used to control the clock signal provided to the odd-row driving circuit and the clock signal provided to the even-row driving circuit, respectively. For example, the two level converters include a first level converter controlling the odd-row and a second level converter controlling the even-row. The first level converter includes CLK_IN1 and CLK_IN2, and the second level converter includes CLK_IN1 and CLK_IN2. The timing adjustment of the odd-row or even-row can be achieved by delaying the timing of CLK_IN1 and CLK_IN2 of the odd-row or even-row, for example, referring to... Figure 2 The timing of the scan signal can be delayed by postponing the timing of CLK_IN1 and CLK_IN2 for odd-numbered rows, thereby increasing the charging time of odd-numbered rows and improving display uniformity.

[0258] The display device according to at least one embodiment of the present invention further includes a display control circuit; the driving module includes an odd-numbered row driving circuit and an even-numbered row driving circuit;

[0259] The timing controller is used to provide the display control circuit with a first input clock signal, a second input clock signal, a third input clock signal and a fourth input clock signal;

[0260] The display control circuit is used to provide a first set of output clock signals to the odd-row driving circuit according to the first input clock signal and the second input clock signal, and to provide a second set of output clock signals to the even-row driving circuit according to the third input clock signal and the fourth input clock signal;

[0261] The odd row driving circuit is used to generate a corresponding odd row scanning signal according to the first set of output clock signals, and to provide the odd row scanning signal to the odd row pixel circuit;

[0262] The even-row driving circuit is used to generate a corresponding even-row scanning signal according to the second set of output clock signals, and to provide the even-row scanning signal to the even-row pixel circuit.

[0263] The display device provided in this embodiment of the invention can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0264] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A driving method applied to a display panel, the display panel comprising multiple rows of scan lines, multiple columns of data lines, and multiple rows and columns of pixel circuits, wherein the pixel circuits are electrically connected to corresponding row scan lines and corresponding column data lines respectively; characterized in that, The driving method includes: The first charging time is controlled to be greater than 0.5 times the second charging time, and the first charging time is controlled to be less than the second charging time. Wherein, the first charging time is the time for the A-row M-column pixel circuit to be charged by the A-th data voltage on the M-th column data line; The second charging time is the time it takes for the pixel circuit in row B and column M to be charged by the data voltage in data line A and data line B. A, B, and M are all positive integers; The voltage of data A is the same as the voltage of data B; The A-th data voltage and the B-th data voltage have the same signal and the same voltage value; The pixel circuit in row A and column M is electrically connected to the scan line in row A, and the pixel circuit in row B and column M is electrically connected to the scan line in row B; the scan line in row A is used to provide the scan signal in row A, and the scan line in row B is used to provide the scan signal in row B; The driving method includes controlling the time interval between the falling edge time of the A-row scan signal and the falling edge time of the B-row scan signal to be less than half the time for charging the pixel circuit of the B-row M-column by the A-row data voltage and the B-row data voltage. The effective pulse width of the scan signal in row A is greater than the effective pulse width of the scan signal in row B.

2. The driving method as described in claim 1, characterized in that, In frame N, the pixel circuit in row A and column M is an even-numbered pixel circuit, and the pixel circuit in row B and column M is an odd-numbered pixel circuit; N is an integer.

3. The driving method as described in claim 1, characterized in that, In the (N+1)th frame, the pixel circuit in row A and column M is an odd-numbered pixel circuit, and the pixel circuit in row B and column M is an even-numbered pixel circuit; N is a positive integer.

4. A driving method applied to a display panel, the display panel comprising multiple rows of scan lines, multiple columns of data lines, and multiple rows and columns of pixel circuits, wherein the pixel circuits are electrically connected to corresponding row scan lines and corresponding column data lines respectively; characterized in that, The driving method includes: The first charging time is controlled to be greater than 0.5 times the second charging time, and the first charging time is controlled to be less than the second charging time. Wherein, the first charging time is the time for the A-row M-column pixel circuit to be charged by the A-th data voltage on the M-th column data line; The second charging time is the time it takes for the pixel circuit in row B and column M to be charged by the data voltage in data line A and data line B. A, B, and M are all positive integers; The voltage of data A and the voltage of data B are the same voltage; the pixel circuit of row A and column M is electrically connected to the scan line of row A, and the pixel circuit of row B and column M is electrically connected to the scan line of row B; the scan line of row A is used to provide the scan signal of row A, and the scan line of row B is used to provide the scan signal of row B; The driving method further includes: controlling the first time to be greater than the second time; The first time is the time when the Mth column data line begins to provide the Ath data voltage, and the time interval between the falling edge time of the Ath row scan signal; The second time is the time interval between the falling edge time of the A-row scan signal and the falling edge time of the B-row scan signal; The effective pulse width of the scan signal in row A is not equal to the effective pulse width of the scan signal in row B.

5. A driving method applied to a display panel, the display panel comprising multiple rows of scan lines, multiple columns of data lines, and multiple rows and columns of pixel circuits, wherein the pixel circuits are electrically connected to corresponding row scan lines and corresponding column data lines respectively; characterized in that, The driving method includes: When the fall time of the A-row scan signal provided by the A-row scan line is less than the fall time of the B-row scan signal provided by the B-row scan line, the third time is controlled to be greater than the fourth time. The third time is the time from when the Mth column data line starts providing the Ath data voltage to the time when the Ath row Mth column pixel circuit starts to decrease, and the time interval between these two times. The fourth time is the time from when the Mth column data line starts providing the Bth data voltage to the time when the pixel circuit of the Bth row and Mth column starts to decrease, and the time interval between these two times. A, B, and M are all positive integers, and A is not equal to B; The time interval between the time when the potential of the A-row scan signal begins to fall and the time when the M-column data line stops providing the A-data voltage is greater than the time interval between the time when the potential of the B-row scan signal begins to fall and the time when the M-column data line stops providing the B-data voltage.

6. The driving method as described in claim 5, characterized in that, The voltage of data A is not equal to the voltage of data B.

7. The driving method as described in claim 5 or 6, characterized in that, The driving method is applied to a display panel, the display panel including a first gate driving circuit and a second gate driving circuit. The first gate driving circuit and the second gate driving circuit share a pull-up node; both the first gate driving circuit and the second gate driving circuit are connected to a first clock signal terminal that provides a first clock signal and a second clock signal terminal that provides a second clock signal. When the potential of the first clock signal changes from the first level to the second level, the potential of the pull-up node is the first voltage value; when the potential of the second clock signal changes from the first level to the second level, the potential of the pull-up node is the second voltage value. The first voltage value is not equal to the second voltage value; When the potential of the first clock signal changes from high to low, the potential of the pull-up node becomes the third voltage value; when the potential of the second clock signal changes from high to low, the potential of the pull-up node becomes the fourth voltage value; the third voltage value and the fourth voltage value are not equal.

8. A display device, characterized in that, Includes display panel, timing controller and drive module; The timing controller includes a storage unit and a comparison unit; The storage unit stores specific images; The comparison unit is used to compare the screen to be displayed with a specific screen. When the screen to be displayed and the specific screen are the same or partially the same, an indication signal is provided to the driving module. The driving module is used to invoke the driving method as described in any one of claims 1 to 7 when it receives the indication signal.

9. The display device as claimed in claim 8, characterized in that, It also includes a display control circuit; the timing controller is used to provide a first input clock signal and a second input clock signal to the display control circuit; The display control circuit is used to provide and output multiple output clock signals according to the first input clock signal and the second input clock signal; The drive module is used to generate a corresponding scan signal based on the output clock signal.

10. The display device as claimed in claim 8, characterized in that, It also includes a display control circuit; the driving module includes odd-row driving circuits and even-row driving circuits; The timing controller is used to provide the display control circuit with a first input clock signal, a second input clock signal, a third input clock signal and a fourth input clock signal; The display control circuit is used to provide a first set of output clock signals to the odd-row driving circuit according to the first input clock signal and the second input clock signal, and to provide a second set of output clock signals to the even-row driving circuit according to the third input clock signal and the fourth input clock signal; The odd row driving circuit is used to generate a corresponding odd row scanning signal according to the first set of output clock signals; The even-row driving circuit is used to generate corresponding even-row scanning signals based on the second set of output clock signals.

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