An alternating display field sequence pixel driving circuit

Abstract

This invention discloses an alternating display field-sequence pixel driving circuit, comprising: a first sub-driving circuit and a second sub-driving circuit. Both the first and second sub-driving circuits include a first transistor, a second transistor, a third transistor, a pixel electrode, a reference electrode, a storage capacitor, and a liquid crystal element. Specifically, the gate of the first transistor in the first sub-driving circuit is coupled to a first control signal line; the gate of the second transistor in the first sub-driving circuit is coupled to a second global signal line; and the gate of the third transistor in the first sub-driving circuit is coupled to the first global signal line. Similarly, the gate of the first transistor in the second sub-driving circuit is coupled to a second control signal line; the gate of the second transistor in the second sub-driving circuit is coupled to the first global signal line; and the gate of the third transistor in the second sub-driving circuit is coupled to the second global signal line.

Description

Technical Field

[0001] This invention relates to the field of pixel driving technology, and more specifically to a field-sequence pixel driving circuit for alternating displays. Background Technology

[0002] In field sequential or color sequential display technologies, the backlight can only be turned on after all the liquid crystals in the screen have deflected to a stable state to avoid screen chaos. Therefore, how to speed up the liquid crystal driving time and increase the backlight turn-on time is an urgent problem to be solved in this field.

[0003] In traditional color-sequential display technology, the pixel driving circuit of an LCD first charges the electrodes of each row of pixels sequentially within a frame, then waits for all liquid crystals to deflect to a stable position, and finally turns on the backlight. If the backlight is turned on immediately after the last row of pixels has finished charging, the liquid crystals corresponding to the pixels charged later are not yet stable, which will cause differences in brightness and color, resulting in a chaotic image. Therefore, the time allotted for backlight activation within a frame in the pixel driving circuit is very short, making it difficult to achieve high brightness and high frequency display, while also placing higher demands on backlight brightness specifications and lifespan, thus increasing product costs.

[0004] In summary, traditional pixel driving circuits suffer from short backlight turn-on time. Summary of the Invention

[0005] In view of this, the present invention provides an alternating display field sequence pixel driving circuit, which solves the problem of short backlight turn-on time in traditional pixel driving circuits by improving the circuit structure and driving timing.

[0006] To solve the above problems, the technical solution of the present invention is to employ an alternating display field-sequence pixel driving circuit, comprising: a first sub-driving circuit and a second sub-driving circuit. Both the first and second sub-driving circuits include a first transistor, a second transistor, a third transistor, a pixel electrode, a reference electrode, a storage capacitor, and a liquid crystal element. Specifically, the gate of the first transistor in the first sub-driving circuit is coupled to a first control signal line; the gate of the second transistor in the first sub-driving circuit is coupled to a second global signal line; and the gate of the third transistor in the first sub-driving circuit is coupled to the first global signal line. Similarly, the gate of the first transistor in the second sub-driving circuit is coupled to a second control signal line; the gate of the second transistor in the second sub-driving circuit is coupled to the first global signal line; and the gate of the third transistor in the second sub-driving circuit is coupled to the second global signal line.

[0007] Optionally, the first sub-driving circuit is configured such that: the first source and drain of the first transistor of the first sub-driving circuit are coupled to a data signal line, the gate is coupled to a first control signal line, and the second source and drain are coupled to a pixel electrode; the first source and drain of the second transistor of the first sub-driving circuit are coupled to a pixel electrode, the gate is coupled to a second global signal line, and the second source and drain are coupled to a reference electrode; the first source and drain of the third transistor of the first sub-driving circuit are coupled to a reference electrode, the gate is coupled to a first global signal line, and the second source and drain are coupled to a common electrode line; one end of the storage capacitor of the first sub-driving circuit is coupled to the common electrode line, and the other end is coupled to a pixel electrode; one end of the liquid crystal element of the first sub-driving circuit is coupled to a pixel electrode, and the other end is coupled to a reference electrode.

[0008] Optionally, the second sub-driving circuit is configured such that: the first source and drain of the first transistor of the second sub-driving circuit are coupled to a data signal line, the gate is coupled to a second control signal line, and the second source and drain are coupled to a pixel electrode; the first source and drain of the second transistor of the second sub-driving circuit are coupled to a pixel electrode, the gate is coupled to a first global signal line, and the second source and drain are coupled to a reference electrode; the first source and drain of the third transistor of the second sub-driving circuit are coupled to a reference electrode, the gate is coupled to a second global signal line, and the second source and drain are coupled to a common electrode line; one end of the storage capacitor of the second sub-driving circuit is coupled to the common electrode line, and the other end is coupled to a pixel electrode; one end of the liquid crystal element of the second sub-driving circuit is coupled to a pixel electrode, and the other end is coupled to a reference electrode.

[0009] Optionally, the driving timing of the field-sequence pixel driving circuit is configured such that, in the Nth frame, the first global signal line remains at a low level, and the second global signal line jumps to a high level and remains there. At this time, the second transistor of the first sub-driving circuit is turned on under the control of the second global signal, and the third transistor remains off. The pixel electrode and the reference electrode are in a conducting state, and the voltage across the liquid crystal element is 0. After the first control signal line jumps to a high potential, the first transistor of the first sub-driving circuit turns on and writes the data signal voltage to the pixel electrode and the reference electrode based on the data signal. At the same time, the third transistor of the second sub-driving circuit is turned on under the control of the second global signal, and the second transistor remains off. The pixel electrode and the reference electrode are in a closed state, and the reference electrode is connected to the common electrode line. Therefore, a voltage difference is generated across the liquid crystal element of the second sub-driving circuit according to the data signal voltage written to the pixel electrode in the (N-1)th frame.

[0010] Optionally, in the (N+1)th frame, the second global signal line transitions to a low level, and the first global signal line transitions to a high level and remains high. At this time: the third transistor of the first sub-driving circuit is turned on under the control of the second global signal, while the second transistor remains off. The pixel electrode and the reference electrode are in an off state, and the reference electrode and the common electrode line are connected. Therefore, the two ends of the liquid crystal element of the first sub-driving circuit generate a voltage difference according to the data signal voltage written to the pixel electrode in the Nth frame. At the same time, the second transistor of the second sub-driving circuit is turned on under the control of the second global signal, while the third transistor remains off. The pixel electrode and the reference electrode are in a connected state, and the voltage across the liquid crystal element is 0. After the first control signal line transitions to a high potential, the first transistor of the second sub-driving circuit turns on and writes the data signal voltage to the pixel electrode and the reference electrode based on the data signal.

[0011] Optionally, when entering the Nth frame, the backlight is turned off until the liquid crystal element of the second sub-driving circuit completes the flipping of the liquid crystal driven by the voltage difference generated by the data signal voltage written to the pixel electrode in the N-1th frame, and then the backlight is turned on.

[0012] Optionally, when entering the N+1th frame, the backlight is turned off until the liquid crystal element of the first sub-driving circuit completes the flipping of the liquid crystal based on the voltage difference generated by the data signal voltage written to the pixel electrode in the Nth frame.

[0013] Optionally, the first transistor, the second transistor, and the third transistor are all configured as N-type thin-film field-effect transistors.

[0014] Optionally, both the pixel electrode and the reference electrode are electrode plates formed of a transparent conductive material.

[0015] Optionally, the liquid crystal element is configured in a normally black mode.

[0016] The primary improvement of this invention lies in the provided alternating display field-sequence pixel driving circuit. By setting a first sub-driving circuit and a second sub-driving circuit, it can be ensured that in each frame, a sub-pixel corresponding to one sub-driving circuit is in a normal light-emitting state, while the sub-pixel corresponding to the other sub-driving circuit can synchronously write the pixel voltage signal required for the next frame. Since its pixel electrode and reference electrode are in a conductive state, this sub-pixel liquid crystal element will not transmit light and will not display incorrect grayscale. Through the aforementioned driving circuit and corresponding signal timing control, the function of alternating light emission of sub-pixels in each frame is achieved. This allows for synchronous writing of data signal voltage and light emission, thereby significantly increasing the light emission time, improving the brightness of the display device, or reducing the power consumption of the backlight unit while achieving field-sequence display. Simultaneously, the data signal voltage writing time can also be significantly increased, which is beneficial for realizing high-resolution, high-refresh-rate display devices. Attached Figure Description

[0017] Figure 1 This is a simplified circuit diagram of the alternating display field sequence pixel driving circuit of the present invention;

[0018] Figure 2 This is a timing diagram of the driving circuit for the alternating display field sequence pixels of the present invention. Detailed Implementation

[0019] To enable those skilled in the art to better understand the technical solutions of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0021] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0022] The embodiments of the technical solution of this application will now be described in detail with reference to the accompanying drawings. These embodiments are only used to more clearly illustrate the technical solution of this application and are therefore merely examples, and should not be used to limit the scope of protection of this application.

[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims, and foregoing description of the drawings are intended to cover non-exclusive inclusion.

[0024] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.

[0025] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0026] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0027] Specifically, such as Figure 1 As shown, an alternating field-sequence pixel driving circuit includes: a first sub-driving circuit and a second sub-driving circuit. Both the first and second sub-driving circuits include a first transistor T11, a second transistor T12, a third transistor T13, a pixel electrode, a reference electrode VREF, a storage capacitor Cs1, and a liquid crystal element Clc. In the first sub-driving circuit, the gate of the first transistor T11 is coupled to a first control signal line Scan_O; the gate of the second transistor T12 is coupled to a second global signal line EN20; and the gate of the third transistor T13 is coupled to the first global signal line EN10. Similarly, in the second sub-driving circuit, the gate of the first transistor T11 is coupled to a second control signal line Scan_E; the gate of the second transistor T12 is coupled to the first global signal line EN10; and the gate of the third transistor T13 is coupled to the second global signal line EN20. The liquid crystal element Clc is configured in a normally black mode, meaning that when the voltage between the pixel electrode and the reference electrode VREF is 0, the liquid crystal is opaque.

[0028] Furthermore, the first sub-driving circuit is configured such that: the first source and drain of the first transistor T11 of the first sub-driving circuit are coupled to the data signal line Data, the gate is coupled to the first control signal line Scan_O, and the second source and drain are coupled to the pixel electrode; the first source and drain of the second transistor T12 of the first sub-driving circuit are coupled to the pixel electrode, the gate is coupled to the second global signal line EN20, and the second source and drain are coupled to the reference electrode VREF; the first source and drain of the third transistor T13 of the first sub-driving circuit are coupled to the reference electrode VREF, the gate is coupled to the first global signal line EN10, and the second source and drain are coupled to the common electrode line Vcom; one end of the storage capacitor Cs1 of the first sub-driving circuit is coupled to the common electrode line Vcom, and the other end is coupled to the pixel electrode; one end of the liquid crystal element Clc of the first sub-driving circuit is coupled to the pixel electrode, and the other end is coupled to the reference electrode VREF.

[0029] Furthermore, the second sub-driving circuit is configured such that: the first source and drain of the first transistor T11 of the second sub-driving circuit are coupled to the data signal line Data, the gate is coupled to the second control signal line Scan_E, and the second source and drain are coupled to the pixel electrode; the first source and drain of the second transistor T12 of the second sub-driving circuit are coupled to the pixel electrode, the gate is coupled to the first global signal line EN10, and the second source and drain are coupled to the reference electrode VREF; the first source and drain of the third transistor T13 of the second sub-driving circuit are coupled to the reference electrode VREF, the gate is coupled to the second global signal line EN20, and the second source and drain are coupled to the common electrode line Vcom; one end of the storage capacitor Cs1 of the second sub-driving circuit is coupled to the common electrode line Vcom, and the other end is coupled to the pixel electrode; one end of the liquid crystal element Clc of the second sub-driving circuit is coupled to the pixel electrode, and the other end is coupled to the reference electrode VREF.

[0030] Specifically, to facilitate understanding of the operating timing of the pixel driving circuit, as follows: Figure 2 As shown.

[0031] In the Nth frame, the first global signal line EN10 remains low, and the second global signal line EN20 jumps to a high level and remains high. At this time, the second transistor T12 of the first sub-driving circuit is turned on under the control of the second global signal, and the third transistor T13 remains off. The pixel electrode and the reference electrode VREF are in a conducting state, and the voltage across the liquid crystal element Clc is 0, so it is in an opaque state. In this frame, the pixel corresponding to the first sub-driving circuit does not emit light. After the first control signal line Scan_O jumps to a high potential line by line (Scan_O1~Scan_O n, where 1 and n represent pixels in different rows. In a liquid crystal panel, there are 2n rows of pixels by default, which corresponds to n first sub-driving circuits and n second sub-driving circuits), the first transistor T11 of the first sub-driving circuit turns on and writes the data signal voltage to the pixel electrode and the reference electrode VREF based on the data signal.

[0032] Simultaneously, the third transistor T13 of the second sub-driving circuit is turned on under the control of the second global signal, while the second transistor T12 remains off. The pixel electrode and the reference electrode VREF are in an off state, and the reference electrode VREF is connected to the common electrode line Vcon. Therefore, the two ends of the liquid crystal element Clc in the second sub-driving circuit generate a voltage difference according to the data signal voltage written to the pixel electrode in the (N-1)th frame, thereby driving the liquid crystal to flip. This flipping time is the liquid crystal response time (LCResponse). After the liquid crystal flipping is completed, the backlight is turned on, and the pixel corresponding to the second sub-driving circuit begins to emit light until the end of the current frame, which is one frame of normal display time.

[0033] At frame N+1, the second global signal line EN20 goes low, and the first global signal line EN10 goes high and remains high. At this time:

[0034] The third transistor T13 of the first sub-driving circuit is turned on under the control of the second global signal, while the second transistor T12 remains off. The pixel electrode and the reference electrode VREF are in an off state, and the reference electrode VREF is connected to the common electrode line Vcon. Therefore, the two ends of the liquid crystal element Clc in the first sub-driving circuit generate a voltage difference based on the data signal voltage written to the pixel electrode in the Nth frame, thereby driving the liquid crystal to flip. This flipping time is the liquid crystal response time (LCResponse). After the liquid crystal flipping is complete, the backlight is turned on, and the pixel corresponding to the first sub-driving circuit begins to emit light until the end of the current frame, which is one frame of normal display time.

[0035] Simultaneously, the second transistor T12 of the second sub-driving circuit is turned on under the control of the second global signal, while the third transistor T13 remains off. The pixel electrode and the reference electrode VREF are in a conducting state, and the voltage across the liquid crystal element Clc is 0, so it is in an opaque state. In this frame, the pixel corresponding to the first sub-driving circuit does not emit light. After the first control signal line Scan_O jumps to a high potential line by line, the first transistor T11 of the second sub-driving circuit turns on and writes the data signal voltage to the pixel electrode and the reference electrode VREF based on the data signal.

[0036] It should be noted that N is an odd number and a positive integer, which can be configured as 1, 3, 5, 7... in the above embodiments.

[0037] It should also be noted that the terms "high potential" and "low potential" as used in this invention refer to the difference in potential relative to the common electrode potential. For example, a potential higher than Vcom is considered a high potential, and a potential lower than Vcon is considered a low potential.

[0038] This invention, by setting up a first sub-driving circuit and a second sub-driving circuit, ensures that in each frame, one sub-pixel corresponding to a sub-driving circuit is in a normal light-emitting state, while the sub-pixel corresponding to the other sub-driving circuit can synchronously write the pixel voltage signal required for the next frame. Since its pixel electrode and reference electrode are in a conductive state, this sub-pixel liquid crystal element will not transmit light and will not display incorrect grayscale. Through the aforementioned driving circuit and corresponding signal timing control, the function of sub-pixels alternately emitting light frame by frame is achieved. This allows for the synchronous writing of data signal voltage and light emission, thereby significantly increasing the light emission time and improving the brightness of the display device, or reducing the power consumption of the backlight unit, while simultaneously achieving field-sequence display. Furthermore, the data signal voltage writing time can also be significantly increased, which is beneficial for realizing high-resolution, high-refresh-rate display devices.

[0039] Furthermore, when entering the Nth frame, the backlight is turned off until the liquid crystal element Clc of the second sub-driving circuit is driven by the voltage difference generated by the data signal voltage written to the pixel electrode in the N-1th frame to complete the flipping of the liquid crystal, and then the backlight is turned on.

[0040] Furthermore, when entering the N+1th frame, the backlight is turned off until the liquid crystal element Clc of the first sub-driving circuit completes the flipping of the liquid crystal based on the voltage difference generated by the data signal voltage written to the pixel electrode in the Nth frame, and then the backlight is turned on.

[0041] It should be noted that in this embodiment, R, G, and B light are emitted frame by frame by backlight, and the visual persistence effect of the human eye is used to realize the display of color images. The order of R, G, and B backlight can be interchanged.

[0042] Furthermore, both the pixel electrode and the reference electrode VREF are electrode plates formed of a transparent conductive material (preferably ITO). The electrode plate can be a single surface, a comb shape, or other shapes, depending on the display mode.

[0043] Furthermore, the first transistor T11, the second transistor T12, and the third transistor T13 are all configured as N-type thin-film field-effect transistors, thereby achieving the following: Figure 2 The gate control signal voltage shown can turn on the TFT (transistor) when it is high and turn off the TFT when it is low, but this does not limit the scope of protection of this application. Those skilled in the art can adapt it by changing all or part of the TFT to P-type thin film field effect transistors based on the control principle.

[0044] The above describes the alternating display field-sequence pixel driving circuit provided by the embodiments of the present invention. The various embodiments are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section. It should be noted that those skilled in the art can make several improvements and modifications to the present invention without departing from the principle of the invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

[0045] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in connection with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can implement the described functions using different methods for each specific application, but such implementation should not be considered beyond the scope of the invention. The steps of the methods or algorithms described in connection with the embodiments disclosed herein can be implemented directly in hardware, software modules executed by a processor, or a combination of both. Software modules can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the art.

Claims

1. An alternate display field sequential pixel drive circuit, characterized by, include: First sub-drive circuit and second sub-drive circuit The first sub-driving circuit is configured such that: the first source and drain of the first transistor (T11) of the first sub-driving circuit are coupled to the data signal line (Data), the gate is coupled to the first control signal line (Scan_O), and the second source and drain are coupled to the pixel electrode; the first source and drain of the second transistor (T12) of the first sub-driving circuit are coupled to the pixel electrode, the gate is coupled to the second global signal line (EN20), and the second source and drain are coupled to the reference electrode (VREF); the first source and drain of the third transistor (T13) of the first sub-driving circuit are coupled to the reference electrode (VREF), the gate is coupled to the first global signal line (EN10), and the second source and drain are coupled to the common electrode line (Vcom); one end of the storage capacitor (Cs1) of the first sub-driving circuit is coupled to the common electrode line (Vcom), and the other end is coupled to the pixel electrode; one end of the liquid crystal element (Clc) of the first sub-driving circuit is coupled to the pixel electrode, and the other end is coupled to the reference electrode (VREF); The second sub-driving circuit is configured such that: the first source and drain of the first transistor (T11) of the second sub-driving circuit are coupled to the data signal line (Data), the gate is coupled to the second control signal line (Scan_E), and the second source and drain are coupled to the pixel electrode; the first source and drain of the second transistor (T12) of the second sub-driving circuit are coupled to the pixel electrode, the gate is coupled to the first global signal line (EN10), and the second source and drain are coupled to the reference electrode (VREF); the first source and drain of the third transistor (T13) of the second sub-driving circuit are coupled to the reference electrode (VREF), the gate is coupled to the second global signal line (EN20), and the second source and drain are coupled to the common electrode line (Vcom); one end of the storage capacitor (Cs1) of the second sub-driving circuit is coupled to the common electrode line (Vcom), and the other end is coupled to the pixel electrode; one end of the liquid crystal element (Clc) of the second sub-driving circuit is coupled to the pixel electrode, and the other end is coupled to the reference electrode (VREF). This ensures that in each frame, one sub-pixel corresponding to a sub-driving circuit is in a normal light-emitting state, while the sub-pixel corresponding to another sub-driving circuit can synchronously write the pixel voltage signal required for the next frame. Since its pixel electrode and reference electrode are in a conducting state, the sub-pixel liquid crystal element will not transmit light.

2. The field sequential pixel drive circuit according to claim 1, characterized in that The driving timing of the field-sequence pixel driving circuit is configured such that, in the Nth frame, the first global signal line (EN10) remains low, and the second global signal line (EN20) jumps to a high level and remains high. At this time: the second transistor (T12) of the first sub-driving circuit is turned on under the control of the second global signal, and the third transistor (T13) remains off. The pixel electrode and the reference electrode (VREF) are in a conducting state, and the voltage across the liquid crystal element (Clc) is 0. After the first control signal line (Scan_O) jumps to a high potential, the first sub-driving circuit... A transistor (T11) turns on and writes a data signal voltage to the pixel electrode and the reference electrode (VREF) based on the data signal. At the same time, the third transistor (T13) of the second sub-driving circuit turns on under the control of the second global signal and the second transistor (T12) remains off. The pixel electrode and the reference electrode (VREF) are in an off state, and the reference electrode (VREF) is connected to the common electrode line (Vcom). Therefore, a voltage difference is generated across the liquid crystal element (Clc) of the second sub-driving circuit according to the data signal voltage written to the pixel electrode in the (N-1)th frame.

3. The field sequential pixel drive circuit according to claim 2, wherein At frame N+1, the second global signal line (EN20) switches to low level, and the first global signal line (EN10) switches to high level and remains high. At this time: the third transistor (T13) of the first sub-driving circuit is turned on under the control of the second global signal, while the second transistor (T12) remains off. The pixel electrode and the reference electrode (VREF) are in an off state, and the reference electrode (VREF) and the common electrode line (Vcom) are connected. Therefore, the two ends of the liquid crystal element (Clc) of the first sub-driving circuit generate a voltage difference according to the data signal voltage written to the pixel electrode in frame N. At the same time, the second transistor (T12) of the second sub-driving circuit is turned on under the control of the second global signal, while the third transistor (T13) remains off. The pixel electrode and the reference electrode (VREF) are in a connected state, and the voltage across the liquid crystal element (Clc) is 0. After the first control signal line (Scan_O) switches to high potential, the first transistor (T11) of the second sub-driving circuit turns on and writes the data signal voltage to the pixel electrode and the reference electrode (VREF) based on the data signal.

4. The field-sequence pixel driving circuit according to claim 2, characterized in that, When the Nth frame is entered, the backlight is turned off until the liquid crystal element (Clc) of the second sub-driving circuit is driven to complete the flipping of the liquid crystal by the voltage difference generated by the data signal voltage written to the pixel electrode in the N-1th frame, and then the backlight is turned on.

5. The field-sequence pixel driving circuit according to claim 3, characterized in that, When the N+1th frame is entered, the backlight is turned off until the liquid crystal element (Clc) of the first sub-driving circuit is driven to complete the flipping of the liquid crystal by the voltage difference generated by the data signal voltage written to the pixel electrode in the Nth frame, and then the backlight is turned on.

6. The field-sequence pixel driving circuit according to claim 1, characterized in that, The first transistor (T11), the second transistor (T12), and the third transistor (T13) are all configured as N-type thin-film field-effect transistors.

7. The field-sequence pixel driving circuit according to claim 1, characterized in that, Both the pixel electrode and the reference electrode (VREF) are electrode plates formed of transparent conductive material.

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