A narrow pulse filter circuit and chip

Abstract

This article relates to a narrow pulse filter circuit and chip, including two charging and discharging modules, two comparison modules and RS trigger RS1; the first charging and discharging module controls the charging and discharging of the first energy storage element according to the input pulse signal and the output signal of the #imgabs0# output terminal of RS1, and the second charging and discharging module controls the charging and discharging of the second energy storage element according to the reverse signal of the input pulse signal and the output signal of the Q output terminal of RS1; the first comparison module performs waveform transformation according to the set first threshold interval and the voltage value of the first energy storage element, and inputs the waveform transformation result to the Set input terminal of RS1; the second comparison module performs waveform transformation according to the second threshold interval and the voltage value of the second energy storage element, and inputs the waveform transformation result to the Reset input terminal of RS1; the Q output terminal of RS1 outputs the filtered pulse signal. It realizes the limitation of the minimum pulse width of the filtered signal, ensuring that the signal can be processed by the subsequent circuit.

Description

Technical Field

[0001] The present invention relates to the field of signal processing technology, and in particular to a narrow pulse filter circuit and chip. Background Art

[0002] Digital signal transmission is easily interfered by noise signals, and low-pass filters are usually used to filter out high-frequency narrow pulse noise signals. For noise signals with wide pulse widths, the subsequent circuit can identify and process them by itself. However, in the prior art, when the frequency of the noise signal is at the critical value of the low-pass filter, narrow pulses will still exist in the noise signal after filtering, causing abnormal operation of the subsequent circuit.

[0003] How to filter narrow pulses and avoid the existence of narrow pulses in the filtered signal is a technical problem that needs to be solved urgently. Summary of the invention

[0004] In order to solve the problems in the prior art, the embodiments of this article provide a narrow pulse filtering circuit and chip, which limit the minimum pulse width of the filtered signal, thereby ensuring that the signal with the minimum pulse width can be normally recognized and processed by the subsequent circuit, and solves the problem that when the frequency of the noise signal in the signal is at the critical value of the low-pass filter, narrow pulses will still exist in the noise signal after filtering, causing abnormal operation of the subsequent circuit.

[0005] On the one hand, the embodiments of this specification provide a narrow pulse filter circuit, including: a first charge and discharge module, a second charge and discharge module, a first comparison module, a second comparison module and a first RS trigger RS1;

[0006] The first charging and discharging module is used to charge and discharge the battery according to the input pulse signal and RS1. The output signal of the output terminal controls the charging and discharging of the first energy storage element in the first charging and discharging module, thereby changing the voltage value of the first energy storage element;

[0007] The second charge and discharge module is used to control the charge and discharge of the second energy storage element in the second charge and discharge module according to the reverse pulse signal of the input pulse signal and the output signal of the Q output terminal of RS1, thereby changing the voltage value of the second energy storage element;

[0008] The first comparison module is used to perform waveform transformation according to a set first threshold interval and a voltage value of the first energy storage element, and input the waveform transformation result to the Set input terminal of RS1, wherein the first threshold interval is set according to a narrow pulse filter width and a capacity of the first energy storage element;

[0009] The second comparison module is used to perform waveform transformation according to a second threshold interval and a voltage value of the second energy storage element, and input the waveform transformation result to the Reset input terminal of RS1, wherein the second threshold interval is set according to the narrow pulse filter width and the capacity of the second energy storage element;

[0010] RS1 is used to control the Q output terminal of RS1 to output a filtered output pulse signal corresponding to the input pulse signal according to the waveform transformation result of the first comparison module and the waveform transformation result of the second comparison module.

[0011] Furthermore, when the input pulse signal and RS1 When the output signals at the output end are all high level, the first energy storage element discharges; when the input pulse signal is low level or RS1 When the output signal at the output end is at a low level, the first energy storage element is charged;

[0012] When the input pulse signal is at a low level and the output signal of the Q output terminal of RS1 is at a high level, the second energy storage element discharges; when the input pulse signal is at a high level or the output signal of the Q output terminal of RS1 is at a low level, the second energy storage element charges.

[0013] Further, the first threshold interval includes a first threshold voltage and a second threshold voltage, the first threshold voltage is greater than the second threshold voltage, when the voltage value of the first energy storage element is higher than the first threshold voltage, the first comparison module outputs a low level; when the voltage value of the first energy storage element is lower than the second threshold voltage, the first comparison module outputs a high level; when the voltage value of the first energy storage element is between the first threshold voltage and the second threshold voltage, the output level of the first comparison module remains unchanged;

[0014] The second threshold interval includes a third threshold voltage and a fourth threshold voltage, the third threshold voltage is greater than the fourth threshold voltage, when the voltage value of the second energy storage element is higher than the third threshold voltage, the second comparison module outputs a low level; when the voltage value of the second energy storage element is lower than the fourth threshold voltage, the second comparison module outputs a high level; when the voltage value of the second energy storage element is between the third threshold voltage and the fourth threshold voltage, the output level of the second comparison module remains unchanged;

[0015] Between the starting high level of the Set input terminal of RS1 and the starting high level of the Reset input terminal, the Q output terminal of RS1 outputs a high level.

[0016] Further, the first charging and discharging module includes PMOS tubes P1 and P2, NMOS tubes N1 and N2, current sources I1 and I2, and the first energy storage element;

[0017] The gate of P1 and the gate of N1 are both connected to the input pulse signal, the source of P1 and the source of P2 are both connected to the second end of I1, the first end of I1 is connected to the power supply, I1 is used to provide charging current to the first charging and discharging module, the drain of P1, the drain of P2 and the drain of N1 are all connected to the charging and discharging port of the first energy storage element, the gate of P2 and the gate of N2 are both connected to the At the output end, the source of N1 is connected to the drain of N2, the source of N2 is connected to the first end of I2, the second end of I2 is grounded, and I2 is used to control the magnitude of the discharge current of the first charge and discharge module.

[0018] Further, the second charge and discharge module includes PMOS tubes P3 and P4, NOMS tubes N3 and N4, current sources I3 and I4, and the second energy storage element;

[0019] The gate of P3 and the gate of N3 are both connected to the reverse pulse signal of the input pulse signal, the source of P3 and the source of P4 are both connected to the second end of I3, the first end of I3 is connected to the power supply, I3 is used to provide charging current to the second charge and discharge module, the drain of P3, the drain of P4 and the drain of N3 are all connected to the charge and discharge port of the second energy storage element, the gate of P4 and the gate of N4 are both connected to the Q output end of RS1, the source of N3 is connected to the drain of N4, the source of N4 is connected to the first end of I4, the second end of I4 is grounded, and I4 is used to control the discharge current of the second charge and discharge module.

[0020] Furthermore, the first comparison module includes a Schmitt trigger SMIT1 and an inverter, the input end of SMIT1 is connected to the charge and discharge port of the first energy storage element, the output end of SMIT1 is connected to the input end of the inverter, and the output end of the inverter is connected to the Set input end.

[0021] Furthermore, the second comparison module includes a Schmitt trigger SMIT2 and an inverter, the input end of SMIT2 is connected to the charge and discharge port of the second energy storage element, the output end of SMIT2 is connected to the input end of the inverter, and the output end of the inverter is connected to the Reset input end.

[0022] Furthermore, the narrow pulse filter circuit also includes an inverter group consisting of an even number of inverters connected in series, the input end of the inverter group is connected to the Q output end of RS1, the inverter group is used to perform an even number of reverse transformations on the output pulse signal to improve the driving capability of the output pulse signal, and output the output pulse signal after an even number of reverse transformations through the output end of the inverter group.

[0023] Furthermore, the narrow pulse filtering circuit further comprises a second RS trigger RS2, the Set input terminal of RS2 is connected to the Set input terminal of RS1. Output connection, the Reset input of RS2 is connected to the Q output of RS1;

[0024] The first charge and discharge module is used to control the charge and discharge of the first energy storage element in the first charge and discharge module according to the input pulse signal and the output signal of the Q output terminal of RS2;

[0025] The second charging and discharging module is used to charge and discharge the battery according to the reverse pulse signal of the input pulse signal and the reverse pulse signal of RS2. The output signal of the output terminal controls the charging and discharging of the second energy storage element in the second charging and discharging module;

[0026] RS2 is used according to RS1 The output signal of the output terminal and the output signal of the Q output terminal of RS1 control the output of RS2 The output end outputs a filtered output pulse signal corresponding to the input pulse signal.

[0027] On the other hand, an embodiment of the present specification further provides a chip on which the above-mentioned narrow pulse filter circuit is formed.

[0028] The embodiment of this specification abandons the method of using a low-pass filter circuit to filter out high-frequency narrow pulse noise signals in the prior art, and instead uses two charging and discharging modules, two comparison modules and an RS trigger to filter the input pulse signal. The output signal at the output end controls the charging and discharging of the first energy storage element in the first charging and discharging module, and controls the charging and discharging of the second energy storage element in the second charging and discharging module according to the reverse pulse signal of the input pulse signal and the output signal of the Q output end of the RS trigger. The first comparison module performs waveform transformation according to the set first threshold interval and the voltage value of the first energy storage element to obtain a first control signal, and the second comparison module performs waveform transformation according to the set second threshold interval and the voltage value of the second energy storage element to obtain a second control signal, and then the two control signals are respectively input into the corresponding input ends of the RS trigger. By utilizing the characteristics of the RS trigger, a high level is output through the Q output end between the starting high level of the Set input end and the starting high level of the Reset input end of the RS trigger to obtain a filtered output pulse signal.

[0029] Through the narrow pulse filtering circuit of the embodiment of the present specification, the filtered output pulse signal output from the Q output terminal of the RS trigger has a minimum pulse width limitation, thereby ensuring that the signal with the minimum pulse width can be normally recognized and processed by the subsequent circuit, and solving the problem that when the frequency of the noise signal in the signal is at the critical value of the low-pass filter, narrow pulses will still exist in the noise signal after filtering, causing abnormal operation of the subsequent circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of this article or the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of this article. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0031] Figure 1 It is a structural schematic diagram of a narrow pulse filter circuit in an embodiment of this specification;

[0032] Figure 2 This is a key node waveform diagram when the input signal pulse width is greater than a preset threshold in the embodiment of this specification;

[0033] Figure 3 This is a key node waveform diagram when the input signal pulse width is approximately a preset threshold in the embodiment of this specification;

[0034] Figure 4 This is a key node waveform diagram when the input signal pulse width is less than a preset threshold in the embodiment of this specification;

[0035] Figure 5 It is a structural schematic diagram of a narrow pulse filter circuit in an embodiment of this specification;

[0036] Figure 6It is a schematic diagram of the structure of a narrow pulse filter circuit in another embodiment of this specification.

[0037] [Description of Reference Numerals]

[0038] 101. A first charging and discharging module;

[0039] 1011. a first energy storage element;

[0040] 102. A second charging and discharging module;

[0041] 1021. a second energy storage element;

[0042] 103. A first comparison module;

[0043] 104. A second comparison module;

[0044] RS1, the first RS flip-flop;

[0045] RS2, the second RS flip-flop;

[0046] P1, P2, P3, P4, PMOS tube;

[0047] N1, N2, N3, N4, NOMS tube;

[0048] I1, I2, current source;

[0049] C1, C2, capacitors;

[0050] SMIT1, SMIT2, Schmitt trigger;

[0051] INV1, INV2, INV3, INV4, inverter. DETAILED DESCRIPTION

[0052] The following will be combined with the drawings in the embodiments of this article to clearly and completely describe the technical solutions in the embodiments of this article. Obviously, the described embodiments are only part of the embodiments of this article, not all of the embodiments. Based on the embodiments of this article, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this article.

[0053] Figure 1 The schematic diagram of the structure of the narrow pulse filter circuit in the embodiment of the present specification includes a first charge and discharge module 101, a second charge and discharge module 102, a first comparison module 103, a second comparison module 104 and a first RS trigger RS1;

[0054] The first charging and discharging module 101 is used to charge and discharge the battery according to the input pulse signal and RS1. The output signal of the output terminal controls the charging and discharging of the first energy storage element 1011 in the first charging and discharging module 101, thereby changing the voltage value of the first energy storage element 1011;

[0055] The second charge and discharge module 102 is used to control the charge and discharge of the second energy storage element 1021 in the second charge and discharge module 102 according to the reverse pulse signal of the input pulse signal and the output signal of the Q output terminal of RS1, thereby changing the voltage value of the second energy storage element 1021;

[0056] The first comparison module 103 is used to perform waveform transformation according to a set first threshold interval and a voltage value of the first energy storage element 1011, and input the waveform transformation result to the Set input terminal of RS1, wherein the first threshold interval is set according to a narrow pulse filter width and a capacity of the first energy storage element 1011;

[0057] The second comparison module 104 is used to perform waveform transformation according to a second threshold interval and a voltage value of the second energy storage element 1021, and input the waveform transformation result to the Reset input terminal of RS1, wherein the second threshold interval is set according to the narrow pulse filter width and the capacity of the second energy storage element 1021;

[0058] RS1 is used to control the Q output terminal of RS1 to output the filtered output pulse signal corresponding to the input pulse signal according to the waveform transformation result of the first comparison module 103 and the waveform transformation result of the second comparison module 104 .

[0059] The embodiments of this specification are based on the input pulse signal and the RS trigger The output signal at the output end controls the charging and discharging of the first energy storage element 1011 in the first charging and discharging module 101, and controls the charging and discharging of the second energy storage element 1021 in the second charging and discharging module 102 according to the reverse pulse signal of the input pulse signal and the output signal of the Q output end of the RS trigger. The first comparison module 103 performs waveform transformation according to the set first threshold interval and the voltage value of the first energy storage element 1011, and the second comparison module 104 performs waveform transformation according to the set second threshold interval and the voltage value of the second energy storage element 1021.

[0060] If the width of a certain high level segment of the input pulse signal is greater than or equal to the filtering width, the first comparison module 103 outputs a first control signal, the second comparison module 104 outputs a second control signal, and the width between the starting high levels of the two control signals is equal to the width of this high level segment of the input pulse signal, thereby utilizing the characteristics of the RS trigger to achieve a high level output at the Q output terminal of the RS trigger between the starting high level of the Set input terminal of the RS trigger and the starting high level of the Reset input terminal, so that the width of the high level output at the Q output terminal is equal to the width of this high level segment of the input pulse signal.

[0061] If the high level width of the input pulse signal is smaller than the filtering width, the first comparison module 103 and the second comparison module 104 do not output a control signal, and thus cannot trigger the Q output terminal of the RS trigger to output a high level, and thus the input pulse signal is filtered out.

[0062] In the embodiments of this specification, the first energy storage element 1011 or the second energy storage element 1021 may be an energy storage element in the form of a single capacitor or multiple capacitors in parallel, or other types of energy storage elements, which are not limited in the embodiments of this specification.

[0063] In the embodiment of this specification, when the input pulse signal and RS1 When the output signals at the output end are all high level, the first energy storage element 1011 discharges; when the input pulse signal is low level or RS1 When the output signal of the output terminal is at a low level, the first energy storage element 1011 is charged;

[0064] When the input pulse signal is at a low level and the output signal of the Q output terminal of RS1 is at a high level, the second energy storage element 1021 discharges; when the input pulse signal is at a high level or the output signal of the Q output terminal of RS1 is at a low level, the second energy storage element 1021 charges.

[0065] The first threshold interval includes a first threshold voltage and a second threshold voltage, the first threshold voltage is greater than the second threshold voltage, when the voltage value of the first energy storage element 1011 is higher than the first threshold voltage, the first comparison module 103 outputs a low level; when the voltage value of the first energy storage element 1011 is lower than the second threshold voltage, the first comparison module 103 outputs a high level; when the voltage value of the first energy storage element 1011 is between the first threshold voltage and the second threshold voltage, the output level of the first comparison module 103 remains unchanged;

[0066] The second threshold interval includes a third threshold voltage and a fourth threshold voltage, the third threshold voltage is greater than the fourth threshold voltage, when the voltage value of the second energy storage element 1021 is higher than the third threshold voltage, the second comparison module 104 outputs a low level; when the voltage value of the second energy storage element 1021 is lower than the fourth threshold voltage, the second comparison module 104 outputs a high level; when the voltage value of the second energy storage element 1021 is between the third threshold voltage and the fourth threshold voltage, the output level of the second comparison module 104 remains unchanged;

[0067] Between the starting high level of the Set input terminal of RS1 and the starting high level of the Reset input terminal, the Q output terminal of RS1 outputs a high level.

[0068] like Figure 2 and Figure 3 As shown, IN represents the input pulse signal, W represents the high level width of the input pulse signal, TH represents the narrow pulse filter width, the voltage value at point X represents the voltage value of the first energy storage element 1011, the voltage value at point Y represents the voltage value of the second energy storage element 1021, the voltage value at point S represents the waveform transformation result of the first comparison module 103 (that is, the voltage value of the Set input terminal of RS1), the voltage value at point R represents the waveform transformation result of the second comparison module 104 (that is, the voltage value of the Reset input terminal of RS1), and OUT represents the output signal of the Q output terminal of RS1.

[0069] The discharge of the first energy storage element 1011 in the first charge and discharge module 101 is caused by the input pulse signal and RS1. The output signal of the output terminal is controlled together. When the input pulse signal IN and RS1 When the output signals at the output terminals are all high level (RS1 The output signal of the output terminal is initially high level, and the output signal of the Q output terminal of RS1 is initially low level), the first energy storage element 1011 discharges, and as the first energy storage element 1011 continues to discharge, the voltage value of the first energy storage element 1011 gradually decreases. That is, when IN changes from low level to high level, the voltage value of point X gradually decreases, indicating that the first energy storage element 1011 is discharged.

[0070] When the voltage value of the first energy storage element 1011 is lower than the second threshold voltage, the first comparison module 103 outputs a high level, that is, when the voltage value of point X is lower than the second threshold voltage (not shown in the figure), point S changes from a low level to a high level. At this time, point R is still at a low level. According to the characteristics of the RS trigger, when the Set input terminal is at a high level and the Reset input terminal is at a low level, the Q output terminal is at a high level (that is, OUT changes to a high level). The output is low level.

[0071] Then because The output terminal controls the charging of the first energy storage element 1011 (when the input pulse signal is low level or RS1 When the output signal at the output end is at a low level, the first energy storage element 1011 is charged), so when OUT becomes a high level, the first energy storage element 1011 is charged, and the voltage value at point X gradually increases.

[0072] When the voltage value at point X is higher than the first threshold voltage (not shown in the figure), the first comparison module 103 outputs a low level, that is, shortly after the voltage value at point X gradually increases, point S changes from a high level to a low level. At this time, point R is still at a low level. According to the characteristics of the RS trigger, when the Set input terminal is at a low level and the Reset input terminal is at a low level, the Q output terminal and The level of the output terminal does not change, so the Q output terminal is still high. The output is still low.

[0073] The discharge of the second energy storage element 1021 in the second charge and discharge module 102 is controlled by the reverse signal of the input pulse signal and the output signal of the Q output terminal of RS1. When the input pulse signal is at a low level, the reverse signal of the output pulse signal is at a high level, and the output signal of the Q output terminal of RS1 is at a high level, the second energy storage element 1021 discharges. As the second energy storage element 1021 continues to discharge, the voltage value of the second energy storage element 1021 gradually decreases. That is, when IN changes from a high level to a low level, the voltage value at point Y gradually decreases, indicating that the discharge begins.

[0074] When the voltage value of the second energy storage element 1021 is lower than the fourth threshold voltage, the second comparison module 104 outputs a high level, that is, when the voltage value of the Y point is lower than the fourth threshold voltage (not shown in the figure), the R point changes from a low level to a high level. At this time, the S point has changed from a high level to a low level. According to the characteristics of the RS trigger, when the Set input terminal is low and the Reset input terminal is high, the Q output terminal is low (that is, OUT changes to a low level). The output is high level.

[0075] Therefore, if Figure 2 and Figure 3 As shown, when the high level width W of the input pulse signal is greater than the narrow pulse filter width TH, the high level width outputted by the Q output terminal is the same as the high level width W of the input pulse signal. When the high level width W of the input pulse signal is approximately equal to the narrow pulse filter width TH, the high level width outputted by the Q output terminal is the same as the narrow pulse filter width TH.

[0076] Then, because the Q output terminal controls the charging of the second energy storage element 1021 (when the input pulse signal is high or the output signal of the Q output terminal of RS1 is low, the second energy storage element 1021 is charged), when OUT becomes low, the second energy storage element 1021 is charged and the voltage value at point Y gradually increases.

[0077] When the voltage value at point Y is higher than the third threshold voltage (not shown in the figure), the second comparison module 104 outputs a low level, that is, shortly after the voltage value at point Y gradually increases, point R changes from a high level to a low level. At this time, point S is still at a low level. According to the characteristics of the RS trigger, when the Set input terminal is at a low level and the Reset input terminal is at a low level, the Q output terminal and The level of the output terminal does not change, so the Q output terminal is still at a low level. At this time, the first energy storage element 1011 and the second energy storage element 1021 are both in a charging state (RS1 When the output signal of the output end is low, the first energy storage element is charged; when the output signal of the Q output end of RS1 is low, the second energy storage element is charged) until the first energy storage element 1011 and the second energy storage element 1021 are completely charged, and the voltage values ​​of the first energy storage element 1011 and the second energy storage element 1021 are both VDD.

[0078] like Figure 4 As shown, when the high level width W of the input pulse signal is smaller than the narrow pulse filter width TH, although as IN changes from a low level to a high level, the first energy storage element 1011 starts to discharge and the voltage value at point X gradually decreases, but because the high level width W is smaller than the narrow pulse filter width TH, the voltage value at point X becomes a low level before it is lower than the second threshold voltage (not shown in the figure), the first energy storage element 1011 starts to charge, and the voltage value at point X gradually increases.

[0079] Therefore, when the high level width W of the input pulse signal is smaller than the narrow pulse filter width TH, S, R, and OUT will not change, and OUT is still in a low level state, thereby filtering out the input pulse signal whose high level width W is smaller than the narrow pulse filter width TH.

[0080] Specifically, Figure 5 FIG. 1 is a detailed structural diagram of a narrow pulse filter circuit in an embodiment of this specification. Figure 5 As shown, the first charge and discharge module 101 includes PMOS tubes P1 and P2, NMOS tubes N1 and N2, current sources I1 and I2, and the first energy storage element (capacitor C1);

[0081] The gate of P1 and the gate of N1 are both connected to the input pulse signal, the source of P1 and the source of P2 are both connected to the second end of I1, the first end of I1 is connected to the power supply VDD, I1 is used to provide charging current to the first charging and discharging module 101, the drain of P1, the drain of P2 and the drain of N1 are all connected to the charging and discharging port of the first energy storage element (capacitor C1), the gate of P2 and the gate of N2 are both connected to the At the output end, the source of N1 is connected to the drain of N2 , the source of N2 is connected to the first end of I2 , the second end of I2 is grounded, and I2 is used to control the magnitude of the discharge current of the first charge and discharge module 101 .

[0082] The second charge and discharge module 102 includes PMOS tubes P3 and P4, NOMS tubes N3 and N4, current sources I3 and I4, and the second energy storage element (capacitor C2);

[0083] The gate of P3 and the gate of N3 are both connected to the reverse pulse signal of the input pulse signal, the source of P3 and the source of P4 are both connected to the second end of I3, the first end of I3 is connected to the power supply VDD, I3 is used to provide charging current to the second charge and discharge module 102, the drain of P3, the drain of P4 and the drain of N3 are all connected to the charge and discharge port of the second energy storage element (capacitor C2), the gate of P4 and the gate of N4 are both connected to the Q output end of RS1, the source of N3 is connected to the drain of N4, the source of N4 is connected to the first end of I4, the second end of I4 is grounded, and I4 is used to control the magnitude of the discharge current of the second charge and discharge module 102.

[0084] The first comparison module 103 includes a Schmitt trigger SMIT1 and an inverter, the input end of SMIT1 is connected to the charge and discharge port of the first energy storage element (capacitor C1), the output end of SMIT1 is connected to the input end of the inverter, and the output end of the inverter is connected to the Set input end.

[0085] The second comparison module 104 includes a Schmitt trigger SMIT2 and an inverter, the input end of SMIT2 is connected to the charge and discharge port of the second energy storage element (capacitor C2), the output end of SMIT2 is connected to the input end of the inverter, and the output end of the inverter is connected to the Reset input end.

[0086] It should be noted that the first comparison module or the second comparison module may also implement the above functions through a comparator, and the embodiments of this specification do not limit this.

[0087] In the embodiment of this specification, when RS1 When the output signal of the output terminal is high and the output signal of the Q output terminal of RS1 is low (initial state), when the input pulse signal IN changes from low level to high level, P1 and P2 are cut off, N1 and N2 are turned on, and the charge on the capacitor C1 begins to discharge through N1 and N2. I2 controls the size of the discharge current to I2. 放 , the voltage at point X starts to decrease from VDD. When it decreases to the second threshold voltage VIL1 (let the use time be t1), SMTI1 starts to flip, and the signal at the Set input end changes from low level to high level. At this time, the Q output end changes from low level to high level. The output terminal changes from high level to low level;

[0088] when The output terminal is low level, the Q output terminal is high level, N2 is turned off, and P2 is turned on. At this time, the capacitor C1 no longer discharges through N1 and N2, and the current source I1 charges the capacitor C1. When the voltage at point X rises to the first threshold voltage VIH1, SMTI1 starts to flip, and the signal at the Set input terminal changes from high level to low level. Because the Reset terminal is still low level at this time, The Q output terminal remains at a low level and the Q output terminal remains at a high level.

[0089] Where, t1 = C1 (VDD-VIL1) / I2 放 , t1 is the narrow pulse filter width, C1 is the capacitance of capacitor C1, and the second threshold voltage VIL1 can be calculated. The second threshold voltage VIL1<the first threshold voltage VIH1<VDD. In actual implementation, the first threshold voltage VIH1 can be slightly higher than the second threshold voltage VIL1.

[0090] when The output terminal is low level, the Q output terminal is high level, when IN changes from high level to low level, P3 and P4 are cut off, N3 and N4 are turned on, and the charge on capacitor C2 begins to discharge through N3 and N4. I4 controls the size of the discharge current to I4. 放 , the voltage at point Y starts to decrease from VDD. When it decreases to the fourth threshold voltage VIL2 (assuming that the use time is t2), SMTI2 starts to flip, and the Reset terminal changes from low level to high level. At this time, the Set input terminal is still at a low level, so The output terminal changes from low level to high level, and the Q output terminal still changes from high level to low level;

[0091] when The output terminal is high level, the Q output terminal is low level, N4 is turned off, and P4 is turned on. At this time, capacitor C2 no longer discharges through N3 and N4, and current source I3 charges capacitor C2. When the voltage at point Y rises to the third threshold voltage VIH2, SMTI2 starts to flip, and the Reset terminal changes from high level to low level. At this time, the Set input terminal is still low level, so The Q output terminal remains at a high level and the Q output terminal remains at a low level.

[0092] Where, t2 = C2 (VDD-VIL2) / I4 放 , t2 is the narrow pulse filter width, t2=t1, C2 is the capacitance of capacitor C2, and the fourth threshold voltage VIL2 can be calculated. The fourth threshold voltage VIL2<the third threshold voltage VIH2<VDD. In actual implementation, the third threshold voltage VIH2 can be slightly higher than the fourth threshold voltage VIL2.

[0093] When IN changes from low level to high level again, the above process is repeated.

[0094] If the high level width W of IN is less than the narrow pulse filter width TH, then when RS1 When the output signal of the output terminal is high and the output signal of the Q output terminal of RS1 is low (initial state), when the input pulse signal IN changes from low level to high level, P1 and P2 are cut off, N1 and N2 are turned on, and the charge on the capacitor C1 begins to discharge through N1 and N2. I2 controls the size of the discharge current to I2. 放 , the voltage at point X starts to decrease from VDD, but when the voltage at point X does not decrease to VIL1, IN changes from high level to low level. At this time, the current source I1 charges the capacitor C1, and the voltage at point X gradually increases, so SMTI1 is not triggered to flip, and the output signal at the Q output end of RS1 is still low level, thereby filtering out the signal whose pulse width is less than the narrow pulse filter width TH.

[0095] In the embodiment of this specification, in order to realize that the input pulse signal controls the charging and discharging of the capacitor C1 in the first charging and discharging module 101, and the reverse signal of the input pulse signal controls the charging and discharging of the capacitor C2 in the second charging and discharging module 102, as shown in FIG. Figure 5 As shown, the narrow pulse filter circuit of the embodiment of this specification also includes inverters INV1 and INV2, wherein the input end of the inverter INV1 inputs a pulse signal, and after inversion, the output end of INV1 outputs an inverse signal to the gate of P3 and the gate of N3. At the same time, the output end of INV1 is connected to the input end of the inverter INV2, and after inversion of INV2, the output end of INV1 outputs a pulse signal identical to the input pulse signal to the gate of P1 and the gate of N1.

[0096] It should be noted that in addition to using Figure 5 In addition to the inverters INV1 and INV2 shown, other methods can also be used to implement the input pulse signal to control the charging and discharging of the capacitor C1 in the first charging and discharging module 101, and at the same time, the reverse signal of the input pulse signal controls the charging and discharging of the capacitor C2 in the second charging and discharging module 102. This specification is an embodiment and is not limited to this.

[0097] In the embodiments of the present specification, in order to increase the driving capability of the output pulse signal after filtering, the narrow pulse filter circuit also includes an inverter group consisting of an even number of inverters connected in series, the input end of the inverter group is connected to the Q output end of RS1, and the inverter group is used to perform an even number of reverse transformations on the output pulse signal to improve the driving capability of the output pulse signal, and output the output pulse signal after an even number of reverse transformations through the output end of the inverter group.

[0098] It should be noted that an inverter group may be formed by using an even number of inverters connected in series, such as 2 inverters, 4 inverters, 6 inverters, etc., and the embodiments of this specification do not limit this.

[0099] Preferably, if Figure 5 As shown, the narrow pulse filter circuit also includes inverters INV3 and INV4, the input end of INV3 is connected to the Q output end of RS1, the input end of INV4 is connected to the output end of INV3, and the output end of INV4 outputs a pulse signal with enhanced driving capability.

[0100] In practical applications, the larger the minimum pulse width of the filtered pulse signal output by the narrow pulse filter circuit, the easier it is to process in the subsequent circuit. Figure 6 As shown, the narrow pulse filtering circuit also includes a second RS trigger RS2, the Set input terminal of RS2 is connected to the Set input terminal of RS1. Output connection, Reset input of RS2 is connected to Q1 output of RS1;

[0101] The first charge and discharge module 101 is used to control the charge and discharge of the first energy storage element 1011 in the first charge and discharge module 101 according to the input pulse signal and the output signal of the Q output terminal of RS2;

[0102] The second charging and discharging module 102 is used to generate a reverse pulse signal according to the input pulse signal and the reverse pulse signal of RS2. The output signal of the output terminal controls the charging and discharging of the second energy storage element 1021 in the second charging and discharging module 102;

[0103] RS2 is used according to RS1 The output signal of the output terminal and the output signal of Q1 output terminal of RS1 control the output of RS2 The output end outputs a filtered output pulse signal corresponding to the input pulse signal.

[0104] According to the principle of RS trigger, The pulse width of the output signal at the output end is slightly larger than the pulse width of the output signal at the Q output end, and the difference is approximately tdh. Therefore, after adding one level of RS trigger, the minimum pulse width of the output pulse signal after the input pulse signal passes through the narrow pulse filter circuit is TH≈t1+tdh (or TH≈t2+tdh).

[0105] Based on the same inventive concept, an embodiment of the present specification further provides a chip, on which the narrow pulse filter circuit described in the embodiment of the present specification is formed.

[0106] It should be understood that in the various embodiments of this document, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this document.

[0107] It should also be understood that in the embodiments of this article, the term "and / or" is only a description of the association relationship of the associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0108] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this article.

[0109] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0110] In the several embodiments provided herein, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of the units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, or can be electrical, mechanical or other forms of connection.

[0111] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the embodiments of this article.

[0112] In addition, each functional unit in each embodiment of this invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above integrated unit may be implemented in the form of hardware or in the form of software functional unit.

[0113] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this article is essentially or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of this article. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program codes.

[0114] Specific embodiments are used in this article to illustrate the principles and implementation methods of this article. The description of the above embodiments is only used to help understand the methods and core ideas of this article. At the same time, for general technicians in this field, according to the ideas of this article, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as a limitation on this article.

Claims

1. A narrow pulse filter circuit, It is characterized in that include: A first charge and discharge module, a second charge and discharge module, a first comparison module, a second comparison module and a first RS trigger RS1; The first charging and discharging module is used to charge and discharge the battery according to the input pulse signal and RS1. The output signal of the output terminal controls the charging and discharging of the first energy storage element in the first charging and discharging module, thereby changing the voltage value of the first energy storage element; The second charge and discharge module is used to control the charge and discharge of the second energy storage element in the second charge and discharge module according to the reverse pulse signal of the input pulse signal and the output signal of the Q output terminal of RS1, thereby changing the voltage value of the second energy storage element; The first comparison module is used to perform waveform transformation according to a set first threshold interval and a voltage value of the first energy storage element, and input the waveform transformation result to the Set input terminal of RS1, wherein the first threshold interval is set according to a narrow pulse filter width and a capacity of the first energy storage element; The second comparison module is used to perform waveform transformation according to a second threshold interval and a voltage value of the second energy storage element, and input the waveform transformation result to the Reset input terminal of RS1, wherein the second threshold interval is set according to the narrow pulse filter width and the capacity of the second energy storage element; RS1 is used to control the Q output terminal of RS1 to output a filtered output pulse signal corresponding to the input pulse signal according to the waveform transformation result of the first comparison module and the waveform transformation result of the second comparison module.

2. The narrow pulse filter circuit according to claim 1, It is characterized in that When the input pulse signal and RS1 When the output signals at the output end are all high level, the first energy storage element discharges; when the input pulse signal is low level or RS1 When the output signal at the output end is at a low level, the first energy storage element is charged; When the input pulse signal is at a low level and the output signal of the Q output terminal of RS1 is at a high level, the second energy storage element discharges; when the input pulse signal is at a high level or the output signal of the Q output terminal of RS1 is at a low level, the second energy storage element charges.

3. The narrow pulse filter circuit according to claim 1, It is characterized in that The first threshold interval includes a first threshold voltage and a second threshold voltage, the first threshold voltage is greater than the second threshold voltage, when the voltage value of the first energy storage element is higher than the first threshold voltage, the first comparison module outputs a low level; when the voltage value of the first energy storage element is lower than the second threshold voltage, the first comparison module outputs a high level; when the voltage value of the first energy storage element is between the first threshold voltage and the second threshold voltage, the output level of the first comparison module remains unchanged; The second threshold interval includes a third threshold voltage and a fourth threshold voltage, the third threshold voltage is greater than the fourth threshold voltage, when the voltage value of the second energy storage element is higher than the third threshold voltage, the second comparison module outputs a low level; when the voltage value of the second energy storage element is lower than the fourth threshold voltage, the second comparison module outputs a high level; when the voltage value of the second energy storage element is between the third threshold voltage and the fourth threshold voltage, the output level of the second comparison module remains unchanged; Between the starting high level of the Set input terminal of RS1 and the starting high level of the Reset input terminal, the Q output terminal of RS1 outputs a high level.

4. The narrow pulse filter circuit according to claim 1, It is characterized in that The first charge and discharge module includes PMOS tubes P1 and P2, NMOS tubes N1 and N2, current sources I1 and I2, and the first energy storage element; The gate of P1 and the gate of N1 are both connected to the input pulse signal, the source of P1 and the source of P2 are both connected to the second end of I1, the first end of I1 is connected to the power supply, I1 is used to provide charging current to the first charging and discharging module, the drain of P1, the drain of P2 and the drain of N1 are all connected to the charging and discharging port of the first energy storage element, the gate of P2 and the gate of N2 are both connected to the At the output end, the source of N1 is connected to the drain of N2, the source of N2 is connected to the first end of I2, the second end of I2 is grounded, and I2 is used to control the magnitude of the discharge current of the first charge and discharge module.

5. The narrow pulse filter circuit according to claim 1, It is characterized in that The second charge and discharge module includes PMOS tubes P3 and P4, NOMS tubes N3 and N4, current sources I3 and I4, and the second energy storage element; The gate of P3 and the gate of N3 are both connected to the reverse pulse signal of the input pulse signal, the source of P3 and the source of P4 are both connected to the second end of I3, the first end of I3 is connected to the power supply, I3 is used to provide charging current to the second charge and discharge module, the drain of P3, the drain of P4 and the drain of N3 are all connected to the charge and discharge port of the second energy storage element, the gate of P4 and the gate of N4 are both connected to the Q output end of RS1, the source of N3 is connected to the drain of N4, the source of N4 is connected to the first end of I4, the second end of I4 is grounded, and I4 is used to control the discharge current of the second charge and discharge module.

6. The narrow pulse filter circuit according to claim 1, It is characterized in that The first comparison module includes a Schmitt trigger SMIT1 and an inverter, the input end of SMIT1 is connected to the charge and discharge port of the first energy storage element, the output end of SMIT1 is connected to the input end of the inverter, and the output end of the inverter is connected to the Set input end.

7. The narrow pulse filter circuit according to claim 1, It is characterized in that The second comparison module includes a Schmitt trigger SMIT2 and an inverter, the input end of SMIT2 is connected to the charge and discharge port of the second energy storage element, the output end of SMIT2 is connected to the input end of the inverter, and the output end of the inverter is connected to the Reset input end.

8. The narrow pulse filter circuit according to claim 1, It is characterized in that The narrow pulse filter circuit also includes an inverter group consisting of an even number of inverters connected in series, the input end of the inverter group is connected to the Q output end of RS1, the inverter group is used to perform an even number of reverse transformations on the output pulse signal to improve the driving ability of the output pulse signal, and output the output pulse signal after an even number of reverse transformations through the output end of the inverter group.

9. The narrow pulse filter circuit according to claim 1, It is characterized in that The narrow pulse filtering circuit further includes a second RS trigger RS2, the Set input terminal of RS2 is connected to the Set input terminal of RS1 Output connection, the Reset input of RS2 is connected to the Q output of RS1; The first charge and discharge module is used to control the charge and discharge of the first energy storage element in the first charge and discharge module according to the input pulse signal and the output signal of the Q output terminal of RS2; The second charging and discharging module is used to charge and discharge the battery according to the reverse pulse signal of the input pulse signal and the reverse pulse signal of RS2. The output signal of the output terminal controls the charging and discharging of the second energy storage element in the second charging and discharging module; RS2 is used according to RS1 The output signal of the output terminal and the output signal of the Q output terminal of RS1 control the output of RS2 The output end outputs a filtered output pulse signal corresponding to the input pulse signal.

10. A chip, It is characterized in that The narrow pulse filter circuit described in any one of claims 1 to 9 is formed on the chip.

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