Current sharing control method, device and medium for bidirectional CLLLC circuit

Abstract

The present invention discloses a current sharing control method, device and medium of a bidirectional CLLLC circuit, which relates to the technical field of power conversion. The current difference of the primary side of each CLLLC branch is detected in real time to obtain the primary current error factor; at the same time, the zero-crossing point of the secondary output current of each CLLLC branch is detected to generate a time difference relative to the zero point. According to the primary current error factor, the duty cycle of the primary tube of each CLLLC branch is controlled and adjusted through the negative feedback of the PI loop; at the same time, the switch of the secondary synchronous rectification tube is controlled through the time difference, so that the primary and secondary sides jointly control the gain of each CLLLC branch, thereby realizing the current sharing adjustment of each CLLLC branch, and solving the problem of uneven current of different CLLLC branches caused by the staggered parallel control method of the bidirectional CLLLC circuit of multiple branches.

Description

Technical Field

[0001] The present invention relates to the technical field of power conversion, and in particular to a current sharing control method, device and medium for a bidirectional CLLLC circuit. Background Art

[0002] With the continuous development of power electronics technology, the application of bidirectional CLLLC resonant DC / DC converter is becoming more and more extensive. It is a very important main topology of switching power supply, which can realize bidirectional transmission of energy. Soft switching in the full load range can be achieved near the resonant switching frequency. It has excellent soft switching characteristics, high efficiency, high power density and other advantages, and has become a hot spot in the power supply industry. With the increasing demand for bidirectional CLLLC high-power switching power supplies, high-power applications are becoming more and more extensive. The increase in magnetic components such as the resonant cavity inductor and transformer of the high-power bidirectional CLLLC circuit increases the output current ripple, and the output filter capacitor also increases. This will lead to increased losses, reduced efficiency, decreased power density, and increased cost and volume of the bidirectional CLLLC topology circuit. In order to pursue the principles of high power density, high efficiency, low cost and small volume, multiple parallel bidirectional CLLLC branches are generated to share power, and the staggered parallel method is used to reduce the output current ripple. The staggered parallel connection of the bidirectional CLLLC circuit is to keep the switching frequencies of the parallel multiple bidirectional CLLLC branches consistent, and each branch is staggered by a certain phase, which can greatly reduce the output current ripple.

[0003] When a bidirectional CLLLC circuit with multiple branches adopts an interleaved parallel control method, it will also bring about the problem of current sharing in different CLLLC branches. If the bidirectional CLLLC branches are not current-balanced, the components of the bidirectional CLLLC branches with excessive bias current may heat up seriously or even burn out, posing a serious safety hazard. At the same time, as more bidirectional CLLLC branches are connected in parallel, it is difficult to make the parameters of the magnetic components of each branch consistent. The inconsistency of the parameters of the magnetic components will bring about the problem of uneven current sharing in each branch, seriously affecting the reliability of the CLLLC circuit. Summary of the invention

[0004] The object of the present invention is to provide a current sharing control method, device and medium for a bidirectional CLLLC circuit, which can realize current sharing regulation and control of bidirectional CLLLC circuits in different parallel modes.

[0005] To achieve the above object, the present invention provides the following solutions:

[0006] A current sharing control method for a bidirectional CLLLC circuit, wherein the bidirectional CLLLC circuit is a multi-channel parallel circuit, and the multi-channel parallel bidirectional CLLLC circuit includes a plurality of CLLLC branches, and the plurality of CLLLC branches are bidirectionally staggered in parallel; the primary sides of the forward and reverse CLLLC branches adopt staggered phase control, and the secondary sides of the CLLLC branches adopt synchronous rectification control, and the current sharing control method for the bidirectional CLLLC circuit includes:

[0007] Real-time detection of the primary current of each CLLLC branch, and calculation of the primary current error factor of each CLLLC branch according to the primary current value;

[0008] Real-time detection of the zero-crossing point of the secondary-side output current of each CLLLC branch, and calculation of the time difference between the switching time of the secondary-side synchronous rectifier tube and the zero-crossing time according to the detected zero-crossing point;

[0009] The duty cycle of the primary switch tube of each CLLLC branch is controlled according to the primary current error factor and the PI operation; at the same time, the switch of the secondary synchronous rectifier tube of each CLLLC branch is controlled according to the time difference to realize the current sharing control of the bidirectional CLLLC circuit.

[0010] A computer device includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the above-mentioned current sharing control method for a bidirectional CLLLC circuit.

[0011] A computer-readable storage medium stores a computer program, which, when executed by a processor, implements the above-mentioned current sharing control method for a bidirectional CLLLC circuit.

[0012] According to the specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0013] The present invention provides a current sharing control method, device and medium for a bidirectional CLLLC circuit. The method detects the primary current error factor of each CLLLC branch in real time and performs PI operation to obtain the duty cycle adjustment amount of the primary switch tube of each branch. At the same time, the switch of the secondary synchronous rectification tube is controlled by the time difference ΔS, so that the primary and secondary sides jointly control the gain of each CLLLC branch, and the current sharing adjustment control of the bidirectional CLLLC circuit in different parallel modes can be realized. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0015] Figure 1 A flow chart of a current sharing control method for a bidirectional CLLLC circuit provided by the present invention;

[0016] Figure 2 A detailed flow chart of a current sharing control method for a bidirectional CLLLC circuit provided by the present invention;

[0017] Figure 3 A schematic diagram of a bidirectional CLLLC circuit with parallel input and parallel output provided by the present invention;

[0018] Figure 4 A schematic diagram of a bidirectional CLLLC circuit with serial input and parallel output provided by the present invention;

[0019] Figure 5 A schematic diagram of a bidirectional CLLLC circuit with parallel input and series output provided by the present invention;

[0020] Figure 6 A schematic diagram of the voltage gain of a bidirectional CLLLC in a frequency modulation mode provided by the present invention;

[0021] Figure 7 A schematic diagram for comparing the output current ripples of two CLLLC circuits staggered π / 2 provided by the present invention;

[0022] Figure 8 The relationship diagram between the primary and secondary tube drive and the secondary current provided by the present invention. DETAILED DESCRIPTION

[0023] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0024] The purpose of the present invention is to provide a current sharing control method, device and medium for a bidirectional CLLLC circuit. By controlling the duty cycle of the primary side of each CLLLC branch and controlling the opening and closing time of the secondary side synchronous tube, the gain of each CLLLC branch can be better adjusted to achieve current sharing control of multiple parallel bidirectional CLLLC circuits.

[0025] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0026] Example 1

[0027] like Figure 1 and Figure 2 As shown, a current sharing control method for a bidirectional CLLLC circuit in this embodiment is specifically a current sharing control method for a multi-way parallel bidirectional CLLLC circuit, wherein the multi-way parallel bidirectional CLLLC circuit comprises a plurality of CLLLC branches bidirectionally staggered in parallel; the primary sides of each forward and reverse CLLLC branch adopt staggered phase control, and the secondary sides of each CLLLC branch adopt synchronous rectification control, and the current sharing control method for the bidirectional CLLLC circuit comprises:

[0028] S1: Real-time detection of the primary current of each CLLLC branch, and calculation of the primary current error factor ε(n) of each CLLLC branch according to the primary current value. ε(n) is the primary current error factor of a CLLLC branch at the nth moment.

[0029] S2: Detect the zero-crossing point of the secondary output current of each CLLLC branch in real time, and calculate the time difference ΔS between the switching time of the secondary synchronous rectifier tube and the zero-crossing time according to the detected zero-crossing point.

[0030] S3: Control the duty cycle of the primary switch tube of each CLLLC branch according to the primary current error factor ε(n) and the PI operation; at the same time, control the switch of the secondary synchronous rectifier tube of each CLLLC branch according to the time difference ΔS to achieve the primary and secondary sides jointly controlling the gain of each CLLLC branch, thereby achieving current equalization regulation of each CLLLC branch.

[0031] The time difference ΔS relative to the zero point is generated according to the zero-crossing point of the secondary output current of each CLLLC branch, which is a control method for synchronous rectification acting on the secondary side.

[0032] Wherein, in step S3, the duty cycle of the primary switch tube of each CLLLC branch is controlled according to the primary current error factor and the PI operation, which specifically includes:

[0033] (1) Substitute the primary current error factor of each CLLLC branch into the PI calculation formula to obtain the current sharing adjustment factor of each CLLLC branch.

[0034] Wherein, the calculation formula of the primary current error factor is:

[0035] ε i =I i-(I1+I2+I3+I4+.....I N ) / N;

[0036] Where i=1~N; i and N are integers, N is the number of CLLLC branches; I i is the primary current of the i-th CLLLC branch. I1, I2, I3, I4.....I N They correspond to the primary currents of the 1st, 2nd, 3rd, 4th, ... Nth CLLLC branches respectively. ε i is the primary current error factor of the i-th CLLLC branch, which can be written as ε i (n), which represents the primary current error factor of the i-th CLLLC branch at the n-th moment.

[0037] The PI calculation formula is: d(n)=d(n-1)+Kp×ε(n)+K I ×ε(n); where d(n) represents the current sharing adjustment factor of the CLLLC branch at the nth moment, d(n-1) represents the current sharing adjustment factor of the CLLLC branch at the n-1th moment; ε(n) represents the primary current error factor of the CLLLC branch at the nth moment; Kp and K I They represent the proportional coefficient and integral coefficient of the PI controller respectively.

[0038] (2) Determine the duty cycle of the primary switch tube of each CLLLC branch according to the current sharing adjustment factor of each CLLLC branch.

[0039] As an optional implementation, before executing the step of "substituting the primary current error factor of each CLLLC branch into the PI calculation formula to obtain the current sharing adjustment factor of each CLLLC branch", it is necessary to compare the primary current error factor with the corresponding maximum and minimum values ​​to perform limiting control, such as Figure 2 As shown, specifically including:

[0040] For each CLLLC branch, determine whether the primary current error factor ε(n) is greater than the maximum primary current error factor ε max If so, the value of the primary current error factor ε(n) is replaced by the maximum value of the primary current error factor ε max If not, determine whether the primary current error factor ε(n) is less than the minimum primary current error factor ε min If so, the value of the primary current error factor ε(n) is replaced by the minimum value of the primary current error factor ε min If not, no replacement operation is performed on the primary current error factor.

[0041] As an optional implementation manner, before executing the step of “determining the duty cycle of the primary switch tube of each CLLLC branch according to the current sharing adjustment factor of each CLLLC branch”, it also includes:

[0042] 1) For each CLLLC branch, determine whether the current sharing adjustment factor d(n) is greater than the maximum value of the current sharing adjustment factor d max If yes, then replace the value of the current sharing adjustment factor d(n) with the maximum value of the current sharing adjustment factor d max If not, determine whether the current sharing adjustment factor d(n) is less than the minimum value d of the current sharing adjustment factor. min If yes, then replace the value of the current sharing adjustment factor d(n) with the minimum value of the current sharing adjustment factor d min If not, no replacement operation is performed on the current sharing adjustment factor.

[0043] 2) Determine the duty cycle of the primary switch of each CLLLC branch according to the current sharing adjustment factor d(n) of each CLLLC branch. Figure 2 As shown, this step specifically includes:

[0044] 21) Determine whether the primary current of the i-th CLLLC branch is greater than the primary current of the i+1-th CLLLC branch.

[0045] 22) If yes, then the duty cycle of the primary switch tube of the i-th CLLLC branch is subtracted from the current sharing adjustment factor to obtain an updated duty cycle value of the primary switch tube of the i-th CLLLC branch, that is, D i (n) = D i (n)-d(n); add the duty cycle of the primary switch tube of the i+1th CLLLC branch to the current sharing adjustment factor to obtain the updated duty cycle value of the primary switch tube of the i+1th CLLLC branch, that is, D i+1 (n) = D i+1 (n)+d(n). Where D i (n) represents the duty cycle of the primary switch of the i-th CLLLC branch; D i+1 (n) represents the duty cycle of the primary switch tube of the i+1th CLLLC branch.

[0046] 23) If not, add the current sharing adjustment factor to the duty cycle of the primary switch tube of the i-th CLLLC branch to obtain an updated duty cycle value of the primary switch tube of the i-th CLLLC branch, D i (n) = D i (n)+d(n); subtract the current sharing adjustment factor from the duty cycle of the primary switch tube of the i+1th CLLLC branch to obtain an updated duty cycle value of the primary switch tube of the i+1th CLLLC branch, Di+1 (n) = D i+1 (n)-d(n).

[0047] As an optional implementation, after executing step S2 of "calculating the time difference between the switching time of the secondary synchronous rectifier tube and the zero-crossing time according to the detected zero-crossing point", it is necessary to further compare the time difference with the corresponding maximum and minimum values, such as Figure 2 As shown, this step further includes:

[0048] (1) Determine whether the time difference ΔS is greater than the maximum time difference ΔS max .

[0049] (2) If yes, then replace the value of the time difference ΔS with the maximum value of the time difference ΔS max .

[0050] (3) If not, determine whether the time difference ΔS is less than the minimum time difference ΔS min .

[0051] (4) If yes, then replace the value of the time difference ΔS with the minimum time difference ΔS min .

[0052] (5) If not, no replacement operation is performed on the time difference.

[0053] Among them, Figure 2 As shown, in the CLLLC branch with a relatively large output current, the secondary synchronous rectifier tube is turned on by the time difference ΔS in advance of the first zero crossing of the secondary output current, and is turned off by the time difference ΔS in delay at the second zero crossing. In the CLLLC branch with a relatively small output current, the secondary synchronous rectifier tube is turned on and off at the first and second zero crossings of the secondary output current. In step S3, the switch of the secondary synchronous rectifier tube of each CLLLC branch is controlled according to the time difference, specifically including:

[0054] (1) If the primary current of the i-th CLLLC branch is greater than the primary current of the i+1-th CLLLC branch, the secondary synchronous rectifier of the i-th CLLLC branch is turned on ΔS ahead of the first zero crossing of the output current and turned off ΔS behind the second zero crossing; the secondary synchronous rectifier of the i+1-th CLLLC branch is turned on at the first zero crossing of the output current and turned off at the second zero crossing.

[0055] (2) If the primary current of the i-th CLLLC branch is less than the primary current of the i+1-th CLLLC branch, the secondary synchronous rectifier of the i-th CLLLC branch is turned on at the first zero crossing of the output current and turned off at the second zero crossing; the secondary synchronous rectifier of the i+1-th CLLLC branch is turned on ΔS time in advance at the first zero crossing of the output current and turned off ΔS time in advance at the second zero crossing.

[0056] In this embodiment, the primary current error factor ε is obtained by real-time detection of the current difference of the primary side of each CLLLC branch; at the same time, the zero-crossing point of the secondary output current of each CLLLC branch is detected to generate a time difference ΔS relative to the zero point. According to the primary current error factor ε, the duty cycle of the primary tube of each CLLLC branch is controlled and adjusted in combination with the negative feedback of the PI loop; at the same time, the switch of the secondary synchronous rectifier tube is controlled by the time difference ΔS, so that the primary and secondary sides jointly control the gain of each CLLLC branch, thereby realizing the equal current regulation of each CLLLC branch. The present invention can better adjust the gain of each CLLLC branch by controlling the duty cycle D of the primary side of each CLLLC branch and controlling the opening and closing time of the secondary synchronous tube, thereby realizing the equal current control of multi-way parallel bidirectional CLLLC circuits.

[0057] Example 2

[0058] In order to achieve current sharing regulation of multiple parallel bidirectional CLLLC circuits and pursue the requirements of high efficiency and high power density, the current sharing control method of Example 1 can be applied to three types of bidirectional CLLLC parallel circuits. The staggered parallel bidirectional CLLLC circuit can meet the high power density output of high power, and the current sharing of multiple parallel circuits can be achieved through current sharing control regulation. Figures 3 to 5 .

[0059] The following is the gain calculation formula for the CLLLC topology circuit:

[0060]

[0061] The parameters in the above formula are defined as follows:

[0062] , represents the quality factor; , represents the equivalent resistance reflected from the output load resistance to the primary side, and p is the turns ratio between the primary side and the secondary side of the transformer; , represents the normalized switching frequency; , represents the resonant frequency; , represents the minimum switching frequency, that is, the resonance of the resonant inductance and the excitation inductance; , which represents the ratio of the primary overall inductance to the resonant inductance. Lr represents the resonant inductance, Cr represents the resonant capacitor capacity, R0 represents the output load equivalent resistance, and Lm represents the excitation inductance.

[0063] For different Q values ​​and different m values, draw a curve between the CLLLC resonant cavity gain G and the switching frequency, such as Figure 6 As shown, Figure 6 middle, Yes In Use f s It means that according to the bidirectional CLLLC topology principle, the switching frequency f is selected in the design. s The range is: f m <f s <f max ;f max is the maximum switching frequency, which is determined according to the losses of different bidirectional CLLLC circuits.

[0064] According to the gain calculation formula and the previous paragraph, the gain of the CLLLC circuit topology is adjustable. When the Q value and m value of the circuit topology are fixed, the gain can be changed by changing the switching frequency of the CLLLC topology according to the gain calculation formula. By changing the duty cycle of the primary MOS tube and the zero-crossing turn-on and turn-off time difference ΔS of the secondary synchronous rectifier tube, the switching frequency of the CLLLC topology is changed, that is, the gain of the topology is changed, thereby realizing the current sharing control of multiple CLLLC circuits.

[0065] For a bidirectional CLLLC circuit with two paths interlaced in parallel, to achieve the two paths interlaced in parallel, the switching frequencies of the two paths need to be kept consistent to achieve the phase stagger of the two paths. The phase stagger of the two paths is π / 2, which can further reduce the output current ripple of the two paths.

[0066] The output current waveform of the first bidirectional CLLLC circuit is approximately a sine wave, that is:

[0067] ;

[0068] The second bidirectional CLLLC circuit is out of phase with the first circuit by π / 2, and its output current waveform is:

[0069] ;

[0070] The current waveform of the two parallel outputs is: ,like Figure 7 As shown, by adding two output currents with a phase difference of π / 2, it can be seen that the output current ripple can be greatly reduced.

[0071] The bidirectional CLLLC circuit operates near the resonant frequency point. When the Q and m values are fixed, in order to overcome the current sharing problem caused by the inconsistency of hardware parameters such as the resonant cavities of the two-way CLLLC circuits, it is necessary to adjust the duty cycles of the two paths and the on and off timings of the secondary synchronous rectifier transistors to jointly change the gains of the two-way CLLLC circuits.

[0072] Since the upper and lower transistors on the primary side are in a complementary wave generation mode, the adjustment range of the duty cycle D is: D min < D < 0.5, and the adjustment of the duty cycle and the gain size are in a proportional relationship.

[0073] The current sharing control method of the present invention is applied to the two-way interleaved parallel CLLLC circuit. The technical solution adopted to solve the current sharing of the two-way interleaved parallel CLLLC circuit is: the primary sides of each CLLLC branch in the forward and reverse directions adopt interleaved phase control, and the secondary side adopts synchronous rectification control. By detecting the current difference of the primary sides of each CLLLC branch in real time, the primary side current error factor ε is obtained; at the same time, the zero-crossing points of the secondary side output currents of each CLLLC branch are detected to generate a time difference ΔS relative to the zero point. According to the primary side current error factor ε, combined with the negative feedback of the PI loop, the duty cycle D of the primary side transistors of each CLLLC branch is controlled and adjusted; at the same time, the switching of the secondary side synchronous rectifier transistors is controlled by the time difference ΔS to realize the joint control of the gains of each CLLLC branch by the primary side and the secondary side, thereby realizing the current sharing adjustment of each CLLLC branch.

[0074] Figure 3 A bidirectional CLLLC circuit with input parallel and output parallel (two-way interleaved parallel CLLLC circuit) is shown.

[0075] Among them, L1 and L2 are the two-way CLLLC branches of the two paths respectively. In the first branch L1, the input voltage is: Vin1 = (Vin+) - (Vin-), where Q1, Q2, Q3, Q4 are the switching transistors of the primary side CLLLC of the full bridge, Lr1, Lr2 are the primary side resonant inductors, C1 is the primary side resonant capacitor, T1, T2 are transformers, T1-1, T1-2 are the primary side and secondary side of transformer T1, T2-1, T2-2 are the primary side and secondary side of transformer T2, Lr3, Lr4 are the secondary side resonant inductors, C2 is the secondary side resonant capacitor, C3 is the output filter capacitor, and Q5, Q6, Q7, Q8 are the secondary side CLLLC synchronous rectification switching transistors of the full bridge;

[0076] In the second branch L2, the input voltage is: Vin2 = (Vin+) - (Vin-), where Q9, Q10, Q11, and Q12 are the primary CLLLC switches of the full bridge, Lr5 and Lr6 are the primary resonant inductors, C4 is the primary resonant capacitor, T3 and T4 are transformers, T3-1 and T3-2 are the primary and secondary sides of transformer T3, T4-1 and T4-2 are the primary and secondary sides of transformer T4, Lr7 and Lr8 are the secondary resonant inductors, C5 is the secondary resonant capacitor, C6 is the output filter capacitor, Q13, Q14, Q15, and Q16 are the secondary CLLLC synchronous rectifier switches of the full bridge, and R1 is the output load. IL1 and IL2 are the primary resonant cavity currents of the first and second CLLLC branches, respectively. Iout1 and Iout2 are the output currents of the first and second CLLLC branches, respectively. The two bidirectional CLLLC circuits control the primary switch tubes to generate waves by staggered parallel connection at the same frequency. The two phases are staggered by π / 2, and the switching frequency of the primary full-bridge switch tubes is consistent, which can greatly reduce the output current ripple. The specific effects are as follows: Figure 7 As shown. The secondary side adopts synchronous rectification control, and the switch tube on the secondary side follows the wave of the switch tube on the primary side. The synchronous rectification can greatly reduce the loss of the secondary side switch tube, thereby preventing the switch tube body diode from overheating and damage, and can also reduce the module size and cost. The current sharing error of the two-way bidirectional CLLLC circuit is ε(n)=IL1-IL2, which represents the difference in the primary current or ε(n)=Iout1-Iout2, which represents the difference in the secondary current. In this embodiment, the primary current error factor ε(n)=IL1-IL2 is selected for current sharing control, and the secondary current error factor ε(n)=Iout1-Iout2 is not selected for current sharing control. The current sharing control process of the two-way bidirectional CLLLC circuit is as follows. Figure 2 As shown, the primary current error ε is first limited. When ε(n)>ε max， Then ε(n)=ε max ; When ε(n)<ε min， Then ε(n)=ε min ; When ε min <ε(n))<ε max， Then ε(n)=ε(n). d(n)=d(n-1)+Kp×ε(n)+K I ×ε(n), where d(n-1) is the current sharing adjustment factor of the CLLLC branch at the n-1th moment, d(n) is the current sharing adjustment factor of the CLLLC branch at the nth moment, Kp is the proportional coefficient of the PI controller, K Iis the integral coefficient of the PI controller, and ε(n) is the error factor of the CLLLC branch at the nth moment. The current sharing regulation factor d(n) of the CLLLC branch at the nth moment is limited. When d(n) > d max， then d(n) = d max ; when d(n) < d min， then d(n) = d min； When d min < d(n) ) < d max , then d(n) = d(n). Since the upper and lower tubes are in a complementary wave - emitting mode, where d max corresponds to a maximum duty cycle of 0.5, and d min corresponds to a minimum duty cycle of 0. Taking Figure 3 as an example, when IL1 > IL2, the duty cycle of the first primary side is D1(n) = D1(n) - d(n), and the duty cycle of the second primary side is D2(n) = D2(n) + d(n). The synchronous tube of the first secondary side turns on ΔS time in advance at the first zero - crossing of the output current and turns off ΔS time after the second zero - crossing. The synchronous tube of the second secondary side turns on and off at the first and second zero - crossing moments of the output current. When IL1 < IL2, the duty cycle of the first primary side is D1(n) = D1(n) + d(n), and the duty cycle of the second primary side is D2(n) = D2(n) - d(n). The synchronous tube of the first secondary side turns on and off at the first and second zero - crossing moments of the output current ILr3, and the synchronous tube of the second secondary side turns on ΔS time in advance at the first zero - crossing of the output current ILr7 and turns off ΔS time after the second zero - crossing. The ΔS time is limited according to the primary - side switching frequency. The switching frequency range of the primary - side tubes is 70KHZ - 300KHZ. The time ΔS for the tube to turn on in advance is limited to 100ns - 500ns, and the time ΔS for the tube to turn off with delay is limited to 500ns - 1.3us. The relationship diagram between the driving waveforms of Q1 and Q5 tubes and the secondary - side current ILr3 is as Figure 8 shown. The driving of Q5 tube follows that of Q1 tube. The driving of Q5 tube is within the envelope of the driving of Q1 tube, that is, the rising edge of the driving of Q5 tube lags behind that of Q1 tube, and the falling edge of the driving of Q5 tube is ahead of that of Q1 tube.

[0077] As Figure 4 shown, a bidirectional CLLLC circuit with input series and output parallel is presented. Among them, L1 and L2 are two bidirectional CLLLC branches respectively. In the first branch L1, the input capacitor is C7 and the input voltage is Vin1; in the second branch L2, the input capacitor is C8 and the input voltage is Vin2. The input capacitors C7 and C8 are in series, and the total input voltage Vin = Vin1 + Vin2. The current sharing control method of the two - way CLLLC circuit is as Figure 2As shown, the current error factor ε is obtained by real-time detection of the current difference of the primary side of each CLLLC branch; at the same time, the zero-crossing point of the secondary output current of each CLLLC branch is detected to generate the time difference ΔS relative to the zero point. According to the primary current error factor ε, the duty cycle D of the primary tube of each CLLLC branch is controlled and adjusted through the negative feedback of the PI loop; at the same time, the switch of the secondary synchronous rectifier tube is controlled through the time difference ΔS, so that the primary and secondary sides jointly control the gain of each CLLLC branch, thereby realizing the current equalization regulation of each CLLLC branch.

[0078] like Figure 5 As shown in the figure, a bidirectional CLLLC circuit with parallel input and series output is shown. L1 and L2 are two bidirectional CLLLC branches. In the first branch L1, the output capacitor is C3 and the output voltage is Vout1; in the second branch L2, the output capacitor is C6 and the output voltage is Vout2. The output capacitor C3 and the output capacitor C6 are connected in series, and the total output voltage Vout = Vout1 + Vout2. The current sharing control method of the two-way bidirectional CLLLC circuit is shown in Figure 2 As shown, the primary current error factor ε is obtained by real-time detection of the current difference of the primary side of each CLLLC branch; at the same time, the zero-crossing point of the secondary output current of each CLLLC branch is detected to generate the time difference ΔS relative to the zero point. According to the primary current error factor ε, the duty cycle D of the primary tube of each CLLLC branch is controlled and adjusted through the negative feedback of the PI loop; at the same time, the switch of the secondary synchronous rectifier tube is controlled through the time difference ΔS, so that the primary and secondary sides jointly control the gain of each CLLLC branch, thereby realizing the current equalization regulation of each CLLLC branch.

[0079] In the present invention Figures 3 to 5 The three examples are two-way bidirectional CLLLC circuits. Figures 3 to 5 In the three examples shown, the two paths are staggered by π / 2, but other staggered values ​​are also possible. Figure 7 As shown in the figure, the two-way phase shift of π / 2 is the optimal solution, which can minimize the output current ripple.

[0080] Example 3

[0081] The current sharing control method of the first embodiment can also be applied to the current sharing control of a multi-way parallel bidirectional CLLLC circuit. In an N-way parallel bidirectional CLLLC circuit, the mutual phase shift value is π / N.

[0082] For a CLLLC circuit with serial input and parallel output, or a CLLLC circuit with parallel input and parallel output, or a bidirectional CLLLC circuit with parallel input and serial output, the current error factor ε i =I i-(I1+I2+I3+I4+.....I N ) / N, (i=1~N, i and N are integers), where I i is the current of the i-th CLLLC branch, I1, I2, I3, I4.....I N The circuits corresponding to the 1st, 2nd, 3rd, 4th, ..... Nth CLLLC branches. The PI operation of the primary current error ε(n) is d(n)=d(n-1)+Kp×ε(n)+K I ×ε(n), where d(n-1) is the current sharing adjustment factor of the CLLLC branch at the n-1th moment, d(n) is the current sharing adjustment factor of the CLLLC branch at the nth moment, Kp is the proportional coefficient of the PI controller, K I is the integral coefficient of the PI controller, and ε(n) is the error factor of the CLLLC branch at the nth moment.

[0083] The time difference ΔS relative to the zero point is generated according to the zero-crossing point of the secondary output current of each CLLLC branch, which is a control method for synchronous rectification acting on the secondary side. In the CLLLC branch with a relatively small output current, the secondary synchronous rectifier tube is turned on by the time difference ΔS in advance when the secondary output current crosses the zero point for the first time, and is turned off by the time difference ΔS at the second zero-crossing point. In the CLLLC branch with a relatively large output current, the secondary synchronous rectifier tube is turned on and off at the first and second zero-crossing points of the secondary output current. By real-time detection of the uneven current difference ε of multiple CLLLC circuits, the duty cycle of multiple channels is controlled, and the switching timing of the secondary synchronous rectifier tube is controlled at the same time, the current balancing factor of multiple CLLLC circuits is realized.

[0084] Example 4

[0085] A computer device includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement a current sharing control method for a bidirectional CLLLC circuit in embodiment 1.

[0086] Example 5

[0087] A computer-readable storage medium stores a computer program, which, when executed by a processor, implements a current sharing control method for a bidirectional CLLLC circuit in embodiment 1.

[0088] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0089] The principles and implementation methods of the present invention are described in this article using specific examples. The description of the above embodiments is only used to help understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A current sharing control method for a bidirectional CLLLC circuit, wherein the bidirectional CLLLC circuit is a multi-way parallel circuit, the multi-way parallel bidirectional CLLLC circuit comprises a plurality of CLLLC branches, the plurality of CLLLC branches are bidirectionally staggered in parallel; the primary sides of the forward and reverse CLLLC branches are staggered in phase control, and the secondary sides of the CLLLC branches are synchronously rectified, wherein: The current sharing control method of the bidirectional CLLLC circuit comprises: Real-time detection of the primary current of each CLLLC branch, and calculation of the primary current error factor of each CLLLC branch according to the primary current value; Real-time detection of the zero-crossing point of the secondary-side output current of each CLLLC branch, and calculation of the time difference between the switching time of the secondary-side synchronous rectifier tube and the zero-crossing time according to the detected zero-crossing point; The duty cycle of the primary switch tube of each CLLLC branch is controlled according to the primary current error factor and the PI operation; at the same time, the switch of the secondary synchronous rectifier tube of each CLLLC branch is controlled according to the time difference to realize the current sharing control of the bidirectional CLLLC circuit.

2. A current sharing control method for a bidirectional CLLLC circuit according to claim 1, characterized in that: The duty cycle of the primary switch tube of each CLLLC branch is controlled according to the primary current error factor and the PI operation, specifically including: Substitute the primary current error factor of each CLLLC branch into the PI calculation formula to obtain the current sharing adjustment factor of each CLLLC branch; the PI calculation formula is: d(n)=d(n-1)+Kp×ε(n)+K I ×ε(n); where d(n) represents the current sharing adjustment factor of the CLLLC branch at the nth moment, d(n-1) represents the current sharing adjustment factor of the CLLLC branch at the n-1th moment; ε(n) represents the primary current error factor of the CLLLC branch at the nth moment; Kp and K I Respectively represent the proportional coefficient and integral coefficient of the PI controller; The duty cycle of the primary switch tube of each CLLLC branch is determined according to the current sharing adjustment factor of each CLLLC branch.

3. A current sharing control method for a bidirectional CLLLC circuit according to claim 2, characterized in that: Before executing the step of "substituting the primary current error factor of each CLLLC branch into the PI calculation formula to obtain the current sharing adjustment factor of each CLLLC branch", the method includes: For each CLLLC branch, determine whether the primary current error factor is greater than the maximum value of the primary current error factor; if so, replace the value of the primary current error factor with the maximum value of the primary current error factor; if not, determine whether the primary current error factor is less than the minimum value of the primary current error factor; if so, replace the value of the primary current error factor with the minimum value of the primary current error factor; if not, do not perform the replacement operation on the primary current error factor.

4. The current sharing control method of a bidirectional CLLLC circuit according to claim 2, characterized in that: The calculation formula of the primary current error factor is: ε i =I i -(I1+I2+I3+I4+.....I N ) / N; Where i=1~N; i and N are integers, N is the number of CLLLC branches; I i is the primary current of the i-th CLLLC branch; ε i is the primary current error factor of the i-th CLLLC branch.

5. The current sharing control method of a bidirectional CLLLC circuit according to claim 2, characterized in that: Before executing the step of "determining the duty cycle of the primary switch tube of each CLLLC branch according to the current sharing adjustment factor of each CLLLC branch", it also includes: For each CLLLC branch, determine whether the current sharing adjustment factor is greater than the maximum value of the current sharing adjustment factor; if so, replace the value of the current sharing adjustment factor with the maximum value of the current sharing adjustment factor; if not, determine whether the current sharing adjustment factor is less than the minimum value of the current sharing adjustment factor; if so, replace the value of the current sharing adjustment factor with the minimum value of the current sharing adjustment factor; if not, do not perform the replacement operation on the current sharing adjustment factor.

6. A current sharing control method for a bidirectional CLLLC circuit according to claim 5, characterized in that: Determining the duty cycle of the primary switch tube of each CLLLC branch according to the current sharing adjustment factor of each CLLLC branch specifically includes: Determine whether the primary current of the i-th CLLLC branch is greater than the primary current of the i+1-th CLLLC branch; If yes, then the duty cycle of the primary switch tube of the i-th CLLLC branch is subtracted from the current sharing adjustment factor to obtain an updated duty cycle value of the primary switch tube of the i-th CLLLC branch; the duty cycle of the primary switch tube of the i+1-th CLLLC branch is added to the current sharing adjustment factor to obtain an updated duty cycle value of the primary switch tube of the i+1-th CLLLC branch; If not, add the current balancing adjustment factor to the duty cycle of the primary switch tube of the i-th CLLLC branch to obtain an updated duty cycle value of the primary switch tube of the i-th CLLLC branch; subtract the current balancing adjustment factor from the duty cycle of the primary switch tube of the i+1-th CLLLC branch to obtain an updated duty cycle value of the primary switch tube of the i+1-th CLLLC branch.

7. A current sharing control method for a bidirectional CLLLC circuit according to claim 6, characterized in that: After executing the step of "calculating the time difference between the switching time of the secondary synchronous rectifier tube and the time of the zero crossing point according to the detected zero crossing point", it also includes: Determine whether the time difference is greater than a maximum time difference; If yes, then replace the value of the time difference with the maximum value of the time difference; If not, determining whether the time difference is less than a minimum time difference; If yes, then replace the value of the time difference with the minimum value of the time difference; If not, no replacement operation is performed on the time difference.

8. A current sharing control method for a bidirectional CLLLC circuit according to claim 7, characterized in that: Controlling the switch of the secondary-side synchronous rectifier tube of each CLLLC branch according to the time difference specifically includes: If the primary current of the i-th CLLLC branch is greater than the primary current of the i+1-th CLLLC branch, the secondary synchronous rectifier of the i-th CLLLC branch is turned on ΔS in advance when the secondary output current crosses zero for the first time, and is turned off with a delay of ΔS when the secondary output current crosses zero for the second time; the secondary synchronous rectifier of the i+1-th CLLLC branch is turned on when the secondary output current crosses zero for the first time, and is turned off when the secondary output current crosses zero for the second time; ΔS represents the time difference; If the primary current of the i-th CLLLC branch is less than the primary current of the i+1-th CLLLC branch, the secondary synchronous rectifier tube of the i-th CLLLC branch is turned on when the secondary output current crosses zero for the first time, and is turned off when the secondary output current crosses zero for the second time; the secondary synchronous rectifier tube of the i+1-th CLLLC branch is turned on ΔS time in advance when the secondary output current crosses zero for the first time, and is turned off with a delay of ΔS time when the secondary output current crosses zero for the second time.

9. A computer device comprising: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement a current sharing control method for a bidirectional CLLLC circuit as described in any one of claims 1 to 8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, a current sharing control method for a bidirectional CLLLC circuit according to any one of claims 1 to 8 is implemented.

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