Data transmission method, product, device and medium

Abstract

The present invention discloses a data transmission method, product, device and medium, and relates to the field of computer technology. In this solution, a microcontroller is set at the accelerator end to receive DMA configuration information sent by the host end, and transmit the DMA configuration information to the processor at the accelerator end, that is, an out-of-band configuration method is adopted, which can receive multiple DMA configuration information at one time, avoiding waiting for the completion of one configuration information transmission before initiating the next transmission, and effectively improving the data transmission efficiency; at the same time, since the accelerator end is controlled by the microcontroller for DMA transmission, the processor is only responsible for data transmission and calculation, thereby reducing the difficulty of processor logic development. In addition, the solution adopts a first communication bus to transmit DMA configuration information, and transmits the target data corresponding to the DMA configuration information through a second communication bus, which can realize the real-time execution of DMA operations and improve the real-time performance of data transmission.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a data transmission method, product, device and medium. Background Art

[0002] In order to meet the growing demand for computing power from technologies such as big data and cloud computing, data centers often use methods such as increasing server computing power and expanding accelerators. Direct Memory Access (DMA) is the fastest data transmission method in the high-speed peripheral component interconnect express (PCIE) interface, which can effectively liberate the central processing unit (CPU) and improve transmission efficiency.

[0003] DMA transmission modes include block DMA and chained DMA. During block DMA transmission, after the CPU sets the source address, destination address and length, the DMA controller can transmit the data and inform the host through an interrupt after the transmission is completed. However, block DMA can only transmit data of one continuous physical memory block at a time, and the transmission efficiency for discrete memory blocks is low. Chained DMA records the transmission information of discrete memory blocks through descriptors. The device side performs DMA data transmission according to the descriptor, and continues to execute the next transmission according to the address information in the descriptor after one transmission is completed until all descriptors are executed. Although chained DMA can solve the transmission problem under multiple data blocks, the number of blocks transmitted each time is limited, and it is necessary to wait for one transmission to be completed before initiating the next transmission, which is inefficient.

[0004] In view of the above problems, how to solve the problem that the current DMA transmission method needs to wait for one transmission to be completed before initiating the next transmission, resulting in low data transmission efficiency, is an urgent problem to be solved by technicians in this field. Summary of the invention

[0005] The purpose of the present invention is to provide a data transmission method, product, device and medium to solve the problem that the current DMA transmission mode needs to wait for one transmission to be completed before initiating the next transmission, resulting in low data transmission efficiency.

[0006] In order to solve the above technical problems, the present invention provides a data transmission method, which is applied to a host side; the method comprises:

[0007] Obtaining each direct memory access configuration information; wherein the direct memory access configuration information includes a source address, a destination address and a transmission length;

[0008] Sending each of the direct memory access configuration information to the microcontroller at the accelerator end through the first communication bus, so that the microcontroller at the accelerator end caches each of the direct memory access configuration information, and sending each of the direct memory access configuration information to the processor at the accelerator end, the processor at the accelerator end calls a direct memory access mover based on each of the direct memory access configuration information and a direct memory access controller, and obtains target data corresponding to each of the direct memory access configuration information from the memory of the accelerator end through the direct memory access mover;

[0009] The target data transmitted by the processor at the accelerator end are received through the second communication bus.

[0010] On the one hand, before obtaining each direct memory access configuration information, it also includes:

[0011] Request a preset amount of cache based on memory;

[0012] Setting a data sending buffer and a data receiving buffer based on all the buffers;

[0013] The cache size, first address and usage status of each cache are recorded respectively.

[0014] On the other hand, the obtaining of each direct memory access configuration information includes:

[0015] Monitor direct memory access configuration information sending request;

[0016] When the direct memory access configuration information sending request is received, each of the direct memory access configuration information corresponding to the direct memory access configuration information sending request is copied to each of the data sending buffers;

[0017] The direct memory access configuration information in each of the data sending buffers is obtained respectively according to the first address of each of the data sending buffers.

[0018] On the other hand, the receiving, through the second communication bus, each of the target data transmitted by the processor of the accelerator end includes:

[0019] Monitoring target data receiving request;

[0020] When the target data receiving request is received, determining the size of each target data according to the target data receiving request;

[0021] Determining a target data receiving buffer among all the data receiving buffers according to the size of each target data, the buffer size and the usage status of each data receiving buffer;

[0022] The first address of each target data receiving buffer is obtained, and each target data is stored in the corresponding target data receiving buffer according to the first address of each target data receiving buffer.

[0023] On the other hand, the microcontroller at the accelerator end caches each of the direct memory access configuration information, including:

[0024] The microcontroller at the accelerator end stores each of the direct memory access configuration information in a corresponding cache queue respectively;

[0025] The microcontroller at the accelerator end sets a status flag of the cache queue storing the direct memory access configuration information to indicate that the cache queue is occupied.

[0026] On the other hand, the microcontroller at the accelerator side sends each of the direct memory access configuration information to the processor at the accelerator side, including:

[0027] The microcontroller at the accelerator end obtains each of the direct memory access configuration information based on each of the cache queues;

[0028] The microcontroller at the accelerator side sends each of the direct memory access configuration information to the processor at the accelerator side through a third communication bus.

[0029] On the other hand, after the microcontroller at the accelerator sends each of the direct memory access configuration information to the processor at the accelerator through the third communication bus, the method further includes:

[0030] The microcontroller at the accelerator end monitors the transmission completion information transmitted by the processor at the accelerator end through the third communication bus; wherein the transmission completion information indicates that the target data transmission corresponding to the direct memory access configuration information is completed;

[0031] When receiving the transmission completion information, the microcontroller at the accelerator end resets the status flag of the cache queue corresponding to the transmission completion information, and clears all data in the cache queue whose status flag is reset.

[0032] On the other hand, after the microcontroller at the accelerator sends each of the direct memory access configuration information to the processor at the accelerator through the third communication bus, the method further includes:

[0033] The microcontroller at the accelerator end monitors the status flags of each cache queue to determine whether the status flags of all cache queues have been reset;

[0034] If the microcontroller at the accelerator side confirms that the status flags of all the cache queues have been reset, the microcontroller at the accelerator side sets a transmission completion address register.

[0035] On the other hand, if the microcontroller at the accelerator side confirms that the status flag of the target cache queue is not reset, the method further includes:

[0036] The microcontroller at the accelerator end determines whether the duration of the setting of the status flag of the target cache queue is greater than a preset time threshold;

[0037] If the microcontroller at the accelerator side confirms that the duration of the setting of the status flag of the target cache queue is greater than a preset time threshold, then outputting an alarm message indicating that the target data transmission corresponding to the target cache queue has failed;

[0038] The direct memory access configuration information in the target cache queue is deleted, and a status flag of the target cache queue is reset.

[0039] On the other hand, it also includes:

[0040] Monitoring the transmission completion address register of the microcontroller at the accelerator end, and determining whether the transmission completion address register of the microcontroller at the accelerator end is set;

[0041] If it is confirmed that the transmission completion address register of the microcontroller at the accelerator end is set, it is confirmed that the current transmission of all the target data is completed, and all the cache is recovered.

[0042] On the other hand, it also includes:

[0043] Generate a direct memory access data transmission log according to each of the direct memory access configuration information and the corresponding target data;

[0044] The direct memory access data transmission log is uploaded to a server.

[0045] In order to solve the above technical problems, the present invention also provides another data transmission method, which is applied to the accelerator end; the method comprises:

[0046] Receive each direct memory access configuration information sent by the microcontroller; wherein the direct memory access configuration information includes a source address, a destination address and a transmission length; each direct memory access configuration information is obtained by the host end, sent to the microcontroller through the first communication bus and cached by the microcontroller;

[0047] Based on each of the direct memory access configuration information and the direct memory access controller, calling a direct memory access mover, and obtaining target data corresponding to each of the direct memory access configuration information from a memory through the direct memory access mover;

[0048] Each of the target data is sent to the host end via the second communication bus.

[0049] In order to solve the above technical problem, the present invention also provides a computer program product, including a computer program or instructions, which implement the steps of the above data transmission method when executed by a processor.

[0050] In order to solve the above technical problems, the present invention further provides a data transmission device, comprising:

[0051] Memory for storing computer programs;

[0052] A processor is used to implement the steps of the above-mentioned data transmission method when executing the computer program.

[0053] In order to solve the above technical problem, the present invention also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the above data transmission method are implemented.

[0054] The data transmission method provided by the present invention specifically obtains each direct memory access configuration information; wherein the direct memory access configuration information includes a source address, a destination address and a transmission length; sends each direct memory access configuration information to a microcontroller at an accelerator end through a first communication bus, so that the microcontroller at the accelerator end caches each direct memory access configuration information, and sends each direct memory access configuration information to a processor at the accelerator end, the processor at the accelerator end calls a direct memory access mover based on each direct memory access configuration information and a direct memory access controller, and obtains target data corresponding to each direct memory access configuration information from a memory at the accelerator end through the direct memory access mover; and receives each target data transmitted by the processor at the accelerator end through a second communication bus.

[0055] The beneficial effect of the present invention is that the present solution sets a microcontroller at the accelerator end to receive the DMA configuration information sent by the host end, and transmits the DMA configuration information to the processor at the accelerator end, that is, adopts an out-of-band configuration method, can receive multiple DMA configuration information at one time, avoids waiting for the completion of one configuration information transmission before initiating the next transmission, and effectively improves the data transmission efficiency; at the same time, since the accelerator end is controlled by the microcontroller for DMA transmission, the processor is only responsible for data transmission and calculation, thus reducing the difficulty of processor logic development. In addition, the solution adopts the first communication bus to transmit the DMA configuration information, and transmits the target data corresponding to the DMA configuration information through the second communication bus, which can realize the real-time execution of DMA operations and improve the real-time performance of data transmission.

[0056] On the other hand, in the present invention, the host side specifically applies for data sending cache and data receiving cache in advance before DMA data transmission by means of memory pre-application, thereby avoiding frequent memory applications during data transmission and improving the stability of the system. The microcontroller on the accelerator side specifically stores each direct memory access configuration information in the corresponding cache queue, and sets the status flag of the cache queue storing the direct memory access configuration information to indicate that the cache queue is occupied, so as to better store the DMA configuration information. The microcontroller on the accelerator side monitors the transmission completion information transmitted by the processor on the accelerator side through the third communication bus. When the transmission completion information is received, the status flag of the cache queue corresponding to the transmission completion information is reset, and all data in the cache queue whose status flag is reset is cleared, saving the storage space of the microcontroller.

[0057] In addition, the present invention also provides a computer program product, a data transmission device and a medium, which have the same effects as above. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0059] Figure 1 A schematic diagram of a data transmission system provided by an embodiment of the present invention;

[0060] Figure 2 A flow chart of a data transmission method applied to a host end provided by an embodiment of the present invention;

[0061] Figure 3 A schematic diagram of a cache queue provided by an embodiment of the present invention;

[0062] Figure 4 A flow chart of a data transmission method applied to an accelerator end provided by an embodiment of the present invention;

[0063] Figure 5 A schematic diagram of a data transmission device applied to a host end provided by an embodiment of the present invention;

[0064] Figure 6 A schematic diagram of a data transmission device applied to an accelerator end provided by an embodiment of the present invention;

[0065] Figure 7 A schematic diagram of a data transmission device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0066] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0067] The core of the present invention is to provide a data transmission method, product, device and medium to solve the problem that the current DMA transmission mode needs to wait for one transmission to be completed before initiating the next transmission, resulting in low data transmission efficiency.

[0068] In order to enable those skilled in the art to better understand the solution of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0069] With the development of big data and cloud computing technologies, data centers are facing an increasing demand for computing power. In order to improve computing power, in addition to improving the performance of the server itself, data centers also expand artificial intelligence (AI) accelerators such as graphics processing units (GPUs), general-purpose graphics processing units (GPGPUs), and field programmable gate arrays (FPGAs) through the PCIE interface to enhance parallel computing capabilities. In the PCIE interface, DMA is the fastest data transmission method. It allows the CPU to only perform transmission control without participating in actual transmission. The DMA controller is responsible for copying data between the two address spaces, thereby effectively freeing up the CPU and improving transmission efficiency.

[0070] At present, there are two common DMA modes: block DMA and chained DMA. In block DMA transmission, the CPU sets the source address, destination address and length. The source address and destination address correspond to the master chip double data rate (DDR) memory address and the slave chip DDR address respectively. After address conversion by the input / output memory management unit (IOMMU) module, the DMA controller performs data transmission between the host and the device according to the configuration information. After the transmission is completed, the host is notified through interrupt X (INT-X) or message signaled interrupt (MSI). However, block DMA can only transfer one continuous physical memory block at a time, and the transmission efficiency for discrete memory blocks is low. Chained DMA fills the transmission information of discrete memory blocks into the descriptor. The device first reads the descriptor through DMA transmission, and then performs data transmission according to the information in the descriptor. After one transmission is completed, the address of the next descriptor recorded in the descriptor is continued to be read and the next DMA transmission is executed until all descriptors are executed. Then, the host reconfigures the descriptor and initiates the next transmission. Although chained DMA can solve the transmission problem of multiple data blocks, the number of blocks transmitted each time is limited, and the next transmission can only be initiated after one chained DMA transmission is completed. Therefore, in order to solve the above problems, the present invention provides a data transmission method.

[0071] Figure 1 Schematic diagram of a data transmission system provided by an embodiment of the present invention. It should be noted that the method provided by the present invention is applied to Figure 1 The host end shown. The host end and the accelerator end are connected to each other through a first communication bus and a second communication bus. A microcontroller and a processor are provided in the accelerator end. The host end transmits DMA configuration information to the microcontroller through the first communication bus. The microcontroller receives and manages the DMA configuration information and transmits the DMA configuration information to the processor. The processor completes the DMA operation according to the DMA configuration information, obtains the target data from the memory, and transmits the target data to the host end through the second communication bus, thereby completing the DMA data transmission.

[0072] It should be noted that in this embodiment, there is no restriction on the specific type of the accelerator end, for example, it can be a GPU accelerator, a GPGPU accelerator or an FPGA accelerator. There is no restriction on the processor in the accelerator, for example, it can correspond to a GPU, a GPGPU or an FPGA, depending on the specific implementation situation.

[0073] In addition, the specific types of the first communication bus and the second communication bus are not limited in this embodiment. For example, since the host end and the accelerator end are generally connected through the PCIE bus communication, and the PCIE interface has a system management bus (System Management Bus, SMBUS) interface in addition to the PCIE signal, the first communication bus can be set to be the SMBUS bus, and the second communication bus can be set to be the PCIE bus. The following is a detailed description of this solution in conjunction with specific method steps.

[0074] Figure 2 Flow chart of a data transmission method applied to a host side provided by an embodiment of the present invention. Figure 2 As shown, the method includes:

[0075] S10: Obtain each direct memory access configuration information.

[0076] The direct memory access configuration information includes a source address, a destination address and a transmission length.

[0077] In a specific implementation, when DMA data transmission is performed, the host side first obtains various DMA configuration information. It is understandable that the DMA configuration information specifically includes a source address, a destination address, and a transfer length. It should be noted that the specific method for obtaining the DMA configuration information is not limited in this embodiment and is determined according to the specific implementation situation.

[0078] S11: Sending each direct memory access configuration information to the microcontroller on the accelerator side through the first communication bus, so that the microcontroller on the accelerator side caches each direct memory access configuration information, and sends each direct memory access configuration information to the processor on the accelerator side. The processor on the accelerator side calls the direct memory access mover based on each direct memory access configuration information and the direct memory access controller, and obtains the target data corresponding to each direct memory access configuration information from the memory on the accelerator side through the direct memory access mover.

[0079] Furthermore, the host side sends each DMA configuration information to the microcontroller at the accelerator side through the first communication bus. After receiving the DMA configuration information, the microcontroller at the accelerator side caches each DMA configuration information. In this embodiment, there is no restriction on the specific manner in which the microcontroller caches the DMA configuration information. For example, all DMA configuration information can be uniformly stored in one storage space, or each DMA configuration information can be independently stored, depending on the specific implementation situation.

[0080] The microcontroller on the accelerator side further sends each DMA configuration information to the processor on the accelerator side. It is understandable that the processor on the accelerator side includes a DMA controller and a DMA mover. As a hardware module, the DMA controller is responsible for managing and controlling DMA transmission. It has a transmission control function and can start and stop DMA transmission according to configuration parameters such as source address, destination address and transmission length. At the same time, the DMA controller is also responsible for address management, ensuring correct access to memory by maintaining source address and destination address counters. Interrupt management is also one of its important functions, which can generate an interrupt when the transmission is completed or an error occurs, and notify the CPU to process it. In addition, the DMA controller can directly exchange data with the memory and peripherals through the system bus without the participation of the CPU to achieve data transmission.

[0081] As a functional module of the DMA controller, the DMA mover focuses on data movement. It is responsible for copying data from the source address to the destination address, and supports transfers from memory to memory, memory to peripherals, or peripherals to memory. The DMA mover supports multiple data transfer modes, including single transfer, block transfer, and circular buffer transfer. It can also support different data widths, such as 8 bits, 16 bits, or 32 bits. In order to improve transmission efficiency, the DMA mover usually includes a First In, First Out (FIFO) buffer for temporary storage of data. Through these functions, the DMA mover achieves efficient data movement and reduces the burden on the CPU.

[0082] The processor at the accelerator side specifically calls the DMA mover based on each DMA configuration information and the DMA controller, obtains the target data corresponding to each DMA configuration information from the memory at the accelerator side through the DMA mover, and executes the DMA operation.

[0083] S12: receiving target data transmitted by the processor at the accelerator end through the second communication bus.

[0084] Finally, after the DMA mover of the accelerator-side processor obtains the target data corresponding to each DMA configuration information from the memory, each target data is transmitted to the host side through the second communication bus, thereby completing the DMA data transmission. It should be noted that the specific method for the host side to receive the target data is not limited in this embodiment, and it depends on the specific implementation situation.

[0085] In this embodiment, a microcontroller is set at the accelerator end to receive the DMA configuration information sent by the host end and transmit the DMA configuration information to the processor at the accelerator end, that is, an out-of-band configuration method is adopted, which can receive multiple DMA configuration information at one time, avoiding waiting for the completion of one configuration information transmission before initiating the next transmission, and effectively improving the data transmission efficiency; at the same time, since the accelerator end is controlled by the microcontroller for DMA transmission, the processor is only responsible for data transmission and calculation, thus reducing the difficulty of processor logic development. In addition, the scheme adopts the first communication bus to transmit DMA configuration information, and transmits the target data corresponding to the DMA configuration information through the second communication bus, which can realize the real-time execution of DMA operation and improve the real-time performance of data transmission.

[0086] In order to improve the stability of the host end system, based on the above embodiments, in some embodiments, before obtaining each direct memory access configuration information, it also includes:

[0087] S13: applying for a preset amount of cache based on the memory;

[0088] S14: Setting a data sending buffer and a data receiving buffer based on all buffers;

[0089] S15: Record the cache size, first address and usage status of each cache respectively.

[0090] In a specific implementation, before DMA data transmission is performed, a preset number of caches are applied for based on the memory of the host side, and all the caches are divided into two parts, one part is a data sending cache, and the other part is a data receiving cache.

[0091] It should be noted that the data sending buffer is a buffer for storing data to be sent, and the data receiving buffer is a buffer for storing received data. In this embodiment, there is no limit on the preset number of buffers, for example, a 2N-block buffer can be set, and the buffer can be equally divided into two parts, thereby obtaining N-block data sending buffers and N-block data receiving buffers.

[0092] In addition, after setting the data sending buffer and the data receiving buffer, it is also necessary to record the buffer size, first address and usage status of each buffer respectively, so as to facilitate the calling of the buffer during data transmission.

[0093] In this embodiment, the host side applies for a data sending buffer and a data receiving buffer in advance before DMA data transmission by pre-applying for memory, thereby avoiding frequent memory applications during data transmission and improving system stability.

[0094] Based on the above embodiments, in some embodiments, obtaining each direct memory access configuration information includes:

[0095] S101: monitoring direct memory access configuration information sending request;

[0096] S102: when a direct memory access configuration information sending request is received, each direct memory access configuration information corresponding to the direct memory access configuration information sending request is copied to each data sending buffer;

[0097] S103: Obtaining direct memory access configuration information in each data sending buffer according to the first address of each data sending buffer.

[0098] Since the data sending buffer is set in advance before DMA data transmission, when obtaining DMA configuration information, the host side specifically monitors the DMA configuration information sending request. When the host side receives the DMA configuration information sending request, each DMA configuration information corresponding to the DMA configuration information sending request is copied to each data sending buffer. It can be understood that the data sending buffer here should be an unoccupied buffer. When DMA configuration information transmission is required, the DMA configuration information in each data sending buffer is obtained according to the first address of each data sending buffer, so as to send the DMA configuration information to the microcontroller on the accelerator side.

[0099] In summary, the acquisition of DMA configuration information is realized. By storing each DMA configuration information in the data transmission buffer applied in advance, frequent memory application during data transmission is avoided, and the stability of the system is improved.

[0100] Based on the above embodiment, in some embodiments, receiving each target data transmitted by the processor at the accelerator end through the second communication bus includes:

[0101] S121: monitoring target data receiving request;

[0102] S122: when a target data receiving request is received, determining the size of each target data according to the target data receiving request;

[0103] S123: determining a target data receiving buffer among all the data receiving buffers according to the size of each target data, the buffer size and the usage status of each data receiving buffer;

[0104] S124: Acquire the first address of each target data receiving buffer, and store each target data in the corresponding target data receiving buffer according to the first address of each target data receiving buffer.

[0105] Since the data receiving cache is set in advance before the DMA data transmission, when receiving the target data transmitted by the accelerator, the host side specifically monitors the target data receiving request; when the target data receiving request is received, the size of each target data is determined according to the target data receiving request. In order to select the optimal target data receiving cache corresponding to the target data, the target data receiving cache is determined in all the data receiving caches according to the size of each target data, the cache size of each data receiving cache and the usage status. It can be understood that the usage status of the target data receiving cache should be unused, and its cache size should not be less than the size of the corresponding target data. Finally, the first address of each target data receiving cache is obtained, and each target data is stored in the corresponding target data receiving cache according to the first address of each target data receiving cache.

[0106] In summary, the host side receives and stores target data. By storing each target data in the target data receiving buffer applied in advance, frequent memory application during data transmission is avoided, and the stability of the system is improved.

[0107] Based on the above embodiments, in some embodiments, the microcontroller at the accelerator end caches each direct memory access configuration information, including:

[0108] S131: The microcontroller at the accelerator end stores each direct memory access configuration information into a corresponding cache queue;

[0109] S132: The microcontroller at the accelerator side sets a status flag of a cache queue storing direct memory access configuration information to indicate that the cache queue is occupied.

[0110] In order to better cache the DMA configuration information, in a specific implementation, the microcontroller at the accelerator side specifically stores each DMA configuration information in a corresponding cache queue. Figure 3 A schematic diagram of a cache queue provided by an embodiment of the present invention. Figure 3 As shown, the microcontroller includes multiple cache queues, and each cache queue stores a corresponding DMA configuration information, that is, the source address, destination address and transfer length. In addition, each cache queue also includes a corresponding status flag, which is used to indicate whether the corresponding cache queue is occupied; specifically, when the status flag is set, it is confirmed that the corresponding cache queue is occupied, and when the status flag is reset, it is confirmed that the corresponding cache queue is in an idle state. Therefore, after the microcontroller on the accelerator side stores each DMA configuration information in the corresponding cache queue, it is necessary to further set the status flag of the cache queue storing the DMA configuration information to indicate that the cache queue is occupied.

[0111] In this embodiment, the microcontroller at the accelerator side specifically stores each direct memory access configuration information in the corresponding cache queue, and sets the status flag of the cache queue storing the direct memory access configuration information to indicate that the cache queue is occupied, so as to better store the DMA configuration information.

[0112] Based on the above embodiments, in some embodiments, the microcontroller at the accelerator side sends each direct memory access configuration information to the processor at the accelerator side, including:

[0113] S133: The microcontroller at the accelerator end obtains each direct memory access configuration information based on each cache queue;

[0114] S134: The microcontroller at the accelerator side sends each direct memory access configuration information to the processor at the accelerator side through the third communication bus.

[0115] In order to send the DMA configuration information to the processor, in a specific implementation, the microcontroller at the accelerator side specifically obtains each DMA configuration information based on each cache queue, and sends each DMA configuration information to the processor at the accelerator side through the third communication bus.

[0116] It should be noted that the third communication bus is not limited in this embodiment, and may be, for example, a PCIE bus or a Serial Peripheral Interface (SPI) bus, depending on the specific implementation. In this way, the DMA configuration information is sent from the microcontroller to the processor.

[0117] In order to save the storage space of the microcontroller, based on the above embodiments, in some embodiments, after the microcontroller at the accelerator side sends each direct memory access configuration information to the processor at the accelerator side through the third communication bus, the method further includes:

[0118] S135: The microcontroller at the accelerator side monitors the transmission completion information transmitted by the processor at the accelerator side through the third communication bus;

[0119] The transmission completion information indicates that the target data transmission corresponding to the direct memory access configuration information is completed;

[0120] S136: When receiving the transmission completion information, the microcontroller at the accelerator end resets the status flag of the cache queue corresponding to the transmission completion information, and clears all data in the cache queue whose status flag is reset.

[0121] In a specific implementation, after the microcontroller at the accelerator side sends each DMA configuration information to the processor at the accelerator side through the third communication bus, the microcontroller at the accelerator side may further monitor the transmission completion information transmitted by the processor at the accelerator side through the third communication bus.

[0122] It should be noted that the transmission completion information indicates that the target data corresponding to the DMA configuration information has been transmitted from the processor on the accelerator side to the host side, and the DMA data transmission has been completed. Therefore, when the microcontroller on the accelerator side receives the transmission completion information, it is considered that the target data corresponding to the DMA configuration information has been transmitted, and the DMA configuration information in the corresponding cache queue is useless. Therefore, the status flag of the cache queue corresponding to the transmission completion information can be reset, and all data in the cache queue whose status flag is reset can be cleared, thereby releasing the storage space of the cache queue and saving the storage space of the microcontroller.

[0123] In this embodiment, the microcontroller on the accelerator side monitors the transmission completion information transmitted by the processor on the accelerator side through the third communication bus. When the transmission completion information is received, the status flag of the cache queue corresponding to the transmission completion information is reset, and all data in the cache queue with the status flag reset is cleared, thereby saving the storage space of the microcontroller.

[0124] In order to better know the state of DMA data transmission, based on the above embodiments, in some embodiments, after the microcontroller at the accelerator side sends each direct memory access configuration information to the processor at the accelerator side through the third communication bus, it also includes:

[0125] S137: the microcontroller at the accelerator side monitors the status flags of each cache queue to determine whether the status flags of all cache queues have been reset; if the microcontroller at the accelerator side confirms that the status flags of all cache queues have been reset, then proceed to step S138;

[0126] S138: The microcontroller at the accelerator end sets the transfer completion address register.

[0127] In a specific implementation, the microcontroller at the accelerator end will also monitor the status flags of each cache queue to determine whether the status flags of all cache queues have been reset.

[0128] If the microcontroller on the accelerator side confirms that the status flags of all cache queues have been reset, it confirms that the target data corresponding to the DMA configuration information in all cache queues have been sent, and there is currently no DMA data transmission. The microcontroller on the accelerator side sets the transmission completion address register, thereby indicating that the current DMA data transmission has ended.

[0129] If the microcontroller on the accelerator side confirms that the status flag of the target cache queue has not been reset, it is considered that the target data corresponding to the DMA configuration information in the current target cache queue has not been sent. In order to prevent DMA data transmission errors from occupying microcontroller resources for a long time, if the microcontroller on the accelerator side confirms that the status flag of the target cache queue has not been reset, it also includes:

[0130] S139: the microcontroller at the accelerator side determines whether the duration of the setting of the status flag of the target cache queue is greater than the preset time threshold; if the microcontroller at the accelerator side confirms that the duration of the setting of the status flag of the target cache queue is greater than the preset time threshold, then proceeds to step S140;

[0131] S140: Outputting alarm information indicating that target data transmission corresponding to the target cache queue fails;

[0132] S141: Delete the direct memory access configuration information in the target cache queue, and reset the status flag of the target cache queue.

[0133] Specifically, if the accelerator-side microcontroller confirms that the state flag of the target cache queue is not reset, the accelerator-side microcontroller determines whether the duration of the target cache queue state flag being set is greater than a preset time threshold. In this embodiment, there is no restriction on the preset time threshold, which depends on the specific implementation situation.

[0134] If the microcontroller on the accelerator side confirms that the duration of the target cache queue's status flag being set is not greater than the preset time threshold, the monitoring continues. If the microcontroller on the accelerator side confirms that the duration of the target cache queue's status flag being set is greater than the preset time threshold, the target data transmission corresponding to the target cache queue is confirmed to have failed, and an alarm message indicating the failure of the target data transmission corresponding to the target cache queue is output to prompt the user to check the transmission status of the target data corresponding to the target cache queue in time; at the same time, the DMA configuration information in the target cache queue is deleted, and the status flag of the target cache queue is reset, thereby releasing the storage space of the target cache queue for the next DMA data transmission.

[0135] In order to recycle the DMA-related resource information of the host, based on the above embodiments, in some embodiments, the method further includes:

[0136] S16: monitoring the transmission completion address register of the microcontroller at the accelerator end, and determining whether the transmission completion address register of the microcontroller at the accelerator end is set; if it is confirmed that the transmission completion address register of the microcontroller at the accelerator end is set, proceeding to step S17;

[0137] S17: Confirm that all current target data transmission is completed, and recycle all caches.

[0138] In a specific implementation, the host side continuously monitors the transfer completion address register of the microcontroller on the accelerator side to determine whether the transfer completion address register of the microcontroller on the accelerator side is set. It can be understood that the transfer completion address register is set to indicate that all current DMA data transfers have ended.

[0139] If it is confirmed that the transmission completion address register of the microcontroller on the accelerator side is not set, it is confirmed that there is currently target data that has not been transmitted, and the transmission completion address register of the microcontroller on the accelerator side continues to be monitored. If it is confirmed that the transmission completion address register of the microcontroller on the accelerator side is set, it is confirmed that all current target data transmissions are completed, and all caches are recovered. It can be understood that the recovered cache is the data sending cache and data receiving cache pre-applied based on the host-side memory. By recovering all caches, the recovery of host-side DMA-related resource information is realized, saving resources on the host side.

[0140] In order to enable the user to better understand the whole process of DMA data transmission, based on the above embodiments, in some embodiments, the method further includes:

[0141] S18: Generate a direct memory access data transmission log according to each direct memory access configuration information and its corresponding target data;

[0142] S19: Upload the direct memory access data transfer log to the server.

[0143] Specifically, a DMA data transfer log is generated based on each DMA configuration information and its corresponding target data. In order to enable users to understand the entire DMA transfer process, the DMA data transfer log should contain configuration information such as the source address, destination address, and transfer length, defining the starting point, end point, and data volume of the data transfer; the data transfer direction, that is, the direction of data transfer between the memory and the peripherals; DMA transfer status, including start time, end time, and status changes such as transfer completion, error, or interruption; DMA transfer performance indicators, such as transfer rate, time, and efficiency; DMA controller model, version, and related configuration parameters; and records of interrupts, exceptions, or other related events generated during the DMA transfer process. This information helps system administrators or developers analyze and debug the DMA transfer process, optimize system performance, and solve potential problems.

[0144] Finally, uploading the DMA data transmission log to the server can realize the centralized storage and management of the log, which is convenient for system administrators to uniformly monitor the DMA transmission of multiple devices; ensure data security, and facilitate the recovery of historical logs for analysis or troubleshooting; developers or technical support personnel can remotely analyze and debug to improve work efficiency; by comparing logs of different time periods or devices, evaluate the trend of system performance changes and optimize; the server can analyze the log in real time, identify potential faults or anomalies and issue timely warnings; meet compliance requirements and serve as audit basis; promote log sharing and collaboration among team members. This helps improve the reliability, performance and security of the system.

[0145] Figure 4Flow chart of a data transmission method applied to an accelerator end provided by an embodiment of the present invention. Figure 4 As shown, the method includes:

[0146] S20: Receive direct memory access configuration information sent by the microcontroller.

[0147] The direct memory access configuration information includes a source address, a destination address and a transmission length; each direct memory access configuration information is acquired by the host side, sent to the microcontroller through the first communication bus and cached by the microcontroller.

[0148] S21: calling a direct memory access mover based on each direct memory access configuration information and a direct memory access controller, and obtaining target data corresponding to each direct memory access configuration information from the memory through the direct memory access mover.

[0149] S22: Send each target data to the host end via the second communication bus.

[0150] In this embodiment, a microcontroller is set at the accelerator end to receive the DMA configuration information sent by the host end and transmit the DMA configuration information to the processor at the accelerator end, that is, an out-of-band configuration method is adopted, which can receive multiple DMA configuration information at one time, avoiding waiting for the completion of one configuration information transmission before initiating the next transmission, and effectively improving the data transmission efficiency; at the same time, since the accelerator end is controlled by the microcontroller for DMA transmission, the processor is only responsible for data transmission and calculation, thus reducing the difficulty of processor logic development. In addition, the scheme adopts the first communication bus to transmit DMA configuration information, and transmits the target data corresponding to the DMA configuration information through the second communication bus, which can realize the real-time execution of DMA operation and improve the real-time performance of data transmission.

[0151] In the above embodiments, the data transmission method is described in detail. The present invention also provides a corresponding embodiment of the data transmission device.

[0152] Figure 5 A schematic diagram of a data transmission device applied to a host side provided in an embodiment of the present invention. Figure 5 As shown, the device comprises:

[0153] A first acquisition module 10 is used to acquire each direct memory access configuration information; wherein the direct memory access configuration information includes a source address, a destination address and a transmission length;

[0154] The first sending module 11 sends each of the direct memory access configuration information to the microcontroller at the accelerator end through the first communication bus, so that the microcontroller at the accelerator end caches each of the direct memory access configuration information, and sends each of the direct memory access configuration information to the processor at the accelerator end, and the processor at the accelerator end calls a direct memory access mover based on each of the direct memory access configuration information and a direct memory access controller, and obtains target data corresponding to each of the direct memory access configuration information from the memory of the accelerator end through the direct memory access mover;

[0155] The first receiving module 12 is used to receive the target data transmitted by the processor of the accelerator through the second communication bus.

[0156] Since the embodiments of the apparatus part correspond to the embodiments of the method part, please refer to the description of the embodiments of the method part for the embodiments of the apparatus part, which will not be repeated here.

[0157] Figure 6 A schematic diagram of a data transmission device applied to an accelerator end provided by an embodiment of the present invention. Figure 6 As shown, the device comprises:

[0158] The second receiving module 13 is used to receive each direct memory access configuration information sent by the microcontroller; wherein the direct memory access configuration information includes a source address, a destination address and a transmission length; each direct memory access configuration information is obtained by the host end, sent to the microcontroller through the first communication bus and cached by the microcontroller;

[0159] A second acquisition module 14 is used to call a direct memory access mover based on each of the direct memory access configuration information and a direct memory access controller, and acquire target data corresponding to each of the direct memory access configuration information from a memory through the direct memory access mover;

[0160] The second sending module 15 is used to send each of the target data to the host end through the second communication bus.

[0161] Since the embodiments of the apparatus part correspond to the embodiments of the method part, please refer to the description of the embodiments of the method part for the embodiments of the apparatus part, which will not be repeated here.

[0162] In addition, the present invention also provides a computer program product, including a computer program or instructions, which implement the steps of the above data transmission method when executed by a processor.

[0163] Figure 7 A schematic diagram of a data transmission device provided by an embodiment of the present invention. Figure 7 As shown, the data transmission equipment includes:

[0164] A memory 20, for storing computer programs;

[0165] The processor 21 is used to implement the steps of the data transmission method mentioned in the above embodiment when executing a computer program.

[0166] The data transmission device provided in this embodiment may include but is not limited to a smart phone, a tablet computer, a laptop computer or a desktop computer.

[0167] Among them, the processor 21 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 21 can be implemented in at least one hardware form of a digital signal processor (DSP), a field programmable gate array (FPGA), and a programmable logic array (PLA). The processor 21 may also include a main processor and a coprocessor. The main processor is a processor for processing data in an awake state, also known as a central processing unit (CPU); the coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor 21 may be integrated with a graphics processing unit (GPU), and the GPU is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 21 may also include an artificial intelligence (AI) processor, which is used to process computing operations related to machine learning.

[0168] The memory 20 may include one or more computer-readable storage media, which may be non-transitory. The memory 20 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In this embodiment, the memory 20 is at least used to store the following computer program 201, wherein, after the computer program is loaded and executed by the processor 21, it can implement the relevant steps of the data transmission method disclosed in any of the aforementioned embodiments. In addition, the resources stored in the memory 20 may also include an operating system 202 and data 203, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system 202 may include Windows, Unix, Linux, etc. Data 203 may include but is not limited to data involved in the data transmission method.

[0169] In some embodiments, the data transmission device may further include a display screen 22 , an input / output interface 23 , a communication interface 24 , a power supply 25 , and a communication bus 26 .

[0170] Those skilled in the art will understand that Figure 7 The structure shown in the figure does not constitute a limitation on the data transmission device, and may include more or fewer components than shown in the figure.

[0171] Finally, the present invention also provides an embodiment corresponding to a computer-readable storage medium. A computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps described in the above method embodiment (which may be a method corresponding to the host side, or a method corresponding to the accelerator side, or a method corresponding to both the host side and the accelerator side) are implemented.

[0172] It is understandable that if the method in the above embodiment is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium to execute all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc. Various media that can store program codes.

[0173] The above is a detailed introduction to a data transmission method, product, device and medium provided by the present invention. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the embodiments can be referenced to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the present invention.

[0174] It should also be noted that, in this specification, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

Claims

1. A data transmission method, It is characterized in that Applied to the host side; the method comprises: Obtaining each direct memory access configuration information; wherein the direct memory access configuration information includes a source address, a destination address and a transmission length; Sending each of the direct memory access configuration information to the microcontroller at the accelerator end through the first communication bus, so that the microcontroller at the accelerator end caches each of the direct memory access configuration information, and sending each of the direct memory access configuration information to the processor at the accelerator end, the processor at the accelerator end calls a direct memory access mover based on each of the direct memory access configuration information and a direct memory access controller, and obtains target data corresponding to each of the direct memory access configuration information from the memory of the accelerator end through the direct memory access mover; The target data transmitted by the processor at the accelerator end are received through the second communication bus.

2. The data transmission method according to claim 1, It is characterized in that Before obtaining each direct memory access configuration information, the method further includes: Request a preset amount of cache based on memory; Setting a data sending buffer and a data receiving buffer based on all the buffers; The cache size, first address and usage status of each cache are recorded respectively.

3. The data transmission method according to claim 2, It is characterized in that The obtaining of each direct memory access configuration information includes: Monitor direct memory access configuration information sending request; When the direct memory access configuration information sending request is received, each of the direct memory access configuration information corresponding to the direct memory access configuration information sending request is copied to each of the data sending buffers; The direct memory access configuration information in each of the data sending buffers is obtained respectively according to the first address of each of the data sending buffers.

4. The data transmission method according to claim 2, It is characterized in that The receiving, through the second communication bus, each of the target data transmitted by the processor of the accelerator end includes: Monitoring target data receiving request; When the target data receiving request is received, determining the size of each target data according to the target data receiving request; Determining a target data receiving buffer among all the data receiving buffers according to the size of each target data, the buffer size and the usage status of each data receiving buffer; The first address of each target data receiving buffer is obtained, and each target data is stored in the corresponding target data receiving buffer according to the first address of each target data receiving buffer.

5. The data transmission method according to claim 2, It is characterized in that The microcontroller at the accelerator end caches each of the direct memory access configuration information, including: The microcontroller at the accelerator end stores each of the direct memory access configuration information in a corresponding cache queue respectively; The microcontroller at the accelerator end sets a status flag of the cache queue storing the direct memory access configuration information to indicate that the cache queue is occupied.

6. The data transmission method according to claim 5, It is characterized in that The microcontroller at the accelerator side sends each of the direct memory access configuration information to the processor at the accelerator side, including: The microcontroller at the accelerator end obtains each of the direct memory access configuration information based on each of the cache queues; The microcontroller at the accelerator side sends each of the direct memory access configuration information to the processor at the accelerator side through a third communication bus.

7. The data transmission method according to claim 6, It is characterized in that After the microcontroller at the accelerator sends each of the direct memory access configuration information to the processor at the accelerator through the third communication bus, the method further includes: The microcontroller at the accelerator end monitors the transmission completion information transmitted by the processor at the accelerator end through the third communication bus; wherein the transmission completion information indicates that the target data transmission corresponding to the direct memory access configuration information is completed; When receiving the transmission completion information, the microcontroller at the accelerator end resets the status flag of the cache queue corresponding to the transmission completion information, and clears all data in the cache queue whose status flag is reset.

8. The data transmission method according to claim 6, It is characterized in that After the microcontroller at the accelerator sends each of the direct memory access configuration information to the processor at the accelerator through the third communication bus, the method further includes: The microcontroller at the accelerator end monitors the status flags of each cache queue to determine whether the status flags of all cache queues have been reset; If the microcontroller at the accelerator side confirms that the status flags of all the cache queues have been reset, the microcontroller at the accelerator side sets a transmission completion address register.

9. The data transmission method according to claim 8, It is characterized in that If the microcontroller at the accelerator end confirms that the status flag of the target cache queue is not reset, the method further includes: The microcontroller at the accelerator end determines whether the duration of the setting of the status flag of the target cache queue is greater than a preset time threshold; If the microcontroller at the accelerator side confirms that the duration of the setting of the status flag of the target cache queue is greater than a preset time threshold, then outputting an alarm message indicating that the target data transmission corresponding to the target cache queue has failed; The direct memory access configuration information in the target cache queue is deleted, and a status flag of the target cache queue is reset.

10. The data transmission method according to claim 8, It is characterized in that Also includes: Monitoring the transmission completion address register of the microcontroller at the accelerator end, and determining whether the transmission completion address register of the microcontroller at the accelerator end is set; If it is confirmed that the transmission completion address register of the microcontroller at the accelerator end is set, it is confirmed that the current transmission of all the target data is completed, and all the cache is recovered.

11. The data transmission method according to any one of claims 1 to 10, It is characterized in that Also includes: Generate a direct memory access data transmission log according to each of the direct memory access configuration information and the corresponding target data; The direct memory access data transmission log is uploaded to a server.

12. A data transmission method, It is characterized in that Applied to the accelerator end; the method comprises: Receive each direct memory access configuration information sent by the microcontroller; wherein the direct memory access configuration information includes a source address, a destination address and a transmission length; each direct memory access configuration information is obtained by the host end, sent to the microcontroller through the first communication bus and cached by the microcontroller; Based on each of the direct memory access configuration information and the direct memory access controller, calling a direct memory access mover, and obtaining target data corresponding to each of the direct memory access configuration information from a memory through the direct memory access mover; Each of the target data is sent to the host end via the second communication bus.

13. A computer program product comprising a computer program or instructions, It is characterized in that When the computer program or instruction is executed by a processor, the steps of the data transmission method according to any one of claims 1 to 12 are implemented.

14. A data transmission device, It is characterized in that include: Memory for storing computer programs; A processor, configured to implement the steps of the data transmission method according to any one of claims 1 to 12 when executing the computer program.

15. A computer-readable storage medium, It is characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the data transmission method according to any one of claims 1 to 12 are implemented.

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