A multi-beam multi-data rate frequency domain pulse compression method based on FPGA dynamic queue

Abstract

The present invention discloses a method for implementing multi-beam, multi-data rate frequency domain pulse compression based on an FPGA dynamic queue. The method comprises: obtaining original beam data in the FPGA, preprocessing and parsing the original beam data to obtain initial beam data, wherein the original beam data is multi-beam, multi-data rate data; and performing a first-level rearrangement on the initial beam data to obtain rearranged first-level beam rearranged data. The present invention solves the technical problem of insufficient FPGA cache resources and high processing delay caused by using the internal BRAM resources of the FPGA to cache multi-beam, multi-data rate data in a multi-beam, multi-data rate scenario, then performing a first-level rearrangement of the data at an appropriate time, and performing pulse compression after the rearrangement is completed.

Description

Technical Field

[0001] The present invention relates to the field of digital beam pulse compression, and in particular to a multi-beam multi-data rate frequency domain pulse compression method based on FPGA dynamic queue. Background Art

[0002] Pulse compression is a crucial technique in radar signal processing, a practical application of matched filtering theory. According to radar theory, transmitting a signal with a large duration and bandwidth effectively improves velocity measurement accuracy and resolution, while improving range resolution requires a smaller duration. Pulse compression effectively resolves this conflict. Pulse compression utilizes matched filtering theory to compress a wide pulse into a narrow pulse, creating a peak at the target range gate, suppressing sidelobes and improving the signal-to-noise ratio. Before pulse compression is performed, the raw beam data output by the digital beamformer must be rearranged. The traditional beam rearrangement implementation method uses the block random access memory (BRAM) resources of the field programmable gate array (FPGA) to cache the original beam data. When the PRI data cache is complete, beam rearrangement begins. This method is simple to implement and efficient, but it requires a large amount of BRAM resources. For example, a PRI containing 4096 snapshots and 48 beams (64-bit data) requires 342 36K BRAMs. Considering the need for multiple cache queues when switching between long and short PRIs, BRAM resources will be very limited. To address this issue, one solution is to write the original beam data into the Double-Data-Rate Three Synchronous Dynamic Random Access Memory (DDR3) cache queue and then read the data from DDR3 to the FPGA's BRAM to complete the beam rearrangement operation. This solution can solve the problem of insufficient FPGA cache resources to a certain extent, but it requires reading all the original beam data of a PRI from DDR3 to BRAM and performing beam rearrangement and pulse compression on the BRAM. Especially in multi-beam and multi-data rate scenarios, the FPGA still faces problems with limited cache resources and high processing latency. Therefore, a multi-beam, multi-data-rate frequency-domain pulse compression method based on FPGA dynamic queues is proposed. This method combines the advantages of efficient FPGA reordering with the abundant DDR3 cache resources. The first-level beam reordering is completed through the FPGA and the results are written to the DDR3 in a pipelined manner. The second-level reordering is performed when the data is read from the DDR3. Therefore, the beam reordering is achieved while the FPGA cache resource utilization is greatly reduced. In addition, all snapshots of a beam are read from the DDR3 each time, which can reduce the latency of the entire processing process. Summary of the Invention

[0003] An embodiment of the present invention provides a multi-beam, multi-data-rate frequency-domain pulse compression method based on an FPGA dynamic queue. This method at least addresses the technical issues of insufficient FPGA cache resources and high processing delays caused by using the FPGA's internal BRAM resources to cache multi-beam, multi-data-rate data in multi-beam, multi-data-rate scenarios, then performing a first-level data rearrangement at an appropriate time, and then performing pulse compression after the rearrangement is completed.

[0004] According to one aspect of an embodiment of the present invention, a multi-beam, multi-data-rate frequency-domain pulse compression method based on an FPGA dynamic queue is provided. The method may include: acquiring raw beam data from the FPGA, preprocessing and parsing the raw beam data to obtain initial beam data, wherein the raw beam data is multi-beam, multi-data-rate data; performing a first-level rearrangement on the initial beam data to obtain rearranged first-level beam rearranged data; sequentially writing the first-level beam rearranged data into a fixed memory; performing a second-level rearrangement on the first-level beam rearranged data written into the fixed memory to obtain second-level beam rearranged data; and determining frequency-domain pulse compression data for the raw beam data based on the second-level beam rearranged data and a response function corresponding to the second-level beam rearranged data.

[0005] Optionally, the original beam data is preprocessed and parsed to obtain initial beam data, including: caching the original beam data to obtain cached preprocessed original beam data; parsing the cached preprocessed original beam data to obtain initial beam data.

[0006] Optionally, the initial beam data is subjected to a first-level rearrangement to obtain rearranged first-level beam rearrangement data, including: writing the initial beam data into multiple target buffers for caching to obtain cached initial beam data; and selecting the initial beam data through a selector to obtain first-level beam rearrangement data.

[0007] Optionally, the first-level beam rearrangement data written into the fixed memory is subjected to second-level rearrangement to obtain second-level beam rearrangement data, including: when a beam in the first-level beam rearrangement data is subjected to burst retransmission, determining whether the number of beams subjected to burst retransmission reaches a preset number of retransmissions; if so, determining that the rearrangement of a beam in the first-level beam rearrangement data is completed; if not, increasing the address of a beam in the first-level beam rearrangement data by a fixed number to complete the rearrangement of a beam in the first-level beam rearrangement data; when the rearrangement of a beam in the first-level beam rearrangement data is completed, determining the read start address of the next beam to read the next beam, and then performing second-level rearrangement of the next beam according to the rearrangement method of a beam in the first-level beam rearrangement data; and so on, completing the second-level rearrangement of all beams in the first-level beam rearrangement data to obtain second-level beam rearrangement data.

[0008] Optionally, based on the secondary beam rearrangement data and the response function corresponding to the secondary beam rearrangement data, the frequency domain pulse pressure data of the original beam data is determined, including: performing Fourier transform on the secondary beam rearrangement data and the response function corresponding to the secondary beam rearrangement data to obtain the frequency domain data of the secondary beam rearrangement data and the frequency domain data of the response function; based on the frequency domain data of the secondary beam rearrangement data and the frequency domain data of the response function, the frequency domain pulse pressure data of the original beam data is determined.

[0009] Optionally, before determining the frequency domain pulse pressure data of the original beam data based on the frequency domain data of the secondary beam rearrangement data and the frequency domain data of the response function, the method further includes: aligning the frequency domain data of the secondary beam rearrangement data and the frequency domain data of the response function.

[0010] Optionally, based on the frequency domain data of the secondary beam rearrangement data and the frequency domain data of the response function, the frequency domain pulse pressure data of the original beam data is determined, including: performing a dot product calculation on the frequency domain data of the aligned secondary beam rearrangement data and the frequency domain data of the response function to obtain the frequency domain pulse pressure data of the original beam data.

[0011] Beneficial effects of the present invention:

[0012] 1. The present invention proposes a multi-beam multi-data rate frequency domain pulse compression method based on FPGA dynamic queue, which caches and parses the original beam data packet, and completes the primary beam rearrangement according to the parameters such as the number of beams and the number of distance points analyzed from the original beam data packet; writes the primary rearrangement result into the DDR3 memory, and dynamically allocates the storage space size according to the parsed parameters after parsing the original beam data packet; when the data of a PRI is completely written into the DDR3, a DDR3 read request is generated, and according to the recorded parameter information and the allocated address space, the AXI bus is controlled to read the DDR3 data at the corresponding interval read address to complete the final beam rearrangement; and the beam data is Fourier transformed using the frequency domain pulse compression principle. , and then multiplied by the frequency domain pulse compression coefficient, and finally the inverse Fourier transform is used to obtain the pulse compression output. This solves the problem of using the internal BRAM resources of the FPGA to cache the multi-beam and multi-data rate data in the multi-beam and multi-data rate scenario, and then performing the first-level data rearrangement at the appropriate time. After the rearrangement is completed, pulse compression is performed. This method leads to insufficient FPGA cache resources and high processing delay. In the multi-beam and multi-data rate scenario, the FPGA dynamically adjusts the cache queue size according to the current PRI beam data volume to adapt to the long-short PRI switching and multi-data rate switching scenarios. The two-stage beam rearrangement design is adopted to reduce the FPGA cache resource occupancy and shorten the processing delay. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of this application. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0014] Figure 1 This is a flow chart of a multi-beam multi-data rate frequency domain pulse compression method based on FPGA dynamic queue according to an embodiment of the present invention;

[0015] Figure 2 is a schematic diagram of an arrangement of original beam data according to an embodiment of the present invention;

[0016] Figure 3 is a schematic diagram of a first-level beam rearrangement operation according to an embodiment of the present invention;

[0017] Figure 4 is a schematic diagram of a two-stage beam rearrangement operation according to an embodiment of the present invention;

[0018] Figure 5 2 is a schematic diagram of a structural framework for determining frequency-domain pulse pressure data according to an embodiment of the present invention. DETAILED DESCRIPTION

[0019] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0020] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way are interchangeable where appropriate so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0021] Example 1

[0022] According to an embodiment of the present invention, a multi-beam, multi-data-rate, frequency-domain pulse compression method based on an FPGA dynamic queue is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system including at least one set of computer-executable instructions. Moreover, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown.

[0023] Figure 1 FIG. 1 is a flow chart of a multi-beam multi-data rate frequency domain pulse compression method based on an FPGA dynamic queue according to an embodiment of the present invention. Figure 1 As shown, the method may include the following steps:

[0024] Step S101 : acquiring original beam data in the FPGA, preprocessing and parsing the original beam data to obtain initial beam data, wherein the original beam data is multi-beam, multi-data rate data.

[0025] In the technical solution provided in step S101 of the present invention, the original beam data in the FPGA is obtained, wherein the original beam data can have a maximum of 48 beams, a maximum data rate of 15.36 Gbps, and a beam data bit width of 64b. The original beam data is preprocessed and parsed to obtain initial beam data. When there are 48 initial beam data, each initial beam data has M distance units.

[0026] Step S102 , performing a first-level rearrangement on the initial beam data to obtain rearranged first-level beam rearranged data.

[0027] In the technical solution provided in the above step S102 of the present invention, different beams of each distance unit are rearranged in one level to obtain different distance data of each beam.

[0028] Step S103: write the first-level beam rearrangement data into a fixed memory in sequence.

[0029] In the technical solution provided in step S103 of the present invention, the first-level beam rearrangement data is sequentially written into the DDR3.

[0030] Step S104 , performing secondary rearrangement on the primary beam rearrangement data written into the fixed memory to obtain secondary beam rearrangement data.

[0031] In the technical solution provided in the above step S104 of the present invention, the different distance data of each beam are subjected to secondary arrangement to obtain the different distance data of each beam, so that the arrangement of data of all different queues is completed.

[0032] Step S105 : determining frequency domain pulse compression data of the original beam data based on the secondary beam rearrangement data and a response function corresponding to the secondary beam rearrangement data.

[0033] In the technical solution provided in the above step S105 of the present invention, calculation is performed based on the secondary beam rearrangement data and the response function corresponding to the secondary beam rearrangement data to obtain the frequency domain pulse pressure data of the original beam data.

[0034] The above method of this embodiment is further introduced below.

[0035] As an optional implementation method, step S101 preprocesses and parses the original beam data to obtain initial beam data, including: caching the original beam data to obtain cached preprocessed original beam data; parsing the cached preprocessed original beam data to obtain initial beam data.

[0036] In this embodiment, the cache pre-processing process is as follows: in order to adapt to different lengths and pulse widths of PRI switching, the first-level beam rearrangement data cannot be completely written to DDR3, and the original input data needs to be pre-processed by PING-PONG cache. For example: when the PING data is performing the first-level rearrangement or the first-level rearrangement has been completed but the data is being written to DDR3, if the PONG data has arrived, the PONG data will enter the PONG cache area until the PING data first-level rearrangement module sends a completion signal, and then the PONG data will be read and processed; according to an embodiment of the present invention, a schematic diagram of the arrangement of original beam data is provided. Figure 2 is a schematic diagram of an arrangement of original beam data according to an embodiment of the present invention, such as Figure 2 As shown in the figure, the parsing process of the original beam data after cache preprocessing is as follows: read data from the PING-PONG cache and parse it, including parameter parsing verification and beam data segment identification. Figure 2 The first line of the data contains the frame header, parameters, beam data and frame tail data. The parameters include the Coherent Processing Interval (CPI) count, the current pulse repetition interval (PRI) count, the number of beams N, the number of range units M, and the code type selection. The beam data segment identification is used to remove the parameter part to obtain the initial beam data. The initial beam data is as follows: Figure 2 The frame header, parameters and beam data after the frame tail will be removed.

[0037] As an optional implementation method, step S102 performs a first-level rearrangement on the initial beam data to obtain rearranged first-level beam rearrangement data, including: writing the initial beam data into multiple target buffers for caching to obtain cached initial beam data; selecting the initial beam data through a selector to obtain first-level beam rearrangement data.

[0038] In this embodiment, according to an embodiment of the present invention, a schematic diagram of a first-level beam rearrangement operation is provided. Figure 3 is a schematic diagram of a first-level beam rearrangement operation according to an embodiment of the present invention, such as Figure 3 As shown, based on the number of beams N and the valid flag of the original beam data, the beam counter 0 to N-1 is controlled to count in a loop. Then, based on the beam counter count value, the beam data is written to the corresponding N beam buffer first-in, first-out (FIFO) buffers (referred to as the first-level reordering FIFOs) to achieve reordering that adapts to different numbers of beams. The beam buffer FIFOs use 64-bit writes and 256-bit reads. When the number of readable data in the first FIFO exceeds 16, an AXI bus write request is triggered. After receiving the write request, the AXI bus write control module sequentially writes the data in the N first-level reordering FIFOs to the DDR3 in bursts of 512 bytes each. This is done until all FIFOs pull the high signal, completing the first-level reordering. It should be noted that the frequency of AXI bus write requests cannot be too fast. The control counter is reset by the rising edge of the write request, and the write request is enabled again after a period of time to achieve multi-data rate matching to prevent the first-level reordering FIFO from being abnormally read empty and causing incorrect reordering results. When the final first-level reordering FIFO is normally read empty, if the data is not an integer multiple of 512 bytes, it is necessary to fill it with zeros instead of setting the number of bytes for burst transmission of the AXI bus. When the first-level reordering FIFO is normally read empty, it indicates that the first-level reordering is completed, and the PING-PONG cache can be used to read data.

[0039] As an optional implementation method, step S104 performs secondary rearrangement on the first-level beam rearrangement data written into the fixed memory to obtain secondary beam rearrangement data, including: when a beam in the first-level beam rearrangement data is burst retransmitted, judging whether the number of beams subjected to burst retransmission reaches a preset number of retransmissions; if so, determining that the rearrangement of a beam in the first-level beam rearrangement data is completed; if not, increasing the address of a beam in the first-level beam rearrangement data by a fixed number to complete the rearrangement of a beam in the first-level beam rearrangement data; when the rearrangement of a beam in the first-level beam rearrangement data is completed, determining the read start address of the next beam to read the next beam, and then performing secondary rearrangement of the next beam according to the rearrangement method of a beam in the first-level beam rearrangement data; and so on, completing the secondary rearrangement of all beams in the first-level beam rearrangement data to obtain secondary beam rearrangement data.

[0040] In this embodiment, during the first-level rearrangement, information such as the number of PRI beams, the number of Advanced eXtensible Interface (AXI) bus burst transmissions, and the first address of the PRI write burst transmission is recorded. After the first-level rearrangement is completed, a special read operation of the AXI bus, i.e., a second-level rearrangement operation, is performed. According to an embodiment of the present invention, a schematic diagram of the second-level beam rearrangement operation is provided. Figure 4 FIG. 1 is a schematic diagram of a two-stage beam rearrangement operation according to an embodiment of the present invention. Figure 4 As shown, the specific method is as follows: ① According to the recorded PRI write burst transfer start address, start to execute data reading; ② When a burst transfer is completed, determine whether the number of burst transfers required for a beam is reached (2). If not, increase the read address by N*512 (N is the number of beams); if reached, it indicates that a beam rearrangement is completed, and set the read address to: PRI write burst transfer start address + next beam sequence number * 512 to obtain the read start address of the next beam to be rearranged, and then increase N*512 according to the address completed by a read burst transfer to complete the rearrangement of the next beam, and so on to complete the rearrangement of all beams.

[0041] As an optional implementation method, step S105 determines the frequency domain pulse pressure data of the original beam data based on the secondary beam rearrangement data and the response function corresponding to the secondary beam rearrangement data, including: performing Fourier transform on the secondary beam rearrangement data and the response function corresponding to the secondary beam rearrangement data to obtain the frequency domain data of the secondary beam rearrangement data and the frequency domain data of the response function; and determining the frequency domain pulse pressure data of the original beam data based on the frequency domain data of the secondary beam rearrangement data and the frequency domain data of the response function.

[0042] In this embodiment, according to an embodiment of the present invention, a schematic diagram of a structural framework for determining frequency domain pulse pressure data is provided. Figure 5 FIG. 1 is a schematic diagram of a structural framework for determining frequency domain pulse pressure data according to an embodiment of the present invention. Figure 5As shown, if the actual distance point number of the current beam is M, then the number of Fourier transform (Fast Fourier Transform, abbreviated as FFT) points NFFT = nextpow2(M), nextpow2 means taking the power of 2 that is closest to M and greater than M. For example, if M = 400, then NFFT = 512. Among them, the number of Fast Fourier Transform Points (simplified as NFFT) Fourier transform points will fill the data with zeros when the number of points is insufficient and then give LAST to identify the last data. Frequency domain pulse compression output. While performing FFT on the beam data, perform FFT on the matched filter response function with the corresponding number of points, and then align the FFT output results of the two and perform dot product. The dot product output is used as the FFT IP Fourier transform IP core. At this time, you only need to configure the FFT IP core to the inverse FFT mode to obtain the final frequency domain pulse compression result. Figure 5 The pulse compression coefficient in is the matched filter coefficient. In radar, the matched filter coefficient is generally called the pulse compression coefficient.

[0043] As an optional embodiment, before determining the frequency domain pulse pressure data of the original beam data based on the frequency domain data of the secondary beam rearrangement data and the frequency domain data of the response function, the method also includes: aligning the frequency domain data of the secondary beam rearrangement data and the frequency domain data of the response function.

[0044] In this embodiment, the frequency domain data of the secondary beam rearrangement data and the frequency domain data of the response function are aligned.

[0045] As an optional implementation method, the frequency domain pulse pressure data of the original beam data is determined based on the frequency domain data of the secondary beam rearrangement data and the frequency domain data of the response function, including: performing a dot product calculation on the frequency domain data of the aligned secondary beam rearrangement data and the frequency domain data of the response function to obtain the frequency domain pulse pressure data of the original beam data.

[0046] In this embodiment, the frequency domain data of the aligned secondary beam rearrangement data and the frequency domain data of the response function are multiplied to obtain the frequency domain pulse pressure data of the original beam data.

[0047] In an embodiment of the present invention, by acquiring the original beam data in the FPGA, preprocessing and parsing the original beam data to obtain initial beam data, wherein the original beam data is multi-beam, multi-data rate data; performing a first-level rearrangement on the initial beam data to obtain rearranged first-level beam rearranged data; writing the first-level beam rearranged data into a fixed memory in sequence; performing a second-level rearrangement on the first-level beam rearranged data written into the fixed memory to obtain second-level beam rearranged data; and determining the frequency domain pulse pressure data of the original beam data based on the second-level beam rearranged data and the response function corresponding to the second-level beam rearranged data, thereby solving the problem of the original beam data being a multi-beam, multi-data rate data. In multi-beam, multi-data-rate scenarios, the FPGA's internal BRAM resources are used to cache multi-beam, multi-data-rate data, and then the data is rearranged at the appropriate time. Pulse compression is performed after the rearrangement is completed. This method leads to technical problems such as insufficient FPGA cache resources and high processing delay. In multi-beam, multi-data-rate scenarios, the FPGA dynamically adjusts the cache queue size based on the current PRI beam data volume to adapt to long-short PRI switching and multi-data-rate switching scenarios. The two-stage beam rearrangement design reduces the FPGA cache resource occupancy and shortens the processing delay.

[0048] The serial numbers of the above embodiments of the present invention are for description only and do not represent the advantages or disadvantages of the embodiments.

[0049] In the above embodiments of the present invention, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0050] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only exemplary. For example, the division of units can be a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.

[0051] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple units. Some or all of the units may be selected to achieve the purpose of the present embodiment according to actual needs.

[0052] In addition, the functional units in various embodiments of the present invention may be integrated into a first processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0053] The above are only preferred embodiments of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A multi-beam multi-data rate frequency domain pulse compression method based on FPGA dynamic queue, characterized in that: include: Acquire raw beam data in the FPGA, preprocess and analyze the raw beam data to obtain initial beam data, wherein the raw beam data is multi-beam, multi-data rate data; Performing a first-level rearrangement on the initial beam data to obtain rearranged first-level beam rearranged data; Writing the first-level beam rearrangement data into a fixed memory in sequence; Performing secondary rearrangement on the primary beam rearrangement data written into the fixed memory to obtain secondary beam rearrangement data; comprising: When a beam in the first-level beam rearrangement data is subjected to burst retransmission, determining whether the number of beams subjected to burst retransmission reaches a preset number of retransmissions, and if so, determining that the rearrangement of the beam in the first-level beam rearrangement data is completed; If the number of beams is not reached, the address of one beam in the first-level beam rearrangement data is increased by a fixed number to complete the rearrangement of one beam in the first-level beam rearrangement data; When the rearrangement of one beam in the primary beam rearrangement data is completed, a read start address of the next beam is determined to read the next beam, and then secondary rearrangement of the next beam is performed according to the rearrangement method of one beam in the primary beam rearrangement data, and so on, to complete the secondary rearrangement of all beams in the primary beam rearrangement data, and obtain the secondary beam rearrangement data; Based on the secondary beam rearrangement data and a response function corresponding to the secondary beam rearrangement data, frequency domain pulse compression data of the original beam data is determined.

2. The method according to claim 1, characterized in that The preprocessing and parsing of the original beam data to obtain initial beam data includes: Performing cache preprocessing on the original beam data to obtain cache preprocessed original beam data; The cached pre-processed original beam data is parsed to obtain initial beam data.

3. The method according to claim 1, characterized in that The performing a first-level rearrangement on the initial beam data to obtain rearranged first-level beam rearrangement data includes: Writing the initial beam data into a plurality of target buffers for caching to obtain cached initial beam data; The initial beam data is selected by a selector to obtain first-level beam rearrangement data.

4. The method according to claim 1, wherein The determining, based on the secondary beam rearrangement data and a response function corresponding to the secondary beam rearrangement data, frequency domain pulse compression data of the original beam data includes: Performing Fourier transform on the secondary beam rearrangement data and the response function corresponding to the secondary beam rearrangement data to obtain frequency domain data of the secondary beam rearrangement data and frequency domain data of the response function; Frequency domain pulse pressure data of the original beam data is determined based on the frequency domain data of the secondary beam rearrangement data and the frequency domain data of the response function.

5. The method according to claim 4, characterized in that Before determining the frequency domain pulse pressure data of the original beam data based on the frequency domain data of the secondary beam rearrangement data and the frequency domain data of the response function, the method further includes: The frequency domain data of the secondary beam rearrangement data and the frequency domain data of the response function are aligned.

6. The method according to claim 4 or 5, characterized in that The determining of the frequency domain pulse pressure data of the original beam data based on the frequency domain data of the secondary beam rearrangement data and the frequency domain data of the response function comprises: The frequency domain data of the aligned secondary beam rearrangement data and the frequency domain data of the response function are subjected to a dot product calculation to obtain the frequency domain pulse pressure data of the original beam data.

7. A processor, characterized in that: The processor is configured to run a program, wherein the program executes the method according to any one of claims 1 to 6 when running.

8. A computer-readable storage medium, characterized in that The computer-readable storage medium includes a stored program, wherein when the program is executed, the device where the computer-readable storage medium is located is controlled to execute the method according to any one of claims 1 to 6.

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