Health management method for multichannel optical fiber data receiving based on FPGA and DSP

Abstract

The invention relates to the technical field of data processing, in particular to a health management method for multichannel optical fiber data receiving based on an FPGA (Field Programmable Gate Array) and a DSP (Digital Signal Processor). According to the method, the advantages of the FPGA and the DSP are fully combined, decoupling of the number of data channels, the data rate and the receiving mode can be achieved through parameter configuration, the functions of multi-channel optical fiber data receiving calibration, data verification and alignment and detection information reporting are achieved, and the method is particularly suitable for a radar system with multiple antenna array plane output channels and complex data rate combination. The method has the advantages of being high in universality, good in detection performance, wide in adaptive scene and the like, and accurate and reliable health data can be provided for users.

Description

Technical Field

[0001] The embodiments of this application relate to the field of data processing technology, and in particular to a health management method for multi-channel optical fiber data reception based on FPGA and DSP. Background Technology

[0002] Before processing radar signals, it is necessary to receive array data output from the antenna. As radar functions and missions become increasingly complex, the number of channels output by the radar front-end antenna is also increasing, and the data rate is becoming more and more variable. FPGA, with its inherent characteristics, is well-suited for multi-channel data reception.

[0003] In the implementation of radar signal processing algorithms, it is crucial to be able to detect errors in multi-channel data in a timely manner. This is because in high-speed communication, the clock frequency is very high. To meet the wiring requirements of FPGA, clock data recovery technology is usually used to ensure the accuracy and stability of data acquisition. The accuracy and stability of the input data often determine the performance of subsequent radar detection.

[0004] Traditional FPGA-based multi-channel fiber optic data transceiver methods suffer from coupling in data reception when the number or rate of upstream data channels changes. Furthermore, they lack the ability to verify the correctness of any single data stream, and when data anomalies occur, they cannot quickly locate and report the issue, leading to long debugging cycles. Therefore, given the increasing complexity of radar front-end arrays and the increasingly flexible sampling rates, the ability to quickly achieve health management of data reception has a significant impact on radar target detection performance. Summary of the Invention

[0005] In view of this, embodiments of this application propose a health management method for multi-channel fiber optic data reception based on FPGA and DSP. Through parameter configuration, the number of data channels, data rate and reception method are decoupled. Through detection management, the accuracy of multi-channel data is checked and reported. It has the characteristics of high flexibility, strong versatility, complete detection performance and wide applicability.

[0006] To achieve the above objectives, embodiments of this application propose a health management method for multi-channel fiber optic data reception based on FPGA and DSP, applicable to radar array antennas. The method includes: Step 1, calling the GT high-speed transceiver module through the FPGA to verify the reset code, idle code, and start code in the data item content of each fiber optic channel, and generating a channel GT fiber optic hardware circuit link detection status signal for each fiber optic channel; wherein, each transceiver of the GT high-speed transceiver module internally implements data byte alignment and clock correction functions; Step 2, generating a reset signal according to the reset code, re-counting the effective data length in the data item content of each fiber optic channel, and when the first effective data is a frame header and the effective data length is greater than a preset reception threshold. When the value is reached, a channel data valid flag signal is generated, and the total number of channel data valid flag signals is counted; Step 3, the data of each fiber channel is input into the corresponding buffer interval. When the total number of channel data valid flag signals meets the preset quantity requirement, a read valid pulse is generated, and a read data rate matching the input data rate is generated. Finally, based on the channel GT fiber hardware circuit link detection status signal of each fiber channel, the valid data after multi-channel fiber alignment is obtained; Step 4, the channel GT fiber hardware circuit link status signal and channel data valid flag signal of each fiber channel are packaged together, and after adding frame header information, they are sent to the DSP to realize the rapid positioning of whether the multi-channel fiber data reception is valid and to realize the health management of multi-channel fiber data reception.

[0007] To achieve the above objectives, embodiments of this application also propose a health management system for multi-channel fiber optic data reception based on FPGA and DSP, suitable for radar array antennas. The system includes: a channel GT fiber optic hardware circuit link detection status signal generation module, used to call the GT high-speed transceiver module via FPGA to verify the reset code, idle code, and start code in the data item content of each fiber optic channel, and generate a channel GT fiber optic hardware circuit link detection status signal for each fiber optic channel. Each transceiver in the GT high-speed transceiver module internally implements data byte alignment and clock correction functions; and a channel data valid flag signal generation module, used to generate a reset signal based on the reset code, re-count the valid data length in the data item content of each fiber optic channel, and when the first valid data is a frame header and valid data... When the length exceeds a preset reception threshold, a channel data valid flag signal is generated, and the total number of channel data valid flag signals is counted. The valid data alignment module is used to input the data of each fiber channel into the corresponding buffer interval. When the total number of channel data valid flag signals meets the preset quantity requirement, a read valid pulse is generated, and a read data rate matching the input data rate is generated. Finally, based on the channel GT fiber hardware circuit link detection status signal of each fiber channel, the valid data after multi-channel fiber alignment is obtained. The execution module is used to package the channel GT fiber hardware circuit link status signal and the channel data valid flag signal of each fiber channel, add frame header information, and send them to the DSP to realize the rapid positioning of whether the multi-channel fiber data reception is valid and to realize the health management of multi-channel fiber data reception.

[0008] To achieve the above objectives, embodiments of this application also propose an electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform a health management method for multi-channel fiber optic data reception based on FPGA and DSP as described above.

[0009] To achieve the above objectives, embodiments of this application also propose a computer-readable storage medium storing a computer program that, when executed by a processor, enables a health management method for multi-channel fiber optic data reception based on FPGA and DSP as described above.

[0010] This application proposes a health management method for multi-channel fiber optic data reception based on FPGA and DSP. Targeting multi-channel data output from radar array antennas, this method fully leverages the advantages of FPGA and DSP to adapt to different numbers of output channels and different output data rates. Through parameter configuration, it decouples the number of data channels, data rate, and reception method, enabling calibration, data verification and alignment, and detection information reporting for multi-channel fiber optic data reception. It is particularly suitable for radar systems with numerous antenna array output channels and complex data rate combinations. This method features strong versatility, good detection performance, and wide applicability, providing users with accurate and reliable health data. The method has the function of detecting and reporting data for each fiber optic channel, with strong detection capability and high real-time performance. The input data rate and read data rate are loosely coupled, eliminating the need for a large buffer space and saving storage resources. It decouples the number of output channels of the radar array antenna from the number of high-speed receiving channel modules, enhancing the system's versatility and applicability.

[0011] Optionally, when the output channels of the radar array antenna are expanded or the data rate of the array elements changes, the number of GT high-speed transceiver modules called and the data reading rate can be reconfigured according to the parameters, and the validity of multi-channel data can be detected and reported in real time. By repeating steps 1 to 4, health management of multi-channel fiber optic data reception can be achieved.

[0012] Optionally, the maximum number of channels for the output data of the antenna array of a single FPGA is N, the number of array elements in a single fiber channel is M, the data transmission rate of a single array element is T, the threshold value for the number of data transmitted by a single array element is K, the total number of array elements received by a single FPGA is N×M, the input data rate of a single fiber channel is T×M, and the frequency F of the FPGA's operating clock satisfies F>T×M. The FPGA calls the IP core of the GT high-speed transceiver module, instantiates N GT high-speed transceiver data channels, configures the line rate, data bit width and encoding method, introduces K code to perform boundary judgment and byte alignment on the data received by the GT high-speed transceiver module, and introduces a 4-byte clock check sequence to correct the clock when the read and write rates inside the IP core of the GT high-speed transceiver module are inconsistent. When the rxdisperr signal and rxnotintable signal output by the IP core of the GT high-speed transceiver module are both greater than zero, the GT high-speed transceiver module is considered to be calibrated incorrectly; otherwise, the GT high-speed transceiver module is considered to be calibrated correctly. When the FPGA verifies the reset code, idle code, and start code in the data item content of each fiber channel, the lower 8 bits of the issued reset code, idle code, and start code are consistent with the K code. The idle code is also consistent with the clock verification sequence. When charisk is 1 and any one of the reset code, idle code, and start code is incorrect, it is considered that there is a bit error when the GT high-speed transceiver module receives fiber data. Otherwise, it is considered that there is no bit error. When the calibration is correct and there is no bit error, it is considered that the channel GT fiber hardware circuit connection is normal.

[0013] Optionally, during the generation of the channel data valid flag signal, when charisk is 1 and the reset code is correct, the valid data counter is cleared to zero; when charisk is 0, the data valid enable signal is pulled high, the data valid enable signal is equal to the chariskdata signal, and the data valid counter signal is incremented; when both the data valid enable signal and the data valid counter signal are 1, the data valid enable signal is equal to the frame header, and a data frame header valid flag is generated; when the data valid counter signal is greater than the number of valid data received thresholds K, a data length valid flag is generated. The FPGA internally instantiates N GT high-speed transceiver data channels. The actual number of output channels of the radar array antenna is less than or equal to N. The number of actual output channels can be controlled by parameters. The total number of valid channel data flag signals is counted. When the total number of valid channel data flag signals is equal to the actual number of output channels, the valid channel data flag signal of the actual output channel is pulled high.

[0014] Optionally, the data of N fiber channels are buffered in N FIFOs. The valid enable signal of the data of the first fiber channel is the write enable signal of the first FIFO, the valid flag signal of the channel data of the first fiber channel is the write data signal of the first FIFO, the valid reset code signal of the first fiber channel is the reset signal of the first FIFO, and so on. When the channel data valid flag signal of the actual output channel in step 2 goes high, a FIFO read enable signal is generated. N FIFOs share the same read enable signal, so that the data of N fiber optic channels are aligned and output at the same time until the empty signal of each FIFO goes high. The read data rate is (T×M) / F, ensuring the balance of input and output data rates. The buffer range of each FIFO is greater than the number of valid data thresholds K. When the channel GT fiber optic hardware circuit of any fiber optic channel is connected normally, the valid data read from the FIFO corresponding to that channel will be input to the next level module for processing. Otherwise, the valid data read from the FIFO corresponding to that channel will not be input to the next level module.

[0015] Optionally, the detection flag signals generated by each fiber channel are stored in an arranged manner. The arrangement rule is that the first 4 bytes contain the channel GT fiber hardware circuit link status signal, rxdisperr signal, rxnotintable signal, bit error generation signal, channel data valid flag signal, data frame header valid flag signal and data length valid flag signal of the first fiber channel, and so on, and a frame header is added to the front of the entire data item. The CPI count and PRF count are stored in a pre-agreed memory area with the DSP. At the last PRF cycle of each CPI, an interrupt doorbell signal is generated to inform the DSP to perform parameter reception processing. The DSP analyzes the data reception correctness of any fiber optic channel in the FPGA's multi-channel fiber optic network in real time according to the protocol.

[0016] Optionally, when the output channels of the radar array antenna are expanded or the data rate of the array elements changes, the number of effective channels of the FPGA receiving optical fiber is configured according to the number of array output channels. At the same time, the read rate is configured, and the calibration, verification, alignment and detection information reporting of each optical fiber channel are performed to realize the data reception management function of the new array. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies of this application will be briefly introduced below. Obviously, the following drawings are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. The drawings described herein are only used to explain this application and are not intended to limit this application.

[0018] Figure 1 This is a flowchart of a health management method for multi-channel optical fiber data reception based on FPGA and DSP, provided in one embodiment of this application; Figure 2 This is a schematic diagram illustrating the details of a health management method for multi-channel optical fiber data reception based on FPGA and DSP, provided in one embodiment of this application. Figure 3 This is a schematic diagram of the fiber channel data input timing provided in one embodiment of this application; Figure 4 This is a schematic diagram of the read pulse generation process provided in one embodiment of this application; Figure 5 This is a schematic diagram of cached data aligned output provided in one embodiment of this application; Figure 6This is a timing diagram of the generation of an information reporting interrupt signal provided in one embodiment of this application; Figure 7 This is a schematic diagram of digital array channel expansion provided in one embodiment of this application; Figure 8 This is a schematic diagram of the structure of a health management system based on FPGA and DSP for multi-channel optical fiber data reception, provided in another embodiment of this application. Figure 9 This is a schematic diagram of the structure of an electronic device provided in another embodiment of this application. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the various embodiments of this application will be described in detail below with reference to the accompanying drawings. Those skilled in the art will understand that many technical details have been presented in the embodiments of this application to facilitate better understanding. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments. The division of the following embodiments is for ease of description and should not constitute any limitation on the specific implementation of this application. The following embodiments can be combined with and referenced by each other without contradiction.

[0020] One embodiment of this application proposes a health management method for multi-channel fiber optic data reception based on FPGA and DSP, applicable to radar array antennas. The implementation details of the health management method for multi-channel fiber optic data reception based on FPGA and DSP proposed in this embodiment are described below. The following implementation details are provided for ease of understanding only and are not necessary for implementing this solution.

[0021] The specific process of the health management method for multi-channel fiber optic data reception based on FPGA and DSP proposed in this embodiment can be described as follows: Figure 1 As shown, its visual details can be as follows Figure 2 As shown, the method includes: Step 11: The GT high-speed transceiver module is called through the FPGA to verify the reset code, idle code and start code in the data item content of each fiber channel, and to generate the channel GT fiber hardware circuit link detection status signal for each fiber channel.

[0022] In its implementation, the health management method proposed in this embodiment is based on two processing platforms: FPGA and DSP. The FPGA starts first, calling the GT high-speed transceiver module (GT high-speed transceiver) to verify the reset code, idle code, and start code in the data items of each fiber optic channel, and generating a channel GT fiber optic hardware circuit link detection status signal for each fiber optic channel. Each transceiver in the GT high-speed transceiver module internally implements data byte alignment and clock correction functions.

[0023] In one example, we configure the maximum number of channels for receiving data output from the antenna array of a single FPGA to be N, the number of array elements in a single fiber optic channel to be M (N and M are both integers greater than 1), the data transmission rate of a single array element to be T (T is greater than 0), and the threshold value for the number of data transmitted by a single array element to be K (K is also an integer greater than 1). Based on this, the total number of array elements received by a single FPGA is N×M, the input data rate of a single fiber optic channel is T×M, and the frequency F of the FPGA's operating clock needs to satisfy F>T×M.

[0024] In one example, the FPGA calls the IP core of the GT high-speed transceiver module, instantiates N GT high-speed transceiver data channels, configures the line rate, data bit width, and encoding method, and introduces K-code (K28.5 form) to perform boundary judgment on the data received by the GT high-speed transceiver module for byte alignment. Simultaneously, a 4-byte clock check sequence is introduced to correct the clock when an inconsistency in the read / write rates within the GT high-speed transceiver module's IP core is detected. If both the rxdisperr and rxnotintable signals output by the GT high-speed transceiver module's IP core are greater than zero, the GT high-speed transceiver module is considered to be calibrated incorrectly; if at least one of the rxdisperr and rxnotintable signals is less than or equal to zero, the GT high-speed transceiver module is considered to be calibrated correctly.

[0025] In one example, such as Figure 3 As shown, when the FPGA verifies the reset code, idle code, and start code in the data item content of each fiber channel, the lower 8 bits of the issued reset code, idle code, and start code are consistent with the K code, and the idle code is also consistent with the clock verification sequence. When charisk is 1, and any one of the reset code, idle code, or start code verifications is incorrect, it is considered that there is a bit error in the GT high-speed transceiver module when receiving fiber data; otherwise, it is considered that there is no bit error. When the calibration is correct and there are no bit errors, it is considered that the channel GT fiber hardware circuit connection is normal, and a channel GT fiber hardware circuit connection detection status signal can be generated for that fiber channel.

[0026] Step 12: Generate a reset signal based on the reset code, recount the effective data length in the data item content of each fiber channel, and when the first effective data is a frame header and the effective data length is greater than the preset receiving threshold, generate a channel data valid flag signal and count the total number of channel data valid flag signals.

[0027] In the specific implementation, after generating the channel GT fiber hardware circuit link detection status signal for each fiber channel, it is also necessary to generate a reset signal according to the reset code, recount the effective data length in the data item content of each fiber channel, and when the first effective data is a frame header and the effective data length is greater than the preset reception threshold, a channel data valid flag signal is generated, and the total number of channel data valid flag signals is counted.

[0028] In one example, during the generation of the channel data valid flag signal, when charisk is 1 and the reset code is correct, the valid data counter is cleared to zero. When charisk is 0, the data valid enable signal is pulled high, and the data valid enable signal equals the chariskdata signal, while the data valid counter signal is incremented. When both the data valid enable signal and the data valid counter signal are 1, the data valid enable signal equals the frame header, and a data frame header valid flag is generated; otherwise, it is not generated. When the data valid counter signal is greater than the number of valid received data thresholds K, a data length valid flag is generated; otherwise, it is not generated.

[0029] In other words, the channel data valid flag signal is generated only when the data frame header valid flag and the data length valid flag are both pulled high. The generation method of the data valid flag signal for each channel is the same.

[0030] In one example, the FPGA internally instantiates N high-speed transceiver data channels (GT), while the actual number of channels output by the radar array antenna may be less than or equal to N. The actual number of output channels can be controlled by parameters. The total number of valid channel data flags is counted. When the total number of valid channel data flags equals the actual number of output channels, the valid channel data flag of the actual output channel is pulled high. This process can be described as follows: Figure 4 As shown.

[0031] Step 13: Input the data of each fiber channel into the corresponding buffer area. When the total number of valid data flag signals of the channel meets the preset quantity requirement, generate a valid read pulse and generate a matching read data rate according to the input data rate. Finally, based on the channel GT fiber hardware circuit connection detection status signal of each fiber channel, obtain the valid data after multi-channel fiber alignment.

[0032] In the specific implementation, after generating the channel data valid flag signal, the data of each fiber channel needs to be input into the corresponding buffer interval. When the total number of channel data valid flag signals meets the preset quantity requirement, a read valid pulse is generated, and a read data rate matching the input data rate is generated. Finally, the valid data after multi-channel fiber alignment is obtained based on the channel GT fiber hardware circuit connection detection status signal of each fiber channel.

[0033] In one example, this embodiment buffers the data of N fiber optic channels in N FIFOs. The valid enable signal for the data of the first fiber optic channel is the write enable signal for the first FIFO, the valid flag signal for the channel data of the first fiber optic channel is the write data signal for the first FIFO, the valid reset code signal for the first fiber optic channel is the reset signal for the first FIFO, and so on. The valid enable signal for the data of the Nth fiber optic channel is the write enable signal for the Nth FIFO, the valid flag signal for the channel data of the Nth fiber optic channel is the write data signal for the Nth FIFO, and the valid reset code signal for the Nth fiber optic channel is the reset signal for the Nth FIFO.

[0034] In one example, when the channel data valid flag signal of the actual output channel goes high, a FIFO read enable signal is generated. N FIFOs share the same read enable signal, ensuring that the data from the N fiber optic channels are aligned and output simultaneously. This process can be described as follows: Figure 5 As shown, this continues until the empty signal of each FIFO goes high. The read data rate is (T×M) / F, ensuring a balance between input and output data rates. At this point, the buffer area of ​​each FIFO only needs to be greater than the number of valid data thresholds K, greatly saving storage resources.

[0035] In one example, when the channel GT fiber hardware circuit of any fiber channel is properly connected, the valid data read from the FIFO corresponding to that channel will be input to the next-level module for processing; otherwise, the valid data read from the FIFO corresponding to that channel will not be input to the next-level module.

[0036] Step 14: Pack the channel GT fiber hardware circuit link status signal and channel data validity flag signal of each fiber channel into a unified package, add frame header information, and send it to the DSP to realize the rapid positioning of whether the multi-channel fiber data reception is valid and to realize the health management of multi-channel fiber data reception.

[0037] In practical implementation, after obtaining valid data after multi-channel fiber alignment, the channel GT fiber hardware circuit link status signal and channel data validity flag signal of each fiber channel can be packaged together, and after adding frame header information, sent to the DSP. The DSP processing platform can quickly locate whether the multi-channel fiber data reception is valid and realize the health management of multi-channel fiber data reception.

[0038] In one example, when the output channels of the radar array antenna are expanded or the data rate of the array elements changes, the number of GT high-speed transceiver modules called and the data reading rate can be reconfigured according to the parameters, and the validity of multi-channel data can be detected and reported in real time. By repeating steps 11 to 14, health management of multi-channel fiber optic data reception can be achieved.

[0039] In one example, this embodiment stores the detection flag signals generated by each fiber optic channel in an arranged manner. The arrangement pattern is as follows: the first 4 bytes contain the channel GT fiber optic hardware circuit link status signal, rxdisperr signal, rxnotintable signal, bit error generation signal, channel data validity flag signal, data frame header validity flag signal, and data length validity flag signal for the first fiber optic channel. This continues until the Nth 4-byte contains the same signals. Finally, a frame header is added to the beginning of the entire data item.

[0040] In one example, parameters such as CPI count and PRF count are stored in a pre-agreed memory area with the DSP. At the last PRF cycle of each CPI cycle, an interrupt doorbell signal is generated to notify the DSP to receive and process the parameters. Figure 6 As shown, the DSP can analyze the data reception correctness of any one of the multi-channel optical fibers in the FPGA in real time according to the protocol.

[0041] In one example, when the output channels of the radar array antenna are expanded or the data rate of the array elements changes, the number of effective channels of the FPGA receiving optical fiber is configured according to the number of array output channels. Simultaneously, the read rate is configured, and calibration, verification, alignment, and detection information reporting of each optical fiber channel are performed to realize the data reception management function of the new array. Figure 7As shown. When selecting certain channels from the current number of channels for use, simply set the received data of the unused channels to zero. When adding channels to expand the array, reconfiguring the instantiated number of channels N to the latest number of channels will meet the requirements. If the data rate needs to be adjusted, the processing platform's operating frequency must be greater than the product of the number of array elements and the data rate per array element to achieve a balance between read and write data rates. Finally, by reporting the physical layer calibration information and data validity judgment information of each channel to the DSP processing platform, the health management of the multi-channel fiber optic received data on the FPGA side can be completed.

[0042] This embodiment proposes a health management method for multi-channel fiber optic data reception based on FPGA and DSP. Targeting multi-channel data output from radar array antennas, this method fully leverages the advantages of FPGA and DSP to adapt to different numbers of output channels and different output data rates. Through parameter configuration, it decouples the number of data channels, data rate, and reception method, enabling calibration, data verification and alignment, and detection information reporting for multi-channel fiber optic data reception. It is particularly suitable for radar systems with numerous antenna array output channels and complex data rate combinations, featuring strong versatility, good detection performance, and wide applicability, providing users with accurate and reliable health data. This method has the function of detecting and reporting data for each fiber optic channel, with strong detection capability and high real-time performance. The input data rate and read data rate are loosely coupled, eliminating the need for a large buffer interval, saving storage resources. It decouples the number of output channels of the radar array antenna from the number of high-speed receiving channel modules, enhancing the system's versatility and applicability.

[0043] The steps described above are for clarity only. In implementation, they can be combined into one step, or some steps can be broken down into multiple steps, as long as they involve the same logical relationship, they are all within the scope of protection of this application. Adding insignificant modifications or introducing insignificant designs to the algorithm or process, without changing the core design of the algorithm and process, are also within the scope of protection of this application.

[0044] Another embodiment of this application proposes a health management system for multi-channel fiber optic data reception based on FPGA and DSP, suitable for radar array antennas. The details of the health management system for multi-channel fiber optic data reception based on FPGA and DSP proposed in this embodiment are described in detail below. The following content is only for the convenience of understanding and is not necessary for implementing this example. Figure 8This is a schematic diagram of the structure of a health management system for multi-channel optical fiber data reception based on FPGA and DSP proposed in this embodiment, including: a channel GT optical fiber hardware circuit link detection status signal generation module 21, a channel data valid flag signal generation module 22, a valid data alignment module 23, and an execution module 24.

[0045] The channel GT fiber optic hardware circuit link detection status signal generation module 21 is used to call the GT high-speed transceiver module through the FPGA to verify the reset code, idle code and start code in the data item content of each fiber optic channel, and generate the channel GT fiber optic hardware circuit link detection status signal for each fiber optic channel. Each transceiver of the GT high-speed transceiver module internally implements data byte alignment and clock correction functions.

[0046] The channel data valid flag signal generation module 22 is used to generate a reset signal according to the reset code, recount the valid data length in the data item content of each fiber channel, generate a channel data valid flag signal when the first valid data is a frame header and the valid data length is greater than the preset reception threshold, and count the total number of channel data valid flag signals.

[0047] The effective data alignment module 23 is used to input the data of each fiber channel into the corresponding buffer area. When the total number of channel data valid flag signals meets the preset quantity requirement, a read valid pulse is generated, and a read data rate matching the input data rate is generated. Finally, based on the channel GT fiber hardware circuit connection detection status signal of each fiber channel, the effective data after multi-channel fiber alignment is obtained.

[0048] The execution module 24 is used to package the channel GT fiber hardware circuit link status signal and channel data validity flag signal of each fiber channel into a unified package, add frame header information, and send it to the DSP to realize the rapid positioning of whether the multi-channel fiber data reception is valid and to realize the health management of multi-channel fiber data reception.

[0049] It is not difficult to see that this embodiment is a system embodiment corresponding to the above method embodiments, and this embodiment can be implemented in conjunction with the above method embodiments. The relevant technical details and technical effects mentioned in the above method embodiments are still valid in this embodiment, and will not be repeated here to reduce repetition. Accordingly, the relevant technical details mentioned in this embodiment can also be applied to the above method embodiments.

[0050] It is worth mentioning that all modules and units involved in this embodiment are logical modules. In practical applications, a logical unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. Furthermore, to highlight the innovative aspects of this application, this embodiment does not introduce units that are not closely related to solving the technical problems proposed in this application; however, this does not mean that other units do not exist in this embodiment.

[0051] Another embodiment of this application provides an electronic device, such as Figure 9 As shown, it includes: at least one processor 31; and a memory 32 communicatively connected to the at least one processor 31; wherein the memory 32 stores instructions executable by the at least one processor 31, the instructions being executed by the at least one processor 31 to enable the at least one processor 31 to perform a health management method for multi-channel optical fiber data reception based on FPGA and DSP as described in the above method embodiment.

[0052] The memory and processor are connected via a bus, which includes any number of interconnecting buses and bridges, connecting various circuits of one or more processors and memories. The bus can also connect various other circuits such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and will not be described further herein. The bus interface provides an interface between the bus and the transceiver. The transceiver can be a single element or multiple elements, such as multiple receivers and transmitters, providing a unit for communicating with various other devices over a transmission medium.

[0053] The processor manages the bus and general processing, and also provides various functions, including timing, peripheral interfaces, voltage regulation, power management, and other control functions. Memory is used to store data used by the processor during operation.

[0054] Another embodiment of this application proposes a computer-readable storage medium storing a computer program that, when executed by a processor, enables a health management method for multi-channel optical fiber data reception based on FPGA and DSP as described in the above method embodiments.

[0055] That is, those skilled in the art will understand that all or part of the steps in the above method embodiments can be implemented by a program instructing related hardware. The program is stored in a storage medium and includes several instructions to cause a device (such as a microcontroller, chip, etc.) or processor to execute all or part of the steps of the method described in the method embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory, random access memory, magnetic disks, or optical disks.

[0056] Those skilled in the art will understand that the above embodiments are specific implementations of this application, and in practical applications, various changes can be made in form and detail without departing from the spirit and scope of this application. For those skilled in the art, several improvements and modifications can be made without departing from the principles of this application, and these improvements and modifications are also considered to be within the scope of protection of this application.

Claims

1. A health management method for multi-channel fiber optic data reception based on FPGA and DSP, applicable to radar array antennas, characterized in that, The method includes: Step 1: The GT high-speed transceiver module is called through the FPGA to verify the reset code, idle code and start code in the data item content of each fiber channel, and to generate the channel GT fiber hardware circuit link detection status signal for each fiber channel; wherein, each transceiver of the GT high-speed transceiver module implements data byte alignment and clock correction functions internally. Step 2: Generate a reset signal based on the reset code, recount the effective data length in the data item content of each fiber channel, and when the first effective data is a frame header and the effective data length is greater than the preset receiving threshold, generate a channel data valid flag signal and count the total number of channel data valid flag signals. Step 3: Input the data of each fiber channel into the corresponding buffer area. When the total number of valid data flag signals of the channel meets the preset quantity requirement, generate a valid read pulse and generate a matching read data rate according to the input data rate. Finally, based on the channel GT fiber hardware circuit connection detection status signal of each fiber channel, obtain the valid data after multi-channel fiber alignment. Step 4: Package the channel GT fiber hardware circuit link status signal and channel data validity flag signal of each fiber channel into a unified package, add frame header information, and send it to the DSP to realize the rapid positioning of whether the multi-channel fiber data reception is valid and to realize the health management of multi-channel fiber data reception.

2. The health management method for multi-channel optical fiber data reception based on FPGA and DSP according to claim 1, characterized in that, When the output channels of the radar array antenna are expanded or the data rate of the array elements changes, the number of GT high-speed transceiver modules called and the data reading rate can be reconfigured according to the parameters. The validity of multi-channel data is detected and reported in real time. By repeating steps 1 to 4, health management of multi-channel fiber optic data reception can be achieved.

3. The health management method for multi-channel optical fiber data reception based on FPGA and DSP according to claim 1, characterized in that, The maximum number of channels for receiving antenna array output data of a single FPGA is N, the number of array elements in a single fiber channel is M, the data transmission rate of a single array element is T, the threshold value for the number of data transmitted by a single array element is K, the total number of array elements received by a single FPGA is N×M, the input data rate of a single fiber channel is T×M, and the frequency F of the FPGA's operating clock satisfies F>T×M. The FPGA calls the IP core of the GT high-speed transceiver module, instantiates N GT high-speed transceiver data channels, configures the line rate, data bit width and encoding method, introduces K code to perform boundary judgment and byte alignment on the data received by the GT high-speed transceiver module, and introduces a 4-byte clock check sequence to correct the clock when the read and write rates inside the IP core of the GT high-speed transceiver module are inconsistent. When the rxdisperr signal and rxnotintable signal output by the IP core of the GT high-speed transceiver module are both greater than zero, the GT high-speed transceiver module is considered to be calibrated incorrectly; otherwise, the GT high-speed transceiver module is considered to be calibrated correctly. When the FPGA verifies the reset code, idle code, and start code in the data item content of each fiber channel, the lower 8 bits of the issued reset code, idle code, and start code are consistent with the K code. The idle code is also consistent with the clock verification sequence. When charisk is 1 and any one of the reset code, idle code, and start code is incorrect, it is considered that there is a bit error when the GT high-speed transceiver module receives fiber data. Otherwise, it is considered that there is no bit error. When the calibration is correct and there is no bit error, it is considered that the channel GT fiber hardware circuit connection is normal.

4. The health management method for multi-channel optical fiber data reception based on FPGA and DSP according to claim 3, characterized in that, During the generation of the channel data valid flag signal, when charisk is 1 and the reset code is correct, the valid data counter is cleared to zero. When charisk is 0, the data valid enable signal is pulled high and equals the chariskdata signal. The data valid counter signal is incremented. When both the data valid enable signal and the data valid counter signal are 1, the data valid enable signal equals the frame header and a data frame header valid flag is generated. When the data valid counter signal is greater than the number of valid data received thresholds K, a data length valid flag is generated. The FPGA internally instantiates N GT high-speed transceiver data channels. The actual number of output channels of the radar array antenna is less than or equal to N. The number of actual output channels can be controlled by parameters. The total number of valid channel data flag signals is counted. When the total number of valid channel data flag signals is equal to the actual number of output channels, the valid channel data flag signal of the actual output channel is pulled high.

5. The health management method for multi-channel optical fiber data reception based on FPGA and DSP according to claim 4, characterized in that, The data from N fiber optic channels is buffered in N FIFOs. The valid enable signal for the data of the first fiber optic channel is the write enable signal for the first FIFO, the valid flag signal for the channel data of the first fiber optic channel is the write data signal for the first FIFO, the valid reset code signal for the first fiber optic channel is the reset signal for the first FIFO, and so on. When the channel data valid flag signal of the actual output channel in step 2 goes high, a FIFO read enable signal is generated. N FIFOs share the same read enable signal so that the data of N fiber optic channels are aligned and output at the same time until the empty signal of each FIFO goes high. The read data rate is (T×M) / F, which ensures the balance of input and output data rates. The buffer range of each FIFO is greater than the number of valid data thresholds K. When the GT fiber optic hardware circuit of any fiber channel is properly connected, the valid data read from the FIFO corresponding to that channel will be input to the next-level module for processing; otherwise, the valid data read from the FIFO corresponding to that channel will not be input to the next-level module.

6. The health management method for multi-channel optical fiber data reception based on FPGA and DSP according to claim 3, characterized in that, The detection flag signals generated by each fiber channel are stored in an arranged manner. The arrangement pattern is as follows: the first 4 bytes contain the channel GT fiber hardware circuit link status signal, rxdisperr signal, rxnotintable signal, bit error generation signal, channel data valid flag signal, data frame header valid flag signal, and data length valid flag signal of the first fiber channel, and so on. A frame header is added to the front of the entire data item. The CPI count and PRF count are stored in a pre-agreed memory area with the DSP. At the last PRF cycle of each CPI, an interrupt doorbell signal is generated to inform the DSP to perform parameter reception processing. The DSP analyzes the data reception correctness of any fiber optic channel in the FPGA's multi-channel fiber optic network in real time according to the protocol.

7. The health management method for multi-channel optical fiber data reception based on FPGA and DSP according to claim 6, characterized in that, When the output channels of the radar array antenna are expanded or the data rate of the array elements changes, the number of effective channels of the FPGA receiving optical fiber is configured according to the number of array output channels. At the same time, the read rate is configured, and the calibration, verification, alignment and detection information reporting of each optical fiber channel are performed to realize the data reception management function of the new array.

8. A health management system for multi-channel fiber optic data reception based on FPGA and DSP, suitable for radar array antennas, characterized in that, The system includes: The channel GT fiber optic hardware circuit link detection status signal generation module is used to call the GT high-speed transceiver module through the FPGA to verify the reset code, idle code and start code in the data item content of each fiber optic channel, and generate the channel GT fiber optic hardware circuit link detection status signal for each fiber optic channel. Each transceiver of the GT high-speed transceiver module internally implements data byte alignment and clock correction functions. The channel data valid flag signal generation module is used to generate a reset signal according to the reset code, recount the valid data length in the data item content of each fiber channel, and generate a channel data valid flag signal when the first valid data is a frame header and the valid data length is greater than the preset receiving threshold value, and count the total number of channel data valid flag signals. The effective data alignment module is used to input the data of each fiber channel into the corresponding buffer area. When the total number of channel data valid flag signals meets the preset quantity requirement, a read valid pulse is generated, and a read data rate matching the input data rate is generated. Finally, based on the channel GT fiber hardware circuit connection detection status signal of each fiber channel, the effective data after multi-channel fiber alignment is obtained. The execution module is used to package the channel GT fiber hardware circuit link status signal and channel data validity flag signal of each fiber channel into a unified package, add frame header information, and send it to the DSP to realize the rapid positioning of whether the multi-channel fiber data reception is valid and to realize the health management of multi-channel fiber data reception.

9. An electronic device, characterized in that, include: At least one processor; as well as, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, which, when executed, enable the at least one processor to perform a health management method for multi-channel fiber optic data reception based on FPGA and DSP as described in any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it can implement a health management method for multi-channel optical fiber data reception based on FPGA and DSP as described in any one of claims 1 to 7.

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