Display device

Abstract

The present invention provides a display device comprising a display panel and multiple driver chips. Each driver chip generates a gamma tie-point voltage based on multiple power supply reference voltages, which can be used as a shared voltage by other driver chips. Furthermore, the gamma tie-point voltages generated by at least two driver chips as shared voltages correspond to different grayscales. This allows each driver chip to generate multiple polarity data signals based on the multiple gamma tie-point voltages and the multiple shared voltages it receives, and output them to corresponding data lines. Consequently, the number of gamma tie-point voltages required to be generated by each driver chip is reduced, as is the number of corresponding voltage amplification modules required, which helps reduce the size, power consumption, and cost of the driver chips.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display device. Background Art

[0002] To achieve optimal color quality on a display panel, multiple different tie-point voltages are typically set to correct the gamma value to a target value (e.g., 2.2). The greater the number of tie-point voltages, the easier it is to correct the gamma value. However, as the size of the display panel increases, the gamma voltage transmission path becomes longer, the line impedance increases, and the voltage drop increases. To maintain optimal display quality, it is necessary to increase the number of tie-point voltages or add a voltage amplification circuit to avoid the problem of uneven display panel brightness caused by excessive gamma voltage drop. However, increasing the number of tie-point voltages and adding a voltage amplification circuit will increase the size and power consumption of the driver chip by at least 10%, increasing costs. Summary of the Invention

[0003] An embodiment of the present invention provides a display device that can improve the problem of increased driver chip size, power consumption, and cost due to increased number of tie-point voltages and voltage amplification circuits.

[0004] An embodiment of the present invention provides a display device comprising a display panel and a plurality of driver chips. The display panel comprises a plurality of data lines. The plurality of driver chips are electrically connected to the display panel, and each driver chip is configured to receive a plurality of power supply reference voltages to generate a plurality of gamma binding point voltages, and to share the plurality of gamma binding point voltages as a plurality of shared voltages with at least another driver chip, and to generate a plurality of polarity data signals based on the plurality of gamma binding point voltages and the received plurality of shared voltages and output them to the corresponding data lines. The gamma binding point voltages generated as the shared voltages by at least two of the driver chips have different grayscales mapped thereto.

[0005] The present invention provides a display device comprising a display panel and multiple driver chips. Each driver chip generates a gamma tie-point voltage based on multiple power supply reference voltages, which can be used as a shared voltage by other driver chips. Furthermore, the gamma tie-point voltages generated by at least two driver chips as shared voltages correspond to different grayscales. This allows each driver chip to generate multiple polarity data signals based on the multiple gamma tie-point voltages and the multiple shared voltages it receives, and output them to corresponding data lines. Consequently, the number of gamma tie-point voltages required to be generated by each driver chip is reduced, as is the number of corresponding voltage amplification modules required, which helps reduce the size, power consumption, and cost of the driver chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0007] Figure 1A-1B is a schematic structural diagram of a display device provided by an embodiment of the present invention;

[0008] Figure 2 This is a principle block diagram of a driver chip provided by an embodiment of the present invention;

[0009] Figures 3A to 3D It is a schematic structural diagram of a driver chip provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0010] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention. In the present invention, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; while "inside" and "outside" refer to the outline of the device.

[0011] Figure 1A-1B : is a schematic diagram of the structure of a display device provided by an embodiment of the present invention. Figure 1B The display device shown is only for use with Figure 1A The display devices shown are for comparison and should not be Figure 1B The driver chip shown is understood to be prior art.

[0012] An embodiment of the present invention provides a display device, comprising a display panel DP and a plurality of driver chips DIC. The display device includes a computer, a television, a mobile phone, a virtual reality display device, an augmented reality display device, and the like.

[0013] The display panel DP includes a plurality of data lines DL and a plurality of sub-pixels Spi. The plurality of data lines DL are electrically connected to corresponding sub-pixels Spi. The plurality of sub-pixels Spi are configured to receive polarity data signals transmitted by corresponding data lines DL to implement the display function of the display panel DP.

[0014] A plurality of driver chips DIC are electrically connected to the display panel DP. Each driver chip DIC is configured to receive a plurality of power supply reference voltages VGM to generate a plurality of gamma tie-point voltages iGM, share the plurality of gamma tie-point voltages iGM as a plurality of shared voltages SGM with at least one other driver chip DIC, and generate a plurality of polarity data signals based on the plurality of gamma tie-point voltages iGM and the received plurality of shared voltages SGM, and output them to corresponding data lines DL. The gamma tie-point voltages iGM generated as the shared voltage SGM by at least two driver chips DIC correspond to different grayscales.

[0015] Because the gamma tie-point voltage iGM generated by each driver chip DIC can be used as a shared voltage SGM by other driver chips DIC, and the gamma tie-point voltages iGM generated by at least two driver chips DIC as the shared voltage SGM correspond to different grayscales, the number of gamma tie-point voltages iGM required to be generated by each driver chip DIC is reduced, and the number of voltage amplification modules required is also reduced, which helps reduce the size, power consumption, and cost of the driver chip DIC.

[0016] Figure 2 This is a principle block diagram of a driver chip provided by an embodiment of the present invention. Figures 3A to 3D : is a schematic diagram of the structure of the driver chip provided by an embodiment of the present invention. Figures 3A to 3C Can be used to implement Figure 1A The design shown, Figure 3D Can be used to implement Figure 1B The design shown. It should be noted that Figure 3D The driver chip shown is only used with Figure 3A-3B The driver chip shown is in contrast and should not be Figure 3D The driver chip shown is understood to be prior art.

[0017] Please continue reading Figure 2 and Figure 3A Each driving chip DIC includes a gamma power module 10. The gamma power module 10 is configured to receive a plurality of power supply reference voltages VGM and generate a plurality of gamma reference voltages.

[0018] Optionally, the power reference voltage VGM may be supplied by a power management chip PMIC.

[0019] Optionally, the multiple gamma reference voltages include multiple first gamma reference voltages VA and multiple second gamma reference voltages VB. The power supply reference voltage VGM includes a first power supply reference voltage UH, a second power supply reference voltage UL, a third power supply reference voltage LH, and a fourth power supply reference voltage LL. The first power supply reference voltage UH is greater than the second power supply reference voltage UL, and the third power supply reference voltage LH is greater than the fourth power supply reference voltage LL. The gamma power supply module 10 is configured to generate multiple first gamma reference voltages VA based on the first power supply reference voltage UH and the second power supply reference voltage UL, and to generate multiple second gamma reference voltages VB based on the third power supply reference voltage LH and the fourth power supply reference voltage LL.

[0020] Optionally, the plurality of first gamma reference voltages VA and the plurality of second gamma reference voltages VB may be generated by two gamma power supply units of the gamma power supply module 10. Figure 3A The gamma power module 10 includes a first gamma power unit 101 and a second gamma power unit 102 .

[0021] The first gamma power supply unit 101 is configured to receive a first power reference voltage UH and a second power reference voltage UL and generate a plurality of first gamma reference voltages VA.

[0022] The second gamma power supply unit 102 is configured to receive the third power reference voltage LH and the fourth power reference voltage LL and generate a plurality of second gamma reference voltages VB.

[0023] Optionally, the first gamma power supply unit 101 is configured to generate p1 first gamma reference voltages VA, and the second gamma power supply unit 102 is configured to generate p2 second gamma reference voltages VB. Wherein, p1 is equal to 256, 512, 1024, etc., and p1=p2. Figure 3A VG1 ˜ VG256 in ⁻¹ represent first gamma reference voltages VA, and VG257 ˜ VG512 represent second gamma reference voltages VB.

[0024] Optionally, the gamma power supply module 10 includes an operational amplifier OP and a plurality of resistors connected in series to generate a plurality of gamma reference voltages.

[0025] Please continue to read Figure 3AThe first gamma power supply unit 101 includes a first operational amplifier OP1, a second operational amplifier OP2, and a plurality of first resistors R1. The non-inverting input of the first operational amplifier OP1 is configured to receive a first power supply reference voltage UH, and the inverting input of the first operational amplifier OP1 is electrically connected to the output of the first operational amplifier OP1. The non-inverting input of the second operational amplifier OP2 is configured to receive a second power supply reference voltage UL, and the inverting input of the second operational amplifier OP2 is electrically connected to the output of the second operational amplifier OP2. The plurality of first resistors R1 are connected in series between the output of the first operational amplifier OP1 and the output of the second operational amplifier OP2.

[0026] The second gamma power supply unit 102 includes a third operational amplifier OP3, a fourth operational amplifier OP4, and a plurality of second resistors R2. The non-inverting input terminal of the third operational amplifier OP3 is configured to receive a third power supply reference voltage LH, and the inverting input terminal of the third operational amplifier OP3 is electrically connected to the output terminal of the third operational amplifier OP3. The non-inverting input terminal of the fourth operational amplifier OP4 is configured to receive a fourth power supply reference voltage LL, and the inverting input terminal of the fourth operational amplifier OP4 is electrically connected to the output terminal of the fourth operational amplifier OP4. The plurality of second resistors R2 are connected in series between the output terminal of the third operational amplifier OP3 and the output terminal of the fourth operational amplifier OP4.

[0027] Because the gamma power module 10 in each driver chip DIC needs to generate multiple gamma reference voltages based on multiple power reference voltages VGM. The gamma binding point voltages iGM corresponding to the minimum grayscale (such as grayscale 0) and the maximum grayscale (such as grayscale 255) are mapped. Figure 3A The gamma power supply modules (iGM1, iGM7, iGM8, and iGM14) can all be directly derived from the output of the operational amplifier OP in the gamma power supply module 10, without requiring voltage division through a resistor string. Therefore, each driver chip DIC can directly generate gamma tie-point voltages iGM corresponding to the minimum and maximum grayscales based on the multiple power supply reference voltages VGM it receives, without having to share the gamma tie-point voltages iGM corresponding to the minimum and maximum grayscales as the shared voltage SGM. This allows each driver chip DIC to generate gamma tie-point voltages corresponding to the minimum and maximum grayscales simultaneously with the tie-point voltages to be shared, reducing the number of traces required to transmit the shared voltage SGM.

[0028] Because each driver chip DIC generates gamma tie-point voltages corresponding to the minimum grayscale and maximum grayscale while generating the gamma tie-point voltage iGM to be shared, when the display device includes Y driver chips DIC, and each driver chip DIC is configured to output X gamma tie-point voltages iGM for use as the shared voltage SGM, the Y driver chips DIC output a total of Z gamma tie-point voltages iGM. Here, X>1, Y>1, and Z=4+XY.

[0029] Please continue reading Figure 2 and Figure 3A Each driver chip DIC includes a voltage generation module 20, which is electrically connected to the gamma power supply module 10. The voltage generation module 20 is configured to generate a plurality of gamma binding point voltages iGM according to a plurality of gamma reference voltages, and to generate a plurality of polarity gamma voltages according to the plurality of gamma binding point voltages iGM and a plurality of shared voltages SGM.

[0030] Optionally, the plurality of polarity gamma voltages include a plurality of positive polarity gamma voltages VP and a plurality of negative polarity gamma voltages VN, and the positive polarity gamma voltages VP and the negative polarity gamma voltages VN may be generated by two voltage generating units in the voltage generating module 20. Figure 3A As shown, the voltage generating module 20 includes a first voltage generating unit 201 and a second voltage generating unit 202 .

[0031] The first voltage generating unit 201 is configured to generate at least one first gamma binding point voltage iGMA according to a plurality of first gamma reference voltages VA, share the first gamma binding point voltage iGMA as a first shared voltage SGMA with at least another driving chip DIC, and generate a plurality of positive polarity gamma voltages VP according to the first gamma binding point voltage iGMA and the received plurality of first shared voltages SGMA.

[0032] The second voltage generating unit 202 is configured to generate at least one second gamma binding point voltage iGMB according to a plurality of second gamma reference voltages VB, share the second gamma binding point voltage iGMB as a second shared voltage SGMB with at least another driving chip DIC, and generate a plurality of negative polarity gamma voltages VN according to the second gamma binding point voltage iGMB and the received plurality of second shared voltages SGMB.

[0033] The plurality of gamma binding point voltages iGM include a first gamma binding point voltage iGMA and a second gamma binding point voltage iGMB, and the common voltage SGM includes a first common voltage SGMA and a second common voltage SGMB.

[0034] Since the first voltage generating unit 201 and the second voltage generating unit 202 each generate at least one gamma tie-point voltage iGM and correspondingly receive the gamma tie-point voltage iGM outputted by other driver chips DIC as the shared voltage SGM, the number of gamma tie-point voltages iGM that need to be generated by the first voltage generating unit 201 and the second voltage generating unit 202 in each driver chip DIC is reduced.

[0035] Optionally, the first voltage generating unit 201 is electrically connected to the first gamma power supply unit 101, and the second voltage generating unit 202 is electrically connected to the second gamma power supply unit 102, so that the first voltage generating unit 201 generates a first gamma binding point voltage iGMA and a positive polarity gamma voltage VP according to a plurality of first gamma reference voltages VA output by the first gamma power supply unit 101, and the second voltage generating unit 202 generates a second gamma binding point voltage iGMB and a negative polarity gamma voltage VN according to a plurality of second gamma reference voltages VB output by the second gamma power supply unit 102.

[0036] Optionally, each driver chip DIC is configured to output X gamma tie point voltages iGM used as the common voltage SGM, where X>1. Accordingly, each voltage generating unit outputs V gamma tie point voltages iGM used as the common voltage SGM, where V<X.

[0037] For example, the voltage generation module 20 includes two voltage generation units (i.e., X=2), and each driver chip DIC outputs two gamma-binding voltages iGM used as the common voltage SGM. The first voltage generation unit 201 outputs a first gamma-binding voltage iGMA used as the common voltage SGM, and the second voltage generation unit 202 outputs a second gamma-binding voltage iGMB (i.e., V=1) used as the common voltage SGM.

[0038] Please continue reading Figure 3A At least one of the first voltage generating unit 201 and the second voltage generating unit 202 includes at least one first digital-to-analog conversion circuit DAC1, at least one voltage amplifier circuit GOP, and a polarity voltage generating circuit GR.

[0039] The first digital-to-analog conversion circuit DAC1 is electrically connected to the corresponding gamma power module 10 . The first digital-to-analog conversion circuit DAC1 is configured to generate a binding point voltage according to a plurality of gamma reference voltages.

[0040] The voltage amplifier circuit GOP is electrically connected to the corresponding first digital-to-analog conversion circuit DAC1 . The voltage amplifier circuit GOP is configured to generate a gamma tie-point voltage iGM according to the tie-point voltage.

[0041] The polarity voltage generating circuit GR is electrically connected to the voltage amplifying circuit GOP. The polarity voltage generating circuit GR is configured to generate a plurality of polarity gamma voltages according to a plurality of gamma binding point voltages iGM and a plurality of common voltages SGM.

[0042] Optionally, the voltage amplifier circuit GOP may be a voltage follower to amplify the gamma voltage to obtain the gamma binding point voltage iGM. The polarity voltage generating circuit GR may be a resistor string.

[0043] Optionally, the driver chip DIC outputs X gamma-binding point voltages iGM, which serve as the shared voltage SGM. The voltage generation module 20 of the driver chip DIC includes X first digital-to-analog conversion circuits DAC1 and X voltage amplifier circuits GOP, where X>1. As the number of gamma-binding point voltages iGM output by the driver chip DIC decreases, the number of first digital-to-analog conversion circuits DAC1 and voltage amplifier circuits GOP included in the voltage generation module 20 also decreases, which helps reduce the size, power consumption, and cost of the driver chip DIC.

[0044] Please continue to read Figure 3A Still taking the example of the voltage generation module 20 including two voltage generation units and each driver chip DIC outputting two gamma tie-point voltages iGM serving as the shared voltage SGM, the first voltage generation unit 201 includes a first digital-to-analog conversion circuit DAC1 and a voltage amplifier circuit GOP. The first digital-to-analog conversion circuit DAC1 is used to generate a first tie-point voltage based on a plurality of first gamma reference voltages VA. The voltage amplifier circuit GOP amplifies the first tie-point voltage to obtain a first gamma tie-point voltage iGMA that is reused as the shared voltage SGM. The first gamma tie-point voltage iGMA is then output to the corresponding polarity voltage generation circuit GR and shared with other driver chips DIC. The second voltage generation unit 202 includes a first digital-to-analog conversion circuit DAC1 and a voltage amplifier circuit GOP. The first digital-to-analog conversion circuit DAC1 generates a second tie-point voltage based on a plurality of second gamma reference voltages VB. The voltage amplifier circuit GOP amplifies the second tie-point voltage to obtain a second gamma tie-point voltage iGMB, which is reused as the shared voltage SGM. The second gamma tie-point voltage iGMB is then output to the corresponding polarity voltage generation circuit GR and shared with other driver chips DIC. Therefore, the voltage generation module 20 of the driver chip DIC includes two first digital-to-analog conversion circuits DAC1 and two voltage amplifier circuits GOP.

[0045] Optionally, when the voltage generating module 20 includes two voltage generating units, X may be an even number.

[0046] Optionally, the first grayscale mapped to the first gamma binding point voltage iGMA generated by the same driver chip DIC is equal to the second grayscale mapped to the second gamma binding point voltage iGMB, so that the same driver chip DIC can provide the first gamma binding point voltage iGMA and the second gamma binding point voltage iGMB mapping the same grayscale to other driver chips DIC, while the gamma binding point voltages iGM corresponding to multiple driver chips DIC map different grayscales.

[0047] For example, a display device includes multiple driver chips DIC, each of which outputs two gamma-binding voltages iGM serving as a shared voltage SGM. Among the multiple driver chips DIC, a first grayscale corresponding to a first gamma-binding voltage iGMA output by a first driver chip DIC1 and a second grayscale corresponding to a second gamma-binding voltage iGMB output by the first driver chip DIC1 are equal, and both the first grayscale and the second grayscale correspond to low grayscales. A first grayscale corresponding to a first gamma-binding voltage iGMA output by a second driver chip DIC2 and a second grayscale corresponding to a second gamma-binding voltage iGMB output by the second driver chip DIC2 are equal, and both the first grayscale and the second grayscale corresponding to the second driver chip DIC2 are greater than the first grayscale and the second grayscale corresponding to the first driver chip DIC1.

[0048] Because signal transmission involves signal loss, the impact of signal transmission loss on the shared voltage SGM mapping low grayscales is greater than the impact of the shared voltage SGM mapping high grayscales with the same degree of signal transmission loss. Therefore, a display device can be configured with multiple driver chips DIC that output gamma tie-point voltages iGM corresponding to low grayscales to ensure signal quality for the shared voltage SGM mapping low grayscales.

[0049] Accordingly, please continue to see Figure 1A The plurality of driving chips DIC include a plurality of first driving chips DICA and a plurality of second driving chips DICB.

[0050] The first grayscales mapped by the multiple first driver chips DICA are the same, the second grayscales mapped by the multiple first driver chips DICA are the same, the first grayscales mapped by the multiple second driver chips DICB are different, and the second grayscales mapped by the multiple second driver chips DICB are different.

[0051] The first grayscale and / or the second grayscale mapped to the plurality of second driving chips DICB are greater than the first grayscale and the second grayscale mapped to the plurality of first driving chips DICA.

[0052] By disposing a plurality of first driving chips DICA, the sources of the common voltage SGM corresponding to the low gray scale mapping are increased, so that the signal quality of the common voltage SGM corresponding to the low gray scale mapping is maintained.

[0053] Optionally, to further improve the signal quality of the shared voltage SGM corresponding to low grayscale mapping, multiple second driver chips DICB can be arranged between the two first driver chips DICA to reduce the signal quality difference of the shared voltage SGM corresponding to low grayscale mapping received by the multiple second driver chips DICB.

[0054] Optionally, in order to improve the signal quality of the shared voltage SGM corresponding to the low grayscale mapping, a plurality of voltage amplification circuits GOP may be provided in the branch of the voltage generating unit corresponding to the binding point voltage mapping the low grayscale, so that the binding point voltage is acted upon by the plurality of voltage amplification circuits GOP to obtain the gamma binding point voltage iGM corresponding to the low grayscale mapping. Optionally, the gamma binding point voltage iGM obtained after the plurality of voltage amplification circuits GOP is used as the shared voltage SGM, as shown in FIG. Figure 3B Optionally, after the gamma binding point voltage iGM obtained by a voltage amplifier circuit GOP is shared as a shared voltage SGM to other driver chips, the driver chip receiving the shared voltage SGM is further provided with a voltage amplifier circuit GOP to act on the shared voltage again before outputting it to the corresponding polarity voltage generating circuit GR, as shown in FIG. Figure 3C shown.

[0055] Please continue to read Figure 1A The display device includes a plurality of sharing lines SL electrically connected to a plurality of driver chips DIC. Each sharing line SL is configured to transmit a shared voltage SGM. Multiple second driver chips DICB are electrically connected to the sharing lines SL between two first driver chips DICA. This allows the first driver chips DICA to form a double-sided driving mechanism, thereby providing the required shared voltage SGM to the multiple second driver chips DICB.

[0056] Please continue reading Figure 2 and Figure 3A Each driver chip DIC further includes a signal generating module 30. The signal generating module 30 is electrically connected to the voltage generating module 20. The signal generating module 30 is configured to receive a plurality of polarity gamma voltages and generate a plurality of polarity data signals.

[0057] Optionally, the signal generating module 30 includes a shift register SR, a latch LU, a level conversion circuit LS, a second digital-to-analog conversion circuit DAC2 and an output buffer OB.

[0058] The shift register SR is configured to generate a sampling signal according to a clock control signal CK.

[0059] The latch LU is electrically connected to the shift register SR. The latch LU is configured to generate a plurality of first data voltages according to the sampling signal and the received image signal FD, and latch or release the plurality of first data voltages according to the data latch control signal TP.

[0060] The level shifting circuit LS is electrically connected to the latch LU. The level shifting circuit LS is configured to generate a plurality of second data voltages according to the plurality of first data voltages.

[0061] The second digital-to-analog conversion circuit DAC2 is electrically connected to the level conversion circuit LS and the voltage generation module 20 . The second digital-to-analog conversion circuit DAC2 is configured to generate a plurality of polarity grayscale voltages according to a plurality of second data voltages and the polarity gamma voltages.

[0062] The output buffer OB is electrically connected to the second digital-to-analog conversion circuit DAC2 , and the output buffer OB is configured to generate a plurality of polarity data signals according to a plurality of polarity grayscale voltages.

[0063] The second digital-to-analog conversion circuit DAC2 is configured to generate a plurality of positive polarity grayscale voltages based on the plurality of second data voltages and the positive polarity gamma voltage VP; and to generate a plurality of negative polarity grayscale voltages based on the plurality of second data voltages and the plurality of negative polarity gamma voltages VN. The output buffer OB is configured to generate a plurality of positive polarity data signals based on the plurality of positive polarity grayscale voltages, and to generate a plurality of negative polarity data signals based on the plurality of negative polarity grayscale voltages.

[0064] Optionally, the timing controller Tcon may be used to provide the clock control signal CK, the image signal FD, and the data latch control signal TP to the signal generating module 30 .

[0065] Optionally, the number of driving chips DIC included in the display device may be determined according to the number of output channels of the driving chip DIC and the resolution of the display panel DP.

[0066] Optionally, if the resolution of the display panel DP is R*S and the number of output channels of the driver chip DIC is T, then the number of driver chips DIC is 3R / T, where R>0, S>0, and T>0. For example, if the resolution of the display panel DP is 3840*2160 and the number of output channels of the driver chip DIC is 960, then the number of driver chips DIC is 3840*3 / 960=12.

[0067] It should be noted that each output channel of the driving chip DIC can be used to output a polarity data signal to the corresponding data line DL.

[0068] Please continue reading Figure 1A 、 Figure 2 and Figure 3A, taking a display device including multiple driver chips DIC, each driver chip DIC generating two shared gamma tie point voltages iGM, and each driver chip DIC generating a polarity data signal according to 14 gamma tie point voltages iGM as an example, the working principle of the display device is described.

[0069] While generating the gamma binding point voltage iGM to be shared, each driver chip DIC also generates a first gamma binding point voltage iGMA (recorded as the seventh gamma binding point voltage iGM7) corresponding to the mapping of the minimum grayscale, a first gamma binding point voltage iGMA (recorded as the first gamma binding point voltage iGM1) corresponding to the mapping of the maximum grayscale, a second gamma binding point voltage iGMB (recorded as the eighth gamma binding point voltage iGM8) corresponding to the mapping of the minimum grayscale, and a second gamma binding point voltage iGMB (recorded as the fourteenth gamma binding point voltage iGM) corresponding to the mapping of the maximum grayscale.

[0070] In the first driver chip DIC1, the first gamma power supply unit 101 generates multiple first gamma reference voltages VA based on the first power supply reference voltage UH and the second power supply reference voltage UL, and outputs them to the first voltage generation unit 201. The first digital-to-analog conversion circuit DAC1 in the first voltage generation unit 201 generates a binding point voltage based on the multiple first gamma reference voltages VA. The binding point voltage is amplified by the voltage amplifier circuit GOP in the first voltage generation unit 201 to obtain the sixth gamma binding point voltage iGM6. The sixth gamma binding point voltage iGM6 is output to the polarity voltage generation circuit GR in the first voltage generation unit 201 and is shared with other driver chips DIC. The second gamma power supply unit 102 generates a plurality of second gamma reference voltages VB based on the third power supply reference voltage LH and the fourth power supply reference voltage LL, and outputs the generated second gamma reference voltages VB to the second voltage generating unit 202. The first digital-to-analog conversion circuit DAC1 in the second voltage generating unit 202 generates another binding point voltage based on the plurality of second gamma reference voltages VB. The binding point voltage is amplified by the voltage amplifier circuit GOP in the second voltage generating unit 202 to obtain a ninth gamma binding point voltage iGM9. The ninth gamma binding point voltage iGM9 is output to the polarity voltage generating circuit GR in the second voltage generating unit 202 and is shared with other driver chips DIC.

[0071] In the second driver chip DIC2, the first gamma power supply unit 101 generates multiple first gamma reference voltages VA based on the first power supply reference voltage UH and the second power supply reference voltage UL, and outputs them to the first voltage generation unit 201. The first digital-to-analog conversion circuit DAC1 in the first voltage generation unit 201 generates a binding point voltage based on the multiple first gamma reference voltages VA. The binding point voltage is amplified by the voltage amplifier circuit GOP in the first voltage generation unit 201 to obtain the fifth gamma binding point voltage iGM5. The fifth gamma binding point voltage iGM5 is output to the polarity voltage generation circuit GR in the first voltage generation unit 201 and is shared with other driver chips DIC. The second gamma power supply unit 102 generates a plurality of second gamma reference voltages VB based on the third power supply reference voltage LH and the fourth power supply reference voltage LL, and outputs the generated voltages to the second voltage generating unit 202. The first digital-to-analog conversion circuit DAC1 in the second voltage generating unit 202 generates another binding point voltage based on the plurality of second gamma reference voltages VB. The binding point voltage is amplified by the voltage amplifier circuit GOP in the second voltage generating unit 202 to obtain a tenth gamma binding point voltage iGM10. The tenth gamma binding point voltage iGM10 is output to the polarity voltage generating circuit GR in the second voltage generating unit 202 and is shared with other driver chips DIC.

[0072] Similarly, it can be obtained that the voltage generating module 20 in the third driver chip DIC3 generates the fourth gamma binding point voltage iGM4 and the eleventh gamma binding point voltage iGM11 and shares them with other driver chips DIC; the voltage generating module 20 in the fourth driver chip DIC4 generates the third gamma binding point voltage iGM3 and the twelfth gamma binding point voltage iGM12 and shares them with other driver chips DIC; the voltage generating module 20 in the fifth driver chip DIC5 generates the second gamma binding point voltage iGM2 and the thirteenth gamma binding point voltage iGM13 and shares them with other driver chips DIC.

[0073] In the first driver chip DIC1, the polarity voltage generating circuit GR in the first voltage generating unit 201 generates a plurality of positive polarity gamma voltages VP according to the first gamma binding point voltage iGM1, the sixth gamma binding point voltage iGM6, the seventh gamma binding point voltage iGM7 and the shared voltage SGM (i.e., the second gamma binding point voltage iGM2 to the fifth gamma binding point voltage iGM5) to output them to the second digital-to-analog conversion circuit DAC2 of the signal generating module 30. The second digital-to-analog conversion circuit DAC2 generates a plurality of positive polarity grayscale voltages according to the plurality of second data voltages and the positive polarity gamma voltage VP. The output buffer OB of the signal generating module 30 receives the plurality of positive polarity grayscale voltages to generate a plurality of positive polarity data signals, which are output to the corresponding data lines DL via a plurality of output channels, so that the corresponding sub-pixels Spi receive the positive polarity data signals. The polarity voltage generating circuit GR in the second voltage generating unit 202 generates a plurality of negative polarity gamma voltages VN according to the eighth gamma binding point voltage iGM8, the ninth gamma binding point voltage iGM9, the fourteenth gamma binding point voltage iGM14 and the common voltage SGM (i.e., the tenth gamma binding point voltage iGM10 to the thirteenth gamma binding point voltage iGM13) and outputs them to the second digital-to-analog conversion circuit DAC2 of the signal generating module 30. The second digital-to-analog conversion circuit DAC2 generates a plurality of negative polarity grayscale voltages according to the plurality of second data voltages and the negative polarity gamma voltage VN. The output buffer OB of the signal generating module 30 receives the plurality of negative polarity grayscale voltages and generates a plurality of negative polarity data signals, which are output to the corresponding data lines DL via a plurality of output channels, so that the corresponding sub-pixels Spi receive the negative polarity data signals.

[0074] In the second driver chip DIC2, the polarity voltage generating circuit GR in the first voltage generating unit 201 generates a plurality of positive polarity gamma voltages VP based on the first gamma binding point voltage iGM1, the fifth gamma binding point voltage iGM5, the seventh gamma binding point voltage iGM7 and the shared voltage SGM (i.e., the second gamma binding point voltage iGM2 to the fourth gamma binding point voltage iGM4, and the sixth gamma binding point voltage iGM6) to output to the second digital-to-analog conversion circuit DAC2 of the signal generating module 30. The second digital-to-analog conversion circuit DAC2 generates a plurality of positive polarity grayscale voltages based on the plurality of second data voltages and the positive polarity gamma voltage VP. The output buffer OB of the signal generating module 30 receives the plurality of positive polarity grayscale voltages to generate a plurality of positive polarity data signals, which are output to the corresponding data lines DL via a plurality of output channels, so that the corresponding sub-pixels Spi receive the positive polarity data signals. The polarity voltage generating circuit GR in the second voltage generating unit 202 generates a plurality of negative polarity gamma voltages VN based on the eighth gamma binding point voltage iGM8, the tenth gamma binding point voltage iGM10, the fourteenth gamma binding point voltage iGM14 and the common voltage SGM (i.e., the ninth gamma binding point voltage iGM9, the eleventh gamma binding point voltage iGM11 to the thirteenth gamma binding point voltage iGM13) and outputs them to the second digital-to-analog conversion circuit DAC2 of the signal generating module 30. The second digital-to-analog conversion circuit DAC2 generates a plurality of negative polarity grayscale voltages based on the plurality of second data voltages and the negative polarity gamma voltage VN. The output buffer OB of the signal generating module 30 receives the plurality of negative polarity grayscale voltages and generates a plurality of negative polarity data signals, which are output to the corresponding data lines DL via a plurality of output channels, so that the corresponding sub-pixels Spi receive the negative polarity data signals.

[0075] Similarly, the working principle can be obtained that the third to fifth driver chips DIC3 to DIC5 generate multiple polarity data signals according to the multiple gamma binding point voltages iGM generated by themselves and the multiple shared voltages SGM received, so as to be received by the multiple sub-pixels Spi.

[0076] Therefore, when each driver chip DIC generates two gamma tie point voltages iGM used as the shared voltage SGM, the driver chip DIC only needs to set one voltage amplifier circuit GOP in each of the first voltage generating unit 201 and the second generating unit. Therefore, each driver chip DIC only needs to set two voltage amplifier circuits GOP. Figure 3D Each driver chip DIC shown needs to be equipped with 10 voltage amplifier circuits GOP, using Figure 3A The design shown can significantly reduce the number of voltage amplifier circuits GOP included in the driver chip DIC, which is beneficial to reducing the size, power consumption and cost of the driver chip DIC.

[0077] Furthermore, since each driver chip DIC generates polarity data signals based on 14 gamma-binding voltages iGM, and each driver chip DIC generates two gamma-binding voltages iGM for use as the shared voltage SGM, only five driver chips DIC are required to meet the requirements. That is, the five driver chips DIC generate a total of 10 gamma-binding voltages iGM for use as the shared voltage SGM. Each driver chip DIC also generates four gamma-binding voltages iGM corresponding to the minimum and maximum grayscales mapped based on multiple power supply reference voltages VGM. This results in Z = 4 + XY = 4 + 2*5 = 14.

[0078] Therefore, using Figure 3A In the design shown, when the display device includes 12 driver chips DIC, and each driver chip DIC generates two gamma tie point voltages iGM used as the shared voltage SGM, the 12 driver chips DIC can support the output of 28 (i.e., 4+2*12=28) different gamma tie point voltages iGM. Figure 3D In the design shown, multiple driver chips DIC generate 14 identical gamma tie point voltages iGM. Figure 3D The driver chip DIC shown in the figure uses Figure 3A The design shown can increase the number of gamma binding point voltages iGM without increasing the cost, thereby helping to improve the cost increase problem caused by the differences between different display panels DP, which requires different display panels DP to adapt to different driver chips DIC. It also broadens the application range of the driver chip DIC and improves the versatility of the driver chip DIC.

[0079] As the resolution of the display panel DP increases, the signal transmission path becomes longer, and the signal transmission loss increases. Therefore, to adapt to the resolution of the display panel DP, when the number of driver chips DIC is greater than the required number (i.e., the required number is 5), in order to improve the signal quality of the shared voltage SGM corresponding to the low grayscale mapping, the sixth driver chip DIC6 can also generate the sixth gamma tie point voltage iGM6 and the ninth gamma tie point voltage iGM9, as shown in FIG. Figure 3A As shown. The grayscale mapped by the sixth gamma-binding point voltage iGM6 and the ninth gamma-binding point voltage iGM9 is smaller than the grayscale mapped by the second gamma-binding point voltage iGM2 to the fifth gamma-binding point grayscale voltage and the tenth gamma-binding point voltage iGM10 to the thirteenth gamma-binding point voltage iGM generated by the second driver chip DIC2 to the fifth driver chip DIC5. Accordingly, the first driver chip DIC1 and the sixth driver chip DIC6 correspond to the aforementioned first driver chip DICA, and the second driver chip DIC2 to the fifth driver chip DIC5 correspond to the aforementioned second driver chip DICB.

[0080] In order to further improve the signal quality of the shared voltage SGM corresponding to mapping low grayscale, the first driver chip DIC1 and the sixth driver chip DIC6 are arranged on opposite sides of the second driver chip DIC2 to the fifth driver chip DIC5. Figure 1A shown.

[0081] In order to further improve the signal quality of the shared voltage SGM corresponding to the low grayscale mapping, at least one of the fourth gamma binding point voltage iGM4 to the sixth gamma binding point voltage iGM6 and at least one of the ninth gamma binding point voltage iGM9 to the eleventh gamma binding point voltage iGM11 corresponding to the low grayscale mapping are obtained by the two voltage amplification circuits GOP. Figure 3B to Figure 3C shown.

[0082] In some embodiments, in order to adapt the resolution of the display panel DP and reduce the signal attenuation problem, the first driver chip DICA and the second driver chip DICB can be repeatedly arranged in a group. Figure 1A There are also provided an eighth driver chip DIC8 to a tenth driver chip DIC10 for correspondingly generating the second gamma binding point voltage iGM2 to the fifth gamma binding point voltage iGM5 and the tenth gamma binding point voltage iGM10 to the thirteenth gamma binding point voltage iGM13, and a seventh driver chip DIC7 and a twelfth driver chip DIC12 for correspondingly generating the sixth gamma binding point voltage iGM6 and the ninth gamma binding point voltage iGM9. The first driver chip DIC1 to the sixth driver chip DIC6 form a chipset, and the seventh driver chip DIC7 to the twelfth driver chip DIC12 form another chipset. The shared voltage SGM between multiple chipsets can be shared.

[0083] Please continue reading Figure 1A The display panel DP includes a liquid crystal display panel, a horizontal electric field inversion type liquid crystal display panel, a vertical alignment type liquid crystal display panel, a low-temperature polysilicon display panel, etc.

[0084] Because different types of liquid crystal display panels DP use different materials and structural designs, the optical performance of the display panel DP is also different. The inconsistent performance of the material optical curve will lead to different grayscale change performance of the display panel DP. For example, in the horizontal electric field inversion type liquid crystal display panel, the resistor string in the polarity voltage generating circuit GR is sensitive to the change of the corresponding low grayscale. If the horizontal electric field inversion type liquid crystal display panel directly uses Figure 3D The driver chip DIC shown for vertical alignment liquid crystal display panels will cause the horizontal electric field inversion liquid crystal display panel to have a low grayscale brightness gradient that changes too quickly, the corresponding low grayscale gamma binding point voltage iGM exceeds the lower limit, and the display panel DP has display problems such as color deviation and noise.

[0085] And adopt Figure 3A The design shown in the figure can achieve the purpose of increasing the gamma tie point grayscale voltage and polarity gamma voltage corresponding to the low grayscale mapping without increasing the number of driver chips DIC by sharing the gamma tie point voltage iGM among multiple driver chips DIC. For example, in a vertical alignment type liquid crystal display panel, the corresponding polarity gamma voltages are ±G0, ±G1, ±G31, ±G127, ±G223, ±G254, and ±G255. In a horizontal electric field inversion type liquid crystal display panel, the polarity gamma voltages are ±G0, ±G1, ±G31, ±G127, ±G223, ±G254, and ±G255. Figure 3A In the design shown, the gamma tie point voltage iGM is increased, which can make the polarity gamma voltages of the horizontal electric field inversion type liquid crystal display panel corresponding to ±G0, ±G1, ±G8, ±G16, ±G31, ±G127, ±G223, ±G254, and ±G255 respectively. Figure 3A The gamma tie-point voltage iGM generated by the driver chip DIC shown in the figure can meet the application requirements of both vertical alignment type liquid crystal display panels DP and horizontal electric field inversion type liquid crystal display panels DP. Therefore, the number of driver chips DIC can be reduced and the versatility of the driver chips DIC can be improved. Wherein, + represents positive polarity and - represents negative polarity.

[0086] It should be noted that in some embodiments, multiple first gamma reference voltages VA and multiple second gamma reference voltages VB can also be generated by a single gamma power supply unit. Specifically, control modules such as a timing controller Tcon and a logic controller, in conjunction with register settings, enable the same gamma power supply module 10 to generate the first gamma reference voltages VA and the second gamma reference voltages VB in a time-sharing manner. This further reduces the number of operational amplifiers included in the driver chip DIC. For example, if the gamma power supply module 10 includes only one gamma power supply unit, the gamma power supply unit includes a first operational amplifier OP1, a second operational amplifier OP2, and multiple resistors connected in series. The non-inverting input of the first operational amplifier OP1 is configured to receive the first power supply reference voltage UH or the third power supply reference voltage LH, and the inverting input of the first operational amplifier OP1 is electrically connected to the output of the first operational amplifier OP1. The non-inverting input of the second operational amplifier OP2 is configured to receive the second power supply reference voltage UL or the fourth power supply reference voltage LL, and the inverting input of the second operational amplifier OP2 is electrically connected to the output of the second operational amplifier OP2. The multiple resistors connected in series are connected in series between the output of the first operational amplifier OP1 and the output of the second operational amplifier OP2. In this way, the number of operational amplifiers in the driver chip DIC can be reduced to two.

[0087] Optionally, when multiple first gamma reference voltages VA and multiple second gamma reference voltages VB are generated by the same gamma power supply unit, the first voltage generating unit 201 and the second voltage generating unit 202 can be electrically connected to the gamma power supply unit in a time-sharing manner through control modules such as a timing controller and a logic controller in conjunction with register settings.

[0088] Optionally, the positive gamma voltage VP and the negative gamma voltage VN can also be generated by the same voltage generation unit. That is, through control modules such as a timing controller and a logic controller, in conjunction with register settings, the voltage generation unit generates the first gamma tie point voltage iGMA and the positive gamma voltage VP, and the second gamma tie point voltage iGMB and the negative gamma voltage VN in a time-sharing manner.

[0089] Optionally, each driver chip DIC is configured to output X gamma tie-point voltages iGM serving as the shared voltage SGM. The first gamma reference voltage VA and the second gamma reference voltage VB are generated by the same voltage generation unit, and each driver chip DIC outputs V gamma tie-point voltages iGM serving as the shared voltage SGM, where V = X. For example, if the first gamma reference voltage VA and the second gamma reference voltage VB are generated by the same voltage generation unit, and each driver chip DIC outputs two gamma tie-point voltages iGM serving as the shared voltage SGM (i.e., X = 2), the voltage generation unit time-shares the output of a first gamma tie-point voltage iGMA and a second gamma tie-point voltage iGMB serving as the shared voltage SGM (i.e., V = 2).

[0090] It is understandable that when the first gamma binding point voltage iGMA and the second gamma binding point voltage iGMB are generated by the same voltage generating unit, the number of first digital-to-analog conversion circuits DAC1 and voltage amplification circuits GOP included in the voltage generating module 20 can be further reduced.

[0091] Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A display device, characterized in that: include: a display panel including a plurality of data lines; a plurality of driver chips electrically connected to the display panel, each of the driver chips being configured to receive a plurality of power supply reference voltages to generate a plurality of gamma tie point voltages, share the plurality of gamma tie point voltages as a plurality of shared voltages with at least another driver chip, and generate a plurality of polarity data signals according to the plurality of gamma tie point voltages and the received plurality of shared voltages, and output the signals to the corresponding data lines; The gamma binding point voltages used as the shared voltages generated by at least two of the driver chips correspond to different grayscale mappings; and each of the driver chips comprises: a gamma power supply module, configured to receive a plurality of the power supply reference voltages and generate a plurality of gamma reference voltages; a voltage generating module electrically connected to the gamma power supply module, configured to generate a plurality of gamma binding point voltages according to a plurality of gamma reference voltages, and to generate a plurality of polarity gamma voltages according to the plurality of gamma binding point voltages and a plurality of shared voltages; The signal generating module is electrically connected to the voltage generating module and is configured to receive a plurality of the polarity gamma voltages and generate a plurality of the polarity data signals.

2. The display device according to claim 1, wherein The power supply reference voltage includes a first power supply reference voltage, a second power supply reference voltage, a third power supply reference voltage and a fourth power supply reference voltage; The gamma power supply module includes: a first gamma power supply unit configured to receive the first power supply reference voltage and the second power supply reference voltage and generate a plurality of first gamma reference voltages; as well as The second gamma power supply unit is configured to receive the third power supply reference voltage and the fourth power supply reference voltage and generate a plurality of second gamma reference voltages.

3. The display device according to claim 2, wherein: The voltage generating module includes: a first voltage generating unit electrically connected to the first gamma power supply unit, configured to generate at least one first gamma binding point voltage based on a plurality of the first gamma reference voltages, share the first gamma binding point voltage as a first shared voltage with at least another of the driver chips, and generate a plurality of positive polarity gamma voltages based on the first gamma binding point voltage and the received plurality of the first shared voltages; and a second voltage generating unit, electrically connected to the second gamma power supply unit, configured to generate at least one second gamma binding point voltage based on a plurality of the second gamma reference voltages, share the second gamma binding point voltage as a second shared voltage to at least another of the driver chips, and generate a plurality of negative polarity voltages based on the second gamma binding point voltage and the received plurality of the second shared voltages; The plurality of gamma tie point voltages include the first gamma tie point voltage and the second gamma tie point voltage, the polarity gamma voltages include the positive polarity gamma voltage and the negative polarity gamma voltage, and the shared voltages include the first shared voltage and the second shared voltage.

4. The display device according to claim 3, wherein: At least one of the first voltage generating unit and the second voltage generating unit includes: at least one first digital-to-analog conversion circuit, electrically connected to the corresponding gamma power supply module, and configured to generate a binding point voltage according to a plurality of the gamma reference voltages; at least one voltage amplification circuit, electrically connected to the corresponding first digital-to-analog conversion circuit, and configured to generate the gamma binding point voltage according to the binding point voltage; and The polarity voltage generating circuit is electrically connected to the voltage amplifying circuit and is configured to generate a plurality of polarity gamma voltages according to a plurality of the gamma binding point voltages and a plurality of the common voltages.

5. The display device according to claim 4, wherein: The driving chip outputs X gamma binding point voltages used as the shared voltage; The voltage generating module of the driving chip includes X first digital-to-analog conversion circuits and X voltage amplification circuits; X>1.

6. The display device according to claim 3, wherein: A first grayscale mapped to the first gamma tie-point voltage is equal to a second grayscale mapped to the second gamma tie-point voltage.

7. The display device according to claim 6, wherein: The plurality of driver chips include a plurality of first driver chips and a plurality of second driver chips; the first grayscales mapped to the plurality of first driver chips are the same, the second grayscales mapped to the plurality of first driver chips are the same, the first grayscales mapped to the plurality of second driver chips are different, and the second grayscales mapped to the plurality of second driver chips are different; The first grayscale and / or the second grayscale mapped to the plurality of second driving chips are / is greater than the first grayscale and the second grayscale mapped to the plurality of first driving chips.

8. The display device according to claim 7, wherein: include: a plurality of sharing lines electrically connected to the plurality of driving chips, each of the sharing lines being configured to transmit a sharing voltage; A plurality of second driver chips electrically connected to the shared line are provided between the two first driver chips.

9. The display device according to claim 1, wherein The signal generating module comprises: a shift register configured to generate a sampling signal according to a clock control signal; a latch electrically connected to the shift register, configured to generate a plurality of first data voltages according to the sampling signal and a received image signal, and to latch or release the plurality of first data voltages according to a data latch control signal; a level conversion circuit electrically connected to the latch and configured to generate a plurality of second data voltages according to a plurality of the first data voltages; a second digital-to-analog conversion circuit electrically connected to the level conversion circuit and the voltage generation module, and configured to generate a plurality of polarity grayscale voltages according to a plurality of the second data voltages and the polarity gamma voltages; and The output buffer is electrically connected to the second digital-to-analog conversion circuit and is configured to generate a plurality of polarity data signals according to the plurality of polarity grayscale voltages.

10. The display device according to claim 1, wherein The display device includes Y driving chips, each of the driving chips is configured to output X gamma-binding point voltages used as the common voltage; Wherein, Y driving chips output Z gamma binding point voltages, X>1, Y>1, Z=4+XY.

11. The display device according to claim 1, wherein The display panel includes a horizontal electric field inversion type liquid crystal display panel and a vertical alignment type liquid crystal display panel.

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